A method for predicting the cycle life of an artificial intelligence chip under thermal coupling

Abstract

This invention discloses a method for predicting the cyclic lifespan of an artificial intelligence chip under thermo-coupling conditions, belonging to the field of lifespan prediction technology. The method includes the following steps: 1:1 standardized modeling of the chip entity; identification and elimination of false failures; lifespan identification and assessment under normal rated operating conditions; and lifespan identification and assessment under overload risk conditions. This invention employs a closed-loop method encompassing 1:1 standardized modeling of the chip entity, construction of thermo-coupling alternating loads adapted to the chip's dynamic computing power scheduling logic, identification and elimination of false failures, layered lifespan identification and assessment under normal rated operating conditions and overload risk conditions, and iterative optimization combining bond line S-N fatigue curves and linear fatigue accumulation criteria with the introduction of thermo-coupling correction coefficients. This method addresses the technical problems in existing technologies, such as simplistic and distorted modeling structures, disconnect between load settings and actual dynamic computing power scheduling, large prediction deviations due to incomplete operating condition coverage, and the inability to accurately reflect the chip's full-scenario service life.

Description

Technical Field

[0001] This invention relates to the field of lifetime prediction technology, and in particular to a method for predicting the cyclic lifetime of an artificial intelligence chip under thermal coupling. Background Technology

[0002] The cycle life prediction method for artificial intelligence chips captures degradation characteristics such as temperature, voltage, delay, and power consumption in real time, improving the accuracy and timeliness of life prediction. It can identify anomalies and failure risks in advance, support chip health management and reliability scheduling, and reduce on-site failures and downtime losses. At the same time, it shortens the aging verification cycle, reduces testing costs, and provides a basis for chip design optimization and long-term stable service.

[0003] Currently, existing technologies for predicting the cycle life of AI chips generally suffer from problems such as simplistic and distorted simulation modeling structures, disconnect between load settings and the chip's actual dynamic computing power scheduling logic, insufficient accuracy in screening failure-related data, incomplete coverage of operating conditions, and lack of effective experimental verification and optimization of prediction models. These problems lead to significant systematic deviations between the life prediction results and the actual service state of the chip, making it impossible to accurately and comprehensively reflect the chip's true cycle life across all scenarios from normal steady-state service to extreme overload service. This seriously affects the reliability and practicality of the prediction results, thereby limiting its support for chip reliability design optimization and full life cycle health management.

[0004] Therefore, a method for predicting the cycle life of artificial intelligence chips under thermal coupling is proposed to solve the above problems. Summary of the Invention

[0005] The main objective of this invention is to provide a method for predicting the cycle life of an artificial intelligence chip under thermal coupling, so as to solve the problems mentioned in the background above.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: a method for predicting the cycle life of an artificial intelligence chip under thermal coupling, comprising the following steps:

[0007] Step S1: Standardize the chip entity to a 1:1 scale, complete the 1:1 simulation of the chip's full structure in 3D, input the thermal and mechanical parameters of each component of the chip, construct the thermo-mechanical coupled alternating load spectrum according to the chip's dynamic computing power scheduling logic, set the simulation boundary conditions, compare the load spectrum of the rated working condition with the actual dynamic working condition and complete the marking, monitor the physical parameters of the chip's core failure sensitive points and complete the simulation parameter calibration. Step S2: Failure False Judgment Identification and Removal. Through failure mode and effect analysis, the chip failure-sensitive monitoring points are identified. Data classification and labeling are completed according to whether thermal coupling load is applied to the monitoring points. Unloaded routine data and abnormal invalid data are removed, and valid failure-related data are retained as valid analysis data. Step S3: Rated life identification and assessment under normal operating conditions. Set at least two sets of normal operating conditions, collect the cyclic stress amplitude data and cumulative plastic strain data of the connection points between the bonding wire and the die under the corresponding conditions, and compare the two types of data with the corresponding thresholds of the bonding wire material to complete the life status assessment and parameter verification of the chip under normal operating conditions. Step S4: Overload risk condition lifetime identification and assessment. Set at least two sets of overload risk accelerated operating conditions, and divide the overload risk conditions into the normal to overload stage and the overload continuous operation stage. Collect the stress mutation increment data and strain acceleration accumulation data of the bonding wire and die connection points under the corresponding conditions. Compare the two types of data with the corresponding thresholds to complete the fatigue performance assessment of the chip under overload risk conditions. Combine the bonding wire SN fatigue curve and the linear fatigue accumulation criterion to carry out full-condition cycle lifetime calculation. Introduce the thermo-coupling correction coefficient and iteratively optimize it in combination with the accelerated aging test results to obtain the cycle lifetime of the chip under actual operating conditions.

[0008] Preferably, in step S1, the architecture built by the 1:1 simulation of the full three-dimensional solid structure of the chip includes the bare die, packaging substrate, bonding wire, adhesive, and metal shell, replicating the actual assembly layout of the chip without structural simplification or size scaling. The thermal and mechanical parameters entered are the average values ​​of three repeated measurements of each component.

[0009] Preferably, in step S1, the thermally coupled alternating load logic is constructed based on the power consumption sub-loads corresponding to different computing power output levels within the complete working cycle of the chip, and the thermal load and mechanical load are bound simultaneously. The simulation boundary conditions include thermal boundary conditions and mechanical boundary conditions. The thermal boundary conditions include the chip heat dissipation method, convective heat transfer coefficient, and ambient temperature parameters. The mechanical boundary conditions are that the bottom of the packaging substrate is fixed, restricting the X, Y, and Z translational and rotational degrees of freedom.

[0010] Preferably, in step S1, when comparing the rated working condition load spectrum with the actual dynamic working condition load spectrum, if there is a load fluctuation deviation between the two, the component coordination stress within the deviation range is analyzed. If the component coordination stress is normal and there is no local stress concentration, the actual dynamic load spectrum is marked as the measured working load spectrum, and the rated working condition load spectrum is marked as the ideal standard load spectrum. Based on the changes in physical parameters under load, the chip lifetime loss state is marked as accelerated loss state or steady-state loss state.

[0011] Preferably, in step S2, the locked failure-sensitive monitoring points include the bonding wire connection point and the die interface point. Based on whether the monitoring points are loaded with thermal coupling loads, the monitoring points are divided into an effective load stage and an unloaded stage.

[0012] Preferably, in step S2, stress amplitude, strain amplitude and cycle period data of corresponding points are collected during the effective load stage, and effective data with stable data fluctuations and no abnormal sudden changes are screened and marked as effective failure-related data. During the no-load, no-load phase, the basic physical data of the chip under no-load conditions are collected and marked as no-load routine data. Data that exhibits sudden changes, irregular fluctuations, or exceeds the mechanical properties of the material is marked as abnormal and invalid data.

[0013] Preferably, in step S3, each group of normal rated operating conditions corresponds to a combination of different computing power output levels and different ambient temperatures. Under each group of operating conditions, the chip power consumption is within the rated range and the ambient temperature is within the normal operating range. Cyclic stress amplitude data represents the stress fluctuation amplitude within adjacent cycles at the bond line and the bare sheet connection point, while cumulative plastic strain data represents the cumulative amount of plastic deformation at that point within a single cycle.

[0014] Preferably, in step S3, if the cyclic stress amplitude data exceeds the fatigue limit threshold of the bonding wire material, or the cumulative plastic strain data exceeds the critical plastic strain threshold of the bonding wire material, it is inferred that the real-time life status of the chip under normal rated operating conditions is abnormal. If the cyclic stress amplitude data does not exceed the fatigue limit threshold of the bonding wire material, and the cumulative plastic strain data does not exceed the critical plastic strain threshold of the bonding wire material, it can be inferred that the real-time life status of the chip is normal under normal rated operating conditions. After the simulation evaluation is completed, if there are pre-failure points or abnormal parameters in the chip life parameters, adjust the load parameters or local structural matching parameters. If the chip life parameters meet the standards, retain the current measured data as the baseline for the normal rated operating life.

[0015] Preferably, in step S4, each group of overload risk acceleration conditions corresponds to a combination of different ambient temperatures and different computing power output levels, and the chip ambient temperature exceeds the normal operating range under each group of conditions. The stress mutation increment data is the instantaneous increase in stress value at the connection point between the bond line and the bare die during the normal to overload transition phase, and the strain acceleration accumulation data is the cumulative increase in plastic strain at that point per unit time during the overload continuous operation phase. The accelerated aging test used four sets of parallel chip samples prepared by the same batch and process, with three parallel samples in each set. The cyclic loading frequency was consistent with the actual working cycle of the chip. The failure criterion was a sudden increase in the bonding wire resistance by a set proportion or the occurrence of breakage. The average measured life of the parallel samples was taken as the final actual cycle life, and abnormal sample data with dispersion exceeding the set range were eliminated.

[0016] Preferably, in step S4, the linear fatigue accumulation criterion is calculated using the total fatigue damage degree, the actual number of cycles under each working condition, and the single-cycle life under each working condition. The iterative optimization steps of the thermal coupling correction coefficient are as follows: compare the measured cycle life of the accelerated aging experiment with the simulation calculation value, fit the correction coefficient by the least squares method, iterate repeatedly until the deviation between the simulation value and the measured value does not exceed 1.7%, substitute the actual working parameters of the chip into the optimized calculation logic, and calculate the total cycle life and corresponding working life of the chip under actual working conditions.

[0017] The present invention has the following beneficial effects: 1. This invention employs a closed-loop method for full-process cyclic life calculation of artificial intelligence chips, encompassing 1:1 full-structure standardized modeling of the chip entity, construction of thermo-coupled alternating loads adapted to the chip's dynamic computing power scheduling logic, identification and elimination of failure misjudgments, tiered life assessment of conventional rated operating conditions and overload risk operating conditions, and iterative optimization of full-operating-condition cyclic life calculation by combining bond line SN fatigue curves and linear fatigue accumulation criteria with the introduction of thermo-coupled correction coefficients. This method achieves complete reproduction and quantitative assessment of the life loss process of artificial intelligence chips across all scenarios, from steady-state conventional service to extreme overload service. It accurately matches the stress and heat states of the chip's actual dynamic service. Compared with existing technologies, it can significantly improve the fit between life prediction results and the actual service state of the chip, and greatly reduce the system deviations in simulation modeling, load setting, data filtering, and operating condition coverage. Therefore, it can solve the technical problems commonly found in existing chip life prediction technologies, such as simplistic and distorted modeling structures, disconnect between load setting and actual dynamic computing power scheduling, and large deviations in prediction results due to incomplete operating condition coverage, which fail to truly reflect the chip's full-scenario service life.

[0018] 2. This invention identifies core chip failure-sensitive monitoring points through failure mode and effects analysis (FMEA). It combines the thermal coupling load status of these monitoring points to classify and filter data, eliminating invalid data. This achieves accurate extraction of valid data related to chip failures and comprehensive exclusion of non-failure-related data. Compared to existing technologies, this improves the effectiveness and relevance of lifespan assessment data, significantly reduces redundant interference from full-domain data acquisition, and minimizes misjudgments of failures caused by non-thermal coupling factors. Therefore, it solves the technical problems of insufficient targeting in chip lifespan prediction data filtering, interference from invalid data in non-operating states, distortion of lifespan calculation results due to missing data at key failure points, and misjudgments of failure risks in existing technologies.

[0019] 3. This invention achieves simultaneous verification of the chip's steady-state service life and fatigue resistance performance under extreme conditions by identifying and evaluating the lifespan under conventional rated operating conditions and overload risk conditions, combined with the results of accelerated aging experiments to iteratively optimize the thermal coupling correction coefficient of the lifespan calculation model. Compared with existing technologies, this invention can improve the adaptability of the lifespan prediction model to different computing power output levels and different ambient temperature conditions, and ensure the reliability and versatility of the prediction model. Therefore, it can solve the technical problems in existing technologies where chip lifespan prediction only covers conventional rated operating conditions, cannot assess the failure risk of extreme overload scenarios, has poor versatility due to the lack of experimental verification and optimization of the prediction model, and cannot provide comprehensive support for chip reliability design. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the cycle life prediction method of the present invention; Figure 2 This is a schematic diagram of the failure misjudgment identification and rejection process of the present invention; Figure 3 This is a schematic diagram of the conventional rated service life identification and evaluation process of the present invention. Detailed Implementation

[0021] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0022] Example 1, please refer to Figure 1 The following is illustrated: A method for predicting the cycle life of an artificial intelligence chip under thermal coupling. This embodiment takes an NPU chip used in an autonomous driving vehicle scenario as the implementation object, and includes the following steps: Step S1: Standardize the chip entity to a 1:1 scale, complete the 1:1 simulation of the chip's full structure in 3D, input the thermal and mechanical parameters of each component of the chip, construct the thermo-mechanical coupled alternating load spectrum according to the chip's dynamic computing power scheduling logic, set the simulation boundary conditions, compare the load spectrum of the rated working condition with the actual dynamic working condition and complete the marking, monitor the physical parameters of the chip's core failure sensitive points and complete the simulation parameter calibration. In step S1, the architecture built by the 1:1 simulation of the full three-dimensional solid structure of the chip includes the bare die, packaging substrate, bonding wires, adhesive, and metal shell, replicating the actual assembly layout of the chip without structural simplification or size scaling. The thermal and mechanical parameters entered are the average values ​​of three repeated measurements of each component.

[0023] In step S1, the thermally coupled alternating load logic is constructed based on the power consumption sub-loads corresponding to different computing power output levels within the complete working cycle of the chip, and the thermal load and mechanical load are bound simultaneously. The simulation boundary conditions include thermal boundary conditions and mechanical boundary conditions. The thermal boundary conditions include the chip heat dissipation method, convective heat transfer coefficient, and ambient temperature parameters. The mechanical boundary conditions are that the bottom of the packaging substrate is fixed, restricting the X, Y, and Z translational and rotational degrees of freedom.

[0024] In step S1, when comparing the rated working condition load spectrum with the actual dynamic working condition load spectrum, if there is a load fluctuation deviation between the two, analyze the component matching stress within the deviation range. If the component matching stress is normal and there is no local stress concentration, mark the actual dynamic load spectrum as the measured working load spectrum and mark the rated working condition load spectrum as the ideal standard load spectrum. Based on the changes in physical parameters under load, the chip lifetime loss state is marked as accelerated loss state or steady-state loss state.

[0025] Furthermore, the 1:1 standardized modeling process for the chip entity in step S1 is as follows: Based on the actual internal layout and external packaging structure of the autonomous driving NPU chip, a modeling layout plan was developed. COMSOL finite element analysis software was used to complete the 1:1 simulation of the chip's full three-dimensional solid structure. The simulation architecture includes five core structures: bare die, FR-4 material packaging substrate, Au bonding wire, modified epoxy adhesive, and metal shell. The actual assembly layout of the chip was strictly replicated without structural simplification or size scaling, maximizing the restoration of the chip's true assembly form and avoiding simulation deviations in stress and temperature fields caused by structural simplification. The precise thermal and mechanical parameters were optimized by averaging the structural dimensions and packaging performance parameters of each component after three repeated measurements. The inherent material properties were calibrated using the corresponding industry standard values ​​combined with measured data. Specifically, the bare wafer material is monocrystalline silicon, with dimensions of 10mm × 10mm × 0.5mm, an elastic modulus of 130GPa, a Poisson's ratio of 0.28, a coefficient of thermal expansion of 2.6ppm / ℃, and a thermal conductivity of 148W / (m²). K); the packaging substrate material is FR-4, with an elastic modulus of 25 GPa, Poisson's ratio of 0.18, a coefficient of thermal expansion of 16 ppm / ℃, and a thermal conductivity of 0.3 W / (m). K); the bonding wire is high-purity Au wire, with a diameter of 25μm, a spacing of 100μm, an elastic modulus of 78GPa, a fatigue limit of 380MPa, and a critical plastic strain threshold of 0.35%; the adhesive is a modified epoxy adhesive with a shear strength of 22MPa and a thickness of 50μm, ensuring that the material properties are completely consistent with the physical hardware.

[0026] The dynamic computing power scheduling logic under the actual working state of the chip is acquired. The chip has a rated power of 200W and an operating voltage of 12V. The dynamic computing power scheduling cycle is 10s, which includes three stages: 3s of 100% full computing power output, 4s of 80% computing power output, and 3s of 60% computing power output. Corresponding power consumption sub-loads are set for different computing power output levels. Among them, 100% computing power corresponds to 200W of thermal power, 80% computing power corresponds to 160W of thermal power, and 60% computing power corresponds to 120W of thermal power. The power consumption sub-loads construct an overall load spectrum based on the complete working cycle of the chip, and simultaneously bind thermal loads and mechanical loads to form a thermo-mechanical coupled alternating load spectrum adapted to the actual working state of the chip, thus restoring the stress and heat state of the chip during dynamic service. Set simulation boundary conditions, which include thermal boundary conditions and mechanical boundary conditions; The thermal boundary conditions are as follows: the chip is cooled by air, and the convective heat transfer coefficient is 30 W / (m²). 2 K), initial ambient temperature 25℃, actual application ambient temperature range -40℃~60℃, covering extreme cold and high temperature environments in vehicles; mechanical boundary conditions: the bottom of the packaging substrate is fixed, restricting the X, Y, Z three-axis translation and rotation degrees of freedom, simulating the actual assembly and fixed state of the chip.

[0027] The rated load logic of the chip is compared with the actual dynamic load logic. The rated load logic is constructed and set according to the execution order of the chip's working process, and compared with the actual dynamic load logic. If there is a load fluctuation deviation between the two, the stress of the components within the deviation range is analyzed. If the components are subjected to normal stress and there is no local stress concentration, the current actual dynamic load logic is marked as the measured working load logic, and the rated load logic is marked as the ideal standard load logic. In this step, the dynamic computing power scheduling of the AI ​​chip fluctuates in real time with road conditions and task requirements during actual vehicle operation, and it does not operate under a constant rated load. Therefore, the actual dynamic load logic is used to restore the chip's true working state.

[0028] In a chip simulation scenario, the working cycle is set to different load progress, and the physical parameters of the chip's core failure-sensitive points are monitored in real time. If the current load is at full load and high power consumption, the chip power consumption exceeds the rated threshold, the core temperature rises synchronously, the internal thermal stress increases significantly, and the lifespan loss shows an accelerated accumulation trend, then this stage is marked as an accelerated loss state. If the current load is at a normal light load, the chip power consumption is within the rated range, the core temperature is stable, the internal stress is gentle, and the lifespan loss shows a steady-state accumulation trend, then this stage is marked as a steady-state loss state. Based on the changes in physical parameters under different load conditions, the chip lifespan loss type is marked, parameter calibration is completed in conjunction with actual measured data, and the data changes and preliminary lifespan prediction results are displayed in real time during the simulation process through the interactive terminal of the finite element simulation software.

[0029] Example 2, please refer to Figure 1 and Figure 2 As shown: A method for predicting the cycle life of an artificial intelligence chip under thermal coupling, comprising the following steps: Step S2: Failure False Judgment Identification and Removal. Through failure mode and effect analysis, the chip failure-sensitive monitoring points are identified. Data classification and labeling are completed according to whether thermal coupling load is applied to the monitoring points. Unloaded routine data and abnormal invalid data are removed, and valid failure-related data are retained as valid analysis data. In step S2, the locked failure-sensitive monitoring points include the connection points between the bonding wire and the bare die, and the interface points between the bare die and the adhesive. Based on whether the monitoring points are loaded with thermal coupling loads, the monitoring points are divided into an effective load stage and an unloaded stage.

[0030] In step S2, stress amplitude, strain amplitude and cycle period data of corresponding points are collected during the effective load stage. Valid data with stable fluctuations and no abnormal sudden changes are selected and marked as valid failure-related data. During the no-load, no-load phase, the basic physical data of the chip under no-load conditions are collected and marked as no-load routine data. Data that exhibits sudden changes, irregular fluctuations, or exceeds the mechanical properties of the material is marked as abnormal and invalid data.

[0031] Furthermore, the failure misjudgment identification and elimination process in step S2 is as follows: In a standardized simulation scenario, failure mode and effects analysis (FMEA) is first used to identify key failure factors of the chip as the temperature difference between the core and edge regions and stress concentration at the connection between the bond wire and the die. The key failure mode is fatigue fracture of the bond wire. Based on this, the core monitoring area is locked, and two major failure-sensitive monitoring points are located: the connection point between the bond wire and the die, and the interface point between the die and the adhesive. Then, COMSOL simulation software is used to continuously collect real-time data on temperature, stress, and strain at the locked points, focusing on data collection in high-risk areas to reduce redundancy and interference in global data collection.

[0032] The determination is made based on whether the current monitoring point is loaded with the corresponding thermo-coupling load. If yes, the current monitoring point is in the effective load stage, and the chip is in the coupled stress state of normal operation. The corresponding stress, strain amplitude and cycle data of the corresponding point are collected. Valid data with stable fluctuations, conforming to the hardware stress law and without abnormal changes are screened. Abnormal invalid data with data changes, irregular fluctuations and exceeding the mechanical properties of materials are eliminated. If the monitoring data is within the normal stress fluctuation range and there is no continuous cumulative deviation trend, the corresponding data is marked as valid failure-related data. No, then the current monitoring point is in the no-load stage, the chip is in a non-working state with no power and no computing power output, and the basic physical data of the chip under no-load state are collected, specifically including: the initial stress value, initial strain value, and reference temperature value of the five major structures of bare die, packaging substrate, bonding wire, adhesive and metal shell at 25℃ and normal temperature and pressure. The initial stress value is not greater than 0.1MPa and the initial strain value is not greater than 0.01%. This kind of data is only the intrinsic static parameters of the material under no external force and no thermal load, and there is no thermo-mechanical coupling alternating fatigue effect. It is only used as a reference for simulation data and is marked as no-load conventional data.

[0033] Redundant unloaded routine data and abnormal invalid data are uniformly marked as discarded data and will not be included in subsequent lifetime conversion and evaluation calculations; valid failure-related data are marked as valid analysis data and are specifically used for subsequent lifetime assessment of the chip under normal rated operating conditions and overload risk accelerated operating conditions, so as to eliminate the failure misjudgment caused by uncoupled factors and ensure the accuracy of subsequent lifetime calculations.

[0034] Example 3, please refer to Figure 1 and Figure 3 As shown: A method for predicting the cycle life of an artificial intelligence chip under thermal coupling, comprising the following steps: Step S3: Rated life identification and assessment under normal operating conditions. Set at least two sets of normal operating conditions, collect the cyclic stress amplitude data and cumulative plastic strain data of the connection points between the bonding wire and the die under the corresponding conditions, and compare the two types of data with the corresponding thresholds of the bonding wire material to complete the life status assessment and parameter verification of the chip under normal operating conditions. In step S3, each group of normal rated operating conditions corresponds to a combination of different computing power output levels and different ambient temperatures. Under each group of operating conditions, the chip power consumption is within the rated range and the ambient temperature is within the normal operating range. Cyclic stress amplitude data represents the stress fluctuation amplitude within adjacent cycles at the bond line and the bare sheet connection point, while cumulative plastic strain data represents the cumulative amount of plastic deformation at that point within a single cycle.

[0035] In step S3, if the cyclic stress amplitude data exceeds the fatigue limit threshold of the bonding wire material, or the cumulative plastic strain data exceeds the critical plastic strain threshold of the bonding wire material, it is inferred that the real-time life status of the chip under normal rated operating conditions is abnormal. If the cyclic stress amplitude data does not exceed the fatigue limit threshold of the bonding wire material, and the cumulative plastic strain data does not exceed the critical plastic strain threshold of the bonding wire material, it can be inferred that the real-time life status of the chip is normal under normal rated operating conditions. After the simulation evaluation is completed, if there are pre-failure points or abnormal parameters in the chip life parameters, adjust the load parameters or local structural matching parameters. If the chip life parameters meet the standards, retain the current measured data as the baseline for the normal rated operating life.

[0036] Furthermore, the routine rated service life identification and assessment process in step S3 is as follows: The chip simulation scenario was set to three sets of normal rated operating conditions to fully simulate the chip's daily steady-state service environment. The parameters for each set of operating conditions were: Condition A (100% computing power + 60℃ ambient temperature), Condition B (80% computing power + 40℃ ambient temperature), and Condition C (60% computing power + 20℃ ambient temperature). Under all operating conditions, the chip power consumption was within the rated range, the ambient temperature was within the normal operating range, and the components were subjected to normal stress. There was no overload, no extreme temperature change, and no local stress concentration, which corresponded one-to-one with the three levels of dynamic computing power scheduling of the chip.

[0037] Cyclic stress amplitude data and cumulative plastic strain data were collected for each group under normal rated operating conditions. The cyclic stress amplitude data represents the extreme value of stress fluctuation within adjacent cycles at the chip bonding wire connection point under normal rated operating conditions, and the cumulative plastic strain data represents the total cumulative plastic deformation at that point within a single cycle. Simulation calculations yielded the following results: Under condition A, the highest temperature in the chip core region is 82℃, with a temperature difference of 18℃ from the edge region, and the maximum principal stress at the bonding wire connection to the die is 350MPa; Under condition B, the highest temperature in the core region is 68℃, with a temperature difference of 12℃ from the edge region, and the maximum principal stress is 280MPa; Under condition C, the highest temperature in the core region is 52℃, with a temperature difference of 8℃ from the edge region, and the maximum principal stress is 220MPa. The two types of core data were then compared with the corresponding material thresholds. If the cyclic stress amplitude data of the chip under normal rated operating conditions exceeds the fatigue limit threshold of 380MPa for the corresponding Au bond wire material, or the cumulative plastic strain data exceeds the critical strain threshold of the material by 0.35%, it is inferred that the real-time life status of the chip under normal rated operating conditions is abnormal and there is a risk of pre-failure. The current standard life parameters are compared and collected with the real-time monitoring parameters, the abnormal parameters and points are marked, and the results are displayed through the simulation interactive terminal after the simulation evaluation is completed. If the cyclic stress amplitude data of the chip under normal rated operating conditions does not exceed the fatigue limit threshold of 380MPa for the corresponding Au bond wire material, and the cumulative plastic strain data does not exceed the critical strain threshold of the material by 0.35%, it is inferred that the real-time life status of the chip under normal rated operating conditions is normal and there are no pre-failure points. The current standard life parameters are compared and collected with the real-time monitoring parameters, and the results are displayed through the simulation interactive terminal after the simulation evaluation is completed.

[0038] After the simulation evaluation is completed, the chip life parameters under normal rated operating conditions are checked. If there are pre-failure points or abnormal parameters, the load parameters or local structural matching parameters are adjusted accordingly. If all life parameters meet the standards and there are no abnormalities, there is no need to adjust the load and structural parameters, and the current measured data is retained as the base for normal rated operating conditions.

[0039]

[0040] Example 4, please refer to Figure 1 As shown: A method for predicting the cycle life of an artificial intelligence chip under thermal coupling, comprising the following steps: Step S4: Overload risk condition lifetime identification and assessment. Set at least two sets of overload risk accelerated operating conditions, and divide the overload risk conditions into the normal to overload stage and the overload continuous operation stage. Collect the stress mutation increment data and strain acceleration accumulation data of the bonding wire and die connection points under the corresponding conditions. Compare the two types of data with the corresponding thresholds to complete the fatigue performance assessment of the chip under overload risk conditions. Combine the bonding wire SN fatigue curve and the linear fatigue accumulation criterion to carry out full-condition cycle lifetime calculation. Introduce the thermo-coupling correction coefficient and iteratively optimize it in combination with the accelerated aging test results to obtain the cycle lifetime of the chip under actual operating conditions.

[0041] In step S4, each group of overload risk acceleration conditions corresponds to a combination of different ambient temperatures and different computing power output levels. Under each group of conditions, the chip ambient temperature exceeds the normal operating range. The stress mutation increment data is the instantaneous increase in stress value at the connection point between the bond line and the bare die during the normal to overload transition phase, and the strain acceleration accumulation data is the cumulative increase in plastic strain at that point per unit time during the overload continuous operation phase. The accelerated aging test used four sets of parallel chip samples prepared by the same batch and process, with three parallel samples in each set. The cyclic loading frequency was consistent with the actual working cycle of the chip. The failure criterion was a sudden increase in the bonding wire resistance by a set proportion or the occurrence of breakage. The average measured life of the parallel samples was taken as the final actual cycle life, and abnormal sample data with dispersion exceeding the set range were eliminated.

[0042] In step S4, the linear fatigue accumulation criterion is calculated using the total fatigue damage degree, the actual number of cycles under each working condition, and the single-cycle life under each working condition. The iterative optimization steps of the thermal coupling correction coefficient are as follows: compare the measured cycle life of the accelerated aging experiment with the simulation calculation value, fit the correction coefficient by the least squares method, iterate repeatedly until the deviation between the simulation value and the measured value does not exceed 1.7%, substitute the actual working parameters of the chip into the optimized calculation logic, and calculate the total cycle life and corresponding working life of the chip under actual working conditions.

[0043] Furthermore, the overload risk condition life assessment process in step S4 is as follows: The chip simulation scenario was set up with three sets of overload risk accelerated operating conditions to fully simulate the extreme service environment of the chip in the automotive industry. The parameters of each set of operating conditions are: Operating Condition 1 (85℃ ambient temperature + 100% full computing power output), Operating Condition 2 (70℃ ambient temperature + 80% computing power output), and Operating Condition 3 (65℃ ambient temperature + 60% computing power output). Under all operating conditions, the ambient temperature of the chip exceeds the normal rated range of 60℃, and the stress on each component exceeds the limit. The overload risk operating conditions are divided into the normal to overload stage and the overload continuous operation stage, which correspond to the two extreme scenarios of instantaneous overload and long-term overload of the chip, respectively. Accelerated aging experiments were carried out simultaneously for verification.

[0044] The stress change threshold of 150 MPa and the cumulative strain rate increase threshold of 0.05% / 1000 cycles were calibrated through the following steps: Using high-purity Au bonding wires with a diameter of 25μm, the same specifications as in this embodiment, tensile fatigue tests were conducted at room temperature. The loading frequency was consistent with the chip working cycle at 10s / cycle. Five parallel samples were set up for each test group. The critical values ​​of instantaneous overload stress change and long-term fatigue strain accumulation of the bonding wires were obtained. Based on the chip simulation architecture of this embodiment, extreme working condition simulations were carried out in the full temperature range of -40℃ to 85℃ to verify the stress-strain limit of the bonding wire at different temperatures. Combining fatigue test data and simulation results, the above-mentioned stress change threshold and strain cumulative growth rate threshold were comprehensively calibrated, which are consistent with the instantaneous impact resistance and long-term fatigue deformation characteristics of Au bond lines, and meet the extreme service requirements of autonomous driving chips in vehicles.

[0045] Stress mutation increment data and strain acceleration accumulation data were collected under each group of overload risk accelerated operating conditions. The stress mutation increment data is the instantaneous increase in stress value at the chip bonding wire connection point during the transition from normal to overload. The strain acceleration accumulation data is the cumulative increase in plastic strain at that point per unit time during the continuous overload operation phase.

[0046] Four sets of NPU chip samples of the same specifications were prepared. These samples were from the same batch and manufactured using the same process, with three parallel samples in each set. Sets 1-3 corresponded to three overload risk accelerated operating conditions, while set 4 served as a control group under room temperature rated operating conditions. The cyclic loading frequency was consistent with the actual operating cycle of the chip (10s / cycle). The failure criterion was a sudden increase in bond wire resistance of more than 10% (set according to the bond integrity requirements in GJB548B-2005 "Test Methods and Procedures for Microelectronic Devices") or macroscopic fracture of the bond wire observed under a metallographic microscope. The average measured lifetime of the parallel samples was taken as the final actual cycle lifetime. Abnormal sample data with a dispersion greater than 5% were removed. Cyclic aging tests were conducted under each set of overload risk accelerated operating conditions until bond wire fracture failure occurred. The actual cycle lifetime was recorded: Condition 1: Actual lifetime 1.2 × 10⁻⁶. 4 The actual service life under operating condition 2 is 6.5 × 10⁻⁶. 4 The actual service life under operating condition 3 is 2.8 × 10⁻⁶. 5 Next, compare the two types of overload-specific data with their corresponding preset thresholds. If the incremental data of chip stress change exceeds the stress change threshold of 150MPa during the normal transition to overload phase, or if the cumulative data of strain acceleration exceeds the strain acceleration threshold of 0.05% / 1000 cycles during the continuous overload operation phase, then the chip's fatigue resistance is deemed unqualified under overload risk conditions, and there is a risk of instantaneous fracture or rapid fatigue failure. The failure cycle under the current overload risk acceleration condition is marked as abnormal and displayed through the simulation interactive terminal after the simulation evaluation is completed. If the incremental data of chip stress change during the normal transition to overload phase does not exceed the stress change threshold of 150MPa, and the cumulative data of strain acceleration during the continuous overload operation phase does not exceed the strain acceleration threshold of 0.05% / 1000 cycles, then the chip's fatigue resistance under overload risk conditions is deemed qualified, with no risk of rapid failure. The failure cycle under the current overload risk acceleration condition is marked normally and displayed through the simulation interactive terminal after the simulation evaluation is completed.

[0047] Combining the industry standard SN fatigue curve and linear fatigue accumulation criterion for Au bond wires, a full-condition cycle life calculation was conducted. The SN fatigue curve for Au bond wires was plotted using 25μm diameter high-purity Au bond wires under actual measurements in an on-board environment of -40℃ to 60℃ and a 10s / cycle alternating load. The formula for the linear fatigue accumulation criterion is as follows: Where D is the total fatigue damage (chip failure occurs when D=1), and n i Let N be the actual number of cycles for the i-th working condition. i The single-cycle life under the i-th working condition; the single-cycle fatigue damage amount d i =1 / N i .

[0048] First, based on the SN fatigue curve, the single-cycle life corresponding to a stress of 350MPa under working condition A is found to be 5×10. 4 Each instance of fatigue damage is 2 × 10⁻⁶. -5 Under operating condition B, a stress of 280 MPa corresponds to a single-cycle life of 2 × 10⁻⁶. 5 Each instance of fatigue damage is 5 × 10⁻⁶. -6 Under operating condition C, a stress of 220 MPa corresponds to a single-cycle life of 8 × 10⁻⁶. 5 The fatigue damage per incident was 1.25 × 10⁻⁶. -6 Considering that the chip's dynamic computing power scheduling cycle is 10s / cycle, and combined with the actual usage scenario of the chip working 12 hours a day and 365 days a year, the cycle count ratios for different working conditions are as follows: Working condition A accounts for 30%, Working condition B accounts for 40%, and Working condition C accounts for 30%, which perfectly matches the time ratio of the chip's dynamic computing power scheduling levels. Based on the linear fatigue accumulation criterion, the cumulative fatigue damage calculation for multiple working conditions is completed.

[0049] A thermo-coupling correction coefficient is introduced, and iterative optimization is performed based on accelerated aging test results. The initial correction coefficient of 1.15 is set based on the average error of conventional errors in thermo-coupling simulation and measured results of similar chips. The iterative optimization steps are as follows: the measured cycle life of the accelerated aging test is compared with the simulated value, and the correction coefficient is fitted using the least squares method. The iteration is repeated until the relative deviation between the simulated value and the measured value does not exceed 1.7%. This threshold is set according to the industry accuracy requirements for life prediction of automotive high-reliability chips. Verified by multiple batches of accelerated aging tests of chips, this invention can meet the accuracy requirements for engineering applications. The actual operating parameters of the chip are substituted into the optimized calculation logic to calculate the total cycle life of 3.2 × 10⁻⁶ under actual working conditions. 6 This corresponds to an actual working life of approximately 7.4 ± 0.2 years, which meets the application requirements of autonomous driving scenarios.

[0050] This invention discloses a method for predicting the cycle life of an artificial intelligence chip under thermo-coupling conditions. The method involves first collecting and preprocessing the core parameters of an NPU chip used in autonomous driving, then performing a 1:1 standardized model of the chip to proportionally recreate its full structure and accurate material properties. Dynamic computing power scheduling load logic is matched, and complete thermo-coupling simulation boundary conditions are set. Next, failure mode and effect analysis is used to identify and eliminate core failure-sensitive points, and faulty failure identification is performed. Effective failure-related data is screened, and non-coupling factors and irrelevant data interference are excluded. Subsequently, multiple sets of conventional rated operating conditions are set to assess and evaluate the lifespan under these conditions, calculating the fatigue damage per cycle and determining the chip's steady-state service life. Finally, multiple sets of overload risk accelerated operating conditions are set to assess and evaluate the lifespan under these conditions and conduct accelerated aging experiments. Iterative optimization of simulation calculation parameters is completed, and the chip's fatigue resistance under extreme conditions is verified. Through multi-condition hierarchical evaluation and experimental verification, accurate prediction of the chip's cycle life across all scenarios is achieved.

[0051] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A method for predicting the cycle life of an artificial intelligence chip under thermal coupling, characterized in that, Includes the following steps: Step S1: Standardize the chip entity to a 1:1 scale, complete the 1:1 simulation of the chip's full structure in 3D, input the thermal and mechanical parameters of each component of the chip, construct the thermo-mechanical coupled alternating load spectrum according to the chip's dynamic computing power scheduling logic, set the simulation boundary conditions, compare the load spectrum of the rated working condition with the actual dynamic working condition and complete the marking, monitor the physical parameters of the chip's core failure sensitive points and complete the simulation parameter calibration. Step S2: Failure False Judgment Identification and Removal. Through failure mode and effect analysis, the chip failure-sensitive monitoring points are identified. Data classification and labeling are completed according to whether thermal coupling load is applied to the monitoring points. Unloaded routine data and abnormal invalid data are removed, and valid failure-related data are retained as valid analysis data. Step S3: Rated life identification and assessment under normal operating conditions. Set at least two sets of normal operating conditions, collect the cyclic stress amplitude data and cumulative plastic strain data of the connection points between the bonding wire and the die under the corresponding conditions, and compare the two types of data with the corresponding thresholds of the bonding wire material to complete the life status assessment and parameter verification of the chip under normal operating conditions. Step S4: Overload risk condition lifetime identification and assessment. Set at least two sets of overload risk accelerated operating conditions, and divide the overload risk conditions into the normal to overload stage and the overload continuous operation stage. Collect the stress mutation increment data and strain acceleration accumulation data of the bonding wire and die connection points under the corresponding conditions. Compare the two types of data with the corresponding thresholds to complete the fatigue performance assessment of the chip under overload risk conditions. Combine the bonding wire SN fatigue curve and the linear fatigue accumulation criterion to carry out full-condition cycle lifetime calculation. Introduce the thermo-coupling correction coefficient and iteratively optimize it in combination with the accelerated aging test results to obtain the cycle lifetime of the chip under actual operating conditions.

2. The method for predicting the cycle life of an artificial intelligence chip under thermal coupling according to claim 1, characterized in that, In step S1, the architecture built by the 1:1 simulation of the chip's full-structure three-dimensional entity includes the bare die, packaging substrate, bonding wires, adhesive, and metal shell, replicating the actual assembly layout of the chip without structural simplification or size scaling. The thermal and mechanical parameters entered are the average values ​​of three repeated measurements of each component.

3. The method for predicting the cycle life of an artificial intelligence chip under thermal coupling according to claim 1, characterized in that, In step S1, the thermally coupled alternating load logic is constructed based on the power consumption sub-loads corresponding to different computing power output levels within the complete working cycle of the chip, and the thermal load and mechanical load are bound simultaneously. The simulation boundary conditions include thermal boundary conditions and mechanical boundary conditions. The thermal boundary conditions include the chip heat dissipation method, convective heat transfer coefficient, and ambient temperature parameters. The mechanical boundary conditions are that the bottom of the packaging substrate is fixed, restricting the X, Y, and Z translational and rotational degrees of freedom.

4. The method for predicting the cycle life of an artificial intelligence chip under thermal coupling according to claim 1, characterized in that, In step S1, when comparing the rated working condition load spectrum with the actual dynamic working condition load spectrum, if there is a load fluctuation deviation between the two, the component coordination stress within the deviation range is analyzed. If the component coordination stress is normal and there is no local stress concentration, the actual dynamic load spectrum is marked as the measured working load spectrum, and the rated working condition load spectrum is marked as the ideal standard load spectrum. Based on the changes in physical parameters under load, the chip lifetime loss state is marked as accelerated loss state or steady-state loss state.

5. The method for predicting the cycle life of an artificial intelligence chip under thermal coupling according to claim 1, characterized in that, In step S2, the locked failure-sensitive monitoring points include the connection points between the bonding wire and the bare die, and the interface points between the bare die and the adhesive. Based on whether the monitoring points are loaded with thermal coupling loads, the monitoring points are divided into an effective load stage and an unloaded stage.

6. The method for predicting the cycle life of an artificial intelligence chip under thermal coupling according to claim 5, characterized in that, In step S2, stress amplitude, strain amplitude and cycle period data of corresponding points are collected during the effective load stage. Valid data with stable fluctuations and no abnormal sudden changes are selected and marked as valid failure-related data. During the no-load, no-load phase, the basic physical data of the chip under no-load conditions are collected and marked as no-load routine data. Data that exhibits sudden changes, irregular fluctuations, or exceeds the mechanical properties of the material is marked as abnormal and invalid data.

7. The method for predicting the cycle life of an artificial intelligence chip under thermal coupling according to claim 1, characterized in that, In step S3, each group of normal rated operating conditions corresponds to a combination of different computing power output levels and different ambient temperatures. Under each group of operating conditions, the chip power consumption is within the rated range and the ambient temperature is within the normal operating range. Cyclic stress amplitude data represents the stress fluctuation amplitude within adjacent cycles at the bond line and the bare sheet connection point, while cumulative plastic strain data represents the cumulative amount of plastic deformation at that point within a single cycle.

8. The method for predicting the cycle life of an artificial intelligence chip under thermal coupling according to claim 1, characterized in that, In step S3, if the cyclic stress amplitude data exceeds the fatigue limit threshold of the bonding wire material, or the cumulative plastic strain data exceeds the critical plastic strain threshold of the bonding wire material, it is inferred that the real-time life status of the chip under normal rated operating conditions is abnormal. If the cyclic stress amplitude data does not exceed the fatigue limit threshold of the bonding wire material, and the cumulative plastic strain data does not exceed the critical plastic strain threshold of the bonding wire material, it can be inferred that the real-time life status of the chip is normal under normal rated operating conditions. After the simulation evaluation is completed, if there are pre-failure points or abnormal parameters in the chip life parameters, adjust the load parameters or local structural matching parameters. If the chip life parameters meet the standards, retain the current measured data as the baseline for the normal rated operating life.

9. The method for predicting the cycle life of an artificial intelligence chip under thermal coupling according to claim 1, characterized in that, In step S4, each group of overload risk acceleration conditions corresponds to a combination of different ambient temperatures and different computing power output levels. Under each group of conditions, the chip ambient temperature exceeds the normal operating range. The stress mutation increment data is the instantaneous increase in stress value at the connection point between the bond line and the bare die during the normal to overload transition phase, and the strain acceleration accumulation data is the cumulative increase in plastic strain at that point per unit time during the overload continuous operation phase. The accelerated aging test used four sets of parallel chip samples prepared by the same batch and process, with three parallel samples in each set. The cyclic loading frequency was consistent with the actual working cycle of the chip. The failure criterion was a sudden increase in the bonding wire resistance by a set proportion or the occurrence of breakage. The average measured life of the parallel samples was taken as the final actual cycle life, and abnormal sample data with dispersion exceeding the set range were eliminated.

10. The method for predicting the cycle life of an artificial intelligence chip under thermal coupling according to claim 9, characterized in that, In step S4, the linear fatigue accumulation criterion is calculated using the total fatigue damage degree, the actual number of cycles under each working condition, and the single-cycle life under each working condition. The iterative optimization steps of the thermal coupling correction coefficient are as follows: compare the measured cycle life of the accelerated aging experiment with the simulation calculation value, fit the correction coefficient by the least squares method, iterate repeatedly until the deviation between the simulation value and the measured value is consistent with 1.7%, substitute the actual working parameters of the chip into the optimized calculation logic, and calculate the total cycle life and corresponding working life of the chip under actual working conditions.

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