Global verification method and system for intelligent fee collection of power marketing system

Abstract

The application provides a power marketing system intelligent fee collection global verification method and system, comprising: obtaining a to-be-executed fee collection list and a fee collection result table; traversing the to-be-executed fee collection list, extracting the short message channel record and the voice channel record corresponding to the target non-payment user from the fee collection result table, and merging the short message channel record and the voice channel record into a fixed-length data structure by arranging them adjacently in the memory; calculating a first time difference between the timestamp of the short message channel record and the system time; if the first time difference meets the first time interval condition, reading and calculating a second time difference between the timestamp of the voice channel record and the system time; if the second time difference meets the second time interval condition, counting the communication times of the short message channel record and the voice channel record; if the communication times reach the number threshold, generating the fee collection task data corresponding to the target non-payment user and updating the to-be-executed fee collection list according to the fee collection task data. Thus, the efficiency of the fee collection data verification process is improved.

Description

Technical Field

[0001] This invention relates to the field of communication service technology, and in particular to a global verification method and system for intelligent payment collection in power marketing systems. Background Technology

[0002] Existing smart electricity bill collection systems typically generate a list of outstanding bills based on a preset collection cycle and number of collections, and then execute outbound calls through SMS and voice channels.

[0003] When generating a payment reminder list, it is necessary to verify the payment information that has already been sent. However, data such as payment status and historical reminder dates are usually scattered across different business subsystems. Existing verification methods rely on performing periodic batch queries on independent databases and cross-table cascading comparisons, resulting in low efficiency in generating payment reminder lists. Summary of the Invention

[0004] The technical problem to be solved by this invention is: how to improve the efficiency of the payment reminder data verification process.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A global verification method for intelligent payment collection in an electricity marketing system includes: Obtain the list of outstanding payment reminders and the payment reminder results table; Iterate through the list of unpaid users in the pending collection list. For each target unpaid user, extract the SMS channel record and voice channel record corresponding to the target unpaid user from the collection result table, and merge the SMS channel record and the voice channel record into a fixed-length data structure in memory by arranging them adjacently. Obtain the current system time and calculate the first time difference between the timestamp recorded by the SMS channel and the system time; If the first time difference satisfies the first time interval condition, then read and calculate the second time difference between the timestamp recorded by the voice channel and the system time; If the second time difference meets the second time interval condition, then the number of communications recorded in the SMS channel and the voice channel is counted. If the number of communications reaches the threshold, then collection task data corresponding to the target unpaid user is generated and the collection task data is used to update the collection list to be executed.

[0006] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is as follows: A global verification system for intelligent payment collection in an electricity marketing system includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the various steps of the global verification method for intelligent payment collection in an electricity marketing system as described above.

[0007] The beneficial effects of this invention are as follows: By performing adjacent arrangement operations on SMS channel records and voice channel records in physical memory, and merging the physical data into a fixed-length data structure according to the byte span of the adjacent arrangement; when processing data, the underlying system aligns the fixed-length data structure according to the cache line length parameter of the microprocessor chip, so that the hardware microprocessor chip can accurately complete the underlying data block loading operation in a single bus cycle, thus suppressing the trend of increasing CPU load from the physical hardware level; at the same time, when reading SMS channel records and voice channel records, it can be implemented based on the memory-level pointer addressing jump mechanism, replacing the existing application-layer polling code to process dynamic data stream retrieval mode, significantly reducing the hardware clock cycle waiting delay generated by the bus addressing logic, thereby improving the efficiency of the billing data verification process. Attached Figure Description

[0008] Figure 1 This is a flowchart illustrating the steps of a global verification method for intelligent payment collection in an electricity marketing system according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of an intelligent payment reminder global verification system for an electricity marketing system according to an embodiment of the present invention. Detailed Implementation

[0009] Definitions:

[0010] To explain in detail the technical content, objectives, and effects of the present invention, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0011] In existing technologies, generating a payment reminder list requires verifying the payment information that has already been sent. However, current verification methods rely on performing periodic batch queries on independent databases and cross-table cascading comparisons. This query method is prone to increasing the CPU load and resulting in low efficiency in generating payment reminder lists.

[0012] To address at least some of the aforementioned issues, this invention iterates through the list of unpaid users in the pending payment reminder process. It extracts and merges the SMS and voice channel records corresponding to the target unpaid users into a fixed-length data structure. The timestamps of the SMS and voice channel records are then compared sequentially with preset time interval conditions. Only when the preset time interval conditions are met is the number of communication transactions for the SMS and voice channel records counted, and a decision is made on whether to generate payment reminder task data. Simultaneously, the pending payment reminder list is updated. This approach allows the underlying system to align the fixed-length data structure according to the microprocessor chip's cache line length parameter during data processing. This enables the hardware microprocessor chip to accurately complete the loading of underlying data blocks in a single bus cycle, suppressing the increasing load on the central processing unit at the physical hardware level. Furthermore, reading SMS and voice channel records can be achieved using a memory-level pointer addressing jump mechanism, replacing the existing application-layer polling code-based dynamic data stream retrieval mode. This significantly reduces the hardware clock cycle latency caused by bus addressing logic, thereby improving the efficiency of the payment reminder data verification process.

[0013] The following details a global verification method for intelligent payment collection in an electricity marketing system according to the present invention. Please refer to [link / reference]. Figure 1 The method 100 includes steps 101 to 106: Step 101: Obtain the pending payment reminder list and payment reminder result table. The pending payment reminder list stores the user's unique account number and a settlement identifier indicating payment progress, with a payment status field indicating the current business process stage at the same level. The payment reminder result table stores SMS and voice channel records corresponding to the user's account number, each including a timestamp and a reach status bit. Simultaneously, to handle the massive concurrent data processing pressure from high-voltage industrial and residential users during the month-end settlement cycle of the electricity marketing business, the business application server connects to a relational database to synchronize the pending payment reminder list and payment reminder result table. To construct a unique index entry identifier for subsequent memory-level relational retrieval, a structured query statement is called to compare the settlement identifier in the pending payment reminder list with the predefined unpaid status code in memory. At the relational database index level, user account numbers matching the status code of a paid user are filtered out, and then the user account numbers associated with the unpaid status are extracted into high-speed random access memory to construct a query baseline data set.

[0014] Step 102: Traverse the list of unpaid users in the pending payment reminder list. For each target unpaid user, extract the SMS channel record and voice channel record corresponding to the target unpaid user from the payment reminder result table, and merge the SMS channel record and voice channel record into a fixed-length data structure arranged adjacently in memory. Specifically: extract the user account number marked as unpaid in the pending payment reminder list as the query base data; then traverse the user account number in the query base data.

[0015] Meanwhile, to mitigate the CPU load bottleneck and row-level lock blocking risks caused by cross-table cascading comparisons in existing databases, this embodiment establishes a mapping relationship in the virtual memory address space based on the query baseline data extracted into memory. This mapping relationship is then used to extract associated SMS and voice channel records from external storage. To ensure that the extracted SMS and voice channel records are not physically arranged within the original two-dimensional database table, a contiguous physical memory page is allocated in the operating system's virtual memory address space. The SMS and voice channel records are then arranged adjacently within this allocated physical memory page. Based on the byte span of the adjacent arrangement, the SMS and voice channel records are encapsulated into a fixed-length data structure including a fixed number of short message parameters and a corresponding voice parameter system. Subsequently, compiler instructions are called to obtain the physical row length parameter of the microprocessor chip's L1 cache. The generated fixed-length data structure is then aligned and filled according to the microprocessor chip's cache row length parameter, ensuring that the bytes of the adjacent data structures are aligned with the physical cache boundary. Finally, the entire fixed-length data structure aligned with the cache boundary is loaded into the data cache layer to form a compact data array.

[0016] Step 103: Obtain the current system time and calculate the first time difference between the timestamp of the SMS channel record and the system time. Specifically: The clock chip built into the business application server motherboard generates the system time through periodic oscillation; the operating system kernel allocates multiple concurrent threads to enter the data cache layer in parallel, and performs physical addressing traversal on the fixed-length data structure loaded into the data cache layer; the concurrent threads read the timestamp of the SMS channel record located in the low memory bit according to the starting address of the fixed-length data structure, and the arithmetic logic unit of the microprocessor chip calls the subtraction instruction to calculate the first time difference between the timestamp of the SMS channel record and the system time data.

[0017] Step 104: If the first time difference meets the first time interval condition, then read and calculate the second time difference between the timestamp of the voice channel record and the system time. For example, the first time interval condition is a preset number of days, which can be set according to the SMS sending cycle; the preset time interval condition loaded in the memory of the business application server is specifically mapped to an objective value of 10 days, which comes from the average information attenuation physical cycle caused by the power system sending payment reminder SMS messages to the user's communication terminal. When it is determined that the first time difference meets the preset number of days, the read pointer of the concurrent thread can be controlled to jump directly to the memory address of the voice channel record in the fixed-length data structure, bypassing the SMS channel record, and then read the timestamp of the voice channel record located at the memory address and calculate the second time difference.

[0018] Step 105: If the second time difference meets the second time interval condition, then count the number of communications recorded in the SMS channel and the voice channel. Specifically, when counting the number of communications, the calculation can be based on the reach status bits of the SMS channel records and the reach status bits of the voice channel records. The preset voice interval condition loaded in the memory of the business application server is specifically mapped to an objective value of 5 days. This objective value of 5 days originates from the hard physical limit of the safe call time span stipulated by the anti-harassment interception mechanism of the communication gateway.

[0019] Step 106: If the number of communications reaches a threshold, then generate collection task data corresponding to the target unpaid user and update the pending collection list based on the collection task data. The preset threshold number, internally stored in the microprocessor chip register, is strictly set to an objective value of 3 times. This objective value of 3 times originates from the critical blocking node where the user develops an auditory resistance response mechanism to the collection information. Simultaneously, when generating the collection task data, it is written to the system cache space; subsequently, the collection status field in the pending collection list is updated based on the collection task data, and the query baseline data is released.

[0020] As described above, the beneficial effects of this invention are as follows: by performing adjacent arrangement operations on SMS channel records and voice channel records in physical memory, and merging the physical data into a fixed-length data structure according to the byte span of the adjacent arrangement; when processing data, the underlying system aligns the fixed-length data structure according to the cache line length parameter of the microprocessor chip, so that the hardware microprocessor chip can accurately complete the loading of the underlying data block in a single bus cycle, thus suppressing the trend of increasing CPU load from the physical hardware level; at the same time, when reading SMS channel records and voice channel records, it can be implemented based on the memory-level pointer addressing jump mechanism, replacing the existing application-layer polling code to process dynamic data stream retrieval mode, significantly reducing the hardware clock cycle waiting delay generated by the bus addressing logic, thereby improving the efficiency of the billing data verification process.

[0021] In one embodiment of the present invention, step 104 of reading and calculating the second time difference between the timestamp of the voice channel record and the system time includes: controlling the read pointer of the concurrent thread to be offset by a byte length equal to that of the SMS channel record in a virtual memory address space that loads the fixed-length data structure, jumping to the target memory address, and obtaining the timestamp of the voice channel record; the target memory address is the starting address of the voice channel record.

[0022] Specifically: The microprocessor chip's comparison instruction determines the magnitude of the first time difference against a preset number of days. When the first time difference meets or exceeds the preset number of days, the operating system kernel intervenes in the concurrent thread's read pointer state, adding the fixed-byte length occupied by the SMS channel record to the current physical memory address of the concurrent thread's read pointer to generate a target memory address. Based on the target memory address, the concurrent thread's read pointer undergoes a physical offset equal to the byte length of the SMS channel record within the virtual memory address space containing the fixed-length data structure. This allows the concurrent thread's read pointer to skip the memory space occupied by the SMS channel record and jump directly to the target memory address, which is the first addressing entry point of the voice channel record located in the data cache layer.

[0023] The formula for bitwise shift operations on the target memory address is expressed as: ; In the formula, This represents the target memory address, which points to the starting address of the voice channel record loaded in the data cache layer; The current memory address of the concurrent thread's read pointer corresponds to the starting physical offset of the SMS channel record within the physical memory page. This represents the byte length of the SMS channel record, which is a static, constant value established during the construction phase of the fixed-length data structure.

[0024] The concurrent thread at the jump state landing point reads the pointer to directly extract the timestamp of the voice channel record located at the current memory address. The arithmetic logic unit of the microprocessor chip executes the subtraction instruction again to calculate the second time difference between the timestamp of the voice channel record and the system time data.

[0025] As described above, by calculating the offset parameter equal to the length of the SMS channel record in bytes, the read pointer of the concurrent thread is offset in the virtual memory address space by the same offset as the length of the SMS channel record in bytes. This causes the read pointer of the concurrent thread to skip the memory segment occupied by the SMS channel record and jump directly to the memory address of the voice channel record in the fixed-length data structure. The memory-level pointer addressing jump mechanism completely replaces the existing application-layer polling code for processing dynamic data streams, significantly reducing the hardware clock cycle delay caused by the bus addressing logic.

[0026] In one embodiment of the present invention, step 105, which counts the number of communications between the SMS channel record and the voice channel record, includes: concatenating the arrival status bits of the SMS channel record and the voice channel record in the fixed-length data structure according to the order of communication triggering to generate a continuous mask word; and performing a summation calculation on the continuous mask word to obtain the number of communications.

[0027] As described above, by concatenating the arrival status bits recorded by the SMS channel and the arrival status bits recorded by the voice channel in the order of communication triggering, a continuous mask word occupying a fixed register width is generated by concatenating the independent status bits; and then performing summation calculation based on the continuous mask word, the number of communications can be obtained.

[0028] In one embodiment of the present invention, the summation calculation of the continuous mask word includes: calling Hamming weight calculation hardware instructions to load the continuous mask word into a designated storage space; calculating the total number of non-zero data bits in the continuous mask word in the storage space using the Hamming weight calculation hardware instructions, and using the total number of non-zero data bits as the number of communication visits. The calculation process is achieved by the microprocessor chip hardware logic circuit relying on parallel bit manipulation logic, using the Hamming weight calculation hardware instructions to calculate the total number of valid reach identifiers represented by the non-zero data bits in the continuous mask word in one go. The formula for calculating the number of communication visits is abstracted as follows: ; In the formula, This represents the number of communication contacts reached, which reflects the actual cumulative frequency of responses from the target object. The total bit width of a contiguous mask word is determined by the total number of reach status bits introduced by the concatenation. This represents a continuous mask word, which is composed of the arrival status bits recorded by the SMS channel and the arrival status bits recorded by the voice channel, following the splicing rules. The current bit index variable represents the continuous mask word and controls the detection step size of the microprocessor chip in each clock cycle.

[0029] As described above, the Hamming weight calculation hardware instructions process continuous mask words, relying on low-level logic gates to perform high-throughput parallel bit calculations. The parallel bit calculations determine the total number of non-zero data bits in the continuous mask word in one operation. The system then assigns the absolute value of this total number of non-zero data bits to generate the communication reach count, thus obtaining the precise number of communications. Simultaneously, the hardware-level parallel bit operation mechanism replaces the conventional serial conditional statement code at the application layer, significantly reducing the machine instruction execution cycle of the massive dynamic streaming data collaborative verification logic.

[0030] In one embodiment of the present invention, step 106, generating collection task data corresponding to the target unpaid user and updating the collection list to be executed, includes: obtaining the outstanding amount data corresponding to the target unpaid user; determining whether the outstanding amount data is less than an amount threshold; if so, generating first strategy data including SMS gateway protocol data payload; if not, generating second strategy data including voice session initialization protocol; and encapsulating and generating the collection task data according to the first strategy data or the second strategy data. That is, when it is determined that the number of communication contacts has reached a control threshold set by a preset number of contacts, the business application server initiates a network layer request to the remote data storage node to obtain the outstanding amount data for the current user account number and generate collection task data. For example, the system has a built-in amount threshold of 10,000 yuan, which corresponds to the physical isolation boundary of the outstanding payment risk between high-voltage industrial users and low-voltage residential users. For user accounts with a balance below 10,000 yuan, the system uses SMS gateway protocol data payload to control network communication bandwidth costs; for user accounts with a balance of 10,000 yuan or more, the system forcibly starts voice session initialization protocol signaling flow to strengthen the physical reach of the collection process. The various control condition settings are constrained by objective physical attributes and business quantification benchmarks to jointly constrain the execution path branches of the collection data flow at the underlying level.

[0031] As described above, different collection strategy data can be generated based on different outstanding amounts, which can meet the collection needs in different scenarios.

[0032] In one embodiment of the present invention, step 106, generating collection task data corresponding to the target unpaid user and updating the collection list to be executed, includes: allocating data structure nodes connected end-to-end in system memory; constructing a lock-free circular buffer queue based on the data structure nodes; calling the compare and exchange atomic instruction to control the scheduling thread to compete for an idle buffer node in the circular buffer queue; after obtaining the idle buffer node, writing the collection task data into the idle buffer node, binding the collection task data to the target unpaid user, and executing a memory barrier instruction to synchronize the collection task data to the allocated consumption thread.

[0033] As described above, by constructing a circular buffer queue and calling the comparison and exchange atomic instruction to obtain a free buffer node, the payment reminder task data can be written to the system cache space without locks. The underlying instruction-level atomic operation, combined with the data structure nodes connected end to end, completely eliminates the risk of row-level lock blocking on the core business database caused by multi-threaded concurrent read and write operations from the physical memory stack level.

[0034] In a further embodiment, before invoking the Compare and Exchange atomic instruction to control the scheduling thread to compete for an idle buffer node in the circular buffer queue, the method further includes: obtaining the current system timestamp and querying date data information to obtain holiday time periods; comparing the current system timestamp with the holiday time periods; when it is determined that the current system timestamp is within the holiday time period, intercepting the write request to write the payment reminder task data to the circular buffer queue; constructing a time wheel data structure including a day-level wheel and an hour-level wheel in the system memory; obtaining the memory address pointer corresponding to the payment reminder task data, and invoking the Compare and Exchange atomic instruction to attach the memory address pointer to the time slot in the time wheel data structure; advancing the wheel pointer of the time wheel data structure according to the system clock interrupt signal, and reading the payment reminder task data according to the set time nodes.

[0035] During non-holiday periods, concurrent threads call the Compare and Exchange atomic instruction to control the scheduling thread to compete for free buffer nodes in the circular buffer queue in kernel mode. After acquiring control of the free buffer node, the encapsulated payment reminder task data is written to the free buffer node and a binding relationship is established with the user account number. The underlying soft interrupt is called to execute the memory barrier instruction to refresh the processor cache layer, and the memory visibility status of the payment reminder task data is unidirectionally synchronized with the consumer thread allocated in the background.

[0036] Simultaneously, after writing the payment reminder task data into the idle buffer node, the process further includes: allocating a memory mapping area in the kernel address space and writing a byte stream including a preset promotional text into the memory mapping area; extracting the payment reminder task data; calling memory access hardware instructions to concatenate the payment reminder task data with the byte stream including the preset promotional text in the memory mapping area within the network protocol stack according to the descriptor linked list, generating a network data packet; and sending the network data packet to the communication node.

[0037] In one embodiment of the present invention, step 106, generating collection task data corresponding to the target unpaid user and updating the collection list to be executed, includes: using an allocated read thread to pull the collection task data from the system cache space; calculating the hash value corresponding to the target unpaid user based on the collection task data and assembling the collection task data into a merged update structure; sorting the merged update structure by buckets and generating a merged data update log according to the bucketed sorting order; and using a sequential append write mode to overwrite the collection status field corresponding to the target unpaid user in the collection list to be executed.

[0038] Specifically: The input data for the spatial bucket sorting algorithm is set as a merge-update structure, which encapsulates the memory physical offset identifier corresponding to the payment reminder task data and the system timestamp feature sequence. The internal logic of the spatial bucket sorting algorithm combined with the electricity payment reminder scenario is specifically set as follows: Based on the time span of the system timestamp feature sequence, the processor divides multiple continuous fixed-length physical address intervals in physical memory to form data bucket entities. The memory mapping rule of the data bucket entities is as follows: the system timestamp feature sequence is moduloed according to a preset time slice constant, and the merge-update structure is transferred to the data bucket entity in the corresponding physical address space based on the integer physical index value output by the modulo operation. Within a single data bucket entity, the pointer shift hardware instruction built into the microprocessor chip is used to perform physical linear sorting according to the scalar size of the memory physical offset identifier. The output data of the spatial bucket sorting algorithm is set as the data update log after the update sequence is arranged. According to the specified order of the data update log, the pre-reserved payment reminder status field in the payment reminder list to be executed in the external storage is overwritten and updated using the disk sequential append write mode.

[0039] As described above, the spatial bucket sorting algorithm ensures that the data arrangement order within the data update log is vector-consistent with the optimal write addressing physical direction of the external mechanical disk, thus thoroughly establishing the inherent objective data correlation between the time characteristics of the merged update structure and the physical write order of the disk.

[0040] In one embodiment of the present invention, generating collection task data corresponding to the target unpaid user and updating the collection list to be executed includes: receiving execution result data of the collection task data from a communication node callback; constructing a Bloom filter data structure with a mapping relationship to the collection result table in a data storage space (e.g., in a high-speed data storage space area); inputting the execution result data into the Bloom filter data structure for deduplication; if it is determined that the execution result data is not duplicated, calling a bitmask update hardware instruction to update the information corresponding to the target unpaid user in the collection result table according to the execution result data (i.e., writing it into a specific address element of the reach status bit corresponding to the user's account number in the virtual memory address space), that is, writing the execution result data bit by bit into the reach status bit corresponding to the user's account number in the virtual memory address space.

[0041] Specifically: In this embodiment, the Bloom filter data structure matrix executes the hash function deduplication logic. The input data of the hash function deduplication logic is strictly set to the execution result data of the external communication node callback. The execution result data includes the underlying hash value of the user account number and the reach status feedback code representing the physical feedback result of the communication.

[0042] The initialization state settings of the algorithm logic are as follows: a bit array occupying a continuous fixed byte length is statically allocated in the high-speed data storage space, and multiple independent non-encryption hash functions are configured simultaneously.

[0043] The inherent connection between the hash function deduplication judgment logic and the deduplication scenario of the payment reminder result log is specifically constructed as follows: The instruction execution unit performs binary physical concatenation on the extracted user account number's underlying hash value and the reach status feedback code in the microprocessor register to generate a single base input sequence. Multiple unencrypted hash functions perform underlying hash calculations on the base input sequence in parallel, outputting multiple discrete integer physical addressing indices. Based on the output discrete integer physical addressing indices, the processor uniformly sets the binary bits at the corresponding physical offset positions in the bit array to a high level. The output data of the hash function deduplication judgment logic is set as a hash duplicate collision judgment status flag. In the objective judgment stage, the output flag will generate an objective duplicate logic high-level feedback if and only if all the address bits in the bit array pointed to by the integer physical addressing indices output by the multiple unencrypted hash functions have been judged to be in a set state; otherwise, the output flag will generate a business duplicate logic low-level feedback, establishing an objective physical and mathematical operation correlation between the execution result data feature sequence and the status bits of the underlying memory bitmap.

[0044] The construction of the Bloom filter data structure matrix model includes: pre-allocating a one-dimensional bit array with a fixed byte span in memory; the operating system kernel assigning all binary bits within the one-dimensional bit array a physical low-level value; integrating a non-encrypted hash mapping function within the Bloom filter data structure matrix model; the data input layer receiving the extracted hash value associated with the user ID; the non-encrypted hash mapping function receiving the hash value associated with the user ID as the original independent variable for discretization operations; and the non-encrypted hash mapping function performing hash calculation on the hash value associated with the user ID. The hash calculation outputs independent integer addressable indices, and the hash calculation formula is defined as:

[0045] In the calculation formula, Represents an independent integer addressing subscript, which indicates the exact physical offset bit within a one-dimensional bit array; Represents the underlying hash mapping function. The auxiliary hash function represents the basic hash function. Together with the auxiliary hash function, the basic hash function can convert a data stream of arbitrary length into an integer result of fixed length. The hash value associated with the user account number is represented as a binary bit stream sequence extracted from the execution result data. This represents the incrementing variable for the hash function execution rounds. The incrementing variable controls the specific number of loop probes in the hash calculation. The total length of the one-dimensional bit array is a variable that defines the legal boundaries of the physical memory address. mod represents the modulo operation.

[0046] Assuming the hash value associated with the user ID is resolved to the decimal integer 10025, the system calls the basic hash mapping function to output the integer 500, and calls the auxiliary hash mapping function to output the integer 120; simultaneously, the total length variable of the one-dimensional bit array is statically set to 8192. When the increment variable for the hash function execution round is set to 1, the arithmetic logic unit calculates an independent integer addressing index of 620; when the increment variable for the hash function execution round is set to 2, the arithmetic logic unit calculates an independent integer addressing index of 740. The Bloom filter data structure matrix model performs a logic high-level set operation based on the values ​​620 and 740, respectively, at the corresponding physical offsets within the one-dimensional bit array, thus solidifying the physical state of the execution result data storage path. When subsequent execution result data enters the Bloom filter data structure matrix model, the system compares the storage physical bit state corresponding to the output integer addressing index and objectively determines whether the subsequent execution result data belongs to the new generation incremental original data based on the storage physical bit state.

[0047] As described above, Bloom filter-based data structures can avoid writing duplicate data into memory, thereby ensuring data accuracy.

[0048] In one embodiment of the present invention, the method further includes: allocating concurrent threads to read the timestamps of the SMS channel records in the fixed-length data structure, and allocating an incrementing global generation version number to the concurrent threads through a generation memory reclamation mechanism; determining whether the pending payment reminder list has been updated, and if so, obtaining a memory data block containing the target unpaid user data, and storing the memory data block in a retired memory queue corresponding to the global generation version number; monitoring the current thread generation version number of the concurrent threads; and if the current thread generation version number of the concurrent threads is greater than the global generation version number, triggering the allocated reclamation thread to release the memory data block in the retired memory queue.

[0049] As described above, the underlying memory manager employs a generational memory reclamation mechanism, dynamically allocating monotonically increasing global generation version numbers to concurrent threads executing tasks in parallel. The reclamation thread activated at the underlying level performs erasure operations based on the scalar relationship between the current thread's generation version number and the global generation version number, precisely releasing abandoned memory data blocks in the retired memory queue. The physical targeted release mechanism for memory data blocks cuts off the residency cycle of useless data, significantly reducing the overhead of frequent memory page replacements caused by data retrieval processes.

[0050] This invention provides a specific application scenario to illustrate the above steps: Step 1: The business application server retrieves the pending payment reminder list and payment reminder result table from the physical storage on external memory. The pending payment reminder list includes not only the user account number containing the numerical code 10012345, but also a settlement flag indicating the bill settlement progress and a payment reminder status field representing the task flow node. The synchronously loaded payment reminder result table includes SMS and voice channel records strongly bound to the corresponding user account number. Furthermore, the SMS and voice channel records independently include an underlying millisecond-level timestamp and a binary reach status bit indicating the terminal response status. This leads to step 101.

[0051] Step 2: The business application server traverses the memory matrix structure to extract user IDs whose settlement status is marked as unpaid, using them as the query benchmark data. Based on the extracted query benchmark data, a memory-level mapping relationship is established within the virtual memory address space allocated by the operating system. Utilizing this underlying mapping relationship, the server penetrates the external storage scheduling barrier to extract the SMS and voice channel records corresponding to the query benchmark data. These records are then arranged adjacently in the physical memory pages and merged into a fixed-length data structure with a total space occupation of 128 bytes. The underlying driver calls a hardware probe to obtain the physical motherboard microprocessor chip cache line length parameter. The fixed-length data structure is aligned with the obtained 64-byte microprocessor chip cache line length parameter, ensuring that the internal layout offset boundary precisely coincides with the physical hardware cache boundary. The aligned fixed-length data structure is then loaded into the data cache layer and resides there awaiting concurrent retrieval. This is step 102.

[0052] Step 3: The system kernel obtains the system time through the motherboard's high-frequency oscillator. The underlying scheduler allocates concurrent threads to read the timestamps of SMS channel records in the low-order address space of the fixed-length data structure. The microprocessor chip calls the arithmetic logic unit to perform numerical subtraction operations on the time series, calculating the difference between the system time data and the timestamps of the SMS channel records to obtain the first time difference. This is step 103.

[0053] Step 4: When the hardware comparator built into the microprocessor chip determines that the first time difference meets the set boundary condition of being greater than or equal to the preset number of days (10 days), it triggers the underlying memory pointer cross-level addressing control mechanism. The instruction controller adds the 64-byte length of the statically occupied SMS channel record to the current memory address of the concurrent thread's read pointer, which is the decimal base address value (e.g., 1048576). This generates a target memory address of 1048640 (1048576 + 64 = 1048640). This target memory address directly controls the concurrent thread's read pointer to undergo a physical addressing offset equal to the byte length of the SMS channel record within the virtual memory address space containing the fixed-length data structure. This allows the read pointer to directly jump across the SMS channel record space segment in the non-target read stage to the target memory address. After the space jump, the target memory address is precisely aligned with the starting address of the voice channel record located in the data cache layer. This executes the step 104, which involves obtaining the timestamp of the voice channel record.

[0054] Step 5: Based on the addressing pointer completed by the instruction placement, the processor concurrently reads the timestamp of the voice channel record located at the target memory address. The arithmetic logic unit executes a subtraction instruction again to calculate the difference between the system time and the timestamp of the voice channel record, obtaining the second time difference. That is, the step of calculating the second time difference between the timestamp of the voice channel record and the system time in step 104 is executed.

[0055] Step 6: When the hardware comparison circuit determines that the second time difference fully meets the threshold coverage range defined by the preset number of days variable, the data processing pipeline enters the aggregation judgment process to extract the arrival status bits of the SMS channel record with a binary value of 1 and the voice channel record with a binary value of 1. The extracted independent arrival status bits are then concatenated and assembled according to the physical time sequence of the dual-end communication triggers, ultimately forming a continuous mask word occupying a fixed register width. The system's underlying kernel calls the Hamming weight calculation hardware instruction developed for a specific calculator to load the continuous mask word, represented as a binary combination sequence 11, into a designated high-speed storage space in parallel. Relying on the underlying logic gate addition tree circuit, the Hamming weight calculation hardware instruction calculates the total number of non-zero data bits in the continuous mask word in parallel at once, directly obtaining a summation result of an objective value of 2. The total number of non-zero data bits is then absolutely assigned to the communication arrival count, representing the actual contact attempt frequency. This is step 105.

[0056] Step 7: When the register comparison module determines that the number of communication contacts has reached a preset threshold of 2 (the system's preset upper limit), it initiates a transmission control request to the distributed data storage node to obtain the outstanding amount data for the target user account. After successfully parsing and obtaining the outstanding amount data of 50,000, the system compares the outstanding amount data with the preset amount threshold of 10,000 (the system's security limit). Based on the objectively generated correlation state of 50,000 > 10,000, it determines that the outstanding amount data is greater than or equal to the preset amount threshold. Then, it statically allocates second policy data, including the voice session initialization protocol signaling stream, to the user account. Based on the selected second policy data, it performs a serialization operation to encapsulate and generate structured collection task data, and updates the collection task data to be executed collection list. That is, it executes step 106.

[0057] Please refer to Figure 2 The present invention also provides a global verification system for intelligent payment collection in an electricity marketing system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the various steps of the global verification method for intelligent payment collection in an electricity marketing system as described above.

[0058] This embodiment constructs a comparative experimental example, deploying an existing relational database and a global verification system for intelligent payment collection in the power marketing system, respectively, and inputting 10,000,000 simulated payment collection test data into each. In the data retrieval stage, the existing relational database uses cross-table cascading comparison logic to perform data retrieval, while the global verification system for intelligent payment collection in the power marketing system uses a physical memory pointer addressing jump mechanism. Simultaneously, a performance monitoring hardware probe is used to record the CPU load parameters and memory replacement frequency parameters in real time. Test logs show that the existing cross-table cascading comparison logic causes the CPU's average load to reach a peak of 85%, resulting in a motherboard memory replacement frequency parameter as high as 5000 times per second. In contrast, the global verification system for intelligent payment collection in the power marketing system uses a physical memory pointer addressing jump mechanism to control the CPU's average load to a steady state of 25%, and significantly reduces the motherboard memory replacement frequency parameter to 100 times per second. Experimental test data objectively proves that the physical memory pointer addressing and jumping mechanism significantly reduces the physical consumption of computing resources at the hardware level, and completely solves the bottleneck problem of high-latency computing operation in high-concurrency scenarios.

[0059] In summary, the intelligent global verification method and system for electricity marketing systems provided by this invention extracts SMS and voice channel records corresponding to the query baseline data through the business application server, executes physical memory adjacency arrangement to construct a fixed-length data structure, and performs aligned loading based on the microprocessor chip cache row length parameter; it also utilizes a memory pointer cross-level addressing control mechanism to achieve cross-space jump addressing, calls Hamming weight calculation hardware instructions to calculate consecutive mask words in parallel to obtain the number of communication contacts; it writes the payment reminder task data into a ring buffer queue without locks by comparing and exchanging atomic instructions, and performs delayed scheduling in conjunction with a time wheel data structure. By utilizing hardware-level bitwise operations and memory addressing optimization technology, it eliminates the seek overhead and row-level lock blocking caused by existing cross-table cascading comparisons, improving the verification and processing efficiency of payment reminder data in high-concurrency scenarios. That is, through memory-level filtering technology, pointer addressing jump technology, and asynchronous caching mechanism, it jointly solves the problems of high system latency and concurrency bottlenecks in the collaborative verification of massive heterogeneous payment reminder logs.

[0060] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A global verification method for intelligent payment collection in an electricity marketing system, characterized in that, include: Obtain the list of outstanding payment reminders and the payment reminder results table; Iterate through the list of unpaid users in the pending collection list. For each target unpaid user, extract the SMS channel record and voice channel record corresponding to the target unpaid user from the collection result table, and merge the SMS channel record and the voice channel record into a fixed-length data structure in memory by arranging them adjacently. Obtain the current system time and calculate the first time difference between the timestamp recorded by the SMS channel and the system time; If the first time difference satisfies the first time interval condition, then read and calculate the second time difference between the timestamp recorded by the voice channel and the system time; If the second time difference meets the second time interval condition, then the number of communications recorded in the SMS channel and the voice channel is counted. If the number of communications reaches the threshold, then collection task data corresponding to the target unpaid user is generated and the collection task data is used to update the collection list to be executed.

2. The intelligent payment reminder global verification method for an electricity marketing system according to claim 1, characterized in that, The step of reading and calculating the second time difference between the timestamp of the voice channel record and the system time includes: The read pointer of the concurrent thread is offset by a number of bytes equal to the length of the SMS channel record within a virtual memory address space that contains the fixed-length data structure, and then jumps to the target memory address to obtain the timestamp of the voice channel record. The target memory address is the starting address of the voice channel record.

3. The intelligent payment reminder global verification method for an electricity marketing system according to claim 1, characterized in that, The statistics on the number of communications recorded via SMS and voice channels include: The arrival status bits recorded by the SMS channel and the arrival status bits recorded by the voice channel in the fixed-length data structure are concatenated according to the order of communication triggering to generate a continuous mask word. The number of communications is obtained by performing a summation calculation on the consecutive mask words.

4. The intelligent payment reminder global verification method for an electricity marketing system according to claim 3, characterized in that, The summation calculation of the consecutive mask words includes: The Hamming weight calculation hardware instructions are invoked to load the continuous mask words into the specified storage space; The Hamming weight calculation hardware instructions calculate the total number of non-zero data bits in the continuous mask word in the storage space, and use the total number of non-zero data bits as the number of communications.

5. The intelligent payment reminder global verification method for an electricity marketing system according to claim 1, characterized in that, The step of generating collection task data corresponding to the target unpaid users and updating the pending collection list includes: Obtain the outstanding amount data corresponding to the target unpaid user; Determine whether the outstanding amount is less than the amount threshold. If yes, generate first policy data including SMS gateway protocol data payload; otherwise, generate second policy data including voice session initialization protocol. The collection task data is generated by encapsulating the first strategy data or the second strategy data.

6. The intelligent payment reminder global verification method for an electricity marketing system according to claim 1, characterized in that, The step of generating collection task data corresponding to the target unpaid users and updating the pending collection list includes: Allocate data structure nodes that are connected end to end in the system memory, and construct a circular buffer queue based on the data structure nodes; The comparison and swap atomic instruction is invoked to control the scheduling thread to compete for free buffer nodes in the circular buffer queue; After obtaining the idle buffer node, the collection task data is written to the idle buffer node, the collection task data is bound to the target unpaid user, and a memory barrier instruction is executed to synchronize the collection task data to the allocated consumption thread.

7. The intelligent payment reminder global verification method for an electricity marketing system according to claim 1, characterized in that, The step of generating collection task data corresponding to the target unpaid users and updating the pending collection list includes: Based on the collection task data, calculate the hash value corresponding to the target unpaid user, and assemble the collection task data into a merged update structure; The merged update structure is sorted into buckets, and the merged data update log is generated according to the sorted order. Based on the data update log, the sequential append write mode is used to overwrite the collection status field corresponding to the target unpaid user in the collection collection list.

8. The intelligent payment reminder global verification method for an electricity marketing system according to claim 1, characterized in that, The step of generating collection task data corresponding to the target unpaid users and updating the pending collection list includes: The execution result data of the payment reminder task data received from the communication node callback; Construct a Bloom filter data structure in the data storage space that has a mapping relationship with the payment reminder result table; The execution result data is input into the Bloom filter data structure for deduplication. If it is determined that the execution result data is not duplicated, the bitmask update hardware instruction is invoked to update the information of the target unpaid user in the collection result table according to the execution result data.

9. The intelligent payment reminder global verification method for an electricity marketing system according to claim 1, characterized in that, Also includes: Concurrent threads are allocated to read the timestamps of the SMS channel records in the fixed-length data structure, and an incrementing global generation version number is allocated to the concurrent threads through a generation memory reclamation mechanism; Determine whether the pending payment reminder list has been updated. If so, obtain the memory data block containing the target unpaid user data and store the memory data block in the retired memory queue corresponding to the global generation version number. Monitor the current thread generation version number of the concurrent thread; If the current generation version number of all concurrent threads is greater than the global generation version number, then the allocated recycling thread is triggered to release the memory data block in the retired memory queue.

10. A global verification system for intelligent payment collection in an electricity marketing system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements each step of the intelligent payment collection global verification method for an electricity marketing system as described in any one of claims 1 to 9.

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