Graphics processor, data processing method and electronic device

Abstract

The application provides a graphics processor, a data processing method and an electronic device. The graphics processor comprises at least two levels of translation lookaside buffers, each level of translation lookaside buffer comprises a receiving unit and a data storage unit, the target translation lookaside buffer further comprises a selection unit, the receiving unit of the target translation lookaside buffer is configured to, in response to receiving a first page table entry, send a first target page table entry to the data storage unit of the target translation lookaside buffer and the selection unit of the target translation lookaside buffer, the first target page table entry is determined based on the first page table entry; the data storage unit of the target translation lookaside buffer is further configured to perform an update operation based on the first target page table entry to backfill the first target page table entry into the data storage unit of the target translation lookaside buffer; and the selection unit of the target translation lookaside buffer is configured to return the first target page table entry to the upper level translation lookaside buffer of the target translation lookaside buffer.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of computer technology, and in particular to a graphics processor, a data processing method, and an electronic device. Background Technology

[0002] A Graphics Processing Unit (GPU) is a specialized computing hardware component used to perform graphics processing tasks. GPUs typically possess parallel computing capabilities and high-throughput memory access. They are widely used in electronic devices such as computers, servers, and mobile devices to accelerate tasks such as image rendering, video decoding, and artificial intelligence inference.

[0003] In related technologies, GPUs typically employ two or more levels of Translation Lookaside Buffers (TLBs). When a TLB at a certain level receives a Page Table Entry (PTE) from downstream, it usually first refills the PTE into the data storage unit within that TLB level, then rereads the PTE from the data storage unit within that TLB level, and finally returns the read PTE to upstream. This process suffers from high latency, port resource conflicts, complex and redundant control logic, and low throughput. Summary of the Invention

[0004] This application provides a graphics processor, a data processing method, and an electronic device.

[0005] The technical solution of this application embodiment is implemented as follows: This application provides a graphics processor including at least two levels of conversion backup buffers. Each level of conversion backup buffer includes a receiving unit and a data storage unit. A target conversion backup buffer further includes a selection unit. The target conversion backup buffer is one of the other levels of conversion backup buffers besides the first level. The data storage unit of the target translation backup buffer is used to store at least one page table entry; The receiving unit of the target translation backup buffer is configured to, in response to receiving the first page table entry, send the first target page table entry to the data storage unit and the selection unit of the target translation backup buffer; wherein, the first page table entry is sent by the next-level translation backup buffer of the target translation backup buffer or by the memory management unit of the graphics processor, and the first target page table entry is determined based on the first page table entry. The data storage unit of the target translation backup buffer is also used to perform an update operation based on the first target page table entry, so as to fill the first target page table entry back into the data storage unit of the target translation backup buffer; The target translation backup buffer selection unit is used to return the first target page table entry to the previous level translation backup buffer of the target translation backup buffer.

[0006] This application provides a data processing method applied to a target conversion backup buffer of a graphics processor. The graphics processor includes at least two levels of conversion backup buffers. Each level of conversion backup buffer includes a receiving unit and a data storage unit. The target conversion backup buffer further includes a selection unit. The target conversion backup buffer is one of the other levels of conversion backup buffers besides the first level. The data processing method includes: The first page entry is received by the receiving unit of the target translation backup buffer; wherein the first page entry is sent by the next level translation backup buffer of the target translation backup buffer or by the memory management unit of the graphics processor. The data storage unit of the target translation backup buffer performs an update operation based on the first target page table entry to populate the first target page table entry back into the data storage unit of the target translation backup buffer; wherein, the first target page table entry is determined based on the first page table entry; The first target page table entry is returned to the previous level of the target translation backup buffer through the selection unit of the target translation backup buffer.

[0007] This application provides an electronic device including the aforementioned graphics processor.

[0008] The embodiments of this application have the following beneficial effects: By introducing a selection unit and setting a fast return channel in the target conversion backup buffer, the receiving unit, upon receiving the first page entry, can not only write it to the data storage unit but also simultaneously return it directly to the previous-level conversion backup buffer. This decouples the data update and PTE return actions, achieving the goal of instant PTE return. Compared to related technologies that require writing before reading, this solution offers several advantages: First, since the PTE return does not require waiting for PTE writing and reading, it saves two access cycles, significantly reducing refill latency. Second, because this solution only occupies the write port during refilling, the read port can continue to receive and process other requests, reducing the possibility of queuing and cascading blocking, significantly alleviating port resource conflicts, and thus improving overall throughput. Finally, the fast PTE return channel reduces the complexity and redundancy of the control logic. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the first component structure of a graphics processor provided in an embodiment of this application; Figure 2 This is a schematic diagram illustrating the implementation flow of a data processing method provided in an embodiment of this application; Figure 3 This is a schematic diagram of the second component structure of a graphics processor provided in an embodiment of this application; Figure 4 This is a schematic diagram of the composition structure of a target conversion backup buffer provided in an embodiment of this application.

[0010] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0012] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0013] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0014] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0015] The technical solutions in the embodiments of this application will now be clearly and completely described with reference to the accompanying drawings.

[0016] Figure 1 This is a schematic diagram of the first component structure of a graphics processor provided in an embodiment of this application, as shown below. Figure 1As shown, the graphics processor 100 includes at least two levels of conversion backup buffers 10. Each level of conversion backup buffer 10 includes a receiving unit 11 and a data storage unit 12. The target conversion backup buffer further includes a selection unit 13. The target conversion backup buffer is any of the other levels of conversion backup buffers besides the first level. The data storage unit 12 of the target conversion backup buffer is used to store at least one page table entry; The receiving unit 11 of the target translation backup buffer is used to send the first target page table entry to the data storage unit and the selection unit of the target translation backup buffer in response to receiving the first page table entry; wherein the first page table entry is sent by the next-level translation backup buffer of the target translation backup buffer or by the memory management unit of the graphics processor, and the first target page table entry is determined based on the first page table entry. The data storage unit 12 of the target translation backup buffer is also used to perform an update operation based on the first target page table entry, so as to fill the first target page table entry back into the data storage unit of the target translation backup buffer; The selection unit 13 of the target translation backup buffer is used to return the first target page table entry to the previous level translation backup buffer of the target translation backup buffer.

[0017] Here, the GPU may include two or more levels of TLBs. TLBs are used to accelerate the translation process from Virtual Address (VA) to Physical Address (PA). In other words, the TLB acts as a translator between VA and PA, allowing the GPU to access memory quickly by caching the mapping relationship between VA and PA.

[0018] The target TLB is any TLB that follows the first-level conversion backup buffer (TLB_L1). There can be at least one target TLB.

[0019] In some implementations, when the GPU includes two levels of TLBs, namely TLB_L1 and TLB_L2 (second-level translation back buffer), then the target TLB is only one, i.e., the target TLB is TLB_L2. In practice, TLB_L2 can be an intermediate cache layer with a larger capacity than TLB_L1 but a slightly slower access speed.

[0020] In some implementations, when the GPU includes N (greater than 2) levels of TLBs, the number of target TLBs can be one, two, ..., N-1. That is, at least one TLB from level 2 to (N-1) can be used as the target TLB. For example, the target TLB includes TLB_L2 and subsequent TLBs, where subsequent TLBs can refer to all TLBs higher than L2 (such as TLB_L3, TLB_L4, etc.). For instance, in a four-level TLB structure (i.e., TLB_L1~TLB_L4), the target TLB may include at least one of TLB_L2, TLB_L3, and TLB_L4. TLB_L2, TLB_L3, and TLB_L4 together constitute a multi-level caching system to meet the high bandwidth requirements of complex computing scenarios.

[0021] In some implementations, other TLBs in the GPU besides TLB_L1 typically have larger capacity and lower access speeds, and they can supplement TLB_L1 to reduce latency caused by misses.

[0022] The data storage unit can be any suitable hardware structure for temporarily caching PTEs, supporting fast read and write operations. For example, the data storage unit 12 can be a storage array composed of a single-port Static Random Access Memory (SRAM). Since a single-port SRAM can only perform one read or write operation at a time, the existing refill process must complete the write operation before performing the read operation, resulting in two access cycles required to complete the refill process. The data storage unit is responsible for storing each PTE for subsequent querying. It is understood that the data storage units of each TLB have the same function. In implementation, for non-target TLBs, such as the first-level TLB, the data storage unit can directly return the internally stored PTEs to the upstream; while for the target TLB, the data storage unit sends the internally stored PTEs to the selection unit, that is, the data storage unit and the selection unit can be directly connected. In some implementations, the data storage unit can use an asynchronous write method, so that PTEs can be updated without blocking other requests. This method not only improves the overall efficiency of the TLB, but also reduces resource conflicts and latency problems caused by serial access. In some implementations, the data storage unit can simultaneously perform operations of writing new PTEs and reading other PTEs, thereby achieving concurrent processing.

[0023] In some implementations, each TLB level further includes a tag storage unit for storing at least one tag, with each tag corresponding to a PTE. This tag storage unit can be any suitable hardware unit for caching the tag portion of the virtual address; for example, it can be a storage array composed of SRAM. It is understood that the tag storage unit works in conjunction with the data storage unit to complete the address translation process. It is also understood that the tag storage units in each TLB have the same function.

[0024] The receiving unit is an internal hardware logic circuit or a combined hardware and software unit within the TLB. Its main responsibility is to receive PTEs (Page Entries) sent from downstream sources (such as the MMU (Memory Management Unit), the next-level TLB, etc.) and transmit the PTEs (e.g., the received PTE, or the PTE after data processing (e.g., page table compression, encoding conversion, etc.)) to other units (such as data storage units, selection units, etc.) for subsequent processing or storage. Understandably, for receiving units outside the target TLB, the PTE can be transmitted to the data storage unit. However, for receiving units of the target TLB, in addition to transmitting the PTE to the data storage unit, it is also necessary to transmit the PTE to the selection unit. In other words, the receiving unit of the target TLB has parallel processing capabilities, which can immediately trigger two parallel operations upon receiving the PTE: first, write the PTE to the data storage unit, and second, return the PTE directly through the selection unit. This parallel processing method makes PTE processing more efficient, and achieves the goal of decoupling PTE writing and PTE return without interference between the writing of the data storage unit and the return operation of the selection unit. This avoids the delay problem caused by serial processing (i.e., write first, then read, and finally return) in related technologies.

[0025] The selection unit can be any suitable hardware unit capable of controlling data flow. For example, multiplexers and multiplexers (MLs) are used to send PTEs sent by the receiving unit via a fast channel or PTEs sent by the data storage unit via a normal channel to the next-level TLB. The fast channel, also known as a dedicated path or fast route, is a dedicated transmission link between the receiving unit and the selection unit. In other words, the fast channel can be a direct hardware connection, independent of the read / write ports of the data storage unit and not limited by them. This allows the PTE to be returned to the next-level TLB in a timely manner, significantly reducing latency and improving throughput. The normal channel, also known as the hit channel, is the return channel where a PTE is hit in the target TLB's data storage unit.

[0026] In some implementations, the selection unit can decide whether to enable the fast channel based on the current state of the target TLB (i.e., whether it is in a refill state), where the current state indicates whether the target TLB is in a refill state. If the target TLB is in a refill state, the fast channel is enabled; otherwise, the normal channel is used. This implementation results in a shorter response time for the target TLB without affecting the processing efficiency of other requests.

[0027] In some implementations, the selection unit can select the optimal channel from multiple possible data channels based on current operational needs, such as switching between the hit channel and the fast channel, to improve flexibility and response speed.

[0028] It is understandable that each TLB includes a data storage unit, a tag storage unit, and a receiving unit, while the target TLB also includes a selection unit. Thus, by introducing a selection unit and a fast channel into the target TLB, concurrent updates and returns of the PTE are achieved. This effectively reduces refill latency for the target TLB and resolves issues caused by serial access and resource conflicts in related schemes. Furthermore, since the fast channel bypasses the read operation of the data storage unit, redundant data paths are eliminated, further improving processor performance.

[0029] The Page Frame Number (PTE) (including the first PTE and others mentioned below) is a key data structure for mapping VAs to PAs. PTEs can include, but are not limited to, physical page frame numbers (PFNs), control information (such as access permissions (read / write / execute), cache attributes, etc.). PTEs act as a bridge in memory management, ensuring that the corresponding location in the PA can be correctly located. For example, when a GPU performs computational tasks, it needs to frequently access different VAs; therefore, efficient PTE processing is crucial to overall performance.

[0030] The first PTE is a PTE sent by the downstream device to the target TLB. It can be understood that the downstream device can be an MMU or a next-level TLB. In implementation, the next-level TLB of the target TLB can be another target TLB or a non-target TLB.

[0031] The first target PTE can be either the first PTE itself or a PTE obtained after data processing (such as page table compression, encoding conversion, etc.). In implementation, the receiving unit of the target TLB can forward the processed first PTE to the target TLB's data storage unit and selection unit, or it can directly forward the first PTE to these units. In practice, the receiving unit of the target TLB functions as a data entry point, responsible for receiving the first PTE sent from downstream and passing it, or the processed first PTE, to subsequent units. In some implementations, to improve processing efficiency, the target TLB's selection unit can directly forward the received first PTE to the target TLB's data storage unit.

[0032] An update operation refers to the process of writing the received PTE into the data storage unit, also known as PTE backfilling. It is understood that the object of the update operation is the data storage unit. In some implementations, during the update operation, the received PTE can be processed first, and then the processed PTE can be stored in the data storage unit. It is understood that if the receiving unit has already processed the PTE, the data storage unit can directly store the PTE or process the received PTE again; if the receiving unit has not processed the PTE, the data storage unit can process the received PTE before storing it. In some implementations, it can be assumed that the receiving unit does not process the received PTE, in which case the data storage unit needs to process the received PTE before storing it. In some implementations, if the receiving unit may process the PTE, then any suitable method can be used to instruct the receiving unit whether to process the PTE, allowing the data storage unit to decide whether to process the PTE before storing it. For example, if the data storage unit obtains the identification information of the PTE, and the identification information indicates that the receiving unit has not processed the data of the PTE, then the data storage unit needs to process the data of the PTE before storing it; if the identification information indicates that the receiving unit has processed the data of the PTE, then the data storage unit can directly store the PTE.

[0033] In some implementations, the tag corresponding to the first target PTE can be written to the tag storage unit before writing the first target PTE back to the data storage unit; alternatively, the tag corresponding to the first target PTE can be written to the tag storage unit at the same time as writing the first target PTE back to the data storage unit; or the tag corresponding to the first target PTE can be written to the tag storage unit after the first target PTE has been written back to the data storage unit. This ensures that each query can quickly hit the required first target PTE.

[0034] In practice, the entire target TLB workflow is a highly coordinated process. First, after receiving the first PTE, the receiving unit distributes it to the data storage unit and the selection unit. Then, the data storage unit writes the first target PTE, while the selection unit sends it back to the previous TLB via a fast channel. Finally, the tag storage unit assists in VA matching by synchronously storing the tag corresponding to the first target PTE. Through the coordinated work of these steps, the target TLB achieves low-latency, high-concurrency PTE processing capabilities, significantly improving the overall performance of the GPU.

[0035] In some implementations, the locations of the individual TLBs within the GPU can differ or be partially the same. For example, when the GPU includes TLB_L1 and TLB_L2, TLB_L1 can be located within the Streaming Multiprocessor (SM), while TLB_L2 can be located outside the SM. As another example, when the GPU includes TLB_L1, TLB_L2, and TLB_L3, TLB_L1 can be located within the Streaming Multiprocessor (SM), while TLB_L2 and TLB_L3 can be located outside the SM.

[0036] In this embodiment, by introducing a selection unit and setting a fast return channel in the target conversion backup buffer, the receiving unit, after receiving the first page entry, can not only write it to the data storage unit but also simultaneously return it directly to the previous-level conversion backup buffer. This decouples the data update and PTE return actions, achieving the goal of immediate PTE return. Compared to related technologies that require writing before reading, this solution saves two access cycles and significantly reduces refill latency because the PTE return does not require waiting for PTE writing and reading. Secondly, since this solution only occupies the write port during refilling, the read port can continue to receive and process other requests, reducing the possibility of queuing and cascading blocking, significantly alleviating port resource conflicts, and thus improving overall throughput. Finally, the fast return channel for PTE reduces the complexity and redundancy of the control logic.

[0037] In some implementations, the graphics processor 100 includes a streaming multiprocessor, a first-level translation backup buffer located within the streaming multiprocessor, and subsequent level translation backup buffers located outside the streaming multiprocessor and the graphics processor's memory management unit.

[0038] Here, the SM (Memory Module) is the core computing unit of the GPU, responsible for executing parallel computing tasks. A GPU consists of at least two SMs; that is, the GPU core (i.e., GPU_CORE) can include one SM. An SM can contain multiple processing cores, register files, shared memory, and other resources, enabling efficient handling of large-scale data parallel computations. In implementation, by deploying TLB_L1 within the SM, it is used only by the current SM. That is, TLB_L1 directly serves the threads and computational tasks within the SM, reducing access latency and improving address translation efficiency. In practice, TLB_L1 exhibits lower access latency and a higher hit rate, thereby accelerating thread access to memory.

[0039] The other TLB levels after TLB_L1 are deployed between the SM and MMU, meaning they are located outside the SM but not directly integrated with the MMU. This allows the other TLB levels to be shared among multiple SMs, thereby improving overall utilization and scalability, while also helping to reduce communication overhead caused by address translation between different SMs.

[0040] In implementation, when a TLB_L1 miss occurs, other TLB levels can be accessed directly without traversing the entire chip architecture, thus reducing latency. Simultaneously, other TLB levels, acting as larger cache pools, can serve multiple SMs, reducing the need for each SM to maintain a large-capacity TLB, thereby saving chip area and power consumption. For example, a GPU_CORE can include four SMs, each containing one TLB_L1, while every two SMs share a TLB_L2. The GPU can include at least one GPU_CORE. When a thread in a particular SM requests memory access, it first searches the TLB_L1 within the SM. If the TLB_L1 miss is not found, it then searches the corresponding TLB_L2 within the SM. If the TLB_L2 miss is also not found, the MMU needs to be accessed to complete the address translation. In this way, through the collaborative work of TLBs, fast virtual address to physical address translation is achieved.

[0041] In the embodiments of this application, by rationally arranging the positions of the conversion backup buffers at each level, it is helpful to reduce the data transmission path length, improve data access efficiency and address translation efficiency, reduce access latency, and facilitate unified management and maintenance.

[0042] In some implementations, when the graphics processor 100 includes a two-level conversion backup buffer, the target conversion backup buffer includes a second-level conversion backup buffer; when the graphics processor 100 includes a multi-level conversion backup buffer, the target conversion backup buffer includes at least one level of conversion backup buffer following the first-level conversion backup buffer.

[0043] Here, the target TLB refers to a non-first-level cache structure in a two-level TLB architecture used to receive and cache PTEs returned from downstream devices such as the MMU. The target TLB can directly transmit PTEs back to the upstream TLB through a bypass channel (i.e., a fast channel) without relying on the existing process of writing PTEs to the data storage unit and then reading them from it, thereby reducing access latency.

[0044] In some implementations, the GPU can be configured with two levels of TLBs, namely TLB_L1 and TLB_L2 (i.e., the second-level translation lookup buffer), with TLB_L2 as the target TLB. During implementation, if TLB_L1 is missed, a lookup request is initiated to TLB_L2. If TLB_L2 is also missed, the MMU is triggered to perform a page table traversal and return the PTE obtained by the MMU to TLB_L2 for refilling. In implementation, there is a data interaction relationship between the target TLB (i.e., TLB_L2) ​​and TLB_L1. Specifically, when a miss occurs, TLB_L1 sends a lookup request to the target TLB. If the target TLB hits, it can directly return the hit PTE to TLB_L1 without waiting for the MMU to complete the entire page table traversal process, thus significantly reducing latency. If the target TLB also misses, the lookup request is forwarded to the MMU. When the MMU returns the PTE, it can simultaneously perform an update operation (i.e., write the PTE to the data storage unit of the target TLB) and a fast return operation (i.e., return the PTE directly to TLB_L1).

[0045] In some implementations, the GPU can be configured with multi-level TLBs, such as three or more levels. In a multi-level TLB architecture, the target TLB can be any cache structure located after the first level, meaning these cache structures can include, but are not limited to, second-level and / or third-level TLBs. For example, in a three-level TLB architecture, the target TLB can be TLB_L2 and / or TLB_L3. It is understood that in this scenario, the role of the target TLB is to provide flexible scalability, enabling this solution to be applicable to different levels of TLB structures. The differences between each level of TLB lie in their capacity, access speed, and application scenarios. For example, TLB_L2 typically has a larger capacity but a lower access speed, while TLB_L3 may further expand its capacity to accommodate a wider range of address mapping needs. The target TLB is a key component in the multi-level TLB system, possessing the core functions of quickly responding to PTE requests and reducing latency. The collaborative working mechanism between the target TLB and the TLBs at each level ensures high data access performance in complex memory management environments.

[0046] It is understandable that by introducing a specific hierarchical method for TLB in the GPU, efficient management of cached data can be achieved, thereby improving the GPU's operating efficiency.

[0047] During implementation, by integrating a bypass return mechanism into the target TLB, the lookup latency in that TLB can be effectively reduced, thereby reducing the overall PTE lookup latency and improving the concurrent processing capability of the GPU.

[0048] In the embodiments of this application, by clearly defining the scope of the target conversion backup buffer, it can be ensured that the solution still has efficient data access performance in complex memory management environments, while also making the solution have good scalability and adaptability, suitable for graphics processor architectures with different hierarchical structures.

[0049] In some implementations, the data storage unit 12 of the target conversion backup buffer is specifically used to determine a target data write location from at least one data write location in response to receiving a first target page table entry; and to store the first target page table entry to the target data write location.

[0050] Here, when the first target PTE is received, the data storage unit inside the target TLB is responsible for determining the specific location where the first target PTE should be written. Understandably, the data storage unit has limited storage space and multiple optional data write locations, therefore the most suitable target data write location needs to be selected.

[0051] The method for determining the target data write location can be any suitable method. It is understood that each TLB can use the same method to determine the PTE data write location.

[0052] In some implementations, when there is at least one blank data write position in the data storage unit, a data write position can be selected from the at least one blank data write position as the target data write position. For example, the target data write position can be selected randomly or in a sequential manner. It is understood that when there is only one blank data write position, that blank data write position is selected as the target data write position; when there are at least two blank data write positions, a blank data write position can be selected randomly or in a random order as the target data write position.

[0053] In some implementations, when there is no blank data write location in the data storage unit, the most suitable locations to be replaced can be determined based on the usage frequency and time of each cache entry. For example, when using a replacement algorithm such as the Least Recently Used (LRU) strategy, the data write location corresponding to the least recently accessed cache entry is selected as the target data write location to retain the most frequently used PTEs to the greatest extent.

[0054] After determining the target data write location, the data storage unit can either directly write the received first target PTE to that location, or process the first target PTE (e.g., compress, convert format, etc.) to obtain a usable PTE before writing it to the target data write location. For example, if the receiving unit has already processed the first target PTE, the data storage unit can either directly store the first target PTE or process it before storing it; if the receiving unit has not processed the first target PTE, the data storage unit can process it before storing it.

[0055] Understandably, the process of writing data to the PTE is similar for data storage units that are not in the target TLB.

[0056] In this embodiment of the application, by introducing a write location selection mechanism in the data storage unit, the storage space of page table entries can be managed more flexibly, the cache utilization rate can be improved, and subsequent PTE update operations can be supported more stably.

[0057] In some implementations, each level of the translation backup buffer further includes a tag storage unit; the tag storage unit of the target translation backup buffer is used to store at least one tag, each tag corresponding to a page table entry; the tag storage unit of the target translation backup buffer is also used to determine a target tag write position from at least one tag write position; the tag corresponding to the first target page table entry is stored in the target tag write position, the tag corresponding to the first target page table entry is determined based on the virtual address in the lookup request sent by the previous level of the translation backup buffer of the target translation backup buffer.

[0058] Here, when the receiving unit of the target TLB receives the first PTE, it will also simultaneously inform the tag storage unit of the target TLB so that the tag storage unit stores the tag corresponding to the first target PTE.

[0059] Upon receiving the synchronization signal from the receiving unit, the tag storage unit within the target TLB is responsible for determining the specific location where the tag corresponding to the first target PTE should be written. It is understood that the tag storage unit has limited storage space and multiple selectable tag write locations, therefore the most suitable target tag write location needs to be selected. It is understood that the tag write location refers to the set of locations within the tag storage unit that can be used to store virtual address tags.

[0060] The method for determining the target tag write location can be any suitable method. It is understandable that each TLB can use the same method to determine the tag write location corresponding to the PTE.

[0061] In some implementations, when there is at least one blank tag write position in the tag storage unit, a tag write position can be selected from the at least one blank tag write position as the target tag write position. For example, the target tag write position can be selected randomly or in a specific order. It is understood that when there is only one blank tag write position, that blank tag write position is used as the target tag write position; when there are at least two blank tag write positions, a blank tag write position can be selected randomly or in a random order as the target tag write position.

[0062] In some implementations, if there is no blank tag writing position in the tag storage unit, the tag writing position where the tag corresponding to the most suitable data writing position selected by the data storage unit is located can be used as the target tag writing position.

[0063] In this way, selecting the appropriate target tag writing location in the tag storage unit prepares for subsequent tag writing, which helps reduce overall refill latency and improve response speed.

[0064] The tag corresponding to the first target PTE is generated by parsing the VA in the lookup request to ensure accurate matching of existing entries in the target transformation backup buffer. For example, the entire VA can be used as the tag corresponding to the first target PTE, or the high-order part of the VA (i.e., the tag part) can be used as the tag corresponding to the first target PTE.

[0065] Performing a tag write operation in the tag storage unit aims to establish a mapping relationship between virtual addresses and physical addresses. By writing the tag to the target tag write location, the storage location of the first target page table entry in the target translation back buffer can be quickly located, thus supporting subsequent hit queries and accesses. It is understood that the write operation of the first target PTE and the write operation of the tag corresponding to the first target PTE can be simultaneous or asynchronous. For example, the tag corresponding to the first target PTE can be written first, followed by the first target PTE; or, the first target PTE can be written first, followed by the tag corresponding to the first target PTE; or, both the first target PTE and the tag corresponding to the first target PTE can be written simultaneously.

[0066] In practical implementation, through the coordinated action of the aforementioned units, the selection of the tag writing location and the tag writing operation can be completed in parallel while receiving the PTE, thereby effectively reducing the refill latency of the target conversion backup buffer and improving the response efficiency of the memory management unit. This parallel mechanism relies on the support of coordinated scheduling and control logic between hardware modules. For example, the receiving unit is responsible for receiving the PTE, while the tag storage unit is responsible for writing the tag. The receiving unit and the tag storage unit overlap in execution as much as possible to achieve performance optimization.

[0067] Understandably, the process of writing the tag corresponding to the PTE to a tag storage unit that is not the target TLB is similar.

[0068] In this embodiment, by synchronously writing the tag information corresponding to the page table entry and determining its storage location based on the virtual address, the consistency between the tag and the page table entry is ensured, which helps in the hit judgment of subsequent search requests and improves search efficiency.

[0069] In some implementations, each level of the translation backup buffer further includes a tag storage unit; the tag storage unit of the target translation backup buffer is used to determine the hit result of the search request based on the virtual address in the search request in response to receiving a search request; if the hit result of the search request is the first hit result, the search request is sent to the next level of the target translation backup buffer or the memory management unit of the graphics processor.

[0070] Here, VA (Virtual Address) refers to a logical address generated by the application or operating system. This VA may include, but is not limited to, the high-order tag portion and the low-order index and offset portions. The tag portion is used for matching within the tag storage unit of the target TLB to determine whether a tag in the cache has been hit.

[0071] The search result may include, but is not limited to, a first hit result and a second hit result. A first hit result indicates a miss, meaning that the search request failed to find a corresponding tag match in the tag storage unit of the target TLB. A second hit result indicates a hit, meaning that the search request found a corresponding tag match in the tag storage unit of the target TLB.

[0072] The method for determining the hit result can be any suitable method.

[0073] In some implementations, a correspondence between each virtual address and each hit result can be established in advance. Based on this correspondence, the hit result corresponding to the virtual address can be obtained.

[0074] In some implementations, the tag corresponding to the virtual address (e.g., the entire VA or a portion of the VA's tag) can be compared with the tags stored in the tag storage unit to determine if a match exists. If a match exists, it is considered a second hit result; otherwise, it is considered a first hit result indicating a miss.

[0075] By determining the hit result based on the virtual address in the lookup request, it is possible to quickly determine whether the current lookup request has been hit, thereby reducing the waiting time of subsequent processing and speeding up the entire address translation process, which in turn can reduce the latency of GPU accessing physical addresses.

[0076] The status code corresponding to the first hit result is usually output by the hardware logic circuit, which is used to indicate that the system should proceed to the next level of the search process.

[0077] Once the target TLB's tag storage unit returns the first hit result, the lookup request should be immediately forwarded to the next-level TLB of the target TLB, or directly submitted to the MMU, to avoid unnecessary waiting and resource waste. Understandably, if the target TLB has a next-level TLB, the lookup request is forwarded to that TLB; if the target TLB does not have a next-level TLB, the lookup request is forwarded to the MMU.

[0078] In this embodiment, the tag storage unit performs a preliminary hit judgment on the lookup request, which can quickly identify the miss situation and forward the request to the downstream module in a timely manner, reducing the time resources consumed by invalid lookups and unnecessary waiting and resource occupation, improving the response speed of the entire process, and thus further significantly reducing the refill latency of the target TLB.

[0079] In some implementations, the tag storage unit of the target translation backup buffer is specifically used to take the first hit result as the hit result of the lookup request when each tag in at least one tag does not match the tag corresponding to the virtual address.

[0080] Here, a first hit indicates a lookup failure, meaning that the current virtual address did not find a corresponding physical address in the target TLB. When the hit result is the first hit, the lookup request can be forwarded to the MMU or the next-level TLB to obtain complete PTE information.

[0081] In implementation, when a tag storage unit receives a lookup request, it compares the Tag portion of the virtual address in the lookup request with the tags stored in the tag storage unit. If none of the tags match, it is considered a miss, and the first hit result is returned. This direct hit-or-miss method avoids unnecessary page table traversal operations, significantly reduces refill latency, and improves system response performance.

[0082] In this embodiment, the hit determination is performed by accurately matching tags, which improves the accuracy of search request processing and the overall search efficiency, and helps to reduce the performance loss caused by misjudgment and unnecessary page table traversal operations.

[0083] In some implementations, the tag storage unit of the target conversion backup buffer is specifically used to use the second hit result as the hit result of the lookup request if any tag in at least one tag matches the tag corresponding to the virtual address.

[0084] Here, a second hit indicates a successful lookup, meaning the current virtual address has already been cached with the corresponding physical address in the target TLB. At this point, the corresponding PTE can be read directly from the target TLB's data storage unit without needing to forward the lookup request to the MMU or the next-level TLB.

[0085] In implementation, when a tag storage unit receives a lookup request, it compares the Tag portion of the virtual address in the lookup request with the tags stored in the tag storage unit. If a tag matches the Tag portion of the virtual address in the lookup request, it is considered a hit, and a second hit result is returned. This direct hit-or-miss method avoids unnecessary page table traversal operations, significantly reduces refill latency, and improves system response performance.

[0086] It is understandable that the method for determining the hit result of a lookup request in a non-target TLB is similar to the method for determining the hit result of a lookup request in the target TLB.

[0087] In this embodiment, the hit determination is performed by accurately matching tags, which improves the accuracy of search request processing and the overall search efficiency, and helps to reduce the performance loss caused by misjudgment and unnecessary page table traversal operations.

[0088] In some implementations, the tag storage unit of the target translation backup buffer is specifically used to send a lookup request to the memory management unit when the target translation backup buffer is the last level backup buffer; and to send the lookup request to the next level translation backup buffer when the target translation backup buffer is not the last level backup buffer.

[0089] Here, the tag storage unit is responsible for storing each tag to enable fast search and matching.

[0090] The last-level TLB refers to the lowest cache level in the entire multi-level TLB structure. For example, it can be TLB_L2 or a lower-level TLB. The last-level TLB is the cache level closest to main memory. When the last-level TLB is missed, the MMU must intervene to complete the page table traversal operation.

[0091] The next-level TLB refers to a cache level deeper than the current target TLB. For example, if the target TLB is TLB_L2, the next-level TLB could be TLB_L3. Next-level TLBs typically have larger capacities and lower access frequencies, making them suitable for storing infrequently used information. By passing lookup requests hierarchically, the characteristics of each cache level can be fully utilized, improving overall hit rate and response speed.

[0092] The Memory Management Unit (MMU) is a key hardware module in the GPU, responsible for performing page table traversal operations to convert VAs (Versions) to PAs (Page Entities). The MMU receives lookup requests from the last-level TLB (Telegraphic Library) to retrieve the corresponding PTE (Page Entity Form) and returns the retrieved PTE to the TLB that initiated the request. Understandably, as the final data source, the MMU can immediately initiate the page table traversal process upon receiving a lookup request from the last-level TLB, without waiting for processing from other intermediate caches, thus accelerating the overall response time.

[0093] Understandably, this tag storage unit is not only used for regular tag matching operations, but also has routing capabilities. When it detects that the target TLB is the last-level TLB, it proactively forwards the unsuccessful lookup request to the MMU instead of forwarding it further down the hierarchy, thus avoiding invalid lower-level queries and improving response speed. When the target TLB is not the last-level TLB, the tag storage unit of the target TLB will forward the unsuccessful lookup request to the next-level TLB instead of sending it directly to the MMU, ensuring that the lookup request is passed level by level in hierarchical order until a match is found or the last-level TLB is reached.

[0094] Understandably, the functionality of this tag storage unit has been expanded, not only supporting tag matching but also automatically selecting the correct forwarding path based on the target TLB level, thus improving the level of intelligence. At the same time, it reduces unnecessary forwarding paths, lowers power consumption and resource consumption, thereby significantly reducing refill latency and improving overall performance.

[0095] Understandably, for non-target TLBs, the forwarding of lookup requests is similar to that of target TLBs.

[0096] In this embodiment, by dynamically determining the forwarding path of the lookup request based on the characteristics of the conversion backup buffer at different levels, efficient and intelligent distribution of lookup requests is achieved, avoiding unnecessary redundant operations and improving data return speed.

[0097] In some implementations, the data storage unit 12 of the target translation backup buffer is connected to the selection unit 13 of the target translation backup buffer; the tag storage unit of the target translation backup buffer is further configured to send the tag corresponding to the virtual address to the data storage unit of the target translation backup buffer when the hit result of the lookup request indicates a hit; the data storage unit 12 of the target translation backup buffer is further configured to determine a second page table entry that matches the tag corresponding to the virtual address from at least one page table entry; send the second page table entry to the selection unit of the target translation backup buffer; the selection unit 13 of the target translation backup buffer is further configured to return the second page table entry to the previous level translation backup buffer of the target translation backup buffer.

[0098] Here, the tag storage unit is responsible for storing the tags corresponding to each PTE, used for quickly determining whether a hit has occurred. When a hit occurs, the tag storage unit can also transmit a read signal to trigger the data storage unit to read the PTE. This read signal can carry at least the hit tag so that the data storage unit can locate the correct page table entry and prepare for forwarding the relevant data. This approach improves the concurrency and response speed of data processing. In addition, the tag storage unit can also be used to record other metadata, such as access permissions and cache attributes, to support subsequent processing.

[0099] The data storage unit is a hardware module used to store PTEs (Physical Explanation Forms) and is responsible for caching the mapping information from virtual addresses to physical addresses. The data storage unit has a multi-path PTE filtering function, capable of finding the PTE that best matches the current virtual address among multiple PTEs. When the data storage unit finds a second PTE, it can pass it to the selection unit for subsequent logical processing. This connection method between the data storage unit and the selection unit reduces intermediate caching and read operations, improving data transmission efficiency. In implementation, the connection between the data storage unit and the selection unit is not limited to a direct physical connection; it can also be implemented as a logical data forwarding path through an internal bus or control signals.

[0100] In practice, the various units collaborate closely. First, upon receiving a lookup request, the tag storage unit performs a matching check and, upon a match, sends tag information to the data storage unit to initiate the data retrieval process. Subsequently, the data storage unit filters suitable page table entries based on the tag information and returns these entries to the next-level TLB via a selection unit. This achieves efficient page table entry processing and rapid response without increasing hardware overhead, thereby optimizing overall performance.

[0101] Understandably, for non-target TLBs, since no selection unit is set, the data storage unit of a non-target TLB can directly return the hit PTE upstream (e.g., the parent TLB, or the initiator of the lookup request (such as an LSU (Load Store Unit)) or the sender).

[0102] In this embodiment, the corresponding page table entry is located through a tag matching mechanism, and a normal hit return channel is realized by combining the selection unit, which further improves the response efficiency when a hit occurs and optimizes the overall address translation performance and data processing efficiency.

[0103] In some implementations, the receiving unit 11 of the first-level translation-backup buffer is configured to send a second target page table entry to the data storage unit of the first-level translation-backup buffer in response to receiving a first target page table entry; wherein the second target page table entry is determined based on the first target page table entry; the data storage unit 12 of the first-level translation-backup buffer is configured to perform an update operation based on the second target page table entry, and after the update operation is completed, return the physical address corresponding to the second target page table entry to the upstream of the first-level translation-backup buffer, so that the upstream of the first-level translation-backup buffer can access the target memory based on the physical address corresponding to the second target page table entry.

[0104] Here, TLB_L1 includes a receiving unit, a data storage unit, and a tag storage unit.

[0105] The receiving unit of TLB_L1 is responsible for receiving PTEs returned by the lower-level TLB and triggering the PTE refilling process. When the receiving unit receives a PTE, it can either directly write the PTE to the data storage unit, or perform preliminary processing on the received PTE, such as format checking and permission verification, before writing the processed PTE to the data storage unit. As the first entry point for the data stream, the receiving unit ensures that only valid PTEs can be further processed or cached. This receiving unit can support high-throughput data processing, concurrently receive multiple lookup requests, and provide a basic guarantee for subsequent data update and forwarding operations.

[0106] The second target PTE can be the first target PTE, or it can be a PTE obtained by processing the first target PTE.

[0107] The update operation of the TLB_L1 data storage unit refers to the process of writing the received second target PTE into the TLB_L1 data storage unit. It can be understood that the update operation in TLB_L1 is similar to the update operation in the target TLB. It can also be understood that not only is it necessary to update the second target PTE into the TLB_L1 data storage unit, but also to update the tag corresponding to the second target PTE into the TLB_L1 tag storage unit to complete the entire PTE backfilling process.

[0108] The upstream layer refers to the layer above TLB_L1. It can be the initiator or transmitter of lookup requests, relying on the physical address provided by the TLB to access memory. For example, the upstream of TLB_L1 could be the LSU in the GPU. By directly returning the physical address to the upstream layer, the overall address translation process can be accelerated, reducing the number of main memory accesses and thus improving overall performance.

[0109] The following example using a two-level TLB illustrates how to determine the PA corresponding to the VA in a lookup request: When TLB_L1 receives a lookup request from the upstream, it determines the hit result based on the VA in the lookup request. When the hit result indicates that there is a missing value in TLB_L1 (i.e., no hit in TLB_L1), TLB_L1 forwards the lookup request to TLB_L2; when the hit result indicates that there is a hit in TLB_L1, TLB_L1 returns the corresponding PTE to the upstream. When TLB_L2 receives a lookup request, it determines the hit result based on the VA in the lookup request. If the hit result indicates that a missing value occurs in TLB_L2 (i.e., a miss occurs in TLB_L2), TLB_L2 forwards the lookup request to MMU. If the hit result indicates that a hit occurs in TLB_L2, TLB_L2 returns the corresponding PTE to TLB_L1 to trigger internal refilling in TLB_L1. When the MMU receives a lookup request, it performs a PTW (Page Table Walk) operation to obtain the corresponding PTE and returns the PTE to the receiving unit of TLB_L2. Upon receiving a PTE, the receiving unit of TLB_L2 immediately initiates two parallel operations: First, it can directly send the PTE to its data storage unit, allowing it to write the PTE into the TLB_L2 data storage unit. Second, it can directly return the PTE to TLB_L1 via a fast bypass channel. This means the update operation of TLB_L2 and the PTE return are asynchronous; the PTE can be written to TLB_L2 while simultaneously being returned to TLB_L1 via the fast return channel, without waiting for the write operation to complete. This asynchronous update mechanism effectively decouples the PTE writing and return processes, allowing them to execute concurrently and significantly reducing refill latency. In some implementations, the receiving unit of TLB_L2 can perform data processing (such as page table compression or encoding conversion) on the PTE before sending it, allowing the TLB_L2 data storage unit to directly store the received PTE. In some implementations, the receiving unit of TLB_L2 sends the received PTE directly to the data storage unit of TLB_L2. In this case, the data storage unit of TLB_L2 processes the PTE before storing it.

[0110] When the receiving unit of TLB_L1 receives the PTE, it immediately performs an update operation, writes the received PTE (or processes the PTE) to the corresponding storage location, and returns the PA corresponding to the PTE to the upstream after the writing is completed.

[0111] In actual implementation, since TLB_L1 needs to return the PA corresponding to each lookup request in sequence, TLB_L1 does not need to set a selection unit and a fast channel.

[0112] It is understandable that the backfilling process for non-target TLBs can be the same as that for TLB_L1.

[0113] In this embodiment, the physical address is returned to the upstream after the local update is completed through the first-level translation backup buffer, which ensures the continuity and efficiency of the entire address translation process while ensuring the accuracy of the access.

[0114] Based on the foregoing embodiments, this application also provides a data processing method applied to the target conversion backup buffer of any of the aforementioned graphics processors. Figure 2This is a schematic diagram illustrating the implementation flow of a data processing method provided in an embodiment of this application, such as... Figure 2 As shown, the data processing method includes steps S21 to S23, wherein: Step S21: Receive the first page entry through the receiving unit of the target translation backup buffer; wherein the first page entry is sent by the next level translation backup buffer of the target translation backup buffer or by the memory management unit of the graphics processor. Step S22: The data storage unit of the target translation backup buffer performs an update operation based on the first target page table entry to populate the first target page table entry back into the data storage unit of the target translation backup buffer; wherein, the first target page table entry is determined based on the first page table entry; Step S23: Return the first target page table entry to the next higher level of the target conversion backup buffer through the selection unit of the target conversion backup buffer.

[0115] Here, the target TLB refers to the TLBs after TLB_L1. This target TLB includes a receiving unit, a data storage unit, a tag storage unit, and a selection unit.

[0116] The first target PTE can be the first PTE or the PTE obtained after data processing of the first PTE.

[0117] The receiving unit is used to receive PTEs returned from downstream (e.g., MMU or next-level TLB). In implementation, the process of forwarding PTEs by the receiving unit can be referred to the aforementioned embodiment of the graphics processor.

[0118] The data storage unit is primarily used to store each PTE. In implementation, the process of storing the first target PTE in this data storage unit can be found in the aforementioned graphics processor embodiment.

[0119] The tag storage unit is mainly used to store the tags corresponding to each PTE. In implementation, the process of storing the tag corresponding to the first target PTE in this tag storage unit can be found in the aforementioned embodiment of the graphics processor.

[0120] The selection unit is mainly used to return the PTE sent by the receiving unit or the PTE sent by the data storage unit to the upstream (e.g., the previous level TLB). In implementation, the process of the selection unit returning the PTE can be referred to the aforementioned embodiment of the graphics processor.

[0121] In this embodiment, by introducing a selection unit and setting a fast return channel in the target conversion backup buffer, the receiving unit, after receiving the first page entry, can not only write it to the data storage unit but also simultaneously return it directly to the previous-level conversion backup buffer. This decouples the data update and PTE return actions, achieving the goal of immediate PTE return. Compared to related technologies that require writing before reading, this solution saves two access cycles and significantly reduces refill latency because the PTE return does not require waiting for PTE writing and reading. Secondly, since this solution only occupies the write port during refilling, the read port can continue to receive and process other requests, reducing the possibility of queuing and cascading blocking, significantly alleviating port resource conflicts, and thus improving overall throughput. Finally, the fast return channel for PTE reduces the complexity and redundancy of the control logic.

[0122] In some implementations, the "update operation based on the first target page table entry by the data storage unit of the target translation backup buffer" in step S22 includes: in response to receiving the first target page table entry, the data storage unit of the target translation backup buffer determines a target data write location from at least one data write location and stores the first target page table entry to the target data write location.

[0123] In some implementations, each level of translation backup buffer further includes a tag storage unit; wherein the tag storage unit of the target translation backup buffer stores at least one tag, each tag corresponding to a page table entry; the data processing method further includes: determining a target tag write position from at least one tag write position through the tag storage unit of the target translation backup buffer; storing the tag corresponding to the first target page table entry to the target tag write position through the tag storage unit of the target translation backup buffer, wherein the tag corresponding to the first target page table entry is determined based on the virtual address in the lookup request.

[0124] In some implementations, each level of the translation backup buffer further includes a tag storage unit; the data processing method further includes: in response to receiving a lookup request, the tag storage unit of the target translation backup buffer determines the hit result of the lookup request based on the virtual address in the lookup request; if the hit result of the lookup request is a first hit result, the lookup request is sent to the next level of the target translation backup buffer or the memory management unit of the graphics processor through the tag storage unit of the target translation backup buffer, wherein the first hit result indicates a miss.

[0125] In some implementations, "determining the hit result of the lookup request based on the virtual address in the lookup request by the tag storage unit of the target translation backup buffer" includes: if each tag in at least one tag does not match the tag corresponding to the virtual address, the tag storage unit of the target translation backup buffer uses the first hit result as the hit result of the lookup request; if any tag in at least one tag matches the tag corresponding to the virtual address, the tag storage unit of the target translation backup buffer uses the second hit result as the hit result of the lookup request, the second hit result indicating a hit.

[0126] In some implementations, "sending a lookup request to the next-level translation backup buffer or the memory management unit of the graphics processor via the tag storage unit of the target translation backup buffer" includes: when the target translation backup buffer is the last-level backup buffer, sending the lookup request to the memory management unit via the tag storage unit of the target translation backup buffer; and when the target translation backup buffer is not the last-level backup buffer, sending the lookup request to the next-level translation backup buffer via the tag storage unit of the target translation backup buffer.

[0127] In some implementations, the data storage unit of the target translation backup buffer is connected to the selection unit of the target translation backup buffer; the data processing method further includes: if the hit result of the lookup request indicates a hit, the tag storage unit of the target translation backup buffer sends the tag corresponding to the virtual address to the data storage unit of the target translation backup buffer; in response to receiving the tag corresponding to the virtual address, the data storage unit of the target translation backup buffer determines a second page table entry from at least one page table entry that matches the tag corresponding to the virtual address; the data storage unit of the target translation backup buffer sends the second page table entry to the selection unit of the target translation backup buffer; the selection unit of the target translation backup buffer returns the second page table entry to the previous level translation backup buffer of the target translation backup buffer.

[0128] In some embodiments, the data processing method further includes: in response to receiving a first target page table entry, the receiving unit of the first-level translation back buffer sends a second target page table entry to the data storage unit of the first-level translation back buffer; wherein the second target page table entry is determined based on the first target page table entry; the data storage unit of the first-level translation back buffer performs an update operation based on the second target page table entry, and after the update operation is completed, returns the physical address corresponding to the second target page table entry to the upstream of the first-level translation back buffer, so that the upstream of the first-level translation back buffer accesses the target memory based on the physical address corresponding to the second target page table entry.

[0129] In some implementations, where the graphics processor includes a two-level conversion backup buffer, the target conversion backup buffer includes a second-level conversion backup buffer; where the graphics processor includes a multi-level conversion backup buffer, the target conversion backup buffer includes at least one level of conversion backup buffer following the first-level conversion backup buffer.

[0130] In some implementations, the graphics processor includes a streaming multiprocessor, a first-level translation back buffer located within the streaming multiprocessor, and subsequent translation back buffers located outside the memory management unit of the streaming multiprocessor and the graphics processor.

[0131] The description of the above method embodiments is similar to that of the above graphics processor embodiments, and has similar beneficial effects. For technical details not disclosed in the method embodiments of this application, please refer to the description of the graphics processor embodiments of this application for understanding.

[0132] The technical solution of this application is described in detail below.

[0133] In processors currently employing a multi-level TLB architecture (e.g., including two levels: TLB_L1 and TLB_L2), when a TLB miss occurs and a page table entry needs to be retrieved from the Memory Management Unit (MMU), the data flow and processing procedure typically follow these steps: Step 1, Triggering and Requesting: After a TLB_L1 miss occurs, a lookup request is initiated to TLB_L2. If a TLB_L2 miss also occurs, the processor will initiate a page table traversal request to the MMU.

[0134] Step 2, Data Return and Preliminary Processing: After the MMU completes the page table traversal, it returns the obtained PTE to TLB_L2. At this point, the data cannot be used directly and requires some calculations and verifications. For example, page table format conversion and permission checks.

[0135] Step 3: Write to TLB_L2 storage array: After data processing (such as page table compression, encoding conversion, etc.) to obtain the final usable PTE, TLB_L2 will write the PTE to the storage array (usually SRAM), and the write location is specified by the replacement algorithm.

[0136] Step 4: Read the TLB_L2 storage array: After confirming that the write operation is complete, the TLB_L2 initiates a read operation on the same location, reading the PTE that was just written from the SRAM in one go.

[0137] Step 5: Return to TLB_L1: Return the PTE read from SRAM to TLB_L1.

[0138] Therefore, in a multi-level TLB architecture, when TLB_L2 is missing and a PTE is obtained from the downstream MMU, the existing refill process requires writing to SRAM first and then reading from SRAM before the PTE can be returned upstream. This presents the following three problems: The problem of high refill latency: After the lower-level MMU returns the PTE to TLB_L2, the existing solution requires two serial accesses to the single-port SRAM inside TLB_L2, which is "write first and then read", resulting in an inherent latency of at least 2 SRAM access cycles, which seriously increases the latency of TLB_L1 to obtain data.

[0139] Port resource conflicts and reduced system throughput: Because refilling requires exclusive access to the SRAM port for two accesses, it blocks the normal lookup request from TLB_L1 to TLB_L2, causing request queuing and cascading blocking. This not only affects the requests that trigger refilling, but also reduces the overall service bandwidth and concurrent processing capacity of the TLB subsystem.

[0140] The problem of data path redundancy: Existing architectures require that the same entry data returned from downstream be written to SRAM first, then read from the same address before being returned to the upstream TLB. This "SRAM detour" path is a redundant data flow, introducing unnecessary control logic.

[0141] In a GPU architecture, the LSU needs to obtain the PA corresponding to the VA with the help of the TLB and MMU before it can access the memory. The MMU is responsible for converting the VA into the PA, while the TLB caches the conversion result.

[0142] Typical hierarchical structures such as Figure 3 As shown, the GPU includes multiple GPU_CORE, LLC (Last Level Cache) and HBM (High Bandwidth Memory). The GPU_CORE includes 4 SM, two TLB_L2 and MMU. Each SM has a small and fast TLB_L1, and the two SMs share a large and slow TLB_L2.

[0143] When TLB_L1 is missing, it will send a lookup request to TLB_L2.

[0144] If TLB_L2 is hit, the conversion result is returned directly.

[0145] If a miss also occurs in TLB_L2, a request needs to be sent to the downstream MMU. The MMU will perform PTW (Page-to-Page Wrap) to translate VA (Value Entity) into PA (Page-to-Page Entity). The MMU returns PTE (Page-to-Page Entity). Upon receiving the PTE, TLB_L2 refills its internal cache and then returns the PTE to TLB_L1. Upon receiving the PTE, TLB_L1 refills its internal SRAM and then returns the PA to LSU (Low Subsystem). LSU can then use the PA to access memory. This PA can be composed of the page offsets of PFN (Page-to-Page Number) and VA.

[0146] This application uses a bypass design to decouple the originally coupled PTE update and PTE return actions, allowing them to be executed concurrently. For example... Figure 4 As shown, this GPU contains the following core modules: TLB_L1: Level 1 conversion backup buffer.

[0147] TLB_L2: Secondary translation backup buffer (or lower-level storage), is the core layer optimized in this application.

[0148] MMU: Memory Management Unit, responsible for page table traversal.

[0149] TLB_L2 includes: DATA_SRAM: The data storage array (i.e., data storage unit) of TLB_L2, storing PTEs.

[0150] TAG_SRAM: The tag storage array (i.e., tag storage unit) of TLB_L2, which stores virtual address tags.

[0151] RECEIVE: Data receiving and processing module (i.e., receiving unit).

[0152] SELECT (i.e., data selector (selection unit)) selects either a dedicated path (i.e., fast path) or a normal path.

[0153] The workflow is as follows: When a PTE is missing, TLB_L1 sends a lookup request (translate_req) to TLB_L2. TLB_L2 accesses TAG_SRAM to check if the tag is matched. If it is matched, it reads DATA_SRAM to obtain the PTE and returns it.

[0154] If TLB_L2 is also missing, then send translate_req to the MMU.

[0155] After the MMU completes the page table traversal, it returns the PTE to TLB_L2. The RECEIVE receives the PTE and processes the SRAM update and the PTE return in parallel.

[0156] SRAM update: Write the PTE to DATA_SRAM and the virtual address tag to TAG_SRAM; PTE return: The PTE is returned to the upstream TLB_L1 via the dedicated fast_return path, which completely bypasses DATA_SRAM.

[0157] Therefore, this application differs from related technologies in the following ways: 1. Different data flow: Related technologies use a serial flow of receiving → writing to SRAM → reading from SRAM → returning; while this application uses a parallel flow of receiving → {writing to SRAM, returning directly}, reconstructing the original serial process of "writing to memory array → reading from memory array → returning to the upper level" into a parallel process of "writing to memory array and returning directly to the upper level".

[0158] 2. Different resource usage: Related technologies exclusively occupy the SRAM port (write + read) during refill; this application only occupies the write port during refill, and the read port can serve other requests.

[0159] 3. Different control states: Related technologies require maintaining a "write complete" state before reading can be initiated; the return operation in this application does not depend on the write complete state.

[0160] It should be noted that, in the embodiments of this application, if the above methods are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to related technologies, can be embodied in the form of software products. These software products are stored in a storage medium and include several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware and software combination.

[0161] This application provides an electronic device including any of the aforementioned graphics processors. The electronic device can be various types of terminals such as laptops, tablets, desktop computers, set-top boxes, and mobile devices (e.g., mobile phones, portable music players, personal digital assistants, dedicated messaging devices, portable gaming devices), or it can be implemented as a server. The server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0162] It should be noted that the description of the above device embodiments is similar to the description of the above graphics processor embodiments, and has similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the description of the graphics processor embodiments of this application for understanding.

[0163] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0164] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0165] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0166] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0167] In addition, each functional unit in the embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0168] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0169] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0170] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A graphics processor, characterized in that, The graphics processor includes at least two levels of conversion backup buffers. Each level of the conversion backup buffer includes a receiving unit and a data storage unit. The target conversion backup buffer further includes a selection unit. The target conversion backup buffer is any of the other levels of conversion backup buffers in the at least two levels, excluding the first level. The data storage unit of the target conversion backup buffer is used to store at least one page table entry; The receiving unit of the target translation backup buffer is configured to, in response to receiving the first page table entry, send the first target page table entry to the data storage unit of the target translation backup buffer and the selection unit of the target translation backup buffer; wherein, the first page table entry is sent by the next-level translation backup buffer of the target translation backup buffer or by the memory management unit of the graphics processor, and the first target page table entry is determined based on the first page table entry. The data storage unit of the target conversion backup buffer is also used to perform an update operation based on the first target page table entry, so as to fill the first target page table entry back into the data storage unit of the target conversion backup buffer. The selection unit of the target translation backup buffer is used to return the first target page table entry to the previous level translation backup buffer of the target translation backup buffer.

2. The graphics processor according to claim 1, characterized in that, The data storage unit of the target conversion backup buffer is specifically used to, in response to receiving the first target page table entry, determine the target data write position from at least one data write position; and store the first target page table entry into the target data write position.

3. The graphics processor according to claim 2, characterized in that, Each level of the conversion backup buffer also includes a tag storage unit; The tag storage unit of the target conversion backup buffer is used to store at least one tag, and each tag corresponds to a page table entry. The tag storage unit of the target conversion backup buffer is further configured to determine the target tag write position from at least one tag write position; and store the tag corresponding to the first target page table entry to the target tag write position, wherein the tag corresponding to the first target page table entry is determined based on the virtual address in the lookup request sent by the previous level conversion backup buffer of the target conversion backup buffer.

4. The graphics processor according to claim 1, characterized in that, Each level of the conversion backup buffer also includes a tag storage unit; The tag storage unit of the target conversion backup buffer is used to determine the hit result of the search request based on the virtual address in the search request in response to receiving a search request; If the search request results in a first hit, the search request is sent to the next level of the target translation backup buffer or the memory management unit, where the first hit indicates a miss.

5. The graphics processor according to claim 4, characterized in that, The tag storage unit of the target translation backup buffer is specifically used to send the lookup request to the memory management unit when the target translation backup buffer is the last level backup buffer. If the target conversion backup buffer is not the last-level backup buffer, the lookup request is sent to the next-level conversion backup buffer after the target conversion backup buffer.

6. The graphics processor according to claim 4, characterized in that, The tag storage unit of the target conversion backup buffer is specifically used to take the first hit result as the hit result of the search request when each of the at least one tag does not match the tag corresponding to the virtual address.

7. The graphics processor according to claim 4, characterized in that, The tag storage unit of the target conversion backup buffer is specifically used to take the second hit result as the hit result of the lookup request when any tag in the at least one tag matches the tag corresponding to the virtual address. The second hit result indicates a hit.

8. The graphics processor according to claim 4, characterized in that, The data storage unit of the target conversion backup buffer is connected to the selection unit of the target conversion backup buffer; The tag storage unit of the target translation backup buffer is also used to send the tag corresponding to the virtual address to the data storage unit of the target translation backup buffer when the hit result of the search request indicates a hit. The data storage unit of the target translation backup buffer is further configured to determine a second page table entry that matches the tag corresponding to the virtual address from the at least one page table entry; and send the second page table entry to the selection unit of the target translation backup buffer; The selection unit of the target conversion backup buffer is also used to return the second page table entry to the previous level conversion backup buffer of the target conversion backup buffer.

9. The graphics processor according to claim 1, characterized in that, The receiving unit of the first-level translation backup buffer is configured to send a second target page table entry to the data storage unit of the first-level translation backup buffer in response to receiving the first target page table entry; wherein the second target page table entry is determined based on the first target page table entry. The data storage unit of the first-level translation back buffer is used to perform an update operation based on the second target page table entry, and after the update operation is completed, return the physical address corresponding to the second target page table entry to the upstream of the first-level translation back buffer, so that the upstream of the first-level translation back buffer can access the target memory based on the physical address corresponding to the second target page table entry.

10. The graphics processor according to any one of claims 1 to 9, characterized in that, In the case where the graphics processor includes a two-level conversion backup buffer, the target conversion backup buffer includes a second-level conversion backup buffer; In the case where the graphics processor includes a multi-level conversion backup buffer, the target conversion backup buffer includes at least one level of conversion backup buffer following the first level of conversion backup buffer.

11. The graphics processor according to claim 10, characterized in that, The graphics processor includes a streaming multiprocessor, the first-level translation backup buffer is located in the streaming multiprocessor, and the other-level translation backup buffers after the first-level translation backup buffer are located outside the memory management unit of the streaming multiprocessor and the graphics processor.

12. A data processing method, characterized in that, A target conversion backup buffer is applied to a graphics processor, the graphics processor including at least two levels of conversion backup buffers, each level of the conversion backup buffer including a receiving unit and a data storage unit, the target conversion backup buffer further including a selection unit, the target conversion backup buffer being the other levels of conversion backup buffers besides the first level of the at least two levels of conversion backup buffers, the data processing method including: The first page entry is received by the receiving unit of the target translation backup buffer; wherein the first page entry is sent by the next-level translation backup buffer of the target translation backup buffer or by the memory management unit of the graphics processor. The data storage unit of the target conversion backup buffer performs an update operation based on the first target page table entry to populate the first target page table entry back into the data storage unit of the target conversion backup buffer; wherein, the first target page table entry is determined based on the first page table entry. The first target page table entry is returned to the previous level of the target translation backup buffer through the selection unit of the target translation backup buffer.

13. An electronic device, characterized in that, The graphics processor included in any one of claims 1 to 11.

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