Data access method and device, graphics processor, electronic equipment and storage medium

Abstract

The present disclosure provides a data access method and device, a graphics processor, electronic equipment and a storage medium, and belongs to the technical field of computers. The method comprises the following steps: in the case that an access request sent by a graphics rendering pipeline unit in a graphics processor does not hit any cache entry, selecting one entry from a plurality of entries as a target buffer entry corresponding to the access request; storing target data corresponding to the access request, which is obtained from a local memory of the graphics processor, into the target buffer entry; sending the target data in the target buffer entry to the graphics rendering pipeline unit; and adjusting the storage type of the target buffer entry from a buffer type to a cache type, so that the target data serves as alternative data for hit testing of a cache buffer module. The embodiments of the present disclosure can improve access efficiency and data hit rate, thereby improving the overall graphics rendering processing efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a data access method, a data access device, a graphics processor, an electronic device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] The rendering pipeline of a graphics processing unit (GPU) is a key concept in computer graphics. It is an important processing stage in the GPU, responsible for processing and transforming graphics data for rendering. It mainly consists of a geometry processing stage and a pixel processing stage, and each processing stage includes multiple processing units for performing specific calculations and transformations and other data processing.

[0003] In both the geometry processing and pixel processing stages, multiple processing units typically use a Local Memory Store (LMS) for data exchange. In related technologies, to hide the access latency to the LMS, a buffer region with a fixed depth (e.g., a depth equal to the number of clock cycles of latency to access the LMS) can be used. However, this approach lacks flexibility, and the buffer region cannot fully utilize the locality between access requests. Summary of the Invention

[0004] This disclosure provides a data access method, data access device, graphics processor, electronic device, computer-readable storage medium, and computer program product that can improve the data hit rate by utilizing the locality between access requests, thereby improving the overall graphics rendering processing efficiency.

[0005] In a first aspect, this disclosure provides a data access method applied to a control unit in a graphics processing unit (GPU) for controlling a cache buffer module. The cache buffer module includes multiple entries, including cache entries of type cache and buffer entries of type buffer. The data access method includes: when an access request sent by a graphics rendering pipeline unit in the GPU fails to hit any of the cache entries, selecting one entry from the multiple entries as the target buffer entry corresponding to the access request; storing target data corresponding to the access request, obtained from the GPU's local memory, into the target buffer entry; sending the target data in the target buffer entry to the graphics rendering pipeline unit; and adjusting the storage type of the target buffer entry from the buffer type to the cache type, so that the target data serves as alternative data for a hit test of the cache buffer module.

[0006] Secondly, this disclosure provides a data access device applied to a control unit in a graphics processor for controlling a cache buffer module. The cache buffer module includes multiple entries, including cache entries of storage type caching and buffer entries of storage type buffering. The data access device includes: a selection module, configured to select an entry from the multiple entries as a target buffer entry corresponding to the access request when an access request sent by the graphics rendering pipeline unit in the graphics processor fails to hit any of the cache entries; a storage module, configured to store target data corresponding to the access request obtained from the local memory of the graphics processor into the target buffer entry; a sending module, configured to send the target data in the target buffer entry to the graphics rendering pipeline unit; and an adjustment module, configured to adjust the storage type of the target buffer entry from buffering to cache, so that the target data can be used as alternative data for a hit test of the cache buffer module.

[0007] Thirdly, this disclosure provides a graphics processor, which includes: at least one processing unit, local memory, at least one cache buffer module, and a control unit for controlling the cache buffer module; wherein the control unit is used to execute the data access method described in any one of the embodiments of this disclosure.

[0008] Fourthly, this disclosure provides an electronic device comprising: at least one processor; wherein the at least one processor includes a graphics processor; and a memory communicatively connected to the graphics processor; wherein the memory stores one or more computer programs executable by the at least one graphics processor, the one or more computer programs being executed by the at least one graphics processor to enable the at least one graphics processor to perform the data access method described above.

[0009] Fifthly, this disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a graphics processor, implements the above-described data access method.

[0010] In a sixth aspect, this disclosure provides a computer program product comprising computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a graphics processor of an electronic device, the graphics processor in the electronic device performs the data access method described above.

[0011] The data access method provided in this embodiment includes a cache buffer module in the graphics processor (GPU), comprising cache entries of type cache and buffer entries of type buffer. Cache entries are used to reduce the number of accesses to the GPU's local memory, and buffer entries are used to hide the access latency to the local memory. Based on this, when an access request sent by the graphics rendering pipeline unit in the GPU fails to hit any cache entry, an entry is selected from multiple entries as the target buffer entry corresponding to the access request; the target data corresponding to the access request, obtained from the GPU's local memory, is stored in the target buffer entry; the target data in the target buffer entry is sent to the graphics rendering pipeline unit; and the storage type of the target buffer entry is changed from buffer type to cache type, so that the target data can be used as alternative data for a hit test of the cache buffer module.

[0012] Therefore, the cache buffer module includes two types of entries: cache entries provide caching functionality to store historical access data, thereby reducing the number of accesses to local memory; and buffer entries provide buffering functionality to store data prefetched from local memory, thereby hiding the access latency to local memory. Thus, a single storage unit can provide two storage functions, offering high flexibility. Specifically, firstly, buffer entries allow data to be moved from local memory into the buffer entries in advance. For continuous accesses initiated by the graphics rendering pipeline unit, the corresponding data can be directly obtained from the buffer entries, making the access latency imperceptible to the graphics rendering pipeline unit. This hides the access latency to local memory and reduces local memory access latency. Firstly, it addresses the bandwidth overhead of the storage; secondly, when a cache miss occurs, an entry can be selected as the target buffer entry. Utilizing the pass-through forwarding capability of the buffer entry, it eliminates the need to wait for the target data to be fully filled from local storage. The data can be forwarded to the requester as soon as a portion of the target data arrives. Furthermore, it avoids the need to perform state adjustments and checks on the cache entry to overcome false hits and address conflicts, thus reducing hardware complexity. Thirdly, unlike related technologies that release the target data after transmission, this approach adjusts the target buffer entry into a cache entry. This allows for more effective utilization of the locality between access requests, further improving the data hit rate and ultimately enhancing the overall graphics rendering efficiency.

[0013] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0014] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0015] Figure 1 This is a flowchart of a data access method provided in an embodiment of the present disclosure.

[0016] Figure 2 This is a schematic diagram of a cache buffer module provided in an embodiment of the present disclosure.

[0017] Figure 3 This is a schematic diagram of a cache hit test provided in an embodiment of the present disclosure.

[0018] Figure 4 This is a schematic diagram of a process for selecting a target buffer entry, provided as an embodiment of the present disclosure.

[0019] Figure 5 This is a flowchart illustrating a data access method provided in an embodiment of the present disclosure.

[0020] Figure 6 This is a schematic diagram illustrating the processing steps of a data access method provided in an embodiment of this disclosure.

[0021] Figure 7 This is a block diagram of a data access device provided in an embodiment of the present disclosure.

[0022] Figure 8 This is a block diagram of a graphics processor provided in an embodiment of the present disclosure.

[0023] Figure 9 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0024] Figure 10 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0026] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0027] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0029] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0030] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information in this technical solution comply with relevant laws and regulations and do not violate public order and good morals. The use of user data in this technical solution follows relevant national laws and regulations (e.g., the "Information Security Technology - Personal Information Security Specification"). For example, appropriate measures are taken for personal information access control; restrictions are imposed on the display of personal information; the purpose of using personal information does not exceed the scope of direct or reasonable association; and explicit identity targeting is eliminated when using personal information to avoid precisely identifying specific individuals.

[0031] In some implementations, to improve the processing performance of the graphics processing unit (GPU), the Local Memory Store (LMS) can be designed to be located close to the shader. For example, the LMS and shader components can be designed in the same partition. This design can effectively reduce the latency of shader accessing the LMS and improve the shader's read and write performance to the LMS. The corresponding cost is that some processing units in the rendering pipeline (e.g., culling and elimination units, rasterization units, pixel manipulation units, etc.) need to access the LMS across partitions, which will introduce significant latency and thus affect the overall system performance.

[0032] In related technologies, a buffer region with a fixed depth can be set to hide this access latency. However, since the depth of this buffer region is a fixed value, its flexibility is poor, and it cannot be adaptively adjusted when the access latency changes. In addition, after a read request is completed, the corresponding buffer entry needs to be released for the next possible read request. Therefore, it cannot make good use of the locality between access requests, resulting in low bandwidth utilization.

[0033] In view of the above, embodiments of this disclosure provide a data access method, a data access device, a graphics processor, an electronic device, a computer-readable storage medium, and a computer program product.

[0034] In this embodiment of the disclosure, a configurable number of cache entries and buffer entries are provided through a cache buffer module. The former can provide caching functionality, while the latter can hide access latency. Since the number of entries is configurable, it can be adaptively adjusted as the access latency value changes, thereby better adapting to different access latencies and providing high flexibility.

[0035] Figure 1 This is a flowchart illustrating a data access method provided in an embodiment of the present disclosure. The data access method can be applied to a control unit in a graphics processor for controlling a cache buffer module. The cache buffer module includes multiple entries, including cache entries of storage type caching and buffer entries of storage type buffering.

[0036] Therefore, it can be seen that the application scenarios of this disclosure include graphics processing scenarios. For this application scenario, a cache buffer module and a corresponding control unit are added to the graphics processor. The cache buffer module can provide two types of entries to meet diverse storage needs, while the control unit can control data access and other operations of the cache buffer module with a single entry as the basic control granularity.

[0037] Reference Figure 1 The data access method may include the following steps.

[0038] Step S11: If the access request sent by the graphics rendering pipeline unit in the graphics processor does not hit any cache entry, select one entry from multiple entries as the target buffer entry corresponding to the access request.

[0039] Step S12: The target data corresponding to the access request, which is obtained from the local memory of the graphics processor, is stored in the target buffer entry.

[0040] Step S13: Send the target data in the target buffer entry to the graphics rendering pipeline unit.

[0041] Step S14: Change the storage type of the target buffer entry from buffer type to cache type so that the target data can be used as alternative data for hit testing of the cache buffer module.

[0042] For example, the Rendering Pipeline unit is a processing unit in the graphics processor used to perform graphics rendering. It consists of multiple processing stages, each of which performs specific geometric calculations and transformations, and other data processing.

[0043] For example, a graphics rendering pipeline unit includes the following processing stages.

[0044] 1. Vertex Input: This stage passes vertex data from the application to the geometry pipeline. Vertex data includes attribute data such as position, color, and normals.

[0045] 2. Vertex Shader: In this stage, the vertex shader performs calculations on each input vertex and can perform various transformations and operations, such as model transformation, view transformation, projection transformation, etc. It can also calculate the vertex's lighting, texture coordinates, etc.

[0046] 3. Primitive Assembly: In the current stage, the primitive assembler converts vertices into complete geometric primitives, such as points, line segments, triangles, etc.

[0047] 4. Geometry Shader: In the geometry shading stage, the geometry shader can manipulate and generate geometric primitives, including creating new primitives and changing the shape, size, position and other attributes of primitives.

[0048] 5. Clipping: At this stage, the clipper can compare primitives with the screen boundaries and discard parts that are outside the view volume.

[0049] 6. Screen Mapping: This stage maps the clipped primitives to pixel coordinates in screen space.

[0050] 7. Rasterization: The rasterization stage converts geometric primitives into pixels on the screen and determines the position, color, and other attributes of each pixel.

[0051] 8. Fragment Shader: During the fragment shading stage, the fragment shader performs calculations for each rasterized pixel. It can perform pixel-level lighting calculations, texture sampling, depth testing, and other operations.

[0052] 9. Pixel Operations: The final stage is pixel operations, which perform the final pixel processing, such as blending, dithering, and anti-aliasing.

[0053] In summary, the goal of the graphics rendering pipeline unit is to process geometry and generate the final image in an efficient manner. Through parallel processing and specialized hardware support, the GPU is able to perform these calculations quickly to achieve real-time graphics rendering.

[0054] In some alternative embodiments, the graphics rendering pipeline unit may include at least one of a geometry processing pipeline unit, a pixel processing pipeline unit, and a rasterization engine unit.

[0055] For example, the geometry processing pipeline unit is mainly used to perform coordinate transformation, attribute processing, primitive assembly and clipping on the vertex data of 3D (3-Dimension) models, thereby outputting effective primitives in screen space and providing input for rasterization.

[0056] For example, the rasterization engine unit is mainly used to discretize continuous geometric data into a raster image, determine which pixels each primitive covers, thereby generating the corresponding fragment (or piece) to prepare for fragment coloring.

[0057] For example, the pixel processing pipeline unit is mainly responsible for converting the rasterized fragments into the final displayable pixels on the screen. The main processing steps include performing interpolation calculations, texture sampling, lighting rendering, depth / stencil testing, and color mixing for each potential pixel, and finally outputting 2D image pixels with correct visual effects.

[0058] In some optional embodiments, upon receiving an access request from the graphics rendering pipeline unit in the graphics processor, a cache hit test can be performed on the cache buffer module based on the address parameters carried in the access request. If a cache hit occurs, the target data is directly returned. If a cache miss occurs, a target buffer entry can be allocated for the access request, and the target data can be retrieved from the local memory according to the address parameters and stored in the target buffer entry. The target data in the target buffer entry is then fed back to the graphics rendering pipeline unit. Based on this, the graphics rendering pipeline unit can perform graphics rendering based on the received target data. Furthermore, the storage type of the target buffer entry can be changed from buffer type to cache type, so that the target data can be used as alternative data for the cache buffer module's hit test.

[0059] In some optional embodiments, cache entries are used to store historical access data, while buffer entries are used to store stored data prefetched from local memory. In other words, the cache / buffer module includes two types of entries: cache entries and buffer entries. Cache entries primarily reduce the number of accesses to the graphics processor's local memory, while buffer entries primarily hide the access latency to local memory. Therefore, by setting two different types of entries in a single functional module, different functions can be achieved, providing both caching and latency hiding capabilities.

[0060] Therefore, in this embodiment of the present disclosure, a cache buffer module is provided in the graphics processor, including cache entries of type cache and buffer entries of type buffer. Cache entries are used to reduce the number of accesses to the local memory of the graphics processor, and buffer entries are used to hide the access latency to the local memory. Based on this, if an access request sent by the graphics rendering pipeline unit in the graphics processor does not hit any cache entry, an entry is selected from multiple entries as the target buffer entry corresponding to the access request; the target data corresponding to the access request obtained from the local memory of the graphics processor is stored in the target buffer entry; the target data in the target buffer entry is sent to the graphics rendering pipeline unit; and the storage type of the target buffer entry is changed from buffer type to cache type so that the target data can be used as alternative data for the hit test of the cache buffer module.

[0061] Therefore, the cache buffer module includes two types of entries: cache entries provide caching functionality to store historical access data, thereby reducing the number of accesses to local memory; and buffer entries provide buffering functionality to store data prefetched from local memory, thereby hiding the access latency to local memory. Thus, a single storage unit can provide two storage functions, offering high flexibility. Specifically, firstly, buffer entries allow data to be moved from local memory into the buffer entries in advance. For continuous accesses initiated by the graphics rendering pipeline unit, the corresponding data can be directly obtained from the buffer entries, making the access latency imperceptible to the graphics rendering pipeline unit. This hides the access latency to local memory and reduces local memory access latency. Firstly, it addresses the bandwidth overhead of the storage; secondly, when a cache miss occurs, an entry can be selected as the target buffer entry. Utilizing the pass-through forwarding capability of the buffer entry, it eliminates the need to wait for the target data to be fully filled from local storage. The data can be forwarded to the requester as soon as a portion of the target data arrives. Furthermore, it avoids the need to perform state adjustments and checks on the cache entry to overcome false hits and address conflicts, thus reducing hardware complexity. Thirdly, unlike related technologies that release the target data after transmission, this approach adjusts the target buffer entry into a cache entry. This allows for more effective utilization of the locality between access requests, further improving the data hit rate and ultimately enhancing the overall graphics rendering efficiency.

[0062] The data access method of this disclosure embodiment will be described in detail below.

[0063] In some optional embodiments, each entry in the cache buffer module includes a type field, a valid identifier field, a tag field, and a data field to characterize the storage type. The valid identifier field is used to store the identifier value of the valid identifier, the tag field is used to store some address data, counter values ​​(such as pseudo-least recently used (PLRU) counter values), and the data field is used to store the specific storage data.

[0064] Furthermore, the valid identifier includes a first identifier value to indicate validity and a second identifier value to indicate invalidity. When the valid identifier of an entry is the first identifier value, it indicates that the stored data in the entry is valid and usable. When the valid identifier of an entry is the second identifier value, it indicates that the stored data in the entry is invalid and cannot be used. Moreover, the storage type of the current entry is uncertain (i.e., the value of the type field is also invalid). It can be configured as a cached entry or a buffered entry as needed.

[0065] It should be noted that if a buffer entry is changed to an invalid entry, in order to ensure the buffer entry's ability to hide access latency, you can choose either an existing invalid entry or a cached entry and configure its storage type as a buffer type to ensure that the number of buffer entries is still the same as (or at least close to) the number of buffer entries indicated in the entry configuration information.

[0066] In some optional embodiments, the cache buffer module may further include a configuration unit, which can configure the number of cache entries and the number of buffer entries in the cache buffer module.

[0067] In some optional embodiments, the cache buffer module includes a configuration unit; correspondingly, the data access method may further include: sending acquired entry configuration information to the configuration unit; wherein the entry configuration information is used to instruct the configuration unit to configure the number of cache entries and the number of buffer entries in the cache buffer module; the entry configuration information is determined based on access latency information to local memory.

[0068] Local memory includes a private, low-speed buffer storage area based on video memory in the GPU architecture that is oriented towards a single thread or thread bundle. Access latency information includes latency duration (such as the number of latency clock cycles).

[0069] In some optional embodiments, if the configuration unit directly obtains the entry configuration information, it can determine the number of cached entries and the number of buffered entries in the cache buffer module based on the entry configuration information.

[0070] The item configuration information can be determined by the graphics processor based on at least one of historical task information, simulation data, statistical data, and empirical data, and this disclosure does not limit this.

[0071] It should be noted that cache entries are mainly used to reduce the number of accesses to the local memory of the graphics processor, while buffer entries are mainly used to hide the access latency to local memory. Their core functions are different. Based on this, when determining the entry configuration information, the access latency between the cache buffer module and the local memory can be considered, and it can be determined how many buffer entries need to be configured to cover up or hide the access latency, thereby determining the number of buffer entries to be configured, and the remaining entries can be configured as cache entries.

[0072] For example, the cache buffer module has 32 pre-set entries. According to the entry configuration information, 21 of these entries can be configured as buffer entries, and the remaining 11 entries can be configured as cache entries. The 21 buffer entries correspond exactly to the 21 partition delays between the cache buffer module and the main memory, and are used to hide this part of the access latency.

[0073] It should be noted that the above examples regarding the number of items are merely illustrative and are not intended to limit the scope of this disclosure.

[0074] Therefore, the configuration unit can flexibly determine the number of buffer entries in the cache buffer module, so that the number of buffer entries can meet the access latency of local memory and realize the local access latency of some data processing (such as data processing for the downstream processing stage of the current processing stage). At the same time, the remaining entries are configured as cache entries, and the cache function is provided through the cache entries. Considering that memory access tends to repeatedly access recently used addresses, access adjacent addresses, or access some related data, setting cache entries can make full use of the locality between access requests, improve the hit rate, and thus improve the overall processing efficiency.

[0075] In some optional embodiments, when the access latency information changes, the number of cache entries and buffer entries in the cache buffer module can be adaptively adjusted based on the updated access latency information so that the adjusted number of entries can better match the changed access latency.

[0076] In some optional embodiments, the data access method may include: upon obtaining updated entry configuration information, sending the updated entry configuration information to a configuration unit, so that the configuration unit adjusts the number of cached entries and the number of buffered entries in the cache buffer module according to the updated entry configuration information; wherein the updated entry configuration information is determined in response to a change in access latency information and based on the changed access latency information.

[0077] For example, if the updated access latency information indicates a shorter access latency, the number of buffer entries can be reduced proportionally. For instance, some buffer entries can be configured as cache entries proportionally.

[0078] For example, if the updated access latency information indicates an increased access latency, the number of buffer entries can be increased proportionally. For instance, a portion of the cached entries can be configured as buffer entries proportionally.

[0079] Therefore, in this embodiment of the present disclosure, the number of cache entries and buffer entries in the cache buffer module is not fixed, but can be flexibly adjusted to ensure that the buffer entries can always effectively hide access latency while still providing a certain level of caching functionality. In other words, this embodiment of the present disclosure can reuse existing graphics rendering architectures. For different access latencies, the number of the two types of entries in the cache buffer module can be configured or adjusted by the configuration unit to match the access latency, thereby effectively masking the access latency.

[0080] Figure 2This is a schematic diagram of a cache buffer module provided in an embodiment of this disclosure. Figure 2 As shown, the cache buffer module includes a control unit, a configuration unit, and multiple entries. Each entry includes a type field, a valid identifier field, a tag field, and a data field.

[0081] It should be noted that the positions of the control unit and the configuration unit are merely illustrative examples. The control unit and the configuration unit can be integrated inside the cache buffer module or placed outside the cache buffer module. This disclosure does not limit this.

[0082] In some optional embodiments, after receiving an access request, a cache hit test can be performed in the cache buffer module. The cache entries in the cache buffer module are used for the cache hit test.

[0083] In some optional embodiments, before selecting a target entry from multiple entries as the target buffer entry corresponding to the access request when the access request sent by the graphics rendering pipeline unit in the graphics processor fails to hit any cache entry, the data access method further includes: performing a cache hit test based on the cache entries that are in a valid state among the multiple entries to obtain the test result of the access request.

[0084] For example, if the access request carries an address parameter, a cache hit test can be performed on the cache entries in the cache buffer module that are in a valid state based on the address parameter, and the test result can be obtained.

[0085] In some optional embodiments, a cache hit test is performed based on cache entries that are in a valid state among multiple entries to obtain the test result of the access request. This includes: for any test entry among multiple entries, obtaining the identifier value of the valid identifier of the test entry; if the identifier value indicates that the test entry is in a valid state, obtaining the storage type of the test entry; if the storage type is a cache type, determining whether the test entry hits the access request based on the address parameters of the access request; if the test entry hits the access request, generating a test result indicating a cache hit; if the identifier value indicates that the test entry is in an invalid state, the storage type is a buffer type, or the test entry does not hit the access request, taking the next entry adjacent to the test entry as a new test entry for testing; and if the last test entry in the cache buffer module does not hit the access request, generating a test result indicating a cache miss.

[0086] For example, based on the storage order of multiple entries in the cache buffer module, the first entry among the multiple entries is taken as the entry to be tested, and the identifier value of the valid identifier of the entry to be tested is obtained; if the identifier value indicates that the entry to be tested is valid, the storage type of the entry to be tested is obtained; if the storage type is cache type, it is determined whether the entry to be tested hits the access request based on the address parameter; if the entry to be tested hits the access request, a test result indicating a cache hit is generated; if the identifier value indicates that the entry to be tested is invalid, or if the storage type is cache type, or if the entry to be tested does not hit the access request, it is checked whether there is a next entry adjacent to the entry to be tested; if there is, the next entry adjacent to the entry to be tested is taken as a new entry to be tested, and the operation of obtaining the identifier value of the valid identifier of the entry to be tested is returned; if there is no entry, a test result indicating a cache miss is generated.

[0087] For example, when performing a cache hit test according to the storage order of multiple entries in the cache buffer module, for any entry to be tested, the identifier value of the valid identifier of the entry to be tested can be obtained; if the identifier value indicates that the entry to be tested is invalid, if there is a next entry adjacent to the entry to be tested, then the next entry adjacent to the entry to be tested is used as a new entry to be tested; if there is no next entry, a test result indicating a cache miss can be generated; if the identifier value indicates that the entry to be tested is valid, the storage type of the entry to be tested is obtained; if the storage type is cache type, the address parameter is used to determine whether the entry to be tested hits the access request; if the entry to be tested hits the access request, a test result indicating a cache hit is generated; if the access request is missed, or if the storage type is buffer type, if there is a next entry adjacent to the entry to be tested, then the next entry adjacent to the entry to be tested is used as a new entry to be tested; if there is no next entry, a test result indicating a cache miss can be generated. The address parameter is used to accurately locate the storage location of the target data.

[0088] Therefore, the next entry adjacent to the entry to be tested can be used as a new entry to be tested. Furthermore, if the last entry to be tested in the cache buffer module fails to trigger an access request, a test result representing a cache miss can be generated. Based on this, it can be ensured that an accurate test result can be given even when the last entry in the cache buffer module fails to trigger an access request.

[0089] Therefore, when conducting cache hit testing, invalid entries can be filtered out first by using the valid identifier field, thus quickly filtering out invalid entries without having to perform addressing or other processing based on address parameters in invalid entries. This improves processing efficiency, shortens the time for executing cache hit detection, and, by performing cache hit testing item by item, can effectively reduce the possibility of missing a certain entry, thereby obtaining accurate test results.

[0090] The following is combined Figure 3 The process of cache hit detection is illustrated by example. Figure 3 This is a schematic diagram illustrating a cache hit test process provided in an embodiment of this disclosure. Figure 3 As shown, the process may include the following steps:

[0091] Step S301: Receive an access request sent by the graphics rendering pipeline unit in the graphics processor.

[0092] Step S302: Select the entry with entry index value i of 1 in the cache buffer module as the entry to be tested.

[0093] Where i is the entry index value, used to represent the storage order of multiple entries in the cache buffer module, and i is an integer greater than or equal to 1.

[0094] Step S303: Obtain the identifier value of the valid identifier of the item to be tested.

[0095] Step S304: Determine whether the item to be tested is invalid based on the identifier value of the valid identifier of the item to be tested.

[0096] If the flag value indicates that the item to be tested is invalid, proceed to step S305; if the flag value indicates that the item to be tested is valid, proceed to step S308.

[0097] Step S305: Update the entry index value i to i+1.

[0098] Step S306: Determine whether the updated entry index value i+1 is valid.

[0099] If the updated entry index value i+1 is valid, proceed to step S303; if the updated entry index value i+1 is invalid, proceed to step S307.

[0100] For example, if the total number of entries in the cache module is N, then if i+1≤N, it means the updated entry index value i+1 is valid; if i+1>N, it means the updated entry index value i+1 exceeds the total number of entries, and therefore the updated entry index value i+1 is invalid. Here, N is an integer greater than 1.

[0101] Therefore, we can detect whether there is a next entry adjacent to the entry to be tested by using the entry index value, so that cache hit testing can be carried out in an orderly and comprehensive manner.

[0102] Step S307: Generate and return test results representing cache misses.

[0103] Step S308: Determine whether the entry to be tested is a cached entry.

[0104] If the item to be tested is a cached item, proceed to step S309; ​​if the item to be tested is not a cached item, proceed to step S305.

[0105] Step S309: Determine whether the entry to be tested matches the access request based on the address parameters carried in the access request.

[0106] If the access request to be tested is met, proceed to step S310; if the access request to be tested is not met, proceed to step S305.

[0107] Step S310: Generate and return test results representing the hit cache, with the test results carrying the hit target data.

[0108] In some alternative embodiments, a second entry mask may be maintained within the control unit, through which cache hit tests can also be performed.

[0109] In some optional embodiments, multiple entries correspond to a second entry mask, which includes a second mask value corresponding one-to-one with each entry. The second mask value corresponding to each entry is a third value or a fourth value. The third value is used to indicate invalid entries and buffered entries, and the fourth value is used to indicate cached entries. Accordingly, a cache hit test is performed based on the cached entries that are in a valid state among the multiple entries to obtain the test result of the access request. This includes: for any entry to be tested among the multiple entries, determining the second target mask value corresponding to the entry to be tested according to the second entry mask; if the second target mask value is the fourth value, determining whether the entry to be tested hits the access request according to the address parameters of the access request; if the entry to be tested hits the access request, generating a test result indicating a cache hit; if the second target mask value is the third value or the entry to be tested does not hit the access request, taking the next entry adjacent to the entry to be tested as a new entry to be tested; and if the last entry to be tested in the cache buffer module does not hit the access request, generating a test result indicating a cache miss.

[0110] Therefore, the second entry mask can accurately and intuitively reflect the status and storage type of each entry. Based on this, when conducting cache hit tests, the second entry mask can be used to filter valid cache entries in order to determine the cache data that can participate in the test.

[0111] In some optional embodiments, based on the storage order of multiple entries in the cache buffer module, the first entry among the multiple entries is taken as the entry to be tested, and the second target mask value corresponding to the entry to be tested is determined according to the second entry mask; if the second target mask value is the fourth value, it is determined whether the entry to be tested hits the access request according to the address parameter; if the entry to be tested hits the access request, a test result representing a cache hit is generated; if the second target mask value is the third value or the entry to be tested does not hit the access request, it is checked whether there is a next entry adjacent to the entry to be tested; if there is, the next entry adjacent to the entry to be tested is taken as the new entry to be tested, and the operation of determining the second target mask value corresponding to the entry to be tested according to the second entry mask is returned; if there is no entry, a test result representing a cache miss is generated.

[0112] Therefore, for each entry, there is a corresponding second mask value. If the entry is invalid or a buffered entry, its second mask value is the third value; if the entry is a cached entry, its second mask value is the fourth value. Based on this, when performing a cache hit test, if the second target mask value corresponding to the entry to be tested is the third value, it means that the entry to be tested is invalid (i.e., an invalid entry) or a buffered entry, and the next entry can be used as a new entry to be tested for a hit. If the second target mask value corresponding to the entry to be tested is the fourth value, it means that the entry to be tested is a valid cached entry, and the address parameter can be used to determine whether the entry to be tested has been hit. If it has been hit, the hit target data is returned; if it has not been hit, the next entry is used as a new entry to be tested for a hit. This process continues until the last entry is still not hit, at which point a test result indicating a hit is generated.

[0113] It should be noted that when the storage type or validity status of any entry changes, the second entry mask must be updated synchronously to ensure the accuracy of the second entry mask, so that cache hit tests can be performed accurately through the second entry mask.

[0114] It should also be noted that since the data volume of the second entry mask is small, it only requires a small amount of storage space to accurately reflect the storage type and validity status of each entry. Therefore, the cache hit test can be performed accurately and quickly using the second entry mask to obtain the corresponding test results.

[0115] As mentioned earlier, if the test results indicate that the cache has not been hit, it is necessary to select one entry from multiple entries as the target cache entry corresponding to the access request.

[0116] In some optional embodiments, selecting an entry from multiple entries as the target buffer entry corresponding to the access request includes: determining whether there is an invalid entry among the multiple entries based on the identifier value of the valid identifier of each entry; if there is, selecting an entry from the invalid entries as the target buffer entry corresponding to the access request; if there is no invalid entry, selecting an entry from the cache entries whose storage type is cache type as the target buffer entry.

[0117] In other words, for any pending entry among multiple entries, obtain the valid identifier value of the pending entry; if the identifier value indicates that the pending entry is invalid, then the pending entry can be used as the target buffer entry; if the identifier value indicates that the pending entry is valid, then the storage type of the pending entry can be obtained; if the storage type is cache type, add the pending entry to the candidate cache entry list; if the storage type is buffer type, treat the next entry adjacent to the pending entry as a new pending entry; if the valid identifier of the last pending entry in the cache buffer module is valid, select an entry from the candidate cache entry list as the target buffer entry.

[0118] Therefore, it can be seen that an entry can be selected from multiple entries in the cache buffer module to carry the target data obtained from local memory, thereby returning the target data to the graphics rendering pipeline unit and ensuring that the graphics rendering pipeline unit can perform subsequent data processing based on the target data. Moreover, when selecting a target buffer entry, invalid entries are preferred. The data stored in these invalid entries is invalid and can be released at any time without affecting the data hit rate.

[0119] It should be noted that there are two scenarios when selecting an entry as the target buffer entry. The first is selecting an invalid entry, including entries containing expired data. The second is selecting a valid cached entry. Regardless of the scenario, since the target buffer entry's storage type will be subsequently converted to a cached type, the number of buffer entries in the cache buffer module will not be affected, and therefore, the cache buffer module's ability to mask access latency will not be affected. Furthermore, to ensure that the number of buffer entries matches the access latency, the target buffer entry can be switched back from a buffer entry to a cached entry, while retaining the target data stored within it.

[0120] In other words, because the number of buffer entries is related to the access latency to be hidden, it is necessary to ensure that the number of buffer entries remains constant to guarantee the cache buffer module's ability to hide access latency. The number of cache entries, however, is relatively more flexible. There are two scenarios when selecting an entry as the target buffer entry: First, the selected entry is itself a cache entry; since the target buffer entry will be converted back to a cache entry later, this will not affect the number of buffer entries. Second, an invalid entry is selected; invalid entries are not valid buffer entries, so selecting this type of entry will not affect the existing number of buffer entries. In short, regardless of the scenario, selecting the target buffer entry will not affect the number of buffer entries in the cache buffer module, and therefore will not affect the cache buffer module's ability to hide access latency.

[0121] Furthermore, when sending the target data in the target buffer entry to the graphics rendering pipeline unit, considering that the target data is recently accessed data and has a high probability of being accessed repeatedly in the near future, the storage type of the target buffer entry is changed from buffer type to cache type, and the target data stored therein is retained. If a subsequent access request for the target data is initiated, the hit data (i.e., the target data) can be directly fed back to the graphics rendering pipeline unit by hitting the cache, without having to read the corresponding data from the local memory. The hit rate is high and the access efficiency is also high, thus improving the overall graphics rendering efficiency.

[0122] The following is combined Figure 4 The process of selecting a target buffer entry is illustrated by way of example. Figure 4 This is a schematic diagram of a process for selecting a target buffer entry, provided as an embodiment of this disclosure. Figure 4 As shown, the process may include the following steps:

[0123] Step S401: The entry with entry index value i of 1 in the cache buffer module is taken as the entry to be processed.

[0124] Where i is an integer greater than or equal to 1.

[0125] Step S402: Obtain the identifier value of the valid identifier of the entry to be processed.

[0126] Step S403: Determine whether the entry to be processed is invalid based on the identifier value of the valid identifier of the entry to be processed.

[0127] If the flag value indicates that the entry to be processed is invalid, proceed to step S404; if the flag value indicates that the entry to be processed is valid, proceed to step S405.

[0128] Step S404: The entry to be processed is used as the target buffer entry.

[0129] Step S405: Determine whether the entry to be processed is a cached entry.

[0130] If the storage type is cache type, proceed to step S406; if the storage type is not cache type, proceed to step S407.

[0131] Step S406: Add the entry to be processed to the candidate cache entry list.

[0132] After adding the pending entries to the candidate cache entry list, S407 continues to be executed.

[0133] Step S407: Update the entry index value i to i+1.

[0134] Step S408: Determine whether the updated entry index value i+1 is valid.

[0135] If the updated entry index value i+1 is valid, proceed to step S402; if the updated entry index value i+1 is invalid, proceed to step S409.

[0136] For example, if the total number of entries in the cache module is N, then if i+1≤N, it means the updated entry index value i+1 is valid; if i+1>N, it means the updated entry index value i+1 exceeds the total number of entries, and therefore the updated entry index value i+1 is invalid. Here, N is an integer greater than 1.

[0137] Step S409: Select an entry from the candidate cache entry list as the target cache entry.

[0138] In some alternative embodiments, a first entry mask may be maintained within the control unit, through which the allocation of target buffer entries may also be performed.

[0139] In some optional embodiments, multiple entries correspond to a first entry mask, which includes a first mask value corresponding to each entry. The first mask value corresponding to each entry is a first value or a second value. The first value is used to indicate invalid entries and cached entries, and the second value is used to indicate buffered entries. Selecting an entry from multiple entries as the target buffered entry corresponding to the access request includes: for any pending entry from multiple entries, determining the first target mask value corresponding to the pending entry based on the first entry mask; if the first target mask value is the first value, obtaining the identifier value of the valid identifier of the pending entry; if the identifier value indicates that the pending entry is invalid, using the pending entry as the target buffered entry corresponding to the access request; if the identifier value indicates that the pending entry is valid, adding the pending entry to the candidate cached entry list; if the first target mask value is the second value, processing the next entry adjacent to the pending entry as a new pending entry; and if the valid identifier of the last pending entry in the cache buffer module is valid, selecting an entry from the candidate cached entry list as the target buffered entry.

[0140] Therefore, the first entry mask can accurately and intuitively reflect the status and storage type of each entry. Based on this, when selecting target buffer entries, invalid entries or valid cache entries can be filtered out as target buffer entries to store target data without affecting the number of buffer entries.

[0141] In some optional embodiments, based on the storage order of multiple entries in the cache buffer module, the first entry among the multiple entries is taken as the entry to be processed, and the first target mask value corresponding to the entry to be processed is determined according to the first entry mask; if the first target mask value is a first value, the identifier value of the valid identifier of the entry to be processed is obtained; if the identifier value indicates that the entry to be processed is invalid, the entry to be processed is taken as the target buffer entry corresponding to the access request; if the identifier value indicates that the entry to be processed is valid, the entry to be processed is added to the candidate cache entry list, and it is checked whether the entry to be processed is the last entry of the cache buffer module; if the first target mask value is a second value, it is checked whether the entry to be processed is the last entry of the cache buffer module; if not, the next entry adjacent to the entry to be processed is taken as the new entry to be processed, and the operation of determining the first target mask value corresponding to the entry to be processed according to the first entry mask is returned; if yes, an entry is selected from the candidate cache entry list as the target buffer entry.

[0142] For example, for any entry to be processed, a first target mask value corresponding to the entry to be processed can be determined according to a first entry mask; if the second target mask value is a first value, the identifier value of the valid identifier of the entry to be processed is obtained; if the identifier value indicates that the entry to be processed is an invalid entry, the entry to be processed is used as a target buffer entry; if the identifier value indicates that the entry to be processed is a valid entry, the entry to be processed can be added to the candidate cache entry list, and it can be detected whether the entry to be processed is the last entry of the cache buffer module; if not, the next entry adjacent to the entry to be processed is processed as a new entry to be processed; if so, an entry is selected from the candidate cache entry list as a target buffer entry; furthermore, if the second target mask value is a second value, it can also be detected whether the entry to be processed is the last entry of the cache buffer module; if not, the next entry adjacent to the entry to be processed is processed as a new entry to be processed; if so, an entry is selected from the candidate cache entry list as a target buffer entry.

[0143] In other words, for the last pending entry of the cache buffer module, if the first target mask value corresponding to the pending entry is a first value and the corresponding valid identifier value indicates that the pending entry is in a valid state, or if the first target mask value corresponding to the pending entry is a second value, then an entry is selected from the candidate cache entry list as the target buffer entry.

[0144] It should be noted that before each target buffer entry allocation, the historical candidate cache entry list can be deleted or initialized to avoid the historical candidate cache entry list affecting the current processing. The historical candidate cache entry list refers to the list of candidate cache entries generated before the current moment.

[0145] Therefore, for each entry, there is a corresponding first mask value. If the entry is invalid (i.e., it is an invalid entry) or is a cached entry, its first mask value is the first value; if the entry is a cached entry, its first mask value is the second value. Based on this, when allocating target cache entries, if the first target mask value of the entry to be processed is the first value, it indicates that the entry to be processed is either invalid or a cached entry. Therefore, it is necessary to further determine whether the entry to be processed is invalid or a cached entry. If it is invalid, it can be directly selected as the target cache entry. If it is a cached entry, it can be added to the candidate cache entry list, and the next entry can be processed. Conversely, if the first target mask value of the entry to be processed is the second value, it indicates that the entry to be processed is a cached entry, and the next entry can be directly processed as a new entry to be processed. This process continues until the last entry is still not invalid, in which case a cached entry is selected from the candidate cache entry list as the target cache entry.

[0146] It should be noted that since the first entry mask has a small data volume, it only requires a small amount of storage space to accurately reflect the storage type and validity status of each entry. Therefore, the allocation of target buffer entries can be performed accurately and quickly using the first entry mask.

[0147] In some optional embodiments, multiple entries correspond to a first entry mask, which includes a first mask value corresponding one-to-one with each entry. The first mask value for each entry is either a first value or a second value. The first value indicates invalid entries and cached entries, and the second value indicates buffered entries. Accordingly, selecting an entry from the multiple entries as the target buffer entry corresponding to the access request includes: for any pending entry among the multiple entries, determining the first target mask value corresponding to the pending entry based on the first entry mask; if the first target mask value is the first value, selecting the pending entry as the target buffer entry corresponding to the access request. Conversely, if the first target mask value corresponding to the pending entry is the second value, then the pending entry is not selected as the target buffer entry.

[0148] For example, for any one of the multiple entries to be processed, the first target mask value corresponding to the entry to be processed can be determined firstly based on the first entry mask. If the first target mask value corresponding to the entry to be processed is a first value, the entry to be processed can be used as a target buffer entry. If the first target mask value corresponding to the entry to be processed is a second value, the next entry adjacent to the entry to be processed can be used as a new entry to be processed.

[0149] Therefore, when the first target mask determines that the entry to be processed is invalid or belongs to the cached entry (i.e., when the first target mask value is the first value), the entry to be processed can be directly used as the target buffer entry without having to perform filtering on subsequent entries. This makes it easier and more efficient to select the target buffer entry and improves the overall processing efficiency.

[0150] It should be noted that when the storage type or validity status of any entry changes, the first entry mask must be updated synchronously to ensure the accuracy of the first entry mask, so that the target buffer entry can be quickly selected through the first entry mask.

[0151] Furthermore, if there are no invalid entries in the cache buffer module and an invalid entry cannot be selected as the target cache entry, then a cache entry can be selected from the candidate cache entry list as the target cache entry.

[0152] In some optional embodiments, selecting a cache entry as the target cache entry from the candidate cache entry list can be based on a preset selection strategy. The preset selection strategy includes at least one of a random selection strategy and a Least Recently Used (LRU) strategy. Furthermore, the preset selection strategy can be determined based on the current task type, data processing requirements, etc.

[0153] For example, when the preset selection strategy is a random selection strategy, a cache entry can be randomly selected from the list of candidate cache entries, and its storage type can be changed from cache type to buffer type to obtain the target buffer entry.

[0154] For example, if the preset selection strategy is the least recently used strategy, it can record the time when each entry was last accessed. Based on this, the least recently accessed cache entry can be selected from the candidate cache entry list, and its storage type can be changed from cache type to buffer type to obtain the target buffer entry.

[0155] It should be noted that the above examples of preset selection strategies are merely illustrative and are not intended to limit the scope of this disclosure.

[0156] Therefore, by selecting an appropriate preset selection strategy, the cache entry that best matches the current requirement can be chosen from the candidate cache entries as the target cache entry. For example, if the current data processing requirement tends to access duplicate data or related data, the LRU strategy can be selected to improve the cache hit rate, thereby improving access efficiency. Conversely, if the current data processing requirement does not tend to access duplicate data, a more convenient random selection strategy can be chosen, thus eliminating the need to maintain information such as the last access time of each entry.

[0157] In summary, the original entry selected as the target buffer entry can be an invalid entry or a cached entry. Once selected, it needs to be configured as a buffer type so that the target data can be stored in that target buffer entry. Furthermore, to fully utilize the locality of access requests and improve the hit rate, the target buffer entry can be changed from a buffer type to a cache type.

[0158] In some optional embodiments, any buffer entry has pass-through forwarding capability, and correspondingly, the target buffer entry also has pass-through forwarding capability. In other words, the buffer entry does not need to store the complete data payload in its own storage domain. After receiving partial data, it can use this partial data to quickly match through routing, address indexing, etc., thereby skipping the local temporary storage and cache residency process and forwarding the received data stream through the directly established transmission path.

[0159] In some optional embodiments, sending target data in a target buffer entry to a graphics rendering pipeline unit includes: in response to receiving a portion of the target data obtained from local memory based on the target buffer entry, forwarding the target data to the graphics rendering pipeline unit based on the obtained portion of the data.

[0160] Therefore, when using target buffer entries to feed back target data, the pass-through capability of the buffer entries can be utilized. It is not necessary to receive and cache the complete data packet (i.e., target data). Only partial data (such as header control information, address identifiers, routing fields, and other key data) needs to be collected. After using this partial data to complete path matching, forwarding can be initiated, achieving simultaneous reception and forwarding, resulting in high access efficiency. Furthermore, while forwarding target data, the complete target data can be asynchronously written to the target buffer entry in the background. This allows the target data within the target buffer entry to be used to improve cache hit rate after it is subsequently converted into a cache entry.

[0161] It should be noted that if the target data is written to the cache entry when the cache is not hit, the target data needs to be written to the cache entry to complete the storage, and then it can be received by the requester after scheduling, reading, forwarding and other operations. There are multiple delays in writing, dwelling and reading, which limits the access efficiency.

[0162] As mentioned earlier, after returning the target data from the target buffer entry to the graphics rendering pipeline unit, the storage type of the target buffer entry can be changed from buffer type to cache type. Based on this, the previously written target data can participate in the hit test as cache data. Considering the locality between access requests, the cache hit rate can be improved, effectively reducing bandwidth overhead and system power consumption.

[0163] For example, access request 1 indicates the need to read the coordinate data of vertex 1. The data retrieved from local memory and stored in the target cache entry based on access request 1 can include not only the coordinate data of vertex 1, but also the attribute data of vertex 1, and / or, the coordinate and attribute data of several vertices adjacent to vertex 1. Subsequently, this target cache entry can be adjusted to a cache type, resulting in cache entry L1. When performing a cache hit, a data hit test can be performed on cache entry L1. This approach is adopted primarily because if a piece of data has been recently accessed, then that data or related data is more likely to be accessed in the future. Therefore, through this process, when access request 2 indicates the need to read the attribute data of vertex 1 or the data of its adjacent vertices, the aforementioned cache entry L1 can be directly hit, eliminating the need to read data from local memory, thus reducing the number of accesses to local memory and improving data access efficiency.

[0164] Therefore, it can be seen that the cache area in the cache buffer module can effectively cache previous access data, thereby effectively accelerating access efficiency when there are access requests with the same address.

[0165] Figure 5 This is a flowchart illustrating a data access method provided in an embodiment of this disclosure. Figure 5 As shown, the data access method may include the following steps:

[0166] Step S501: Receive an access request sent by the graphics rendering pipeline unit in the graphics processor.

[0167] Step S502: Based on the address parameters carried in the access request, perform a cache hit test in the cache buffer module to obtain the test results.

[0168] Step S503: If the test result indicates a hit, return the hit target data to the graphics rendering pipeline unit.

[0169] Step S504: If the test result indicates a no-hit, select one entry from multiple entries as the target buffer entry corresponding to the access request.

[0170] Step S505: Initiate a read request to the local memory of the graphics processor according to the address parameters carried in the access request, and receive the target data returned by the local memory.

[0171] Step S506: Fill the target data into the target buffer entry.

[0172] Step S507: Return the data in the target buffer entry to the graphics rendering pipeline unit.

[0173] Step S508: Switch the storage type of the target buffer entry from buffer type to cache type.

[0174] Figure 6 This is a schematic diagram illustrating the processing steps of a data access method provided in an embodiment of this disclosure. For example... Figure 6 As shown, the task generation unit can receive drawing instructions sent by the user, split the task to be executed as indicated by the drawing instructions into multiple task packages, and send these task packages to downstream processing units (such as the first shader engine) for corresponding processing. The drawing instructions can include at least one of Draw instructions and Dispatchmesh instructions. Draw instructions are for the VTG rendering pipeline, and Dispatchmesh instructions are for the mesh shading rendering pipeline.

[0175] Furthermore, such as Figure 6As shown in the diagram, the first shader engine can perform user-configured first specific shader processing on the received task package. The data flow of this processing mainly corresponds to the solid lines connecting the task generation unit to the on-chip storage unit, the shader task construction unit and the task control unit, and the shader execution unit and the local memory. The second shader engine can perform user-configured second specific shader processing on the received task package. The data flow of this processing mainly corresponds to the dashed lines in the diagram. The shader task construction unit can receive shader tasks sent from the first and second shader engines (and possibly from the pixel shader; the data flow of the processing from the pixel shader mainly corresponds to the dotted lines in the diagram), allocate corresponding resources to them, and send the shader tasks to the shader execution unit. Additionally, it can synchronously send corresponding task information to the task control unit. The task information may include… The storage location and format of the color results; the shader execution unit receives and executes the shader tasks from the shader task construction unit to obtain the corresponding color results; the task control unit can receive task information sent from the shader task construction unit to accurately control and process the color tasks from the first shader engine and the second shader engine; for example, the task control unit can send the color results of the first stage executed by the first shader engine to the tessellation and mesh coloring generation unit to perform tessellation and mesh coloring processing, and send the processing results to the second shader engine to perform the second stage of coloring processing (corresponding to the dashed line part connecting the task control unit, the tessellation and mesh coloring generation unit and the second shader engine in the figure); for example, the task control unit can send the pixel coloring instructions of the pixel shader to the shader task construction unit to execute the corresponding pixel coloring processing. The first and second shader engines can correspond to different shader combinations, including vertex shader (VS), hull shader (HS), domain shader (DS), geometry shader (GS), amplifier shader (AS), and mesh shader (MS), etc.

[0176] Furthermore, the processing results and intermediate results of the shader execution unit can be stored in local memory, and the task control unit is equipped with a cache buffer module. On the one hand, at least a portion of the data in the local memory can be temporarily stored in the cache buffer module, realizing a caching function for local memory. On the other hand, the cache buffer module can utilize buffer entries to achieve a buffering function, hiding access latency. In other words, during the access latency phase, other access requests can be processed, and other data processing can be performed, thereby hiding the latency caused by the access operation.

[0177] For example, if the local memory and the shader are located in the same partition, the processing units that perform downstream rendering operations (e.g., pruning and culling units, rasterization units, pixel operation units, etc.) are relatively far away from the local memory, which will result in a large access delay. For these processing units, the data access method of the present disclosure embodiment can hide the cross-partition access delay and reduce the bandwidth overhead of the local memory.

[0178] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0179] In addition, this disclosure also provides a data access device, a graphics processor, an electronic device, and a computer-readable storage medium, all of which can be used to implement any of the data access methods provided in this disclosure. The corresponding technical solutions and descriptions are described in the corresponding section of the method and will not be repeated here.

[0180] Figure 7 This is a block diagram of a data access device provided in an embodiment of the present disclosure.

[0181] Reference Figure 7 This disclosure provides a data access device 700, which can be configured in a graphics processor to control a cache buffer module. The cache buffer module includes multiple entries, including cache entries of storage type cache and buffer entries of storage type buffer. The data access device 700 may include the following modules.

[0182] Selection module 701 is used to select one entry from multiple entries as the target buffer entry corresponding to the access request when the access request sent by the graphics rendering pipeline unit in the graphics processor does not hit any cache entry.

[0183] The storage module 702 is used to store the target data corresponding to the access request obtained from the local memory of the graphics processor into the target buffer entry.

[0184] The sending module 703 is used to send the target data in the target buffer entry to the graphics rendering pipeline unit.

[0185] Adjustment module 704 is used to adjust the storage type of the target buffer entry from buffer type to cache type, so that the target data can be used as alternative data for hit tests against the cache buffer module.

[0186] In this embodiment, a cache buffer module is provided in the graphics processor. The cache buffer module includes entries of two storage types. Cache entries can provide caching functionality to store historical access data, thereby reducing the number of accesses to local memory. Buffer entries can provide buffering functionality to store data prefetched from local memory, thereby hiding the access latency to local memory. Thus, two storage functions can be provided through a single storage unit, offering high flexibility. Specifically, firstly, by using buffer entries, data can be moved from local memory into the buffer entries in advance. For continuous accesses initiated by the graphics rendering pipeline unit, the corresponding data can be directly obtained from the buffer entries, making the graphics rendering pipeline unit unaware of the access latency, thereby hiding the access to local memory. Firstly, it reduces latency and lowers the bandwidth overhead of local memory. Secondly, when a cache miss occurs, an entry can be selected as the target buffer entry. Utilizing the pass-through forwarding capability of buffer entries, it eliminates the need to wait for the target data to be fully filled from local memory. The data can be forwarded to the requester as soon as a portion of the target data arrives. Furthermore, it avoids the need to perform state adjustments and checks on cache entries to overcome false hits and address conflicts, thus reducing hardware complexity. Thirdly, unlike related technologies that release the target data after transmission, this approach adjusts the target buffer entry into a cache entry. This allows for more effective utilization of locality between access requests, further improving the data hit rate and ultimately enhancing overall graphics rendering efficiency.

[0187] Each module in the aforementioned data access device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can invoke and execute the operations corresponding to each module.

[0188] Figure 8 This is a block diagram of a graphics processor provided in an embodiment of the present disclosure.

[0189] Reference Figure 8 This disclosure provides a graphics processor 800, which includes at least one processing unit 810, a local memory 820, at least one cache buffer module 830, and a control unit 840 for controlling the cache buffer module.

[0190] The control unit 840 is used to execute the data access method described in any of the embodiments of this disclosure, the processing unit is a functional unit for performing core data processing, and the local memory 820 is used to provide the main storage function.

[0191] In this embodiment of the disclosure, a cache buffer module is provided in the graphics processor, including cache entries of the cache type and buffer entries of the buffer type. Cache entries can provide caching functions, and buffer entries can provide buffering functions, so that two storage functions can be provided through a single storage unit, which is highly flexible. In addition, buffer entries can hide the access latency to local memory, thereby reducing the bandwidth overhead of local memory. Finally, cache entries can provide caching functions. Therefore, by using cache entries, the locality between access requests can be effectively utilized to improve the data hit rate, thereby improving the overall graphics rendering processing efficiency.

[0192] Figure 9 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0193] Reference Figure 9 This disclosure provides an electronic device comprising: at least one processor 901, at least one memory 902, and one or more I / O interfaces 903; wherein the at least one processor includes a graphics processor, and the memory 902 stores one or more computer programs executable by the at least one graphics processor, the one or more computer programs being executed by the at least one graphics processor to enable the at least one graphics processor to perform the data access method described above.

[0194] Figure 10 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0195] Reference Figure 10 This disclosure provides an electronic device that includes multiple processing cores 1001 and an on-chip network 1002. The multiple processing cores 1001 are all connected to the on-chip network 1002. Among the multiple processing cores 1001 is a graphics processing core. The on-chip network 1002 is used to interact with data between the multiple processing cores and external data.

[0196] One or more processing cores 1001 store one or more instructions, and the one or more instructions are executed by one or more processing cores 1001 to enable one or more processing cores 1001 to perform the above-described data access method.

[0197] The modules in the aforementioned electronic devices can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0198] This disclosure also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a graphics processor, implements the data access method described above. The computer-readable storage medium may be volatile or non-volatile.

[0199] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in the graphics processor of an electronic device, the graphics processor in the electronic device executes the above-described data access method.

[0200] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0201] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable program instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0202] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0203] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0204] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0205] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0206] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0207] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0208] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0209] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A data access method, characterized in that, A control unit applied in a graphics processor for controlling a cache buffer module, the cache buffer module including multiple entries, the multiple entries including cache entries of storage type cache and buffer entries of storage type buffer, the method comprising: If an access request sent by the graphics rendering pipeline unit in the graphics processor does not hit any of the cache entries, an entry is selected from the plurality of entries as the target buffer entry corresponding to the access request; The target data corresponding to the access request, which is obtained from the local memory of the graphics processor, is stored in the target buffer entry; Send the target data in the target buffer entry to the graphics rendering pipeline unit; The storage type of the target buffer entry is adjusted from the buffer type to the cache type, so that the target data can be used as alternative data for a hit test against the cache buffer module.

2. The method according to claim 1, characterized in that, The cache buffer module further includes a configuration unit; the method further includes: The acquired entry configuration information is sent to the configuration unit; The entry configuration information is used to instruct the configuration unit to configure the number of cache entries and the number of buffer entries in the cache buffer module; the entry configuration information is determined based on the access latency information of the local memory.

3. The method according to claim 2, characterized in that, The method further includes: Upon receiving updated entry configuration information, the updated entry configuration information is sent to the configuration unit, so that the configuration unit adjusts the number of cache entries and the number of buffer entries in the cache buffer module according to the updated entry configuration information. The updated entry configuration information is determined in response to a change in the access delay information and based on the changed access delay information.

4. The method according to any one of claims 1 to 3, characterized in that, Selecting one entry from the plurality of entries as the target buffer entry corresponding to the access request includes: Based on the identifier value of the valid identifier of each entry, determine whether there are any invalid entries among the multiple entries; If it exists, select one entry from the invalid entries as the target buffer entry corresponding to the access request; If it does not exist, then select an entry from the cache entries of the storage type of cache as the target buffer entry.

5. The method according to claim 4, characterized in that, Multiple entries correspond to a first entry mask, the first entry mask includes a first mask value that corresponds one-to-one with each entry, the first mask value corresponding to each entry is a first value or a second value, the first value is used to indicate invalid entries and cached entries, and the second value is used to indicate buffered entries; Selecting one entry from the plurality of entries as the target buffer entry corresponding to the access request includes: For any one of the multiple entries to be processed, the first target mask value corresponding to the entry to be processed is determined according to the first entry mask; If the first target mask value is the first value, obtain the identifier value of the valid identifier of the entry to be processed; If the identifier value indicates that the entry to be processed is invalid, the entry to be processed is used as the target buffer entry corresponding to the access request; if the identifier value indicates that the entry to be processed is valid, the entry to be processed is added to the candidate cache entry list. If the first target mask value is the second value, the next entry adjacent to the entry to be processed will be treated as a new entry to be processed. If the valid identifier of the last pending entry in the cache buffer module is valid, an entry is selected from the list of candidate cache entries as the target cache entry.

6. The method according to claim 4, characterized in that, Multiple entries correspond to a first entry mask, the first entry mask includes a first mask value that corresponds one-to-one with each entry, the first mask value corresponding to each entry is a first value or a second value, the first value is used to indicate invalid entries and cached entries, and the second value is used to indicate buffered entries; Selecting one entry from the plurality of entries as the target buffer entry corresponding to the access request includes: For any one of the multiple entries to be processed, a first target mask value corresponding to the entry to be processed is determined based on the first entry mask; When the first target mask value is the first value, the entry to be processed is used as the target buffer entry corresponding to the access request.

7. The method according to any one of claims 1 to 3, characterized in that, The cache entry is used to store historical access data, and the buffer entry is used to store storage data prefetched from the local memory. Each of the buffer entries has pass-through forwarding capability. Sending the target data in the target buffer entry to the graphics rendering pipeline unit includes: In response to receiving a portion of the target data obtained from the local memory based on the target buffer entry, the target data is forwarded to the graphics rendering pipeline unit according to the obtained portion of the data.

8. The method according to any one of claims 1 to 3, characterized in that, Before selecting a target entry from among the multiple entries as the target buffer entry corresponding to the access request when the access request sent by the graphics rendering pipeline unit in the graphics processor fails to hit any of the cache entries, the method further includes: A cache hit test is performed on the cached entries that are in a valid state among the multiple entries to obtain the test result of the access request.

9. The method according to claim 8, characterized in that, The cache hit test is performed based on the cache entries that are in a valid state among the multiple entries to obtain the test result of the access request, including: For any one of the multiple entries to be tested, obtain the identifier value of the valid identifier of the entry to be tested; If the identifier value indicates that the item to be tested is in a valid state, then obtain the storage type of the item to be tested; When the storage type is a cache type, it is determined whether the entry to be tested matches the access request based on the address parameter of the access request; If the access request is matched by the entry to be tested, a test result representing a cache hit is generated; If the identifier value indicates that the entry to be tested is invalid, the storage type is a buffer type, or the entry to be tested does not match the access request, the next entry adjacent to the entry to be tested will be used as a new entry to be tested. In addition, if the last entry to be tested in the cache buffer module fails to match the access request, a test result representing a cache miss is generated.

10. The method according to claim 8, characterized in that, Multiple entries correspond to a second entry mask, the second entry mask includes a second mask value that corresponds one-to-one with each entry, and the second mask value corresponding to each entry is a third value or a fourth value, the third value is used to indicate invalid entries and buffered entries, and the fourth value is used to indicate cached entries; The cache hit test is performed based on the cache entries that are in a valid state among the multiple entries to obtain the test result of the access request, including: For any one of the multiple entries to be tested, the second target mask value corresponding to the entry to be tested is determined according to the second entry mask; When the second target mask value is the fourth value, it is determined whether the entry to be tested matches the access request based on the address parameter of the access request; If the access request is matched by the entry to be tested, a test result representing a cache hit is generated; If the second target mask value is the third value or the entry to be tested does not match the access request, the next entry adjacent to the entry to be tested will be used as a new entry to be tested. In addition, if the last entry to be tested in the cache buffer module fails to match the access request, a test result representing a cache miss is generated.

11. The method according to any one of claims 1 to 3, characterized in that, The method further includes: If the access request hits any of the cache entries, the hit data is sent to the graphics rendering pipeline unit so that the graphics rendering pipeline unit performs graphics rendering based on the hit data.

12. A data access device, characterized in that, A control unit configured in a graphics processor for controlling a cache buffer module, the cache buffer module including multiple entries, the multiple entries including cache entries of storage type cache type and buffer entries of storage type buffer type; the device includes: The selection module is configured to select one entry from a plurality of entries as the target buffer entry corresponding to the access request when the access request sent by the graphics rendering pipeline unit in the graphics processor does not hit any of the cache entries. A storage module is used to store the target data corresponding to the access request, which is obtained from the local memory of the graphics processor, into the target buffer entry; A sending module is used to send the target data in the target buffer entry to the graphics rendering pipeline unit; An adjustment module is used to adjust the storage type of the target buffer entry from the buffer type to the cache type, so that the target data can be used as alternative data for a hit test against the cache buffer module.

13. A graphics processor, characterized in that, include: At least one processing unit, local memory, at least one cache buffer module, and a control unit for controlling the cache buffer module; The control unit is used to execute the data access method as described in any one of claims 1-11.

14. An electronic device, characterized in that, include: At least one processor; wherein the at least one processor includes a graphics processor; The memory is communicatively connected to the graphics processor; wherein, The memory stores one or more computer programs that can be executed by the graphics processor to enable the graphics processor to perform the data access method as described in any one of claims 1-11.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a graphics processor, it implements the data access method as described in any one of claims 1-11.

16. A computer program product, characterized in that, Includes computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in the graphics processor of an electronic device, the graphics processor in the electronic device performs the data access method as described in any one of claims 1-11.

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