VCSEL chip defect detection model, method and device based on small sample

Abstract

The present application relates to the field of VCSEL chip defect identification, in particular to a VCSEL chip defect detection model, method and device based on small samples, which solves the technical problem that the existing VCSEL chip defect detection technology seriously depends on the number of training samples, resulting in limited detection accuracy and reliability. The model includes an encoder, a global attention optimization module and a decoder; the model can utilize the general prior knowledge of the visual basic model under the condition of limited number of defect samples, fully utilize the adaptive module to adjust the input image features, and uniformly enhance the multi-level features through the global attention optimization module, thereby effectively improving the recognition ability of weak defect features in the electroluminescent image. This method reduces the cost of artificial detection, improves the detection efficiency and the stability of the detection result, and is conducive to improving the product quality control level in the VCSEL chip manufacturing process.

Description

Technical Field

[0001] This invention relates to the field of VCSEL chip defect identification, specifically to a VCSEL chip defect detection model, method, and apparatus based on a small sample size. Background Technology

[0002] With the improvement of computer hardware performance and the development of image processing and machine vision technology, automated defect detection methods based on image analysis are gradually being applied to the field of semiconductor device manufacturing, providing a new technical approach for the quality inspection of vertical cavity surface-emitting semiconductor laser (VCSEL) chips.

[0003] In the production and testing of VCSEL chips, chip defects are complex, including both cosmetic defects such as surface scratches and contamination, and functional defects that only appear when the chip is emitting light. These defects typically manifest as uneven light emission, abnormal dark lines or bright spots, and are characterized by low contrast, irregular shapes, and significant size variations. Traditional detection methods that rely on manual experience or rule-based approaches suffer from low efficiency, poor stability, and high subjectivity, making it difficult to meet the accuracy and consistency requirements of VCSEL chip mass production.

[0004] In recent years, deep learning-based defect detection methods have been widely studied in the field of industrial vision and have achieved good results in various detection tasks. However, such methods usually rely on a large number of labeled samples for model training. In the scenario of VCSEL chip defect detection, due to the high cost of chip manufacturing, the randomness of defect occurrence, and the low probability of some defects, the number of defect samples that can be obtained is limited, making it difficult to construct a sufficiently large training dataset. At the same time, defect regions often have characteristics such as weak features and blurred boundaries. Relying on manual annotation is not only inefficient, but also requires a high level of professional experience, leading to a significant increase in sample annotation costs and further limiting the scale of data available for training. Under the conditions of limited training samples and high annotation costs, existing deep learning models are prone to insufficient feature learning or overfitting in practical applications, and the model's generalization ability and detection stability for unknown samples are difficult to guarantee. In addition, VCSEL chip defects in images often exhibit characteristics such as weak features, strong background interference, and coexistence of multiple scales, further increasing the detection difficulty under small sample conditions. Existing methods are mostly designed for scenarios with sufficient samples, and their ability to utilize effective information from limited samples is insufficient. They are difficult to ensure both detection accuracy and model stability, and cannot yet meet the actual requirements of VCSEL chip defect detection for high reliability and high accuracy. Summary of the Invention

[0005] This invention addresses the technical problem that existing VCSEL chip defect detection technologies heavily rely on the number of training samples, leading to limited detection accuracy and reliability. It provides a VCSEL chip defect detection model, method, and apparatus based on a small sample size.

[0006] This invention is achieved using the following technical solution: a VCSEL chip defect detection model based on small samples, comprising:

[0007] An encoder is used to perform multi-level feature extraction on an input VCSEL chip image. It includes an image embedding module and multiple sequentially connected visual Transformer feature extraction modules. The image embedding module converts the input VCSEL chip image into a sequence feature representation. The sequence features are then sequentially input into the multiple visual Transformer feature extraction modules. Each visual Transformer feature extraction module is connected to an adapter module. The adapter module is used to perform targeted feature adjustment on the input sequence features while keeping the parameters of the visual Transformer feature extraction modules frozen, so that the encoder finally outputs a multi-level feature map.

[0008] The global attention optimization module is connected to multiple visual Transformer feature extraction modules. It is used to uniformly regulate and optimize the multi-level feature maps output by the encoder to obtain the fused feature map after global attention optimization.

[0009] The decoder is used to fuse and reconstruct the fused feature map after it has been controlled and optimized by the global attention optimization module, and outputs the detection results used to characterize whether there are defects in the VCSEL chip.

[0010] This invention introduces an adaptation module into the visual Transformer feature extraction module of the encoder, which is used to efficiently adjust the parameters of sequence features under small sample conditions. This enables efficient transfer learning of VCSEL chip defect features while fully inheriting the general visual prior knowledge of large-scale pre-trained models, thereby reducing the model training complexity and the dependence on large-scale labeled samples.

[0011] Furthermore, the adaptation module adopts a multi-scale window-based attention calculation method. By setting multiple windows of different scales, the same sequence features are divided and processed in parallel. Window attention operations are performed in different scale windows, and the sequence feature outputs under each scale window are weighted and adaptively fused to enhance the characterization ability of the VCSEL chip under test for multi-scale defects. Compared with the global attention mechanism, the multi-scale window-based attention calculation method can significantly reduce the computational complexity by performing attention calculations in local windows, and at the same time, it is beneficial to maintain the stability of the model under small sample training conditions.

[0012] Furthermore, the adaptation module consists of three parts: a self-attention layer, a multilayer perceptron, and a multi-scale window adapter.

[0013] The size of the multi-scale window determines the size of its corresponding receptive field, thus affecting the ability to model defect features at different scales. To enhance the adaptability module's ability to represent multi-scale defect features, the adaptability module sets up multiple windows of different sizes to perform parallel partitioning and processing of the same sequence of features. Larger windows are used to observe broader contextual information to extract larger-scale defect features; smaller windows are used to focus on details and texture information in local areas to improve the detection capability of small-scale defect features (targets). Within each window of different sizes, window attention operations are used to model features at the corresponding scale, obtaining multi-scale feature responses. Subsequently, the adaptability module interactively fuses features at different window scales using a weighted adaptive fusion method, adaptively adjusting the contribution ratio of each scale feature according to the scale and distribution of defects in the input features, thereby forming the fused adapted feature output. Through the above adaptability module, the model can achieve targeted adjustment of defect features using multi-scale window attention and weighted fusion mechanisms while keeping the encoder backbone parameters frozen, thus more comprehensively understanding the defect information in the multispectral fused image and improving the robustness and accuracy of defect detection under small sample conditions.

[0014] Furthermore, the global attention optimization module adopts a pyramid-shaped feature fusion structure to aggregate and process multi-level feature maps. The feature maps at different levels are first formed into a multi-level feature set through feature alignment and aggregation operations; then, the importance of features at different levels is evaluated through an attention weight generation mechanism to generate corresponding weight coefficients.

[0015] The weighting coefficients are used to weight and regulate features at different levels, and the weighted features at different levels are fused and output to obtain a fused feature map optimized by global attention, thereby realizing information interaction and complementarity between features at different levels.

[0016] This invention also discloses a VCSEL chip defect detection method based on a small sample size, which is implemented using a VCSEL chip defect detection model based on a small sample size, and includes the following steps:

[0017] S1: Perform preprocessing operations on the input VCSEL chip image. The preprocessing operations include image size normalization, multi-channel format conversion and unified amplification of resolution size according to the model input channel number requirements, so that the preprocessed VCSEL chip image meets the input requirements of the VCSEL chip defect detection model in terms of spatial size and channel dimension.

[0018] S2: The preprocessed VCSEL chip image is input into the encoder of the VCSEL chip defect detection model. The input VCSEL chip image is first converted into a sequence feature representation by the image embedding module, and then the sequence features are sequentially input into the visual Transformer feature extraction module for feature extraction. The adaptation module is used to perform targeted feature adjustment on the input sequence features while keeping the parameters of the visual Transformer feature extraction module frozen, so that the encoder finally outputs a multi-level feature map.

[0019] S3: Input the multi-level feature maps output by each visual Transformer feature extraction module into the global attention optimization module. By modeling the global dependency relationship between the feature maps at each level, weight allocation and enhancement processing are performed on the feature maps at each level to achieve unified control and optimization of the defect-related features that may be contained in the feature maps at each level, and obtain the fused feature map after global attention optimization.

[0020] S4: The fused feature map output by the global attention optimization module is input to the decoder. The decoder processes the fused feature map and fuses it with the feature information of the corresponding level in the encoding stage to gradually restore the spatial resolution of the feature map at each level.

[0021] S5: The decoder outputs the final reconstructed feature map and generates detection results to characterize whether there are defects in the VCSEL chip, thus completing the defect detection process of the VCSEL chip.

[0022] Furthermore, the VCSEL chip image is an electroluminescent image of the VCSEL chip, and the image acquisition conditions must meet the electroluminescence detection requirements of the VCSEL chip, that is, when the VCSEL chip is powered on, the loaded current is lower than the threshold current of the VCSEL chip.

[0023] Furthermore, during the model training phase, the acquired electroluminescent images of the VCSEL chip are annotated. Different regions in the image are distinguished and labeled using annotation software, and the image pixels are divided into different categories to distinguish the background region, the luminescent region, and the luminescent aperture region of the VCSEL chip.

[0024] This invention also discloses a VCSEL chip defect detection device based on small samples, comprising:

[0025] The computer is loaded with a VCSEL chip defect detection model based on a small sample size.

[0026] A two-dimensional electric displacement stage, comprising a base and a displacement block capable of moving in two dimensions on the base;

[0027] An image acquisition platform is used to carry a VCSEL chip, and the image acquisition platform is mounted on a displacement block;

[0028] A slide rail is located above the image acquisition platform, and a slider is mounted on the slide rail.

[0029] An infrared camera is mounted on a slider, with the lens of the infrared camera facing the image acquisition platform below;

[0030] The light source is integrated and installed inside the lens of the infrared camera;

[0031] The objective lens is mounted below the lens of the infrared camera;

[0032] A mechanical limit module, installed on one side of the slide rail, is used to limit the movement of the slider;

[0033] The electric focusing unit is used for switching the magnification of the objective lens and fine-tuning the focal plane.

[0034] An optical imaging system consists of an infrared camera, a light source, and an objective lens;

[0035] The computer is also electrically connected to the two-dimensional electric displacement stage, the slider, and the infrared camera to control their movements.

[0036] Furthermore, when the device is used for detection, it includes the following steps:

[0037] S1: Place the VCSEL chip on the image acquisition platform and apply a working current to put the VCSEL chip into an electroluminescent state;

[0038] S2: Start the two-dimensional electric displacement stage to perform lateral micro-displacement adjustment on the VCSEL chip, so that the light-emitting aperture area of ​​the VCSEL chip enters the preset optical imaging center.

[0039] S3: Adjust the slider to move the infrared camera along the slide rail to the preset detection position, and limit the imaging working distance through the mechanical limit module to achieve the initial positioning of the optical imaging system;

[0040] S4: Activate the electric focusing unit to switch the magnification and fine-tune the focal plane of the objective lens, so that the optical imaging system is precisely matched with the light-emitting aperture area of ​​the VCSEL chip, and complete the electroluminescent image acquisition.

[0041] S5: The acquired electroluminescence image data is transmitted to the computer via the data interface;

[0042] S6: After the computer preprocesses the received image data, it inputs it into the loaded VCSEL chip defect detection model for inference calculation and outputs the corresponding defect detection results, thereby completing the VCSEL chip defect detection process.

[0043] The beneficial effects of this invention are as follows: The VCSEL chip defect detection model based on small samples proposed in this invention can effectively improve the ability to identify weak defect features in electroluminescent images by fully utilizing the adaptation module to specifically adjust multi-scale defect features when the number of defect samples is limited, and by uniformly enhancing multi-level feature maps through the global attention optimization module. This method realizes automated detection of VCSEL chip defects, reduces the cost of manual inspection, improves inspection efficiency and the stability of inspection results, and is conducive to improving the product quality control level in the VCSEL chip manufacturing process. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the VCSEL chip defect detection model structure;

[0045] Figure 2 To adapt to the module structure diagram;

[0046] Figure 3 A schematic diagram of the global attention optimization module structure;

[0047] Figure 4 This is one of the segmentation detection result images described in the embodiments of the present invention;

[0048] Figure 5 This is the second image of the segmentation detection result described in the embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of the defect detection device.

[0050] In the diagram: 1-Computer, 2-Infrared camera, 3-Light source, 4-Objective lens, 5-Image acquisition platform, 6-Slide rail, 7-Two-dimensional electric displacement stage, 8-Mechanical limit module, 9-Electric focusing unit, 10-Light emission area, 11-Light emission aperture area. Detailed Implementation

[0051] The invention will be further described below with reference to the accompanying drawings and embodiments.

[0052] In this embodiment, the detected images are all electroluminescence images used to reflect the internal light-emitting state of the VCSEL chip. The image acquisition conditions must meet the electroluminescence detection requirements of the VCSEL chip, that is, when the chip is powered on, the applied current is lower than the threshold current of the VCSEL chip, to ensure that the acquired electroluminescence images can accurately characterize the light-emitting distribution of the active area of ​​the chip and its potential internal defect features. According to the structural characteristics of the VCSEL chip, its electroluminescence is mainly concentrated and limited within the light-emitting aperture region 11. By placing an infrared camera 2 directly above the VCSEL chip under test for imaging, the spatial correspondence between the light-emitting region 10 and the light-emitting aperture region 11 can be clearly observed. When the VCSEL chip under test is in a normal state, the light-emitting region 10 within its light-emitting aperture region 11 is evenly distributed, and the light-emitting area basically covers the entire light-emitting aperture region 11; when there are defects inside the chip, it will cause abnormal light emission or no light emission in some areas within the light-emitting aperture region 11, thereby reducing the effective light-emitting area and showing obvious dark area features in the electroluminescence image. After acquiring the electroluminescent image, annotation software was used to annotate the acquired image at the pixel level. In this embodiment, based on the physical meaning of different regions in the electroluminescent image, the image pixels were divided into three categories: black background region, luminescent region 10, and luminescent aperture region 11 (see...). Figure 5 The above annotation method clearly distinguishes the luminous aperture region 11 and its internal luminous distribution. Based on the annotation results, the integrity and uniformity of the luminous region 10 within the luminous aperture region 11 are analyzed, thereby enabling the identification of internal defects in the VCSEL chip. When defects exist inside the chip, continuous or localized dark areas will appear within the luminous aperture region 11; while in a normal chip, the luminous region 10 is uniformly distributed, and there are no obvious dark areas within the luminous aperture region 11. The above annotation and analysis methods provide an accurate and reliable data foundation for subsequent training and validation of defect detection models based on small samples.

[0053] The VCSEL chip defect detection model structure described in this invention is as follows: Figure 1 As shown, it includes an encoder, a global attention optimization module, and a decoder; specifically, a lightweight mask decoder is selected in this embodiment. The core innovation of this invention lies in the collaborative design of the adaptation module and the global attention optimization module in the encoder, so as to solve the accuracy bottleneck of VCSEL chip defect detection in small sample scenarios.

[0054] The encoder consists of an image embedding module, multiple cascaded Visual Transformer (ViT) feature extraction modules, and an adaptation module. It is responsible for converting the input image into multi-level feature maps, which is the part where the basic visual model is frozen. The adaptation module, a key sub-module of the encoder, is cascaded after each Visual Transformer feature extraction module. Through an efficient parameter fine-tuning mechanism, it performs targeted feature adjustments on small sample data while freezing the parameters of the backbone Visual Transformer. The global attention optimization module receives the multi-level feature maps output by the encoder and enhances the expression of defect-related features through cross-layer global dependency modeling and dynamic weight allocation. The decoder receives the globally optimized fused feature map, performs feature reconstruction and upsampling, restores the image spatial resolution, and outputs the defect segmentation result.

[0055] The detailed detection process for the VCSEL chip defect detection model is as follows:

[0056] S1: The acquired raw VCSEL chip image undergoes standardized preprocessing to meet network input requirements. Preprocessing includes image size normalization, multi-channel format conversion, and unified resolution augmentation. The preprocessed VCSEL chip image will then be input into the VCSEL chip defect detection model.

[0057] S2: The preprocessed VCSEL chip image is input into the encoder to complete the conversion and adaptation from pixels to multi-level features. The input VCSEL chip image is first embedded into the encoder through an image embedding module and divided into fixed-size image blocks. Each image block is converted into a one-dimensional feature vector through a linear projection layer, and a learnable positional code is added to preserve spatial location information, finally obtaining the initial sequence features, denoted as... Initial sequence features Enter sequentially to A series of cascaded visual Transformer feature extraction modules ( Figure 1 (There are 4 modules in total). An adaptation module is chained after each visual Transformer feature extraction module; this is the core design of this invention for scenarios with few samples. All parameters of the main visual Transformer feature extraction module are frozen during training, while only the adaptation module contains learnable parameters, significantly reducing computational cost and the risk of overfitting.

[0058] S3: Input the multi-level feature maps output by the encoder into the global attention optimization module to perform global modeling and enhancement of cross-level features.

[0059] S4: The fused feature map, optimized by the global attention optimization module, is input into the decoder to gradually restore the spatial resolution of the image. The decoder maps the final fused features into a binary mask through lightweight convolutional layers, where foreground pixels represent defective regions and background pixels represent normal regions. The output mask feature map is denoted as... , These represent the height, width, and number of channels of the mask feature map, respectively.

[0060] S5: The decoder outputs the final mask feature map and generates defect detection results through post-processing. Since weak defects in semiconductor laser (VCSEL) chips are easily interfered with by noise, and the boundaries of defects are often blurred and mixed with the background, it is easy for the model to have problems such as false detection and missed detection during the recognition process. Therefore, in the global attention optimization process, the boundary intersection-union ratio of multi-level feature maps is used as the optimization target. An adaptive weight allocation mechanism is introduced to address the differences between feature maps at different levels. During model training, constrained by the weights of each module, the feature map will learn the information that best fits the optimization target from the visual Transformer feature extraction modules of different depths in the encoder (corresponding to shallow texture, middle structure, and deep semantics, respectively).

[0061] In global attention optimization learning, Dice similarity loss and boundary intersection-union ratio (BIR) loss are calculated simultaneously. Dice similarity is used to alleviate class imbalance caused by minor defects and improve the overall recall of defective regions, while the boundary intersection-union ratio loss is used to impose more refined constraints on the boundaries. The calculation process is as follows:

[0062]

[0063] In the formula, The overall loss value is also the target of optimization during model training. : True mask / label, which is the set of pixels of the actual defect area marked by humans. Predicted mask / label, which is the set of pixels in the defect area predicted by the model. : Indicates the size of the set, here referring to the number of pixels (area) within the region. and : These represent the "intersection" and "union" of sets, respectively. : Weighting coefficient (hyperparameter), used to balance the proportion of boundary intersection loss in the total loss. : The boundary extension area of ​​the actual label. Subscript Represents distance, indicating the distance from the actual region outline. The area within a range of pixels. : The boundary extension region of the predicted label, and its distance from the predicted region outline. The area within a range of pixels. This represents the set of valid boundary pixels of the real label (i.e., only pixels at the edge of the real region). : Represents the set of valid boundary pixels for the predicted label (i.e., only pixels at the edge of the predicted region are taken).

[0064] The structure of each sub-module of the VCSEL chip defect detection model is as follows:

[0065] Specifically, the adaptation module consists of three parts: a self-attention layer, a multilayer perceptron, and a multi-scale window adapter, with the corresponding structure as follows: Figure 2 As shown, the self-attention layer is used to establish the correlation between regions in the image globally, and to model the difference between low-contrast defect regions and luminous regions 10 to enhance the response capability to weak defect features; the multi-scale window adapter is used to extract feature information within local windows of different sizes to achieve adaptive perception of defect regions at different scales. The multi-scale window adapter is the core innovative unit of this module. Its overall structure inherits the output of the visual Transformer feature extraction module, and achieves multi-scale adaptation of small sample defect features while freezing the parameters of the main visual Transformer feature extraction module.

[0066] Input feature map According to the preset window size Divide into, and obtain Group window collection: ,in For the first The number of windows of various sizes For the first The first size Window features, This represents the number of channels in the feature map.

[0067] For each set of windows Each window in Self-attention is computed independently to obtain single-window self-attention output. ,

[0068] in .

[0069] In the formula : No. The first size The single-window attention output features are obtained after self-attention computation for each window.

[0070] These represent the query, key, and value matrices in the self-attention mechanism.

[0071] : These are the learnable linear transformation weight matrices used to generate the above query, key, and value matrices, respectively;

[0072] : represents the dimension space of the linear transformation weight matrix, where For the feature dimension of the attention head;

[0073] Softmax: A normalized exponential function used to transform attention scores into a probability distribution.

[0074] In the The global feature map obtained by restoring the window size is: ( These represent the height, width, and number of channels of the global feature map, respectively.

[0075] : This represents the operation of recombining discrete local window features into a complete image (feature map) dimension.

[0076] To achieve adaptive fusion of multi-scale features, a set of learnable scale weight parameters is constructed. And it is mapped to scale weight coefficients through a normalization function: ,in And satisfy: .

[0077] The feature maps at each scale (i.e., the global feature maps at each of the above scales) are multiplied by their corresponding weights and then summed: And then The mean of the output feature maps at each scale is calculated and used as the residual connection branch: Finally, the weighted features and the residual mean features are weighted and added together to obtain the output of the multi-scale window adapter: .

[0078] The weighted fusion multi-scale feature map is obtained by multiplying the feature maps of each scale by their corresponding dynamic weights and then summing them.

[0079] : All The feature map obtained by simply averaging the feature maps at each scale is used here as a branch of the residual connection.

[0080] The feature map output by the multi-scale window adapter.

[0081] : A learnable scaling factor.

[0082] The global attention optimization module of this invention mainly consists of three parts: an image pyramid adaptive fusion unit, a dual-path pooling weighted unit, and a feature weighted fusion unit. Its core relies on the image pyramid structure and dual-path pooling mechanism to globally optimize the multi-level feature maps output by the encoder. The corresponding structure is as follows: Figure 3 As shown.

[0083] Receive multi-level feature maps from the encoder output, containing outputs from different visual Transformer feature extraction modules. These feature maps are arranged in descending order of spatial resolution to construct an image pyramid from top to bottom. Adaptive fusion is then performed on the constructed image pyramid: the spatial resolution of features at each level is unified through upsampling and downsampling operations, and feature calibration is performed through channel concatenation and 1×1 convolution to make the feature information of different levels complement each other and generate a fused pyramid feature set.

[0084] The adaptively fused pyramid features are input into two parallel processing paths to extract global statistical features and defect saliency features: One branch transforms the pyramid features along the channel dimension using convolutional layers, then extracts global statistical information through global average pooling and global max pooling to generate a global feature vector. This vector reflects the global distribution characteristics of defects throughout the feature map. The other branch transforms the pyramid features using convolutional layers, then generates a defect saliency map using a saliency pooling detection algorithm. Weighted pooling is then applied to the feature map to generate a saliency feature vector, which focuses on key information in the defect region and suppresses background noise interference.

[0085] The feature vectors output from the two paths are multiplied and fused element-wise to generate a global attention weight vector. This vector contains both global statistical information and defect saliency information, which can accurately reflect the contribution of each feature channel of the fused feature map in the depth dimension to the defect detection task.

[0086] The generated global attention weight vector is compared with the feature map output from the top layer of the encoder. Weighted fusion is performed to obtain a preliminarily optimized feature map. Simultaneously, the fused features output from dual-path pooling are further transformed through a convolutional layer and also input into the feature weighted fusion unit, using learnable weight coefficients. and Dynamic weighted fusion is performed, ultimately outputting a fused feature map optimized by global attention. This fused feature map contains both fine-grained details of the low-level features and global semantic information of the high-level features. Furthermore, through dual-path pooling and attention weighting, the expression of defect-related features is highlighted, and it can be directly input into a lightweight mask decoder for subsequent feature reconstruction and defect segmentation.

[0087] like Figure 6 As shown, a VCSEL chip defect detection device based on small sample sizes includes:

[0088] Computer 1 is loaded with a VCSEL chip defect detection model based on a small sample size;

[0089] A two-dimensional electric displacement stage 7, which includes a base and a displacement block capable of moving in two dimensions on the base;

[0090] Image acquisition platform 5 is used to carry VCSEL chip, and the image acquisition platform 5 is mounted on displacement block;

[0091] The slide rail 6 is located above the image acquisition platform 5, and a slider is provided on the slide rail 6;

[0092] Infrared camera 2 is mounted on the slider, with the lens of infrared camera 2 facing the image acquisition platform 5 below;

[0093] Light source 3 is integrated and installed inside the lens of infrared camera 2;

[0094] Objective lens 4 is mounted below the lens of infrared camera 2;

[0095] Mechanical limit module 8 is installed on one side of slide rail 6 and is used to limit the slider.

[0096] The electric focusing unit 9 is used for switching the magnification and fine-tuning the focal plane of the objective lens 4;

[0097] The optical imaging system consists of an infrared camera 2, a light source 3, and an objective lens 4.

[0098] The computer 1 is also electrically connected to the two-dimensional electric displacement stage 7, the slider, and the infrared camera 2 respectively, so as to control the movement of the two-dimensional electric displacement stage 7, the slider, and the infrared camera 2.

[0099] When the device is used for detection, it includes the following steps:

[0100] S1: Place the VCSEL chip on the image acquisition platform 5 and apply a working current to make the VCSEL chip in an electroluminescent state.

[0101] S2: Start the two-dimensional electric displacement stage 7 to perform lateral micro-displacement adjustment on the VCSEL chip, so that the light-emitting aperture region 11 of the VCSEL chip enters the optical imaging center.

[0102] S3: Adjust the slider to move the infrared camera 2 along the slide rail 6 to the preset detection position, and limit the imaging working distance through the mechanical limit module 8 to achieve the initial positioning of the optical imaging system;

[0103] S4: Activate the electric focusing unit 9 to switch the magnification and fine-tune the focal plane of the objective lens 4, so that the optical imaging system is precisely matched with the light-emitting aperture area 11 of the VCSEL chip, and complete the electroluminescent image acquisition.

[0104] S5: The acquired electroluminescence image data is transmitted to computer 1 via the data interface;

[0105] S6: After preprocessing the received image data, computer 1 inputs it into the loaded VCSEL chip defect detection model for inference calculation and outputs the corresponding defect detection results, thereby realizing the automatic identification of the internal defect status of the VCSEL chip. Specifically, if the detection result is a non-conforming product, the corresponding product number is recorded and the detection data is saved; if the detection result is a qualified product, the next VCSEL chip detection process is started.

[0106] This invention introduces a parameter-efficient adaptation module into each Visual Transformer (ViT) feature extraction module. During model training, the pre-trained backbone parameters are frozen, and only the adaptation module is adjusted. This allows for efficient transfer learning of VCSEL chip defect features while fully inheriting the general visual prior knowledge of the large-scale pre-trained model. A global attention optimization module is used to perform global dependency modeling and adaptive weight allocation on the multi-level feature maps output by the encoder, enhancing the model's ability to perceive the overall structure and contextual relationships of the defect region. The decoder reconstructs the fused feature map layer by layer after global attention optimization, outputting the corresponding defect detection results. By introducing a large-scale pre-trained model and combining it with a parameter-efficient adaptation module, this invention achieves stable and accurate detection of weak, multi-scale defects in VCSEL chip electroluminescent images with only a small number of labeled defect samples. This significantly reduces sample acquisition and labeling costs and improves the efficiency and automation level of defect detection.

[0107] To verify the effectiveness and advancement of the proposed model, a quantitative comparative experiment was conducted on the constructed VCSEL chip defect dataset, comparing the proposed model with existing mainstream image segmentation and defect detection models (including SAM, HQ-SAM, SAM-Adapter, SAMed, and ROS-SAM). The evaluation metrics selected were Dice similarity coefficient (Dice), mean intersection-over-union ratio (mIoU), recall, and accuracy (Acc), all commonly used in medical imaging and industrial inspection. The specific comparative experimental results are shown in Table 1.

[0108]

[0109] As shown in Table 1, the model described in this invention achieved the highest values ​​in all four quantitative indicators, including a Dice similarity coefficient of 91.13%, a mean intersection-union ratio (mIoU) of 80.24%, a recall of 92.56%, and an accuracy of 99.98%. All test values ​​comprehensively surpassed the data distribution range of the other five comparative models.

Claims

1. A VCSEL chip defect detection model based on small sample size, characterized in that, include: An encoder is used to perform multi-level feature extraction on an input VCSEL chip image. It includes an image embedding module and multiple sequentially connected visual Transformer feature extraction modules. The image embedding module converts the input VCSEL chip image into a sequence feature representation. The sequence features are then sequentially input into the multiple visual Transformer feature extraction modules. Each visual Transformer feature extraction module is connected to an adapter module. The adapter module is used to perform targeted feature adjustment on the input sequence features while keeping the parameters of the visual Transformer feature extraction modules frozen, so that the encoder finally outputs a multi-level feature map. The global attention optimization module is connected to multiple visual Transformer feature extraction modules. It is used to uniformly regulate and optimize the multi-level feature maps output by the encoder to obtain the fused feature map after global attention optimization. The decoder is used to fuse and reconstruct the fused feature map after it has been controlled and optimized by the global attention optimization module, and outputs the detection results used to characterize whether there are defects in the VCSEL chip.

2. The VCSEL chip defect detection model based on small samples as described in claim 1, characterized in that, The adaptation module adopts an attention calculation method based on multi-scale windows. By setting multiple windows of different scales, the same sequence features are divided and processed in parallel. Window attention operations are performed in different scale windows, and the sequence feature outputs under each scale window are weighted and adaptively fused.

3. The VCSEL chip defect detection model based on small samples as described in claim 2, characterized in that, The adaptation module consists of three parts: a self-attention layer, a multilayer perceptron, and a multi-scale window adapter, and is used to implement an attention calculation method based on multi-scale windows.

4. The VCSEL chip defect detection model based on small samples as described in claim 3, characterized in that, The global attention optimization module adopts a pyramid-shaped feature fusion structure to aggregate and process multi-level feature maps. The feature maps at different levels are first formed into a multi-level feature set through feature alignment and aggregation operations. Then, the importance of features at different levels is evaluated through an attention weight generation mechanism to generate corresponding weight coefficients. The weighting coefficients are used to weight and regulate features at different levels, and the weighted features at different levels are fused and output to obtain a fused feature map optimized by global attention, thereby realizing information interaction and complementarity between features at different levels.

5. A method for VCSEL chip defect detection based on small samples, implemented using the VCSEL chip defect detection model based on small samples as described in claim 4, characterized in that, The steps include the following: S1: Perform preprocessing operations on the input VCSEL chip image. The preprocessing operations include image size normalization processing, and multi-channel format conversion and unified expansion of resolution size according to the model input channel number requirements, so that the preprocessed VCSEL chip image meets the input requirements of the VCSEL chip defect detection model in terms of spatial size and channel dimension. S2: The preprocessed VCSEL chip image is input into the encoder of the VCSEL chip defect detection model. The input VCSEL chip image is first converted into a sequence feature representation by the image embedding module, and then the sequence features are sequentially input into the visual Transformer feature extraction module for feature extraction. The adaptation module is used to perform targeted feature adjustment on the input sequence features while keeping the parameters of the visual Transformer feature extraction module frozen, so that the encoder finally outputs a multi-level feature map. S3: Input the multi-level feature maps output by each visual Transformer feature extraction module into the global attention optimization module. By modeling the global dependency relationship between the feature maps at each level, weight allocation and enhancement processing are performed on the feature maps at each level to achieve unified control and optimization of the defect-related features that may be contained in the feature maps at each level, and obtain the fused feature map after global attention optimization. S4: The fused feature map output by the global attention optimization module is input to the decoder. The decoder processes the fused feature map and fuses it with the feature information of the corresponding level in the encoding stage to gradually restore the spatial resolution of the feature map at each level. S5: The decoder outputs the final reconstructed feature map and generates detection results to characterize whether there are defects in the VCSEL chip, thus completing the defect detection process of the VCSEL chip.

6. The VCSEL chip defect detection method based on small samples as described in claim 5, characterized in that, The VCSEL chip image is an electroluminescent image of the VCSEL chip. The image acquisition conditions must meet the electroluminescence detection requirements of the VCSEL chip, that is, when the VCSEL chip is powered on, the loaded current is lower than the threshold current of the VCSEL chip.

7. The VCSEL chip defect detection method based on small samples as described in claim 6, characterized in that, During the model training phase, the collected electroluminescent images of the VCSEL chip are labeled. Different regions in the image are distinguished and labeled using labeling software, and the image pixels are divided into different categories to distinguish the background region, the light-emitting region (10), and the light-emitting aperture region (11) of the VCSEL chip.

8. A VCSEL chip defect detection device based on small sample size, used to implement the VCSEL chip defect detection method based on small sample size as described in claim 7, characterized in that, include: Computer (1) is loaded with a VCSEL chip defect detection model based on a small sample size; A two-dimensional electric displacement stage (7) includes a base and a displacement block capable of moving in two dimensions on the base; An image acquisition platform (5) is used to carry a VCSEL chip, and the image acquisition platform (5) is mounted on a displacement block; The slide rail (6) is located above the image acquisition platform (5), and a slider is provided on the slide rail (6); An infrared camera (2) is mounted on a slider, with the lens of the infrared camera (2) facing the image acquisition platform (5) below. The light source (3) is integrated and installed inside the lens of the infrared camera (2); Objective lens (4) is mounted below the lens of infrared camera (2); A mechanical limit module (8) is installed on one side of the slide rail (6) to limit the slider; The electric focusing unit (9) is used to switch the magnification and fine-tune the focal plane of the objective lens (4); An optical imaging system is composed of an infrared camera (2), a light source (3), and an objective lens (4); The computer (1) is also electrically connected to the two-dimensional electric displacement stage (7), the slider and the infrared camera (2) respectively, so as to control the movement of the two-dimensional electric displacement stage (7), the slider and the infrared camera (2).

9. The VCSEL chip defect detection device based on small sample size as described in claim 8, characterized in that, When the device is used for detection, it includes the following steps: S1: Place the VCSEL chip on the image acquisition platform (5) and apply a working current to make the VCSEL chip in an electroluminescent state; S2: Start the two-dimensional electric displacement stage (7) to perform lateral micro-displacement adjustment on the VCSEL chip so that the light emission aperture area (11) of the VCSEL chip enters the preset optical imaging center. S3: Adjust the slider to move the infrared camera (2) along the slide rail (6) to the preset detection position, and limit the imaging working distance through the mechanical limit module (8) to achieve the initial positioning of the optical imaging system; S4: Start the electric focusing unit (9) to switch the magnification and fine-tune the focal plane of the objective lens (4) so ​​that the optical imaging system is precisely matched with the light emission aperture area (11) of the VCSEL chip and complete the electroluminescent image acquisition. S5: The acquired electroluminescence image data is transmitted to the computer via the data interface (1). S6: The computer (1) preprocesses the received image data and inputs it into the loaded VCSEL chip defect detection model for inference calculation, outputs the corresponding defect detection results, and thus completes the VCSEL chip defect detection process.

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