Shift register, drive circuit, display device, and drive method

Abstract

The present disclosure provides a shift register, a driving circuit, a driving method and a display device, and relates to the technical field of display. The shift register comprises: a shift circuit configured to control potentials of a first node and a second node, and provide a first power supply voltage or a second power supply voltage to a first output terminal as a first output signal; a gate-on circuit configured to provide a gate-on signal from a gate-on terminal to a third node under the control of a first input signal, a second input signal from a second input terminal and the first output signal; a control circuit configured to provide the potential of the first node to a fourth node and the potential of the second node to a fifth node under the control of the potential of the third node; and an output circuit configured to provide the first power supply voltage or the second power supply voltage to a second output terminal as a second output signal under the control of the potential of the fourth node and the potential of the fifth node.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register, a driving circuit, a display device, and a driving method. Background Technology

[0002] To achieve good compatibility between power consumption and high refresh rates, display products typically employ area refresh technology. By controlling the output of the drive signal within a frame, it is possible to update the data signal of only a portion of the display products.

[0003] Display products typically use TFTs (Thin Film Transistors) as switching or driving transistors. Because TFTs are prone to leakage current, issues such as flickering bright and dark lines can easily occur at the critical points of refresh frequency switching when using area refresh technology. Summary of the Invention

[0004] To at least partially solve the above problems, this disclosure provides a shift register, a driving circuit, a display device, and a driving method.

[0005] One aspect of this disclosure provides a shift register, comprising: a shift circuit configured to control the potentials of a first node and a second node under the control of a first clock signal from a first clock terminal, a second clock signal from a second clock terminal, a first power supply voltage from a first power supply, a second power supply voltage from a second power supply, and a first input signal from a first input terminal, and to provide the first power supply voltage or the second power supply voltage to a first output terminal as a first output signal; a gating circuit configured to provide a gating signal from a gating terminal to a third node under the control of the first input signal, the second input signal from the second input terminal, and the first output signal; a control circuit configured to provide the potential of the first node to a fourth node and the potential of the second node to a fifth node under the control of the potential of the third node; and an output circuit configured to provide the first power supply voltage or the second power supply voltage to a second output terminal as a second output signal under the control of the potentials of the fourth node and the fifth node.

[0006] Another aspect of this disclosure provides a driving circuit comprising M cascaded shift registers as described above, where M is an integer greater than 1.

[0007] Another aspect of this disclosure provides a display device including the driving circuit described above.

[0008] Another aspect of this disclosure provides a driving method applied to the shift register as described above, the method comprising: controlling a gating signal to a first level during a gating phase; and controlling the gating signal to a second level during a de-gating phase. Attached Figure Description

[0009] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1A A schematic diagram of an example pixel circuit is shown.

[0011] Figure 1B A signal timing diagram of an example pixel circuit is shown.

[0012] Figure 2 A schematic diagram of an example shift register is shown.

[0013] Figure 3 A schematic diagram of a highlighting band on an example display panel is shown.

[0014] Figure 4 The signal timing diagram of an example shift register is shown.

[0015] Figure 5 The diagram shows the signal waveforms of an example shift register.

[0016] Figure 6 A block diagram of a shift register according to an embodiment of the present disclosure is shown schematically.

[0017] Figure 7 A schematic diagram of the structure of a shift register according to another embodiment of the present disclosure is shown.

[0018] Figure 8 The diagram schematically illustrates the waveform of the output signal of the shift register in the high refresh rate region according to an embodiment of the present disclosure.

[0019] Figure 9 The diagram schematically illustrates the waveform of the output signal of the shift register in the low refresh rate region according to an embodiment of the present disclosure.

[0020] Figure 10 The diagram schematically illustrates the waveform of the output signal of the shift register that switches between high refresh rate regions and low refresh rate regions according to an embodiment of the present disclosure.

[0021] Figure 11 A signal timing diagram of a shift register 700 according to an embodiment of the present disclosure is shown schematically.

[0022] Figure 12 The diagram illustrates the signal waveforms of a shift register 700 according to an embodiment of the present disclosure.

[0023] Figure 13The illustration shows the effect diagrams of two driving circuits according to embodiments of the present disclosure.

[0024] Figure 14 A schematic diagram of the structure of a shift register according to another embodiment of the present disclosure is shown.

[0025] Figure 15 A schematic diagram of the structure of a shift register according to another embodiment of the present disclosure is shown.

[0026] Figure 16 A schematic diagram of the structure of a shift register according to another embodiment of the present disclosure is shown.

[0027] Figure 17 A schematic diagram of the structure of a shift register according to another embodiment of the present disclosure is shown.

[0028] Figure 18 A schematic diagram of the structure of a shift register according to another embodiment of the present disclosure is shown.

[0029] Figure 19 A schematic diagram of the structure of a shift register according to another embodiment of the present disclosure is shown.

[0030] Figure 20 A schematic diagram of the structure of a drive circuit according to an embodiment of the present disclosure is shown.

[0031] Figure 21 A schematic diagram of the structure of a drive circuit according to another embodiment of the present disclosure is shown.

[0032] Figure 22A A schematic plan view of a semiconductor layer according to an embodiment of the present disclosure is shown.

[0033] Figure 22B A schematic plan view of the first conductive layer according to an embodiment of the present disclosure is shown.

[0034] Figure 22C A schematic plan view of the second conductive layer according to an embodiment of the present disclosure is shown.

[0035] Figure 22D A schematic plan view of a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer according to an embodiment of the present disclosure is shown.

[0036] Figure 22E A schematic plan view of the third and fourth conductive layers according to an embodiment of the present disclosure is shown.

[0037] Figure 22F A schematic plan view of a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer according to an embodiment of the present disclosure is shown.

[0038] Figure 22G A schematic plan view of the fifth conductive layer according to an embodiment of the present disclosure is shown.

[0039] Figure 22H A schematic plan view of the sixth conductive layer according to an embodiment of the present disclosure is shown.

[0040] Figure 22I A schematic plan view of the semiconductor layer, the second conductive layer, the fifth conductive layer, and the sixth conductive layer according to an embodiment of the present disclosure is shown.

[0041] Figure 22J A schematic plan view of the fourth and sixth conductive layers according to an embodiment of the present disclosure is shown.

[0042] Figure 22K A schematic plan view of a semiconductor layer, a second conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer according to an embodiment of the present disclosure is shown.

[0043] Figure 23 A schematic diagram of the structure of a display device according to an embodiment of the present disclosure is shown.

[0044] Figure 24 A flowchart illustrating a driving method according to an embodiment of the present disclosure is shown schematically. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that throughout the accompanying drawings, the same elements are represented by the same or similar reference numerals. In the following description, some specific embodiments are used for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or configurations will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the embodiments of this disclosure.

[0046] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0047] Furthermore, in the description of embodiments of this disclosure, the term "electrical connection" can refer to a direct connection between two components, or it can refer to a connection between two components via one or more other components. Moreover, these two components can be connected or coupled via wired or wireless means.

[0048] The source and drain of the switching transistor used in this embodiment are symmetrical, so their source and drain can be interchanged. In this embodiment, according to its function, one of the source and drain can be called the first terminal, and the other of the source and drain can be called the second terminal.

[0049] Furthermore, in the description of the embodiments of this disclosure, the terms "first power supply voltage" and "second power supply voltage" are used only to distinguish the different amplitudes of the two power supply voltages. For example, the following description uses "first power supply voltage" as a relatively low voltage and "second power supply voltage" as a relatively high voltage. Those skilled in the art will understand that this disclosure is not limited thereto.

[0050] It should be noted that, in the description of the embodiments of this disclosure, INPUT1 can represent either a first input signal terminal or a first input signal provided by the first input terminal. Similarly, the symbol CK can represent either a first clock terminal or a first clock signal provided by the first clock terminal; the symbol CB can represent either a second clock terminal or a second clock signal provided by the second clock terminal; OUT1 can represent either a first output terminal or a first output signal output by the first output terminal; VGL can represent either a first power supply or a first power supply voltage; VGH can represent either a second power supply or a second power supply voltage; MS1 can represent either a first strobe terminal or a first strobe signal, and so on. The following embodiments are the same and will not be described again.

[0051] Figure 1A A schematic diagram of an example pixel circuit is shown. Figure 1B A signal timing diagram of an example pixel circuit is shown.

[0052] like Figure 1A As shown, the pixel circuit 100 can be a 7T1C pixel circuit. In the pixel circuit 100, transistors M1 to M2 and transistors M4 to M7 can be switching transistors, transistor M3 is a driving transistor, transistors M3 to M7 are P-type transistors, and transistors M1 and M2 are N-type transistors.

[0053] like Figure 1BAs shown, during the T1 stage of the pixel circuit 100 operation, the enable signal EM is high and controls transistors M5 and M6 to be turned off; the reset signal RST1 is high and controls transistor M1 to be turned on, so as to pull the potential of node Q1 down to the initialization signal Vinit1, thereby allowing the capacitor Cst to be reset using the initialization signal Vinit.

[0054] During stage T2 of pixel circuit 100 operation, the reset signal RST1 is low, controlling transistor M1 to be off; the drive signal NGate is high, controlling transistor M2 to be on; the drive signal PGate is low, controlling transistor M4 to be on; and the data signal Vdate charges capacitor Cst through transistor M4, drive transistor M3, and transistor M2. When the voltage of drive transistor M3 is Vgs = V(Q1) - V(Q2) = V(Q1) - Vdata = Vth, drive transistor M3 is off, and the voltage maintained by capacitor Cst is V(Q1) = Vdata + Vth. Simultaneously, the drive signal PGate is low, controlling transistor M7 to be on, so that the anode of the light-emitting element EL is reset using the initialization signal Vinit.

[0055] During the T3 stage of the pixel circuit 100, the driving signal NGate is low and controls transistor M2 to be off, the driving signal PGate is high and controls transistors M4 and M7 to be off, the enable signal EM is low and controls transistors M5 and M6 to be on, and the driving transistor M3 has Vgs = V(Q1) - V(Q2) = Vdata + Vth - ELVDD. Therefore, the light-emitting element EL can emit light according to the potential of the data signal Vdata.

[0056] In this example pixel circuit, if the drive signal NGate is high, transistor M2 is turned on, and the data signal Vdata can be written to pixel circuit 100, thereby updating the brightness of the light-emitting element EL of pixel circuit 100. Accordingly, the pixel row where pixel circuit 100 is located is refreshed in the current frame. If the drive signal NGate is low, transistor M2 is always turned off, the data signal Vdata is not written to pixel circuit 100, the brightness of the light-emitting element EL does not change, and the brightness of the pixel row where pixel circuit 100 is located remains unchanged in the current frame.

[0057] Therefore, by controlling the potential of the drive signal NGate, pixel brightness can be refreshed, thus achieving partial refresh of the displayed image. In display products, a shift register is typically used to select the drive signal NGate.

[0058] Figure 2 A schematic diagram of an example shift register is shown.

[0059] like Figure 2 As shown, an example shift register 200 can be a 16T3C+10T4C circuit.

[0060] In the high-frequency region, the strobe signal MS is low. When both input signals Scan(n-1) and Q9(n-2) are low, transistors M8 and M9 are turned on, the strobe signal MS is applied low to node Q3, transistor M10 is turned on, and the potential of node Q4 is equal to that of node Q5. When the input signal Scan(n-1) is high, the potentials of nodes Q5 and Q4 are both low, transistor M11 is turned on, and the output drive signal NGate is VGH. When the input signal Scan(n-1) is low, the potentials of nodes Q5 and Q4 are both high, transistor M11 is turned off, transistor M12 is turned on, and when the clock signal CB is low, the potential of node Q6 is further pulled low, and the potential of node Q7 is also lower than VGL, so transistor M13 is turned on, and the output drive signal NGate is VGL.

[0061] In the low-frequency region, the strobe signal MS is high. When both input signals Scan(n-1) and Q9(n-2) are low, transistors M8 and M9 are turned on, the strobe signal MS is applied high to node Q3, and transistor M10 is turned off. When input signal Scan(n-1) is low, the potential of node Q5 is high, the potential of node Q8 is low, and the output terminal outputs a stepped signal. When the clock signal CB changes from high to low, the potentials of nodes Q6 and Q7 are further pulled low due to the bootstrap effect of the capacitors. At this time, the drive signal NGate output at the terminal is VGL. When input signal Scan(n-1) is high, the low potential of node Q5 cannot be applied to node Q4 due to the turn-off of transistor M10. Therefore, node Q4 remains high, transistor M11 remains off, and node Q7 remains low, transistor M13 remains on. The drive signal NGate output at the terminal is VGL.

[0062] Therefore, in the high-frequency region, the level of the drive signal NGate output by the output terminal can change with the input signal Scan(n-1), while in the low-frequency region, regardless of whether the input signal Scan(n-1) is high or low, the drive signal NGate output by the output terminal is always VGL, thus enabling the selection of the drive signal NGate.

[0063] Due to limitations in component precision and manufacturing processes, shift registers cannot operate ideally, leading to frequent bright band issues at critical refresh rate switching points. Bright bands on the display panel, such as... Figure 3As shown. When the strobe signal MS switches from high frequency to low frequency, the signal timing diagram and signal waveform diagram of shift register 200 can be respectively shown as follows. Figure 4 and Figure 5 As shown.

[0064] Figure 3 A schematic diagram of a highlight band on an example display panel is shown. Figure 4 The following is a signal timing diagram of an example shift register. Figure 5 The diagram shows the signal waveforms of an example shift register. Figure 5 In the diagram, solid lines can represent the signal waveform of the last high-frequency row, while dashed lines can represent the signal waveform of the normal high-frequency row.

[0065] like Figure 3 , Figure 4 and Figure 5 As shown, in this example, when the strobe signal MS switches from high frequency to low frequency, it needs to go through a process of switching from a low level to a high level. At this time, the gate voltages of transistors M8 and M9 differ from those of the normal high-frequency rows in the last row of the high-frequency region. This results in insufficient cutoff of transistors M8 and M9, causing the high level of the strobe signal MS to be applied to node Q3 through leakage current, thus affecting the potential of node Q3. The potential of node Q3 slowly rises, resulting in insufficient conduction of transistors M10 and M12, and a insufficiently low potential for node Q7. Consequently, the conduction of transistor M13 is also less than that of the normal high-frequency rows, leading to a insufficiently low drive signal NGate output from the last row of the high-frequency region, resulting in a relatively high step in the output drive signal NGate. Therefore, the pixel current output from the last row of the high-frequency region differs from that output from the normal high-frequency rows, causing flickering bright and dark lines and other problems in the last row of the high-frequency region.

[0066] For example, multiple cascaded shift registers 200 can drive multiple pixel rows in a pixel array. For example, the low levels of the multiple drive signals NGate output by the multiple cascaded shift registers 200 are sequentially shifted out. For example, when the drive signal NGate is high, the pixel circuit can be refreshed by the data signal, and at this time, the effective level of the drive signal NGate is high. When the effective level of the drive signal NGate output by the shift register is long, there are periods when the drive signals NGate output by adjacent shift registers are simultaneously high. For example, when multiple shift registers output a high-level drive signal NGate, before the drive signal NGate output by the m-th shift register changes from high to low, the drive signal NGate output by the (m+1)-th shift register changes from low to high.

[0067] When multiple cascaded shift registers 200 scan multiple pixel rows line by line, the level of the strobe signal MS can change. For example, the multiple cascaded shift registers 100 can include 1000 shift register stages. When the first 500 shift register stages sequentially output the drive signal NGate, the strobe signal MS is low, and the first 500 shift register stages sequentially output the drive signal NGate to refresh the first 500 pixel rows in the pixel circuit. When the last 500 shift register stages sequentially output the drive signal NGate, the strobe signal MS changes from low to high, and the level of the drive signal NGate output by the last 500 shift register stages remains high, and the last 500 pixel rows in the pixel circuit are not refreshed.

[0068] When the drive signal NGate output from stage 500 transitions from high to low, the strobe signal MS can transition from low to high. The timing of this MS transition can occur after the drive signal NGate output from stage 501 transitions from low to high but before it transitions from high to low. At this point, the drive signal NGate output from stage 501 becomes high. In this situation, as described above, transistor M2 in pixel circuit 100 is briefly turned on, causing partial data writing and resulting in a display anomaly in the 501st pixel row.

[0069] In view of this, this disclosure provides a shift register to at least partially solve problems such as flickering bright and dark lines when switching from high frequency to low frequency.

[0070] Figure 6 A block diagram of a shift register according to an embodiment of the present disclosure is shown schematically.

[0071] like Figure 6 As shown, the shift register 600 may include a shift circuit 610, a gating circuit 620, a control circuit 630, and an output circuit 640.

[0072] The shift circuit 610 can be electrically connected to the first clock terminal CK, the second clock terminal CB, the first power supply VGL, the second power supply VGH, and the first input terminal INPUT1. Under the control of the first clock signal CK from the first clock terminal CK, the second clock signal CB from the second clock terminal CB, the first power supply voltage VGL of the first power supply VGL, the second power supply voltage VGH of the second power supply VGH, and the first input signal INPUT1 from the first input terminal INPUT1, the shift circuit 610 can control the potential of the first node N1 and the second node N2, and provide the first power supply voltage VGL or the second power supply voltage VGH to the first output terminal OUT1 as the first output signal OUT1.

[0073] The gating circuit 620 can be electrically connected to the gating terminal MS, the first input terminal INPUT1, the second input terminal INPUT2, and the first output terminal OUT1. Under the control of the first input signal INPUT1, the second input signal INPUT2 from the second input terminal INPUT2, and the first output signal OUT1, the gating circuit 620 can provide the gating signal MS from the gating terminal MS to the third node N3.

[0074] For example, the first input signal INPUT1, the second input signal INPUT2, and the first output signal OUT1 can jointly control the gating circuit 620 to switch between the connected and cut-off states. When the first input signal INPUT1, the second input signal INPUT2, and the first output signal OUT1 jointly control the gating circuit to be in the connected state, the gating signal MS is written to the third node N3. When the first input signal INPUT1, the second input signal INPUT2, and the first output signal OUT1 jointly control the gating circuit 620 to be in the cut-off state, the potential of the third node N3 can maintain the previous stage state.

[0075] Under the control of the potential of the third node N3, the control circuit 630 can provide the potential of the first node N1 to the fourth node N4 and the potential of the second node N2 to the fifth node N5.

[0076] For example, the potential of the third node N3 can control the control circuit 630 to switch between connected and disconnected states. When the potential of the third node N3 controls the control circuit 630 to be in the connected state, the potential of the second node N2 is written to the fifth node N5. When the potential of the third node N3 controls the control circuit 630 to be in the disconnected state, the potential of the fifth node N5 can maintain the state of the previous stage.

[0077] The output circuit 640 is electrically connected to the first power supply VGL, the second power supply VGH, and the second output terminal OUT2. Under the control of the potential of the fourth node N4 and the fifth node N5, the output circuit 640 can provide the first power supply voltage VGL or the second power supply voltage VGH to the second output terminal OUT2 as the second output signal OUT2.

[0078] For example, the potential of the fourth node N4 can control whether the second power supply VGH and the second output signal OUT2 are in a connected or disconnected state. When the second power supply VGH and the second output signal OUT2 are in a connected state, the output circuit 640 provides the second power supply voltage VGH to the second output terminal OUT2, and the second output terminal OUT2 outputs a high-level signal.

[0079] For example, the potential of the fifth node N5 can control whether the first power supply VGL and the second output signal OUT2 are in a connected or disconnected state. When the first power supply VGL and the second output signal OUT2 are in a connected state, the output circuit 640 provides the first power supply voltage VGL to the second output terminal OUT2, and the second output terminal OUT2 outputs a low-level signal.

[0080] In this embodiment, the second output signal OUT2 can be a scan signal used to drive the transistor M2 in the pixel circuit 100 described above. For example, when the level of the second output signal OUT2 is high, the transistor M2 is turned on, and data signals can be written, thereby achieving screen refresh. When the level of the second output signal OUT2 is low, the transistor M2 is turned off, and data signals cannot be written, thereby achieving screen non-refresh and remaining unchanged.

[0081] In this embodiment of the present disclosure, the first output signal OUT1 output by the shift circuit 610 is connected to the gating circuit 620 as the input of the gating circuit 620. By utilizing the phase difference between the first output signal OUT1 and the first input signal INPUT1, the leakage current of the gating signal MS from the gating terminal MS to the first node N1 is reduced during the switching process of the gating signal MS. This reduces the impact of the leakage current on the turn-on state of the transistor, which can improve the bright band problem at the critical position of refresh frequency switching and effectively improve display performance.

[0082] Optionally, under the control of the first clock signal CK, the first power supply voltage VGL, and the first input signal INPUT1, the shift circuit 610 can provide at least one of the second clock signal CB and the second power supply voltage VGH to the first node N1.

[0083] For example, based on the first clock signal CK and the first power supply voltage VGL, the shift circuit 610 can control the second clock terminal CB to be in a connected or cut-off state with the first node N1. Based on the first clock signal CK and the first input signal INPUT1, the shift circuit 610 can control the second power supply VGH to be in a connected or cut-off state with the first node N1.

[0084] When the second clock input CB is connected to the first node N1, the shift circuit 610 provides the second clock signal CB to the first node N1. Alternatively, when the second power supply VGH is connected to the first node N1, the shift circuit 610 provides the second power supply voltage VGH to the first node N1. Or, when both the second clock input CB and the second power supply VGH are connected to the first node N1, the shift circuit 610 provides the second clock signal CB and the second power supply voltage VGH to the first node N1.

[0085] Optionally, under the control of the first clock signal CK, the shift circuit 610 can provide the first input signal INPUT1 to the second node N2.

[0086] For example, based on the first clock signal CK1, the shift circuit 610 can control the connection or disconnection between the first input terminal INPUT1 and the second node N2. When the first input terminal INPUT1 and the second node N2 are in a connected state, the shift circuit 610 provides the first input signal INPUT1 to the second node N2.

[0087] Optionally, under the control of the potential of the first node N1, the potential of the second node N2, and the first power supply voltage VGL, the shift circuit 610 can provide the first power supply voltage VGL or the second power supply voltage VGH to the first output terminal OUT1 as the first output signal OUT1.

[0088] For example, based on the potential of the second node N2 and the first power supply voltage VGL, the shift circuit can control the first power supply VGL to be in a connected state or a cut-off state with the first output terminal OUT1.

[0089] In this embodiment of the disclosure, the first output signal OUT1 output from the first output terminal OUT1 is provided to other shift registers cascaded with the shift register to implement shift driving of the multiple cascaded shift registers.

[0090] For example, the shift register can be the m-th stage shift register, and the first output signal OUT1 can be provided to the first input terminal of the (m+1)-th stage shift register. The first output signal OUT1 can also be provided to the first input terminal of the (m+2)-th stage shift register.

[0091] Optionally, the control circuit 630 can also be electrically connected to the second power supply VGH and the second output terminal OUT2. Under the control of the potential of the fifth node N5 and the second output signal OUT2, the control circuit can use the second power supply voltage VGH to control the potential of the fourth node N4.

[0092] For example, based on the potentials of the fifth node N5 and the second output terminal OUT2, the control circuit can control the connection or disconnection state between the fourth node N4 and the second power supply VGH. When the fourth node N4 and the second power supply VGH are in a connected state, the control circuit 630 can provide the second power supply voltage VGH to the fourth node N4, at which time the voltage of the fourth node N4 is high. Under the control of the high level, the second output terminal OUT2 and the second power supply VGH are in a disconnected state, thereby preventing the second power supply voltage VGH from affecting the output of a low-level signal from the second output terminal OUT2.

[0093] Optionally, the gating circuit 720 can also be electrically connected to the first power supply VGL and the third input terminal INPUT3. Under the control of the third input signal INPUT3 from the third input terminal INPUT3, the gating circuit can use the voltage of the first power supply VGL to control the potential of the third node N3.

[0094] In this embodiment, the gating circuit is electrically connected to the third input terminal INPUT3, the third node N3, and the first power supply VGL. Under the control of the third input signal INPUT3, the gating circuit can use the first power supply voltage VGL to reset the third node N3 and pull down the potential of the third node N3.

[0095] For example, based on the third input signal INPUT3, the gating circuit can control the connection or disconnection between the first power supply VGL and the third node N3. When the first power supply VGL and the third node N3 are in a connected state, the gating circuit 720 provides the first power supply voltage VGL to the third node N3. For example, the first input signal INPUT1, the second input signal INPUT2, and the first output signal OUT1 can control the connection between the gating terminal MS and the third node N3, so that the gating signal MS can be written to the third node N3; while the third input signal INPUT3 can control the connection between the first power supply VGL and the third node N3, so that the first power supply voltage VGL can be written to the third node N3, resetting the potential of the third node N3.

[0096] For example, when the potential of the third node N3 is high, the second output signal OUT2 output by the output circuit 740 prevents the corresponding pixel row from refreshing. After the display screen refreshes one frame, the gating circuit 720 pulls the potential of the third node N3 low again, so that during the refresh of the next frame, the gating signal MS regains control over the potential of the third node N3. After the display screen refreshes one frame, when the potential of the third node N3 is low, the gating circuit 720 also writes the first power supply voltage VGL into the third node N3 to ensure that the potential of the third node N3 remains stably low. By resetting the potential of the third node N3 using the gating circuit 720, the operational stability of the circuit can be improved.

[0097] Optionally, the strobe signal MS can come from another shift register cascaded with the shift register. The strobe signal MS provided by this other shift register can be used to strobe the second output signal OUT2 of the shift register.

[0098] For example, the shift register can be the m-th stage shift register, and the strobe terminal MS can be electrically connected to the second output terminal OUT2 of the (m-1)-th stage shift register and the (m-2)-th stage shift register, respectively.

[0099] Optionally, the gating circuit 620 includes a first transistor T1, a second transistor T2, and a third transistor T3. The first transistor T1, the second transistor T2, and the third transistor T3 are connected in series between the third node N3 and the gating terminal. The gate of the first transistor T1 is connected to the first output terminal OUT1, the gate of the second transistor T2 is connected to the first input terminal INPUT1, and the gate of the third transistor T3 is connected to the second input terminal INPUT2. (The following is a continuation of the previous paragraph.) Figures 7 to 19 Describe it.

[0100] Figure 7 A schematic diagram of the structure of a shift register according to another embodiment of the present disclosure is shown.

[0101] like Figure 7 As shown, the shift register 700 may include a shift circuit 710, a gating circuit 720, a control circuit 730, and an output circuit 740.

[0102] The gating circuit 720 may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0103] The first terminal of the first transistor T1 is connected to the third node N3, and the second terminal of the first transistor T1 is connected to the sixth node N6.

[0104] The first terminal of the second transistor T2 is connected to the sixth node N6, and the second terminal of the second transistor T2 is connected to the seventh node N7.

[0105] The first terminal of the third transistor T3 is connected to the seventh node N7, and the second terminal of the third transistor T3 is connected to the gate terminal.

[0106] The gate of the fourth transistor T4 is connected to the third input terminal INPUT3, the first terminal of the fourth transistor T4 is connected to the third node N3, and the second terminal of the fourth transistor T4 is connected to the first power supply VGL.

[0107] The control circuit 730 may include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a first capacitor C1.

[0108] The gate of the fifth transistor T5 is connected to the third node N3, the first terminal of the fifth transistor T5 is connected to the second node N2, and the second terminal of the fifth transistor T5 is connected to the fifth node N5.

[0109] The gate of the sixth transistor T6 is connected to the third node N3, the first terminal of the sixth transistor T6 is connected to the first node N1, and the second terminal of the sixth transistor T6 is connected to the fourth node N4.

[0110] The gate of the seventh transistor T7 is connected to the fifth node N5, the first terminal of the seventh transistor T7 is connected to the second terminal of the eighth transistor T8, the second terminal of the seventh transistor T7 is connected to the second power supply VGH, the gate of the eighth transistor T8 is connected to the second output terminal OUT2, and the first terminal of the eighth transistor T8 is connected to the fourth node N4.

[0111] The first terminal of the first capacitor C1 is connected to the fourth node N4, and the second terminal of the first capacitor C1 is connected to the third node N3.

[0112] The output circuit 740 may include a ninth transistor T9, a tenth transistor T10, a second capacitor C2, and a third capacitor C3;

[0113] The gate of the ninth transistor T9 is connected to the fourth node N4, the first terminal of the ninth transistor T9 is connected to the second power supply VGH, and the second terminal of the ninth transistor T9 is connected to the second output terminal OUT2.

[0114] The gate of the tenth transistor T10 is connected to the fifth node N5, the first terminal of the tenth transistor T10 is connected to the second output terminal OUT2, and the second terminal of the tenth transistor T10 is connected to the first power supply VGL.

[0115] The first terminal of the second capacitor C2 is connected to the fourth node N4, and the second terminal of the second capacitor C2 is connected to the second power supply VGH.

[0116] The first terminal of the third capacitor C3 is connected to the fifth node N5, and the second terminal of the third capacitor C3 is connected to the second output terminal OUT2.

[0117] The shift circuit 710 may include eleventh transistor T11 to twenty-seventh transistor T27 and fourth capacitor C4 to seventh capacitor C7.

[0118] The gate of the eleventh transistor T11 is connected to the first power supply VGL, the first terminal of the eleventh transistor T11 is connected to the twelfth node N12, and the second terminal of the eleventh transistor T11 is connected to the tenth node N10.

[0119] The gate of the twelfth transistor T12 is connected to the first power supply VGL, the first terminal of the twelfth transistor T12 is connected to the second node N2, and the second terminal of the twelfth transistor T12 is electrically connected to the eighth node N8.

[0120] The gate of the thirteenth transistor T13 is connected to the control terminal NCX, the first terminal of the thirteenth transistor T13 is electrically connected to the second power supply VGH, and the second terminal of the thirteenth transistor T13 is electrically connected to the second node N2.

[0121] The gate of the fourteenth transistor T14 is connected to the second clock terminal CB, the first terminal of the fourteenth transistor T14 is connected to the thirteenth node N13, and the second terminal of the fourteenth transistor T14 is connected to the fourth node N4.

[0122] The gate of the fifteenth transistor T15 is connected to the first power supply VGL, the first terminal of the fifteenth transistor T15 is connected to the fourteenth node N14, and the second terminal of the fifteenth transistor T15 is connected to the ninth node N9.

[0123] The gate of the sixteenth transistor T16 is connected to the ninth node N9, the first terminal of the sixteenth transistor T16 is connected to the eighth node N8, and the second terminal of the sixteenth transistor T16 is connected to the ninth node N9.

[0124] The gate of the seventeenth transistor T17 is connected to the ninth node N9, the first terminal of the seventeenth transistor T17 is electrically connected to the ninth node N9, and the second terminal of the seventeenth transistor T17 is connected to the fifth node N5.

[0125] The gate of the eighteenth transistor T18 is connected to the fifth node N5, the first terminal of the eighteenth transistor T18 is connected to the first node N1, and the second terminal of the eighteenth transistor T18 is connected to the second power supply VGH.

[0126] The gate of the nineteenth transistor T19 is connected to the first node, the first terminal of the nineteenth transistor T19 is connected to the second power supply VGH, and the second terminal of the nineteenth transistor T19 is connected to the first output terminal OUT1.

[0127] The gate of the twentieth transistor T20 is connected to the eighth node N8, the first terminal of the twentieth transistor T20 is connected to the first output terminal OUT1, and the second terminal of the twentieth transistor T20 is connected to the first power supply VGL.

[0128] The gate of the twenty-first transistor T21 is connected to the first clock terminal CK, the first terminal of the twenty-first transistor T21 is connected to the first input terminal INPUT1, and the second terminal of the twenty-first transistor T21 is connected to the second node N2.

[0129] The gate of the 22nd transistor T22 is connected to the second node N2, the first terminal of the 22nd transistor T22 is connected to the 12th node N12, and the second terminal of the 22nd transistor T22 is connected to the first clock terminal CK.

[0130] The gate of the 23rd transistor T23 is connected to the first clock terminal CK, the first terminal of the 23rd transistor T23 is connected to the first power supply VGL, and the second terminal of the 23rd transistor T23 is connected to the 12th node N12.

[0131] The gate of the 24th transistor T24 is connected to the first clock terminal CK, the first terminal of the 24th transistor T24 is connected to the first input terminal INPUT1, and the second terminal of the 24th transistor T24 is connected to the 14th node N14.

[0132] The gate of the 25th transistor T25 is connected to the 12th node N12, the first terminal of the 25th transistor T25 is connected to the second power supply VGH, and the second terminal of the 25th transistor T25 is connected to the 11th node N11.

[0133] The gate of the 26th transistor T26 is connected to the 10th node N10, the first terminal of the 26th transistor T26 is connected to the second clock terminal CB, and the second terminal of the 26th transistor T26 is connected to the 13th node N13.

[0134] The gate of the twenty-seventh transistor T27 is connected to the ninth node N9, the first terminal of the twenty-seventh transistor T27 is connected to the eleventh node N11, and the second terminal of the twenty-seventh transistor T27 is connected to the second clock terminal CB.

[0135] The first terminal of the fourth capacitor C4 is connected to the first node N1, and the second terminal of the fourth capacitor C4 is connected to the second power supply VGH.

[0136] The first terminal of the fifth capacitor C5 is connected to the first output terminal OUT1, and the second terminal of the fifth capacitor C5 is connected to the first power supply VGL.

[0137] The first terminal of the sixth capacitor C6 is connected to the eleventh node N11, and the second terminal of the sixth capacitor C6 is connected to the ninth node N9.

[0138] The first terminal of the seventh capacitor C7 is connected to the tenth node N10, and the second terminal of the seventh capacitor C7 is connected to the thirteenth node N13.

[0139] In the embodiments of this disclosure, the first transistor T1 to the twenty-seventh transistor T27 are P-type TFT transistors. For example, thin-film transistors with an active layer of low-temperature doped polycrystalline silicon (LTPS). Those skilled in the art will understand that the first transistor T1 to the twenty-seventh transistor T27 in this disclosure can also be N-type TFT transistors, such as thin-film transistors with an active layer of indium gallium zinc oxide (IGZO), by correspondingly changing the level of the gate conduction signal of each transistor.

[0140] Furthermore, those skilled in the art will understand that capacitors can be implemented as single capacitors or multiple capacitor units connected in parallel or series, as long as they can achieve their respective functions.

[0141] In the description of the embodiments of this disclosure, the first node N1 to the fourteenth node N14 do not represent actual existing components, but rather represent the junction points of related circuit connections in the circuit diagram.

[0142] Optionally, for multiple cascaded shift drivers, the shift register can be the m-th stage shift driver. The first input terminal INPUT1 can be connected to the first output terminal OUT1 of the (m-1)-th stage shift driver, the second input terminal INPUT2 can be connected to the thirteenth node N13 of the (m-2)-th stage shift driver, and the third input terminal INPUT3 can be connected to the eleventh node N11 of the (m-1)-th stage shift driver.

[0143] Figure 8 The diagram schematically illustrates the waveform of the output signal of the shift register in the high refresh rate region according to an embodiment of the present disclosure. Figure 9 The diagram schematically illustrates the waveform of the output signal of the shift register in the low refresh rate region according to an embodiment of the present disclosure. Figure 10 The diagram schematically illustrates the waveform of the output signal of a shift register switching between high refresh rate and low refresh rate regions according to an embodiment of the present disclosure. Figure 11 A signal timing diagram of a shift register 700 according to an embodiment of the present disclosure is schematically shown. Figure 12 The diagram schematically illustrates the signal waveforms of a shift register 700 according to an embodiment of the present disclosure. Figure 13 The illustration schematically shows the effect diagrams of two driving circuits according to embodiments of the present disclosure. Figure 12 In this diagram, lines of different gray levels can represent the signal waveforms of the last high-frequency line and the normal high-frequency line, respectively. Darker gray lines represent the signal waveform of the last high-frequency line, while lighter gray lines represent the signal waveform of the normal high-frequency line.

[0144] The following is based on Figure 7 Taking the structure of the shift register 700 shown as an example, combined with... Figures 8 to 13 The operation of the shift register 700 provided in the embodiments of this disclosure is described. Out(1) to out(4) are signal waveform diagrams of the high refresh frequency region, and Out(5) to out(8) are signal waveform diagrams of the low refresh frequency region.

[0145] like Figures 8 to 12 As shown, in the high refresh rate region, the strobe signal MS is at a low level.

[0146] During time period t1, the first input signal INPUT1, the second input signal INPUT2, and the first output signal OUT1 are all low. The first transistor T1, the second transistor T2, and the third transistor T3 are turned on. A low-level strobe signal MS is written to the third node N3, and the sixth transistor T6 is turned on. At this time, the voltage at the fourth node N4 and the voltage at the first node N1 are both high. The ninth transistor T9 is turned off.

[0147] During time period t2, the first input signal INPUT1 is high, the voltage of the fourth node N4 and the voltage of the first node N1 are both low, the ninth transistor T9 is turned on, and the second output signal OUT2 is high. Furthermore, the voltage of the third node N3 is low, and the fifth transistor T5 is turned on. The voltages of the second node N2, the eighth node N8, and the fifth node N5 are all high, and the tenth transistor T10 is turned off.

[0148] During time period t3, the first input signal INPUT1 is at a low level, and the voltages of the second node N2, the eighth node N8, and the ninth node N9 are all at a low level. Since the threshold voltage Vth of the twenty-fourth transistor T24 and the fifteenth transistor T15 will cause the voltage from the first input terminal INPUT1 to the fifth node N5 to decay, the voltage of the fifth node N5 is higher than the first power supply voltage VGL. The tenth transistor T10 is not sufficiently turned on, which results in the second output signal OUT being higher than the first power supply voltage VGL.

[0149] During time period t4, the second clock signal CB changes from high level to low level. Due to the bootstrap effect of capacitor C2, the voltage of the fifth node 5 is lower than the first power supply voltage VGL. The tenth transistor T10 is fully turned on, and the voltage of the second output signal OUT2 is the same as the first power supply voltage VGL.

[0150] In the low refresh rate region, the strobe signal MS is high.

[0151] During time period t1, the first input voltage INPUT1, the second input voltage INPUT2, and the first output signal OUT1 are all at low levels. The first transistor T1, the second transistor T2, and the third transistor T3 are turned on. A high-level strobe signal MS is written to the third node N3, and the sixth transistor is turned off. The voltage at the fourth node N4 remains high from the previous time step, the ninth transistor T9 is turned off, and the second power supply and the second output terminal are in a cutoff state. At this time, the voltages at the second node N2, the eighth node N8, and the ninth node N9 are at low levels, the voltage at the fifth node N5 is at a low level, the tenth transistor T10 is turned on, and the first power supply VGL is connected to the second output terminal OUT2. The second output terminal OUT2 outputs the first power supply voltage VGL.

[0152] During time period t2, the first input voltage INPUT1 is high, the first node N1 is low, the third node N3 is high, the sixth transistor T6 is off, the voltage of the fourth node N4 remains high as in the previous moment, the ninth transistor T9 is off, and the second power supply VGH is in a cutoff state with the second output terminal OUT2. At this time, the voltages of the second node T2, the eighth node N8, and the ninth node N9 are high, the sixteenth, seventeenth, and fifth transistors are off, the fifth node N5 remains low as in the previous moment, and the tenth transistor T10 connects the second output terminal OUT2 with the first power supply VGL, outputting the first power supply voltage VGL from the second output terminal OUT.

[0153] During time period t3, the voltage of the first input signal INPUT1 is low, and the voltages of the second node N2, the eighth node N8, and the ninth node N9 are also low. Since the threshold voltage Vth of the twenty-fourth transistor T24 and the fifteenth transistor T15 causes the voltage from the first input terminal INPUT1 to the fifth node N5 to decay, the voltage of the fifth node N5 is higher than the first power supply voltage VGL. The tenth transistor T10 is not sufficiently turned on, which results in the second output signal OUT2 being higher than the first power supply voltage VGL.

[0154] During time period t4, the second clock signal CB changes from high level to low level. Due to the bootstrap effect of capacitor C2, the voltage of the fifth node 5 is lower than the first power supply voltage VGL. The tenth transistor T10 fully conducts the second output signal OUT2 to output the first power supply voltage VGL.

[0155] In shift register 700, the first output terminal OUT1 is connected to the gate of the first transistor T1, so as to control the on and off states of the first transistor T1 using the first output signal OUT1. Based on the phase difference between the first output signal OUT1 and the first input signal INPUT1, the leakage time from the gating terminal MS to the third node N3 can be reduced, making the levels of the third node N3 and the seventh node N7 tend to be consistent, reducing the impact of this leakage on the on state of the fifth transistor T5, thereby improving the bright band problem at the critical position of refresh frequency switching and effectively improving display performance.

[0156] refer to Figure 13 The first type of driving circuit may include multiple cascaded shift registers 200. The second type of driving circuit may include multiple cascaded shift registers 700. Based on Figure 13 As can be seen from the signal waveforms shown, there is a significant difference between the high-frequency normal row output signal and the high-frequency last row output signal of the first driving circuit, while the high-frequency normal row output signal and the high-frequency last row output signal of the second driving circuit of this embodiment tend to be consistent.

[0157] Figure 14 A schematic diagram of the structure of a shift register according to another embodiment of the present disclosure is shown.

[0158] like Figure 14 As shown, the shift register 1400 may include a shift circuit 1410, a gating circuit 1420, a control circuit 1430, and an output circuit 1440. The shift circuit 1410, control circuit 1430, and output circuit 1440 are similar to the shift circuit 710, control circuit 730, and output circuit 740 described above, and will not be repeated for simplicity. The connection method of the transistors in the gating circuit 1420 is not limited to the connection method shown in the gating circuit 720.

[0159] For example, the gating circuit 1420 may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0160] The first terminal of the first transistor T1 is connected to the third node N3, and the second terminal of the first transistor T1 is connected to the sixth node N6.

[0161] The first terminal of the second transistor T2 is connected to the seventh node N7, and the second terminal of the second transistor T2 is connected to the gate terminal.

[0162] The first terminal of the third transistor T3 is connected to the sixth node N6, and the second terminal of the third transistor T3 is connected to the seventh node N7.

[0163] The gate of the fourth transistor T4 is connected to the third input terminal INPUT3, the first terminal of the fourth transistor T4 is connected to the third node N3, and the second terminal of the fourth transistor T4 is connected to the first power supply VGL.

[0164] Figure 15 A schematic diagram of the structure of a shift register according to another embodiment of the present disclosure is shown.

[0165] like Figure 15 As shown, the shift register 1500 may include a shift circuit 1510, a gating circuit 1520, a control circuit 1530, and an output circuit 1540. The shift circuit 1510, control circuit 1530, and output circuit 1540 are similar to the shift circuit 710, control circuit 730, and output circuit 740 described above, and will not be repeated for simplicity. The connection method of the transistors in the gating circuit 1520 is not limited to the connection method shown in the gating circuit 720.

[0166] For example, the gating circuit 1520 may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0167] The first terminal of the first transistor T1 is connected to the sixth node N6, and the second terminal of the first transistor T1 is connected to the seventh node N7.

[0168] The first terminal of the second transistor T2 is connected to the third node N3, and the second terminal of the second transistor T2 is connected to the sixth node N6.

[0169] The first terminal of the third transistor T3 is connected to the seventh node N7, and the second terminal of the third transistor T3 is connected to the gate terminal.

[0170] The gate of the fourth transistor T4 is connected to the third input terminal INPUT3, the first terminal of the fourth transistor T4 is connected to the third node N3, and the second terminal of the fourth transistor T4 is connected to the first power supply VGL.

[0171] Figure 16 A schematic diagram of the structure of a shift register according to another embodiment of the present disclosure is shown.

[0172] like Figure 16 As shown, the shift register 1600 may include a shift circuit 1610, a gating circuit 1620, a control circuit 1630, and an output circuit 1640. The shift circuit 1610, control circuit 1630, and output circuit 1640 are similar to the shift circuit 710, control circuit 730, and output circuit 740 described above, and will not be repeated for simplicity. The connection method of the transistors in the gating circuit 1620 is not limited to the connection method shown in the gating circuit 720.

[0173] For example, the gating circuit 1620 may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0174] The first terminal of the first transistor T1 is connected to the seventh node N7, and the second terminal of the first transistor T1 is connected to the gate terminal.

[0175] The first terminal of the second transistor T2 is connected to the third node N3, and the second terminal of the second transistor T2 is connected to the sixth node N6.

[0176] The first terminal of the third transistor T3 is connected to the sixth node N6, and the second terminal of the third transistor T3 is connected to the seventh node N7.

[0177] The gate of the fourth transistor T4 is connected to the third input terminal INPUT3, the first terminal of the fourth transistor T4 is connected to the third node N3, and the second terminal of the fourth transistor T4 is connected to the first power supply VGL.

[0178] Figure 17 A schematic diagram of the structure of a shift register according to another embodiment of the present disclosure is shown.

[0179] like Figure 17 As shown, the shift register 1700 may include a shift circuit 1710, a gating circuit 1720, a control circuit 1730, and an output circuit 1740. The shift circuit 1710, control circuit 1730, and output circuit 1740 are similar to the shift circuit 710, control circuit 730, and output circuit 740 described above, and will not be repeated for simplicity. The connection method of the transistors in the gating circuit 1720 is not limited to the connection method shown in the gating circuit 720.

[0180] For example, the gating circuit 1720 may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0181] The first terminal of the first transistor T1 is connected to the sixth node N6, and the second terminal of the first transistor T1 is connected to the seventh node N7.

[0182] The first terminal of the second transistor T2 is connected to the seventh node N7, and the second terminal of the second transistor T2 is connected to the gate terminal.

[0183] The first terminal of the third transistor T3 is connected to the third node N3, and the second terminal of the third transistor T3 is connected to the sixth node N6.

[0184] The gate of the fourth transistor T4 is connected to the third input terminal INPUT3, the first terminal of the fourth transistor T4 is connected to the third node N3, and the second terminal of the fourth transistor T4 is connected to the first power supply VGL.

[0185] Figure 18 A schematic diagram of the structure of a shift register according to another embodiment of the present disclosure is shown.

[0186] like Figure 18 As shown, the shift register 1800 may include a shift circuit 1810, a gating circuit 1820, a control circuit 1830, and an output circuit 1840. The shift circuit 1810, control circuit 1830, and output circuit 1840 are similar to the shift circuit 710, control circuit 730, and output circuit 740 described above, and will not be repeated for simplicity. The connection method of the transistors in the gating circuit 1820 is not limited to the connection method shown in the gating circuit 720.

[0187] For example, the gating circuit 1820 may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0188] The first terminal of the first transistor T1 is connected to the seventh node N7, and the second terminal of the first transistor T1 is connected to the gate terminal.

[0189] The first terminal of the second transistor T2 is connected to the sixth node N6, and the second terminal of the second transistor T2 is connected to the seventh node N7.

[0190] The first terminal of the third transistor T3 is connected to the third node N3, and the second terminal of the third transistor T3 is connected to the sixth node N6.

[0191] The gate of the fourth transistor T4 is connected to the third input terminal INPUT3, the first terminal of the fourth transistor T4 is connected to the third node N3, and the second terminal of the fourth transistor T4 is connected to the first power supply VGL.

[0192] Figure 19 A schematic diagram of the structure of a shift register according to another embodiment of the present disclosure is shown.

[0193] like Figure 19 As shown, the shift register 1900 may include a shift circuit 1910, a gating circuit 1920, a control circuit 1930, and an output circuit 1940. The shift circuit 1910 and control circuit 1930 are similar to the shift circuit 710, control circuit 730, and output circuit 740 described above, and will not be repeated for simplicity. The transistors in the gating circuit 1920 are not limited to the transistors shown in the gating circuit 720.

[0194] For example, the gating circuit 1920 may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The second transistor T2 is a dual-gate transistor. Similarly, in embodiments of this disclosure, at least one of the first transistor T1 and the third transistor T3 may also be a dual-gate transistor.

[0195] The first terminal of the first transistor T1 is connected to the third node N3, and the second terminal of the first transistor T1 is connected to the sixth node N6.

[0196] The first terminal of the second transistor T2 is connected to the sixth node N6, and the second terminal of the second transistor T2 is connected to the seventh node N7.

[0197] The first terminal of the third transistor T3 is connected to the seventh node N7, and the second terminal of the third transistor T3 is connected to the gate terminal.

[0198] The gate of the fourth transistor T4 is connected to the third input terminal INPUT3, the first terminal of the fourth transistor T4 is connected to the third node N3, and the second terminal of the fourth transistor T4 is connected to the first power supply VGL.

[0199] Figure 20 A schematic diagram of the structure of a drive circuit according to an embodiment of the present disclosure is shown.

[0200] like Figure 20As shown, the driver circuit 2000 includes M cascaded shift registers, where M is a positive integer greater than 1. The M shift registers include the first-stage shift register ST1, ..., the m-th-stage shift register STm, ..., and the M-th-stage shift register STM.

[0201] In this embodiment, shift register ST1 can be any one of the shift registers 600, 700, 1400, 1500, 1600, 1700, 1800, and 1900 described above. For example, all M shift registers can be shift register 600. Alternatively, all M shift registers can be shift register 700. Further details will not be provided here.

[0202] In this embodiment of the disclosure, among the M cascaded shift registers, the input signal INPUT1 of the first-stage shift register ST1 is the start signal GSTV.

[0203] Figure 21 A schematic diagram of the structure of a drive circuit according to another embodiment of the present disclosure is shown.

[0204] In this embodiment of the disclosure, the driving circuit 2100 includes M cascaded shift registers.

[0205] In this embodiment of the disclosure, the first input terminal INPUT1 of the m-th stage shift register STm is electrically connected to the first output terminal OUT1 of the (m-1)-th stage shift register STm-1, the second input terminal INPUT2 of the m-th stage shift register STm is electrically connected to the thirteenth node N13 of the (m-2)-th stage shift register, and the third input terminal INPUT3 of the m-th stage shift register is electrically connected to the eleventh node N11 of the (m-1)-th stage shift register, where 2 < m ≤ M, m is an integer, and M is an integer greater than 2.

[0206] In this embodiment of the present disclosure, the first output terminal OUT1 of the m-th stage shift register STm is also connected to the gate of the first transistor T1 in the m-th stage shift register STm. The first output terminal OUT1 of the (m-1)-th stage shift register STm-1 is connected to the gate of the first transistor T1 in the (m-1)-th stage shift register STm-1. The first output terminal OUT1 of the (m-2)-th stage shift register STm-2 is connected to the gate of the first transistor T1 in the (m-2)-th stage shift register STm-2.

[0207] In this embodiment of the present disclosure, the first clock terminal CK of the m-th stage shift register is electrically connected to the clock signal line ck, and the second clock terminal CB of the m-th stage shift register is electrically connected to the clock signal line cb. The first clock terminal CK of the (m+1)-th stage shift register is electrically connected to the clock signal line cb, and the second clock terminal CB of the (m+1)-th stage shift register is electrically connected to the clock signal line ck.

[0208] In this embodiment of the disclosure, the strobe terminal MS is electrically connected to the strobe signal line ms.

[0209] The following description uses the film layer of shift register 1500 as an example to illustrate each film layer of the shift register in this embodiment of the present disclosure.

[0210] Figure 22A A schematic plan view of a semiconductor layer according to an embodiment of the present disclosure is shown. Figure 22B A schematic plan view of the first conductive layer according to an embodiment of the present disclosure is shown. Figure 22C A schematic plan view of the second conductive layer according to an embodiment of the present disclosure is shown. Figure 22D A schematic plan view of a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer according to embodiments of the present disclosure is shown. Figure 22E A schematic plan view of the third and fourth conductive layers according to embodiments of the present disclosure is shown. Figure 22F A schematic plan view of a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer according to an embodiment of the present disclosure is shown.

[0211] like Figures 22A to 22F As shown, semiconductor layer 2210 may be formed using a process employing semiconductor material patterning. Semiconductor layer 2210 includes at least a portion of the active portion of the aforementioned transistors. Exemplarily, semiconductor layer 2210 can be used to fabricate the active portions of transistors T1 to T27 in the aforementioned shift register 1500. The active portion of each transistor includes a channel portion and doped portions located on both sides of the channel portion.

[0212] The portions on both sides of each channel are conductiveized by processes such as ion doping to become the doped portions of each transistor. The doped portions include the source and drain located on both sides of the channel, namely the first and second electrodes mentioned above.

[0213] It should be further noted that the source and drain of each of the above transistors can be symmetrical in structure, so their source and drain can be indistinguishable in physical structure. In the embodiments of this disclosure, in order to distinguish the transistors, except for the gate which serves as the control electrode, one electrode is directly described as the first electrode and the other electrode as the second electrode. Therefore, in the embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0214] The first conductive layer 2220 includes conductive portions GA1 to GA24. At least a portion of the conductive portions GA1 to GA24 may overlap with the channel portion of the transistor to form the gate of the transistor.

[0215] For example, the active portion of the first transistor T1 includes a channel portion CH1a and doped portions located on both sides of the channel portion CH1a. The conductive portion GA1 overlaps with the channel portion CH1a of the first transistor T1 to form the gate of the first transistor T1.

[0216] The active portion of the second transistor T2 includes a channel portion CH1b and doped portions located on both sides of the channel portion CH1b. The conductive portion GA2 overlaps with the channel portion CH1b of the second transistor T2 to form the gate of the second transistor T2.

[0217] The active portion of the third transistor T3 includes a channel portion CH1c and doped portions located on both sides of the channel portion CH1c. The conductive portion GA3 overlaps with the channel portion CH1c of the third transistor T3 to form the gate of the third transistor T3.

[0218] The active portion of the fourth transistor T4 includes a channel portion CH2 and doped portions located on both sides of the channel portion CH2. The conductive portion GA4 overlaps with the channel portion CH2 of the fourth transistor T4 to form the gate of the fourth transistor T4.

[0219] The active portion of the fifth transistor T5 includes a channel portion CH3 and doped portions located on both sides of the channel portion CH3. The conductive portion GA5 overlaps with the channel portion CH3 of the fifth transistor T5 to form the gate of the fifth transistor T5.

[0220] The active portion of the sixth transistor T6 includes a channel portion CH4a and doped portions located on both sides of the channel portion CH4a. The conductive portion GA6 overlaps with the channel portion CH4a of the sixth transistor T6 to form the gate of the sixth transistor T6.

[0221] The active portion of the seventh transistor T7 includes a channel portion CH4b and doped portions located on both sides of the channel portion CH4b. The conductive portion GA7 overlaps with the channel portion CH4b of the seventh transistor T7 to form the gate of the seventh transistor T7.

[0222] The active portion of the eighth transistor T8 includes a channel portion CH4c and doped portions located on both sides of the channel portion CH4c. The conductive portion GA8 overlaps with the channel portion CH4c of the eighth transistor T8 to form the gate of the eighth transistor T8.

[0223] The active portion of the ninth transistor T9 includes a channel portion CH5a and doped portions located on both sides of the channel portion CH5a. The conductive portion GA9 overlaps with the channel portion CH5a of the ninth transistor T9 to form the gate of the ninth transistor T9.

[0224] The active portion of the tenth transistor T10 includes a channel portion CH5b and doped portions located on both sides of the channel portion CH5b. The conductive portion GA7 overlaps with the channel portion CH7b of the tenth transistor T10 to form the gate of the tenth transistor T10.

[0225] The active portion of the eleventh transistor T11 includes a channel portion CH6a and doped portions located on both sides of the channel portion CH6a. The conductive portion GA10 overlaps with the channel portion CH6a of the eleventh transistor T11 to form the gate of the eleventh transistor T11.

[0226] The active portion of the twelfth transistor T12 includes a channel portion CH7a and doped portions located on both sides of the channel portion CH7a. The conductive portion GA11 overlaps with the channel portion CH7a of the twelfth transistor T12 to form the gate of the twelfth transistor T12.

[0227] The active portion of the thirteenth transistor T13 includes a channel portion CH7b and doped portions located on both sides of the channel portion CH7b. The conductive portion GA12 overlaps with the channel portion CH7b of the thirteenth transistor T13 to form the gate of the thirteenth transistor T13.

[0228] The active portion of the fourteenth transistor T14 includes a channel portion CH8 and doped portions located on both sides of the channel portion CH8. The conductive portion GA13 overlaps with the channel portion CH8 of the fourteenth transistor T14 to form the gate of the fourteenth transistor T14.

[0229] The active portion of the fifteenth transistor T15 includes a channel portion CH9 and doped portions located on both sides of the channel portion CH9. The conductive portion GA10 overlaps with the channel portion CH9 of the fifteenth transistor T15 to form the gate of the fifteenth transistor T15.

[0230] The active portion of the sixteenth transistor T16 includes a channel portion CH7c and doped portions located on both sides of the channel portion CH7c. The conductive portion GA14 overlaps with the channel portion CH7c of the sixteenth transistor T16 to form the gate of the sixteenth transistor T16.

[0231] The active portion of the seventeenth transistor T17 includes a channel portion CH7d and doped portions located on both sides of the channel portion CH7d. The conductive portion GA14 overlaps with the channel portion CH7d of the seventeenth transistor T17 to form the gate of the seventeenth transistor T17.

[0232] The active portion of the eighteenth transistor T18 includes a channel portion CH7e and doped portions located on both sides of the channel portion CH7e. The conductive portion GA15 overlaps with the channel portion CH7e of the eighteenth transistor T18 to form the gate of the eighteenth transistor T18.

[0233] The active portion of the nineteenth transistor T19 includes a channel portion CH10a and doped portions located on both sides of the channel portion CH10a. The conductive portion GA16 overlaps with the channel portion CH10a of the nineteenth transistor T19 to form the gate of the nineteenth transistor T19.

[0234] The active portion of the twentieth transistor T20 includes a channel portion CH10b and doped portions located on both sides of the channel portion CH10b. The conductive portion GA17 overlaps with the channel portion CH10b of the twentieth transistor T20 to form the gate of the twentieth transistor T20.

[0235] The active portion of the twenty-first transistor T21 includes a channel portion CH11 and doped portions located on both sides of the channel portion CH11. The conductive portion GA18 overlaps with the channel portion CH11 of the twenty-first transistor T21 to form the gate of the twenty-first transistor T21.

[0236] The active portion of the twenty-second transistor T22 includes a channel portion CH6b and doped portions located on both sides of the channel portion CH6b. The conductive portion GA15 overlaps with the channel portion CH6b of the twenty-first transistor T22 to form the gate of the twenty-first transistor T22.

[0237] The active portion of the 23rd transistor T23 includes a channel portion CH12 and doped portions located on both sides of the channel portion CH12. The conductive portion GA18 overlaps with the channel portion CH12 of the 23rd transistor T23 to form the gate of the 23rd transistor T23.

[0238] The active portion of the 24th transistor T24 includes a channel portion CH13 and doped portions located on both sides of the channel portion CH13. The conductive portion GA18 overlaps with the channel portion CH13 of the 24th transistor T24 to form the gate of the 24th transistor T24.

[0239] The active portion of the 25th transistor T25 includes a channel portion CH14 and doped portions located on both sides of the channel portion CH14. The conductive portion GA19 overlaps with the channel portion CH14 of the 25th transistor T25 to form the gate of the 25th transistor T25.

[0240] The active portion of the 26th transistor T26 includes a channel portion CH15 and doped portions located on both sides of the channel portion CH15. The conductive portion GA20 overlaps with the channel portion CH15 of the 26th transistor T26 to form the gate of the 26th transistor T26.

[0241] The active portion of the 27th transistor T27 includes a channel portion CH16 and doped portions located on both sides of the channel portion CH16. The conductive portion GA14 overlaps with the channel portion CH16 of the 27th transistor T27 to form the gate of the 27th transistor T27.

[0242] The second conductive layer 2230 includes conductive portions GB1 to GB8. At least a portion of the conductive portions GA1 to GA24 can overlap with the conductive portions GB1 to GB8 to form a capacitor.

[0243] For example, conductive part GB1 overlaps with conductive part GA5 to form a first capacitor C1. Conductive part GB2 overlaps with conductive part GA9 to form a second capacitor C2. Conductive part GB3 overlaps with conductive part CA7 to form a third capacitor C3. Conductive part GB4 overlaps with conductive part GA14 to form a fourth capacitor C4. Conductive part GB5 overlaps with conductive part GA21 to form a fifth capacitor C5. Conductive part GB6 overlaps with conductive part GA22 to form a sixth capacitor C6. Conductive part GB7 overlaps with conductive part GA20 to form a seventh capacitor C7.

[0244] The third conductive layer includes adapters GC1 to GC44. Based on the adapters, the semiconductor layer 2210, the first conductive layer 2220, and the second conductive layer 2230 can be connected to obtain multiple film layers 2240. The fourth conductive layer includes a first input signal line input1 connected to the first input terminal INPUT1, a second input signal line input2 connected to the second input terminal INPUT2, a first power line vgl connected to the first power supply VGL, a second power line vgh connected to the second power supply VGL, a first clock signal line ck connected to the first clock signal terminal CK, a second clock signal line cb connected to the clock signal terminal CB, a control signal line ncx, a strobe signal line ms, trace L1, and trace L2. The third conductive layer and the fourth conductive layer can be connected to obtain multiple film layers 2250. Based on the adapters, the semiconductor layer 2210, the first conductive layer 2220, the second conductive layer 2230, and the fourth conductive layer can be connected to obtain multiple film layers 2260.

[0245] For example, the gate of the first transistor T1 is connected to the second terminal of the nineteenth transistor T19 and the first terminal of the twentieth transistor T20 through the adapter GC41, the first terminal of the first transistor T1 is connected to the second terminal of the second transistor T2, and the second terminal of the first transistor T1 is connected to the first terminal of the third transistor T3.

[0246] The gate of the second transistor T2 is connected to the first input signal line input1 through the adapter GC20. The first terminal of the second transistor T2 is connected to the second terminal of the first capacitor C1 through the trace L1. The second terminal of the second transistor T2 is connected to the first terminal of the first transistor T1.

[0247] The gate of the third transistor T3 is connected to the second input signal line input2, the first terminal of the third transistor T3 is connected to the second terminal of the first transistor T1, and the second terminal of the third transistor T3 is connected to the strobe signal line ms through the adapter GC5.

[0248] The first terminal of the fourth transistor T4 is connected to the second terminal of the first capacitor C1 via adapter GC39, and the second terminal of the fourth transistor T4 is connected to the first power signal line vgl via adapter GC38.

[0249] The gate of the fifth transistor T5 is connected to the second terminal of the first capacitor C1. The first terminal of the fifth transistor T5 is connected to the first terminal of the twelfth transistor T12 through the adapter GC18. The second terminal of the fifth transistor T5 is connected to the gate of the tenth transistor T10 through the adapters GC40, GC42 and GC22.

[0250] The gate of the sixth transistor T6 is connected to the second terminal of the first capacitor C1 through the adapter GC28, the first terminal of the sixth transistor T6 is connected to the gate of the nineteenth transistor T19 through the adapter GC21, and the second terminal of the sixth transistor T6 is connected to the gate of the ninth transistor T9 through the adapter GC29.

[0251] The gate of the seventh transistor T7 is connected to the gate of the tenth transistor T10. The first terminal of the seventh transistor T7 is connected to the second terminal of the eighth transistor T8. The second terminal of the seventh transistor T7 is connected to the second power signal line Vgh through the adapter GC35. The gate of the eighth transistor T8 is connected to the second output terminal OUT2. The first terminal of the eighth transistor T8 is connected to the gate of the ninth transistor T9 through the adapter GC29.

[0252] The gate of the ninth transistor T9 is connected to the first terminal of the second capacitor C2, the first terminal of the ninth transistor T9 is connected to the second power line vgh through the adapter GC6, and the second terminal of the ninth transistor T9 is connected to the second output terminal OUT2.

[0253] The gate of the tenth transistor T10 is connected to the first terminal of the third capacitor C3, the first terminal of the tenth transistor T10 is connected to the second output terminal OUT2, and the second terminal of the tenth transistor T10 is connected to the first power supply line Vgl.

[0254] The gate of the eleventh transistor T11 is connected to the first power line vgl through the adapter GC15. The first terminal of the eleventh transistor T11 is connected to the second terminal of the twenty-third transistor T23 through the adapter GC16. The second terminal of the eleventh transistor T11 is connected to the gate of the twenty-sixth transistor T26 through the adapter GC17.

[0255] The gate of the twelfth transistor T12 is connected to the first power line vgl through the adapter GC15. The first terminal of the twelfth transistor T12 is connected to the second terminal of the twenty-first transistor T21. The second terminal of the twelfth transistor T12 is connected to the gate of the twentieth transistor T20 through the connector GC33.

[0256] The gate of the thirteenth transistor T13 is connected to the control signal line ncx via the adapter GC26. The first terminal of the thirteenth transistor T13 is connected to the second power supply line vgh. The second terminal of the thirteenth transistor T13 is connected to the second node N2.

[0257] The gate of the fourteenth transistor T14 is connected to the second clock signal line cb, the first terminal of the fourteenth transistor T14 is connected to the second terminal of the seventh capacitor C7, and the second terminal of the fourteenth transistor T14 is connected to the gate of the ninth transistor T9 through the adapter GC11.

[0258] The gate of the fifteenth transistor T15 is connected to the first power signal line vgl through the adapter GC15. The first terminal of the fifteenth transistor T15 is connected to the second terminal of the twenty-fourth transistor T24 through the adapter GC7. The second terminal of the fifteenth transistor T15 is connected to the gate of the seventeenth transistor T17 through the adapter GC23.

[0259] The gate of the sixteenth transistor T16 is connected to the gate of the seventeenth transistor T17. The first terminal of the sixteenth transistor T16 is connected to the gate of the twentieth transistor T20 through the adapter GC33. The second terminal of the sixteenth transistor T16 is connected to the gate of the seventeenth transistor T17 through the adapter GC32.

[0260] The gate of the seventeenth transistor T17 is connected to the gate of the sixteenth transistor T16. The first terminal of the seventeenth transistor T17 is connected to the gate of the sixteenth transistor T16 through the adapter GC32. The second terminal of the seventeenth transistor T17 is connected to the gate of the tenth transistor T10 through the adapters GC40 and GC42.

[0261] The gate of the eighteenth transistor T18 is connected to the twenty-first transistor T21, the first terminal of the eighteenth transistor T18 is connected to the gate of the ninth transistor T9, and the second terminal of the eighteenth transistor T18 is connected to the second power supply line Vgh.

[0262] The gate of the nineteenth transistor T19 is connected to the gate of the ninth transistor T9. The first terminal of the nineteenth transistor T19 is connected to the second power line vgh through the adapter GC19. The second terminal of the nineteenth transistor T19 is connected to the first output terminal OUT1.

[0263] The gate of the twentieth transistor T20 is connected to the second terminal of the twelfth transistor T20 via the adapter GC33. The first terminal of the twentieth transistor T20 is connected to the first output terminal OUT1. The second terminal of the twentieth transistor T20 is connected to the first power supply line vgl.

[0264] The gate of the twenty-first transistor T21 is connected to the first clock signal line ck. The first terminal of the twenty-first transistor T21 is connected to the first input terminal INPUT1 through the adapter GC2. The second terminal of the twenty-first transistor T21 is connected to the gate of the twenty-second transistor T22 through the adapter GC8.

[0265] The gate of the twenty-second transistor T22 is connected to the second terminal of the twenty-first transistor T21 through the adapter GC8. The first terminal of the twenty-second transistor T22 is connected to the second terminal of the twenty-third transistor T23. The second terminal of the twenty-second transistor T22 is connected to the first clock signal line ck.

[0266] The gate of the twenty-third transistor T23 is connected to the first clock signal line ck, the first terminal of the twenty-third transistor T23 is connected to the first power supply line vgl, and the second terminal of the twenty-third transistor T23 is connected to the first terminal of the eleventh transistor T11.

[0267] The gate of the 24th transistor T24 is connected to the first clock signal line ck. The first terminal of the 24th transistor T24 is connected to the first input terminal INPUT1 through the adapter GC2. The second terminal of the 24th transistor T24 is connected to the first terminal of the 15th transistor T15 through the adapter GC7.

[0268] The gate of the twenty-fifth transistor T25 is connected to the second terminal of the twenty-third transistor T23 through the adapter GC16. The first terminal of the twenty-fifth transistor T25 is connected to the second power line vgh through the adapter GC25. The second terminal of the twenty-fifth transistor T25 is connected to the first terminal of the twenty-seventh transistor T27.

[0269] The gate of the twenty-sixth transistor T26 is connected to the second terminal of the eleventh transistor T11 through the adapter GC17. The first terminal of the twenty-sixth transistor T26 is connected to the second clock signal line cb. The second terminal of the twenty-sixth transistor T26 is connected to the first terminal of the fourteenth transistor.

[0270] The gate of the 27th transistor T27 is connected to the gate of the 17th transistor T17. The first terminal of the 27th transistor T27 is connected to the first terminal of the 25th transistor T25 through adapter GC24 and adapter GC37. The second terminal of the 27th transistor T27 is connected to the second clock signal line cb through adapter GC31.

[0271] The first terminal of the first capacitor C1 is connected to the gate of the ninth transistor T9 via the adapter GC29, and the second terminal of the first capacitor C1 is connected to the first terminal of the second transistor T2.

[0272] The first end of the second capacitor C2 is connected to the gate of the ninth transistor T9 via the adapter GC6, and the second end of the second capacitor C2 is connected to the second power supply line vgh.

[0273] The first terminal of the third capacitor C3 is connected to the gate of the seventh transistor T7, and the second terminal of the third capacitor C3 is connected to the second output terminal OUT2.

[0274] The first terminal of the fourth capacitor C4 is connected to the gate of the ninth transistor T9, and the second terminal of the fourth capacitor C4 is connected to the second power supply line Vgh.

[0275] The first end of the fifth capacitor C5 is connected to the first output terminal OUT1, and the second end of the fifth capacitor C5 is connected to the first power line vgl through the adapter GC44.

[0276] The first terminal of the sixth capacitor C6 is connected to the second terminal of the twenty-fifth transistor T25, and the second terminal of the sixth capacitor C6 is connected to the gate of the seventeenth transistor T17.

[0277] The first terminal of the seventh capacitor C7 is connected to the gate of the twenty-sixth transistor T26, and the second terminal of the seventh capacitor C7 is connected to the second terminal of the twenty-sixth transistor T26 through the adapter GC3.

[0278] The connection relationships of the devices in this disclosure are not limited to those described above. Figure 22F The connection relationship of multiple membrane layers 2260 is shown. Figure 22G A schematic plan view of the fifth conductive layer according to an embodiment of the present disclosure is shown. Figure 22H A schematic plan view of the sixth conductive layer according to an embodiment of the present disclosure is shown. Figure 22I A schematic plan view of the semiconductor layer, the second conductive layer, the fifth conductive layer, and the sixth conductive layer according to embodiments of the present disclosure is shown. Figure 22J A schematic plan view of the fourth and sixth conductive layers according to embodiments of the present disclosure is shown. Figure 22K A schematic plan view of a semiconductor layer, a second conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer according to an embodiment of the present disclosure is shown.

[0279] like Figures 22G to 22JAs shown, the fifth conductive layer 2270 includes conductive portions GD1 to GD24. The shapes and positions of conductive portions GD2 to GD24 are similar to those of conductive portions GA2 to GA24 described above, and will not be described again here. The sixth conductive layer 2280 includes transition portions GE1 to GE44. The shapes and positions of transition portions GE1 to GE19, GE21 to GE40, and GE42 to GE44 are similar to those of transition portions GC1 to GC19, GC21 to GC40, and GC42 to GC44 described above. The shape of conductive portion GD1 is different from that of conductive portion GA1, the shape of transition portion GE20 is different from that of transition portion GC20, and the shape of transition portion GE41 is different from that of transition portion GC41.

[0280] In the multiple film layers 2290, conductive part GD1 and adapter GC20 are connected, and conductive part GD3 and adapter GE41 can be connected, thereby exchanging the connection relationship between the first transistor T1 and the third transistor T3, making the connection relationship between the first transistor T1 and the third transistor T3 in the multiple film layers 2290 different from the connection relationship between the first transistor T1 and the third transistor T3 in the multiple film layers 2280. In other embodiments of this disclosure, the connection relationship between the first transistor T2 and the third transistor T3 can also be exchanged, which will not be described in detail here. Other connection relationships between the first transistor T2, the first transistor T2 and the third transistor T3 can be referred to the shift registers 600, 700, 1400, 1600, 1700, 1800 and 1900 described above, which will not be described in detail here.

[0281] Figure 23 A schematic diagram of the structure of a display device according to an embodiment of the present disclosure is shown.

[0282] like Figure 23 As shown, the display device 2300 may include a driving circuit 2310.

[0283] In this embodiment, the driving circuit 2310 can be any one of the driving circuits 2000 and 2100 described above, and will not be repeated here.

[0284] Figure 24 A flowchart illustrating a driving method according to an embodiment of the present disclosure is shown schematically.

[0285] like Figure 24 As shown, the driving method may include operations S2410 to S2420.

[0286] During the operation of S2410, in the gating phase, the control gating signal is at the first level.

[0287] When operating S2420, during the non-gating phase, the control gating signal is at the second level.

[0288] In this embodiment of the disclosure, operations S2410 to S2420 are similar to the operations performed by the shift register 600 described above, and will not be repeated here.

[0289] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0290] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0291] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A shift register, comprising: The shift circuit is configured to control the potentials of the first node and the second node under the control of a first clock signal from a first clock terminal, a second clock signal from a second clock terminal, a first power supply voltage from a first power supply, a second power supply voltage from a second power supply, and a first input signal from a first input terminal, and to provide the first power supply voltage or the second power supply voltage to the first output terminal as a first output signal. The gating circuit is configured to provide a gating signal from the gating terminal to the third node under the control of the first input signal, the second input signal from the second input terminal, and the first output signal; The control circuit is configured to provide the potential of the first node to the fourth node and the potential of the second node to the fifth node under the control of the potential of the third node. as well as The output circuit is configured to provide either the first power supply voltage or the second power supply voltage to the second output terminal as a second output signal, under the control of the potential of the fourth node and the potential of the fifth node.

2. The shift register according to claim 1, wherein, The gating circuit includes a first transistor, a second transistor, and a third transistor; The first transistor, the second transistor, and the third transistor are connected in series between the third node and the gate terminal. The gate of the first transistor is connected to the first output terminal, the gate of the second transistor is connected to the first input terminal, and the gate of the third transistor is connected to the second input terminal.

3. The shift register according to claim 2, wherein, The first terminal of the first transistor is connected to the third node, and the second terminal of the first transistor is connected to the sixth node; the first terminal of the second transistor is connected to the sixth node, and the second terminal of the second transistor is connected to the seventh node; the first terminal of the third transistor is connected to the seventh node, and the second terminal of the third transistor is connected to the gate terminal.

4. The shift register according to claim 2, wherein, The first terminal of the first transistor is connected to the third node, and the second terminal of the first transistor is connected to the sixth node; the first terminal of the third transistor is connected to the sixth node, and the second terminal of the third transistor is connected to the seventh node; the first terminal of the second transistor is connected to the seventh node, and the second terminal of the second transistor is connected to the gate terminal.

5. The shift register according to claim 2, wherein, The first terminal of the second transistor is connected to the third node, and the second terminal of the second transistor is connected to the sixth node; the first terminal of the first transistor is connected to the sixth node, and the second terminal of the first transistor is connected to the seventh node; the first terminal of the third transistor is connected to the seventh node, and the second terminal of the third transistor is connected to the gate terminal.

6. The shift register according to claim 2, wherein, The first terminal of the second transistor is connected to the third node, and the second terminal of the second transistor is connected to the sixth node; the first terminal of the third transistor is connected to the sixth node, and the second terminal of the third transistor is connected to the seventh node; the first terminal of the first transistor is connected to the seventh node, and the second terminal of the first transistor is connected to the gate terminal.

7. The shift register according to claim 2, wherein, The first terminal of the third transistor is connected to the third node, and the second terminal of the third transistor is connected to the sixth node; the first terminal of the first transistor is connected to the sixth node, and the second terminal of the first transistor is connected to the seventh node; the first terminal of the second transistor is connected to the seventh node, and the second terminal of the second transistor is connected to the gate terminal.

8. The shift register according to claim 2, wherein, The first terminal of the third transistor is connected to the third node, and the second terminal of the third transistor is connected to the sixth node; the first terminal of the second transistor is connected to the sixth node, and the second terminal of the second transistor is connected to the seventh node; the first terminal of the first transistor is connected to the seventh node, and the second terminal of the first transistor is connected to the gate terminal.

9. The shift register according to claim 1, wherein, The gating circuit is also electrically connected to the first power supply and the third input terminal; The gating circuit is further configured to control the potential of the third node using the first power supply voltage under the control of a third input signal from the third input terminal.

10. The shift register according to claim 9, wherein, The gating circuit also includes a fourth transistor; The gate of the fourth transistor is connected to the third input terminal, the first terminal of the fourth transistor is connected to the third node, and the second terminal of the fourth transistor is connected to the first power supply.

11. The shift register according to claim 1, wherein, The shift circuit is configured as follows: Under the control of the first clock signal, the first power supply voltage, and the first input signal, at least one of the second clock signal and the second power supply voltage is provided to the first node; Under the control of the first clock signal, the first input signal is provided to the second node; as well as Under the control of the potential of the first node, the potential of the second node, and the first power supply voltage, the first power supply voltage or the second power supply voltage is provided to the first output terminal as the first output signal.

12. A driving circuit comprising M cascaded shift registers as described in any one of claims 1-11, where M is an integer greater than 1, wherein... The first input terminal of the m-th stage shift register is electrically connected to the first output terminal of the (m-1)-th stage shift register, and the second input terminal of the m-th stage shift register is electrically connected to the (m-2)-th stage shift register, where 2 < m ≤ M, m is an integer, and M is an integer greater than 2.

13. The driving circuit according to claim 12, wherein, The third input terminal of the m-th stage shift register is electrically connected to the (m-1)-th stage shift register.

14. A display device, comprising: The driving circuit as described in claim 12 or 13.

15. A driving method applied to a shift register as described in any one of claims 1 to 11, the method comprising: During the gating phase, the gating signal is controlled to be at the first level; as well as During the non-gating phase, the gating signal is controlled to be at the second level.

Images