Electronic device
By employing a multi-drive mode control method, and utilizing a combination of timing controllers and transistors to manage the drive power of the display device, the risk of electrical damage during drive mode switching is eliminated, thereby improving the stability and lifespan of the display device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SAMSUNG DISPLAY CO LTD
- Filing Date
- 2025-12-31
- Publication Date
- 2026-07-14
Smart Images
Figure CN122392424A_ABST
Abstract
Description
Cross-references to related applications
[0001] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2025-0000579, filed on January 3, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field
[0002] Various embodiments of this disclosure relate to electronic devices. Background Technology
[0003] With the development of information technology, display devices, as the connection medium between users and information, have become increasingly important. Therefore, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) has been steadily increasing.
[0004] The display device includes pixels. Pixels can display a predetermined image by emitting light of a predetermined brightness in response to a drive current flowing from a first power line supplied by a first drive power source to a second power line supplied by a second drive power source via a light-emitting device.
[0005] The foregoing description is intended only to facilitate an understanding of the background art of the technical spirit of this disclosure, and therefore should not be construed as corresponding to prior art known to those skilled in the art. Summary of the Invention
[0006] An electronic device according to an embodiment of the present disclosure may have multiple drive modes, and the purpose is to prevent or mitigate the risk of electrical damage to the electronic device (or the circuitry inside the electronic device) by controlling the value of a second drive power according to the drive mode.
[0007] An electronic device according to an embodiment of the present disclosure includes: a processor that provides input image data to a display device; and the display device that displays an image based on the input image data. The display device includes: a display panel including pixels connected to a first power line, a second power line, a scan line, and a data line; a power generator that supplies a first driving power to the first power line and a second driving power to the second power line; and a timing controller that generates a first enable signal, a second enable signal, a third enable signal, and a fourth enable signal for controlling the second driving power according to a driving mode. The second driving power includes a first (2_1) driving power with a positive value and a second (2_2) driving power with a negative value, and the power generator includes: a second switching unit for outputting the second (2_2) driving power to the second power line in a first mode; and a first switching unit for outputting the second (2_1) driving power to the second power line in a second mode different from the first mode.
[0008] The power generator may further include: a first output section for outputting the (2_1)th drive power based on the third enable signal; and a second output section for outputting the (2_2)th drive power based on the first enable signal.
[0009] The first switching unit may include: a first switch for receiving the (2_1) drive power from the first output portion; and a first switch controller for turning off the first switch in the first mode and turning on the first switch in the second mode in response to the fourth enable signal.
[0010] The second switching unit may include: a second switch for receiving the (2_2) drive power from the second output section; and a second switch controller for turning on the second switch in the first mode and turning off the second switch in the second mode in response to the second enable signal.
[0011] The first switch controller may include: a first (1_1) switch transistor having a first electrode connected to ground, a second electrode connected to a second switch node, and a gate electrode connected to a first switch node; a second capacitor having a first electrode connected to the ground and a second electrode connected to the first switch node; and a second resistor having one end connected to the first switch node and the other end to which the fourth enable signal is supplied.
[0012] The first switch may include: a (1_2) switch transistor having a first electrode connected to a third switch node, a second electrode connected to a fourth switch node, and a gate electrode connected to the second switch node; a third capacitor having a first electrode connected to the second switch node and a second electrode connected to the third switch node; and a third resistor having one end connected to the second switch node and the other end connected to the third switch node.
[0013] The (1_1)th switching transistor can be an N-type transistor and the (1_2)th switching transistor can be a P-type transistor.
[0014] The first switch may further include a fourth capacitor having a first electrode connected to the second switch node and a second electrode connected to the third switch node.
[0015] The second switch controller may include: a (2_1) switch transistor having a first electrode supplied with the first drive power, a second electrode connected to a sixth switch node, and a gate electrode connected to a fifth switch node; a fifth capacitor having a first electrode supplied with the first drive power and a second electrode connected to the fifth switch node; and a sixth capacitor having a first electrode connected to ground and a second electrode connected to the fifth switch node.
[0016] The second switch may include: a (2_2) switch transistor having a first electrode connected to the fourth switch node, a second electrode connected to the seventh switch node, and a gate electrode connected to the sixth switch node; a seventh capacitor having a first electrode connected to the seventh switch node and a second electrode connected to the sixth switch node; and a fourth resistor having one end connected to the seventh switch node and the other end connected to the sixth switch node.
[0017] The (2_1)th switching transistor can be a P-type transistor and the (2_2)th switching transistor is an N-type transistor.
[0018] The second switch may further include: an eighth capacitor having a first electrode connected to the seventh switch node and a second electrode connected to the sixth switch node; and a fifth resistor having one end connected to the seventh switch node and the other end connected to the sixth switch node.
[0019] When switching from the first mode to the second mode, the second enable signal can change from low to high after a first time interval following the transition of the first enable signal from high to low.
[0020] When switching from the first mode to the second mode, after a second time interval following the transition of the second enable signal to the high level, the third enable signal may transition from a low level to a high level, and after a third time interval following the transition of the third enable signal to the high level, the fourth enable signal may transition from a low level to a high level.
[0021] During the second time interval, the value of the second drive power can change from a low level to an intermediate level.
[0022] After the third time interval, the value of the second driving power can change from the intermediate level to a high level.
[0023] In the second mode, the (1_1) switch transistor and the (1_2) switch transistor can be turned on, and the (2_1) switch transistor and the (2_2) switch transistor can be turned off.
[0024] When switching from the second mode to the first mode, the fourth enable signal can change from high to low after a fourth time interval following the transition of the third enable signal from high to low.
[0025] When switching from the second mode to the first mode, the second enable signal can change from high to low after a fifth time interval following the fourth enable signal changing to low, and the first enable signal can change from low to high after a sixth time interval following the second enable signal changing to low.
[0026] In the first mode, the (1_1) switch transistor and the (1_2) switch transistor can be turned off, and the (2_1) switch transistor and the (2_2) switch transistor can be turned on. Attached Figure Description
[0027] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.
[0028] Figure 2 It is shown Figure 1 A diagram illustrating an embodiment of the pixels shown.
[0029] Figure 3 This is a diagram illustrating a timing controller and a power generator according to an embodiment of the present disclosure.
[0030] Figure 4 It is shown Figure 3 A block diagram of an embodiment of a DC-DC converter.
[0031] Figure 5 It shows when Figure 4 A block diagram of an embodiment of a DC-DC converter when it is driven in the first mode.
[0032] Figure 6 It shows when Figure 4 A block diagram of an embodiment of a DC-DC converter being driven in the second mode.
[0033] Figure 7 This is a diagram showing the circuit configuration of the first switching unit and the second switching unit.
[0034] Figure 8It is a diagram showing the waveforms of the first enable signal to the fourth enable signal and the second drive power.
[0035] Figure 9 This is a schematic diagram showing whether the (1_1) switch transistor, the (1_2) switch transistor, the (2_1) switch transistor, and the (2_2) switch transistor are driven according to the driving mode.
[0036] Figure 10 This is a diagram illustrating the operation of the first and second switching units when switching from the first mode to the second mode.
[0037] Figure 11 This is a diagram illustrating the operation of the first and second switching units when switching from the second mode to the first mode.
[0038] Figure 12 This is a diagram illustrating the circuit configuration of a first switching unit and a second switching unit according to an embodiment of the present disclosure.
[0039] Figure 13 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.
[0040] Figure 14 It is shown Figure 13 The diagram shows an example of an electronic device implemented as a smartphone.
[0041] Figure 15 It is shown Figure 13 The diagram shows an example of an electronic device implemented as a tablet personal computer (PC). Detailed Implementation
[0042] In the following, embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the parts necessary for understanding the operation according to the present disclosure may be described, and descriptions of other parts may be omitted so as not to obscure the subject matter of the disclosure. Furthermore, the present disclosure may be embodied in other forms and is not limited to the embodiments described herein. However, embodiments of the present disclosure have been described in detail to enable those skilled in the art to readily implement the technical spirit of the present disclosure.
[0043] Throughout this specification, when a component is “connected” to another component, these components may be “directly connected,” or they may be “indirectly connected” where another element is located between them. The terminology used herein is for describing particular embodiments and is not intended to limit this disclosure. Throughout this specification, unless otherwise stated, where a section “includes” a component, that section may also include another component without excluding that component. The terminology used herein is for describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “a,” “the,” and “at least one” do not indicate a limitation on quantity and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” should not be construed as limiting “a” or “one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. "At least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ). Here, "and / or" includes all combinations of one or more corresponding configurations.
[0044] Here, terms such as “first,” “second,” “the (1_1),” “the (1_2),” “the (2_1),” and “the (2_2)” may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Therefore, without departing from the scope disclosed herein, a first component may be referred to as a second component.
[0045] Spatial relative terms such as “below” and “above” can be used for descriptive purposes to describe the relationship between one element or feature and another element (or feature) or feature (or feature) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are also intended to include other orientations in use, operation, and / or manufacture. For example, when the device shown in the drawings is inverted, an element depicted as positioned “below” other elements or features may be positioned in an orientation “above” other elements or features. Thus, in embodiments, the term “below” can include both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore the spatial relative terms used herein can be interpreted accordingly.
[0046] Furthermore, embodiments of this disclosure may be described herein with reference to the schematic diagrams (and intermediate structures) thereof, such that variations in the illustrated shape may be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes shown, and should be interpreted as including, for example, variations in shape due to manufacturing processes. As described herein, the shapes shown in the figures may not represent the actual shape of any region of the device, and embodiments are not limited thereto.
[0047] Figure 1 This is a diagram illustrating a display device 100 according to an embodiment of the present disclosure.
[0048] Reference Figure 1 The display device 100 according to embodiments of the present disclosure may include a display panel 110, a scan driver 120, a data driver 130, a timing controller 140, a power generator 150, and a current sensor 160. The scan driver 120, data driver 130, timing controller 140, power generator 150, and current sensor 160 may constitute a driving device for driving the display panel 110.
[0049] The display panel 110 can display images. The display panel 110 may include pixels PX connected to the first scan lines SL1, ..., SL1, ..., SLn, the second scan lines SSL1, ..., SSLi, ..., SSLn, the data lines DL1, ..., DLj, ..., DLm, and the readout lines RL1, ..., RLj, ..., RLm (where n and m are each natural numbers greater than or equal to 3, i is a natural number less than or equal to n and greater than or equal to 1, and j is a natural number less than or equal to m and greater than or equal to 1).
[0050] Pixel PX can be connected to one of the first scan lines SL1 to SLn and one of the data lines DL1 to DLm. Additionally, pixel PX can be connected to one of the second scan lines SSL1 to SSLn and one of the readout lines RL1 to RLm.
[0051] For example, a pixel PX located in row i and column j can be connected to the i-th first scan line SLi (hereinafter, first scan line SLi), the i-th second scan line SSLi (hereinafter, second scan line SSLi), the j-th data line DLj (hereinafter, data line DLj), and the j-th readout line RLj (hereinafter, readout line RLj). Furthermore, pixel PX can be connected to the first power line PL1 to which the first drive power VDD is applied, and the second power line PL2 to which the second drive power VSS is applied.
[0052] The driving current flowing through pixel PX can follow a path from the line supplying the first driving power VDD to the line supplying the second driving power VSS. During the emission period of pixel PX, the first driving power VDD can be set to a voltage higher than the voltage of the second driving power VSS.
[0053] Pixel PX can be initialized by initialization power VINT provided via readout line RLj in response to a second scan signal provided via second scan line SSLi, and can be supplied with a data signal (or data voltage) via data line DLj in response to a first scan signal provided via first scan line SLi. In response to the data signal, pixel PX can control the first power line PL1 supplied from the first drive power VDD (see...). Figure 2 ) via light-emitting device LD (see Figure 2 The current flows to the second power line PL2 supplied by the second drive power VSS (see...). Figure 2 The amount of current is used to generate light with a brightness corresponding to the data signal. The initial power VINT can be set to a voltage lower than the operating point (or threshold voltage) of the light-emitting device LD.
[0054] The scan driver 120 can generate a first scan signal and a second scan signal based on the scan control signal SCS. The first scan signal can be sequentially supplied to the first scan lines SL1 to SLn, and the second scan signal can be sequentially supplied to the second scan lines SSL1 to SSLn.
[0055] The scan control signal SCS may include a start signal and a clock signal, and may be provided from the timing controller 140 to the scan driver 120. The scan driver 120 may be implemented as a shift register that sequentially generates and outputs a first scan signal in pulse form by sequentially shifting the start signal in response to the clock signal. Furthermore, the scan driver 120 may generate and output a second scan signal in a manner similar to that used to generate the first scan signal. The scan driver 120 may include a first scan driver for generating the first scan signal and a second scan driver for generating the second scan signal.
[0056] The scan driver 120 may be formed together with the pixel PX in the display panel 110. However, embodiments of this disclosure are not limited thereto, and for example, the scan driver 120 may be mounted on a circuit film and connected to the timing controller 140 via at least one circuit film and a printed circuit board.
[0057] The data driver 130 can generate a data signal (or data voltage) based on the output data Dout and data control signal DCS provided from the timing controller 140, and provide the data signal to the display panel 110 (or pixel PX) via data lines DL1 to DLm. The data control signal DCS may include a data enable signal and / or a data clock signal, etc. The data driver 130 can provide initialization power VINT to the display panel 110 (or pixel PX) via readout lines RL1 to RLm.
[0058] In an embodiment, the data driver 130 may receive sensing signals via readout lines RL1 to RLm during a separate sensing period (e.g., during a sensing period allocated for sensing characteristic information of the pixel PX, such as the threshold voltage and / or mobility of the driving transistors included in the pixel PX). The sensing signals may be used in the data driver 130 and / or timing controller 140 to compensate for the characteristics (or characteristic deviations) of the pixel PX.
[0059] In this embodiment, the readout lines RL1 to RLm can be connected to a separate sensing unit. The sensing unit can supply the initialization power VINT voltage to the display panel 110 or receive sensing signals via the readout lines RL1 to RLm.
[0060] The power generator 150 can supply a first drive power VDD and a second drive power VSS to the display panel 110. The power generator 150 can also supply initialization power VINT to the data driver 130.
[0061] The power generator 150 can generate a first drive power VDD with a predetermined voltage in response to a voltage code Vcode supplied from the timing controller 140. The voltage of the first drive power VDD can be determined corresponding to the voltage code Vcode.
[0062] The power generator 150 can provide the drive voltage required to drive at least one of the scan driver 120, the data driver 130, the timing controller 140, and the current sensor 160. The power generator 150 can be implemented as a power management integrated circuit (PMIC).
[0063] The first drive power VDD can be supplied to the display panel 110 via the first power line PL1. The second drive power VSS can be supplied to the display panel 110 via the second power line PL2. The initialization power VINT can be supplied to the data driver 130 via the third power line PL3. The first power line PL1 and the second power line PL2 can be connected to the pixel PX.
[0064] The sensing resistor Rs can be connected to a second power line PL2 that is commonly connected to the pixel PX. For example, the sensing resistor Rs can be connected between the second power line PL2 and the display panel 110. The voltage (and current) of the second drive power VSS can be supplied to the display panel 110 via the sensing resistor Rs. However, the embodiment is not limited to this. For example, the sensing resistor Rs can be connected to a first power line PL1 that is commonly connected to the pixel PX. For example, the sensing resistor Rs can be connected between the first power line PL1 and the display panel 110.
[0065] Current sensor 160 can be electrically connected to the opposite ends of sensing resistor Rs. Current sensor 160 can sense the current flowing through sensing resistor Rs to generate a global current value GC. The global current value GC generated (or sensed) by current sensor 160 can be provided to timing controller 140.
[0066] The global current value GC can correspond to the current supplied to pixel PX via the second power line PL2. However, embodiments of this disclosure are not limited to this, and for example, a sensing resistor Rs can be connected to the first power line PL1, which is connected to pixel PX, to sense the current flowing through the first power line PL1. The current sensor 160 can generate the global current value GC from the sensing resistor Rs connected to the first power line PL1.
[0067] The timing controller 140 can receive input data Din and control signal CS from an external device (e.g., a graphics processor or an application processor), and generate scan control signal SCS and data control signal DCS based on the control signal CS.
[0068] In one embodiment, the timing controller 140 may respond to the load of pixel PX (see [link]). Figure 3 The voltage of the second drive power VSS is controlled frame by frame. For example, the timing controller 140 can generate a voltage code Vcode in response to the load of pixel PX, so that the second drive power VSS has a predetermined voltage value.
[0069] Figure 2 It is shown Figure 1 A diagram illustrating an embodiment of pixel PX. Figure 2 In the example, pixel PX located in row i and column j is shown. Figure 2 The pixel PX shown is an embodiment, and the structure of the pixel PX in this disclosure is not limited thereto. As an example, the pixel PX in the embodiments of this disclosure may be selected from a variety of currently known circuits.
[0070] Reference Figure 2Pixel PX can be connected to the first scan line SLi, the second scan line SSLi, the data line DLj, and the readout line RLj.
[0071] Pixel PX may include a light-emitting device LD, a first transistor T1 (or a driving transistor), a second transistor T2, a third transistor T3, and a storage capacitor Cst. Each of the first transistor T1, the second transistor T2, and the third transistor T3 may be a thin-film transistor comprising oxide semiconductor, but is not limited thereto, and for example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may comprise polycrystalline silicon semiconductor, or may be implemented using N-type semiconductor or P-type semiconductor.
[0072] The first electrode (or anode electrode) of the light-emitting device LD is connected to the first power line PL1 via the second node N2 and the first transistor T1, and the second electrode (or cathode electrode) can be connected to the second power line PL2. The light-emitting device LD can emit light with a brightness corresponding to the driving current supplied from the first transistor T1.
[0073] The light-emitting device (LD) can be selected as an organic light-emitting diode (OLED). The LD can also be selected as an inorganic light-emitting diode, such as a micro LED or a quantum dot LED. Furthermore, the LD can comprise a combination of organic and inorganic materials. Although... Figure 2 The illustration shows a pixel PX comprising a single light-emitting device LD, but in other embodiments, a pixel PX may comprise multiple light-emitting devices that can be connected in series, in parallel, or in a series-parallel connection.
[0074] The first electrode (e.g., drain electrode) of the first transistor T1 can be connected to the first power line PL1 to which the first driving power VDD is applied, and the second electrode (e.g., source electrode) can be connected to the second node N2. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the amount of current flowing to the light-emitting device LD in response to the voltage of the first node N1 (or the gate-source voltage across the gate electrode and the second electrode of the first transistor T1).
[0075] The first electrode of the second transistor T2 can be connected to the data line DLj, and the second electrode can be connected to the first node N1. The gate electrode of the second transistor T2 can be connected to the first scan line SLi. When the first scan signal is supplied to the first scan line SLi, the second transistor T2 can be turned on to transmit the data signal VDATA from the data line DLj to the first node N1.
[0076] A storage capacitor Cst can be formed or connected between the first node N1 and the second node N2. The storage capacitor Cst can store the voltage of the first node N1.
[0077] The third transistor T3 can be connected between the readout line RLj and the second node N2. The gate electrode of the third transistor T3 can be connected to the second scan line SSLi. When the second scan signal is supplied to the second scan line SSLi, the third transistor T3 can be turned on to transfer the voltage of the initialization power VINT from the readout line RLj to the second node N2.
[0078] When the second transistor T2 and the third transistor T3 are simultaneously turned on in response to the first scan signal and the second scan signal, the voltage difference between the data signal VDATA and the initialization power VINT is stored in the storage capacitor Cst. The first transistor T1 can control the amount of current flowing through the light-emitting device LD in response to the voltage difference stored in the storage capacitor Cst.
[0079] Optionally, when the third transistor T3 is turned on during the sensing period to connect the second node N2 and the readout line RLj, the sensing signal can be provided from the pixel PX to the readout line RLj.
[0080] Figure 3 This is a diagram illustrating a timing controller 140 and a power generator 150 according to an embodiment of the present disclosure.
[0081] Reference Figure 3 According to embodiments of the present disclosure, the power generator 150 may include a digital-to-analog converter (DAC) 152 and a DC-DC converter 154.
[0082] DAC 152 can generate a reference voltage Vref (or feedback voltage) corresponding to the voltage code Vcode and supply the reference voltage Vref to DC-DC converter 154. For example, DAC 152 can supply the reference voltage Vref to DC-DC converter 154 in response to the voltage code Vcode.
[0083] DC-DC converter 154 can generate a second drive power VSS with a predetermined voltage based on a reference voltage Vref, and supply the second drive power VSS to the second power line PL2. The voltage of the second drive power VSS generated by DC-DC converter 154 can be determined based on the voltage of the reference power (i.e., the reference voltage Vref). However, the above description is an example, and the first drive power VDD can also be described in the same manner. In the following description, for ease of description, the second drive power VSS will be described primarily.
[0084] The timing controller 140 according to embodiments of this disclosure may include a load analyzer 141, a current comparator 142, and a main controller 143. The timing controller 140 may also include various other components, however... Figure 4Only the components required for the description in this disclosure are shown.
[0085] Load analyzer 141 can calculate (or analyze) the load of input data Din. For example, load analyzer 141 can calculate the load of input data Din corresponding to a frame. For example, load analyzer 141 can calculate the load by averaging the gray levels of input data Din for a frame. Various currently known methods can be used as methods for calculating the load in load analyzer 141.
[0086] Load can indicate the pixel PX emitting light in the display panel 110 (see...) Figure 2 The ratio of the display panel 110 to all pixels PX. In other words, when the display panel 110 emits light in pure white (for example, when all pixels PX in the display panel 110 emit light at a brightness corresponding to white), the load can be set to 100%.
[0087] The main controller 143 can determine the voltage of the second drive power VSS in response to the load.
[0088] The current comparator 142 can receive the global current value GC from the current sensor 160 and can also receive the load Load from the load analyzer 141. The current comparator 142 receiving the load Load can extract the maximum current value that can flow in the display panel 110 in response to the load Load. The maximum current value can be read from a memory provided in the timing controller 140.
[0089] The current comparator 142 can compare the maximum current value with the global current value GC, and in response to the comparison result, supply the differential current value CC between the maximum current value and the global current value GC to the main controller 143.
[0090] The main controller 143 can receive the load Load from the load analyzer 141. The main controller 143 can receive the differential current value CC from the current comparator 142. Therefore, the main controller 143 compares the differential current value CC with the threshold current value corresponding to the same load Load. When the differential current value CC is smaller than the threshold current value, the main controller 143 can be driven in a first mode. Therefore, in the first mode, the main controller 143 can supply a first enable signal EN1 (see [link to relevant documentation]) to the DC-DC converter 154. Figure 7 ) and the second enable signal EN2 (see Figure 7 ).
[0091] Furthermore, when the differential current value CC is greater than the threshold current value, the main controller 143 can be driven in the second mode. Therefore, in the second mode, the main controller 143 can supply the DC-DC converter 154 with a third enable signal EN3 (see [link to relevant documentation]). Figure 7 ) and the fourth enable signal EN4 (see Figure 7 ).
[0092] The main controller 143 can generate a voltage code Vcode and supply the voltage code Vcode to the power generator 150. The power generator 150 can generate a second driving power VSS in response to the voltage code Vcode and supply the second driving power VSS to the display panel 110.
[0093] Figure 4 It is shown Figure 3 A block diagram of an embodiment of the DC-DC converter 154. Figure 5 It shows when Figure 4 A block diagram of an embodiment of the DC-DC converter 154 being driven in the first mode. Figure 6 It shows when Figure 4 A block diagram of an embodiment of the DC-DC converter 154 being driven in the second mode.
[0094] Reference Figures 4 to 6 The DC-DC converter 154 may include a first output section CVT1, a first switching unit SU1, a second output section CVT2, and a second switching unit SU2.
[0095] As described above, the DC-DC converter 154 can be supplied with a reference power voltage and an enable signal EN, and the components of the DC-DC converter 154 can be driven according to the timing of the supplied enable signal EN.
[0096] The first switching unit SU1 may include a first switching controller SC1 and a first switch SW1. The first switching unit SU1 can control whether to output the (2_1) drive power VSS_1. For example, the first output section CVT1 can be configured according to the enable signal EN (e.g., the third enable signal EN3 (see...)). Figure 7 The first switch SW1 is supplied with the (2_1)th drive power VSS_1. The first switch controller SC1 can determine whether to output the (2_1)th drive power VSS_1 through the first switch SW1. For example, the first switch controller SC1 can supply the first switch control signal LCS1 to the first switch SW1. Therefore, based on the first switch control signal LCS1, the first switch SW1 can output the (2_1)th drive power VSS_1 or it can not output the (2_1)th drive power VSS_1. For example, refer to Figures 4 to 6 In the second mode ( Figure 6 In mode 2), when the (1_1)th switching transistor ST1_1 (see...) Figure 7 When ) is turned on, the first switch SW1 can output the (2_1)th drive power VSS_1. On the other hand, in the first mode ( Figure 5 In mode 1), when the (1_1)th switching transistor ST1_1 (see...) Figure 7 When the switch is closed, the first switch SW1 may not output the (2_1) drive power VSS_1.
[0097] The second switching unit SU2 may include a second switching controller SC2 and a second switch SW2. The second switching unit SU2 can control whether to output the (2_2)th drive power VSS_2. For example, the second output section CVT2 can be configured based on the enable signal EN (e.g., the first enable signal EN1 (see...)). Figure 7 The second switch controller SC2 supplies the (2_2)th drive power VSS_2 to the second switch SW2. The second switch controller SC2 can determine whether to output the (2_2)th drive power VSS_2 through the second switch SW2. For example, the second switch controller SC2 can supply the second switch control signal LCS2 to the second switch SW2. Therefore, based on the second switch control signal LCS2, the second switch SW2 can output the (2_2)th drive power VSS_2 or may not output the (2_2)th drive power VSS_2. For example, refer to... Figures 4 to 6 In the second mode, when the (2_1)th switching transistor ST2_1 (see...) Figure 7 When the second switch SW2 is turned off, it may not output the (2_2)th drive power VSS_2. On the other hand, in the first mode, when the (2_1)th switch transistor ST2_1 (see...) Figure 7 When the circuit is turned on, the second switch SW2 can output the (2_2)th driving power VSS_2.
[0098] Figure 7 This is a diagram showing the circuit configuration of the first switching unit SU1 and the second switching unit SU2. Figure 8 This is a diagram showing the waveforms of the first enable signal EN1 to the fourth enable signal EN4 and the second drive power VSS. Figure 9 This is a schematic diagram showing whether the (1_1) switching transistor ST1_1, the (1_2) switching transistor ST1_2, the (2_1) switching transistor ST2_1, and the (2_2) switching transistor ST2_2 are driven according to the driving mode.
[0099] Reference Figure 7The first switching unit SU1 may include a second resistor R2, a second capacitor C2, a third resistor R3, a third capacitor C3, a (1_1) switching transistor ST1_1, and a (1_2) switching transistor ST1_2.
[0100] One electrode of the (1_1) switching transistor ST1_1 can be grounded (e.g., connected to ground). The other electrode of the (1_1) switching transistor ST1_1 can be connected to the gate electrode of the (1_2) switching transistor ST1_2. The gate electrode of the (1_1) switching transistor ST1_1 can be connected to the first node SN1. In this disclosure, the first node SN1 to the seventh node SN7 can also be referred to as the first switching node SN1 to the seventh switching node SN7.
[0101] One electrode of the second capacitor C2 can be connected to the gate electrode of the (1_1) switching transistor ST1_1 and the first node SN1 to which the second resistor R2 is connected. The other electrode of the second capacitor C2 can be grounded. Therefore, an RC delay effect can be generated in the gate electrode of the (1_1) switching transistor ST1_1. In other words, the slew rate of the voltage charged to the gate electrode of the (1_1) switching transistor ST1_1 can be reduced due to the second capacitor C2 and the second resistor R2 included in the first switching unit SU1. Therefore, the electrical surge applied to the (1_1) switching transistor ST1_1 (or the first switching unit SU1) can be relatively weakened.
[0102] According to an embodiment, the capacitance of the second capacitor C2 can be 2200 nF. The resistance of the second resistor R2 can be 100 kiloohms. However, these values are not limited to these.
[0103] In an embodiment, in the first switching unit SU1, the first switch SW1 can receive the (2_1) drive power VSS_1 from the first output section CVT1, and the first switch controller SC1 can turn off the first switch SW1 in a first mode and turn on the first switch SW1 in a second mode in response to the fourth enable signal EN4. In an embodiment, the (1_1) switching transistor ST1_1 can be driven according to the fourth enable signal EN4 transmitted via the second resistor R2. For example, the gate electrode of the (1_1) switching transistor ST1_1 can receive the fourth enable signal EN4 and turn on / off in response to the fourth enable signal EN4. Therefore, the (1_1) switching transistor ST1_1 can control whether to drive the (1_2) switching transistor ST1_2. For example, when the (1_1) switching transistor ST1_1 is turned on, a predetermined signal can be applied to the gate electrode of the (1_2) switching transistor ST1_2. Therefore, the (1_2) switching transistor ST1_2 can output the (2_1) drive power VSS_1 received from the first output section CVT1.
[0104] One electrode of the (1_2) switching transistor ST1_2 can be connected to the third node SN3. The gate electrode of the (1_2) switching transistor ST1_2 can be connected to the second node SN2. The other electrode of the (1_2) switching transistor ST1_2 can be connected to the fourth node SN4. The (1_2) switching transistor ST1_2 can be connected in parallel with the third capacitor C3 and the third resistor R3. For example, one end of the third resistor R3 can be connected to the second node SN2, and the other end of the third resistor R3 can be connected to the third node SN3. Furthermore, one electrode of the third capacitor C3 can be connected to the second node SN2, and the other electrode can be connected to the third node SN3.
[0105] According to the embodiment, the (1_1) switching transistor ST1_1 can be an N-type transistor. Furthermore, the (1_2) switching transistor ST1_2 can be a P-type transistor. However, the description of the switching transistors is illustrative and the switching transistors are not limited thereto.
[0106] The second switching unit SU2 may include a fourth resistor R4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a (2_1) switching transistor ST2_1, and a (2_2) switching transistor ST2_2.
[0107] One electrode of the fifth capacitor C5 can be connected to the line or terminal to which the first drive power VDD is applied, and the other electrode can be connected to the fifth node SN5. One electrode of the sixth capacitor C6 can be connected to the fifth node SN5, and the other electrode can be connected to ground.
[0108] One electrode of the (2_1) switching transistor ST2_1 can be connected to the line or terminal to which the first drive power VDD is applied. The gate electrode of the (2_1) switching transistor ST2_1 can be connected to the fifth node SN5. The other electrode of the (2_1) switching transistor ST2_1 can be connected to the sixth node SN6.
[0109] In an embodiment, in the second switching unit SU2, the second switch SW2 can receive the (2_2)th drive power VSS_2 from the second output section CVT2, and the second switch controller SC2 can turn on the second switch SW2 in a first mode and turn off the second switch SW2 in a second mode in response to the second enable signal EN2. In an embodiment, the (2_1)th switching transistor ST2_1 can be driven according to the second enable signal EN2. For example, the gate electrode of the (2_1)th switching transistor ST2_1 can receive the second enable signal EN2 and turn on / off in response to the second enable signal EN2. Therefore, the (2_1)th switching transistor ST2_1 can control whether to drive the (2_2)th switching transistor ST2_2. For example, when the (2_1)th switching transistor ST2_1 is turned on, a predetermined signal can be applied to the gate electrode of the (2_2)th switching transistor ST2_2. Therefore, the (2_2)th switching transistor ST2_2 can output the (2_2)th drive power VSS_2 received from the second output section CVT2.
[0110] One electrode of the (2_2) switching transistor ST2_2 can be connected to the fourth node SN4. The gate electrode of the (2_2) switching transistor ST2_2 can be connected to the sixth node SN6. The other electrode of the (2_2) switching transistor ST2_2 can be connected to the seventh node SN7. The (2_2) switching transistor ST2_2 can be connected in parallel with the seventh capacitor C7 and the fourth resistor R4. For example, one end of the fourth resistor R4 can be connected to the seventh node SN7, and the other end of the fourth resistor R4 can be connected to the sixth node SN6. In addition, one electrode of the seventh capacitor C7 can be connected to the seventh node SN7, and the other electrode can be connected to the sixth node SN6.
[0111] According to the embodiment, the (2_1) switching transistor ST2_1 can be a P-type transistor. Furthermore, the (2_2) switching transistor ST2_2 can be an N-type transistor. However, the description of the switching transistors is illustrative and the switching transistors are not limited thereto.
[0112] The first output section CVT1 can receive the third enable signal EN3. Therefore, the first output section CVT1 can output the (2_1)th drive power VSS_1 in response to the third enable signal EN3. The output terminal of the first output section CVT1 can be connected to one end of the first resistor R1. The (2_1)th drive power VSS_1 output from the first output section CVT1 can be controlled by the first switching unit SU1. For example, in the first mode ( Figure 8 In mode 1), the first switching unit SU1 may not output the (2_1) drive power VSS_1 to the second power line PL2. Furthermore, in the second mode ( Figure 8 In mode 2), the first switching unit SU1 can output the (2_1) drive power VSS_1 to the second power line PL2.
[0113] The second output section CVT2 can receive the first enable signal EN1. Therefore, the second output section CVT2 can output the (2_2)th drive power VSS_2 in response to the first enable signal EN1. The output terminal of the second output section CVT2 can be connected to one end of the first capacitor C1. The (2_2)th drive power VSS_2 output from the second output section CVT2 can be controlled by the second switching unit SU2. For example, in the first mode, the second switching unit SU2 can output the (2_2)th drive power VSS_2 to the second power line PL2. Furthermore, in the second mode, the second switching unit SU2 can choose not to output the (2_2)th drive power VSS_2 to the second power line PL2.
[0114] According to an embodiment of the present invention, the (2_1) driving power VSS_1 can be a voltage with a positive value. Furthermore, the (2_2) driving power VSS_2 can be a voltage with a negative value. For example, the (2_1) driving power VSS_1 can be 6.7V, and the (2_2) driving power VSS_2 can be -3V. However, the description of the driving power is illustrative and the driving power is not limited thereto.
[0115] Reference Figure 8 Power generator 150 (see Figure 3The power generator 150 can be driven in either a first mode or a second mode. The first mode can have multiple drive modes. According to an embodiment, the power generator 150 can be turned on (energized) and operate in the first mode, and the power generator 150 can be turned off (de-energized), causing the first mode to terminate. However, this is merely an illustrative example and is not limited thereto. In one embodiment, the power generator 150 may include a low-dropout (“LDO”) regulator. The LDO regulator can be used to reduce (or remove) noise included in the input power (e.g., the second drive power VSS) to supply power at a stable voltage level. That is, the first mode may include an LDO mode for removing noise from the second drive power VSS.
[0116] In LDO mode, the second drive power VSS can be low. The first enable signal EN1 can be high and the second enable signal EN2 can be low. Furthermore, the third enable signal EN3 and the fourth enable signal EN4 can be low.
[0117] After LDO mode, the power generator 150 can be driven normally (i.e., normal operation). At this time, the first enable signal EN1 can be high and the second enable signal EN2 can be low. Furthermore, the third enable signal EN3 and the fourth enable signal EN4 can be low.
[0118] Subsequently, the power generator 150 can be driven in the second mode. According to embodiments of this disclosure, before the power generator 150 is driven in the second mode, the first enable signal EN1 can be pre-transitioned from high to low at predetermined time intervals. For example, before the power generator 150 is driven in the second mode, the first enable signal EN1 can first be transitioned from high to low by an amount equal to the sum of the first time interval H1, the second time interval H2, and the third time interval H3. Therefore, the second output section CVT2 can be turned off. Furthermore, after a first time interval H1 from when the first enable signal EN1 transitions from high to low (or after the first enable signal EN1 transitions from high to low), the second enable signal EN2 can transition from low to high. Therefore, the second switching unit SU2 can be turned off.
[0119] Furthermore, before the power generator 150 is driven in the second mode, the third enable signal EN3 can transition from a low level to a high level. That is, after a second time interval H2 from when the second enable signal EN2 transitions from a low level to a high level (or after the second enable signal EN2 transitions from a low level to a high level), the third enable signal EN3 can transition from a low level to a high level. At this time, the first output section CVT1 can be driven, and the value of the second drive power VSS can transition from a low level to an intermediate level.
[0120] Furthermore, after a third time interval H3 from when the third enable signal EN3 transitions from low to high (or after the third enable signal EN3 transitions from low to high), the fourth enable signal EN4 can transition from low to high. Therefore, the first switching unit SU1 can be turned on, and the value of the second drive power VSS can transition from an intermediate level to a high level. That is, the value of the second drive power VSS is positive, and the power generator 150 can be driven in the second mode.
[0121] According to embodiments of this disclosure, the first mode may include an off_SEN period. The off_SEN period may be a period in which one of the first switching unit SU1 and the second switching unit SU2 is on and the other is off. Additionally, the off_SEN period may include a Vth sensing period and a u sensing period.
[0122] Reference Figures 7 to 9 When the power generator 150 is driven in a first mode (e.g., LDO mode period, normal operation period, and u-sensing period), the (1_1) switching transistor ST1_1 and the (1_2) switching transistor ST1_2 can be in the off state. On the other hand, in the first mode, the (2_1) switching transistor ST2_1 and the (2_2) switching transistor ST2_2 can be in the on state. The u-sensing period can be used to sense the flow through the first transistor T1 (see...). Figure 2 The slope of the current during the time period. Therefore, in the first mode, the value of the second drive power VSS can be negative.
[0123] According to the embodiment, the second mode ( Figure 8Mode 2) may include a Vth sensing period. The Vth sensing period can be a time period used to sense the threshold voltage of the first transistor T1. That is, when the threshold voltage of the first transistor T1 is sensed, the (1_1) switching transistor ST1_1 and the (1_2) switching transistor ST1_2 can be in the on state. On the other hand, the (2_1) switching transistor ST2_1 and the (2_2) switching transistor ST2_2 can be in the off state. Therefore, the value of the second drive power VSS can be changed from negative to positive.
[0124] The power generator 150 can switch from the second mode to the first mode. At this time, the third enable signal EN3 can transition from a high level to a low level. Therefore, the first output section CVT1 can be turned off. After a fourth time interval H4 from when the third enable signal EN3 transitions from a high level to a low level (or after the third enable signal EN3 transitions from a high level to a low level), the fourth enable signal EN4 can transition from a high level to a low level. Therefore, the first switching unit SU1 can be turned off.
[0125] Subsequently, after a fifth time interval H5 following the transition from the fourth enable signal EN4 from high to low (after the fourth enable signal EN4 transitions from high to low), the second enable signal EN2 can transition from high to low. Therefore, the second switching unit SU2 can be turned on. Subsequently, after a sixth time interval H6 following the transition from the second enable signal EN2 from high to low (after the second enable signal EN2 transitions from high to low), the first enable signal EN1 can transition from low to high. At this time, the second drive power VSS can transition from high to low. That is, the second drive power VSS has a negative value, and the power generator 150 can be driven in the first mode.
[0126] The first time interval H1 to the sixth time interval H6 can be the same time interval. However, the embodiments are not limited to this. For example, the first time interval H1 and the second time interval H2 can be different time intervals.
[0127] According to an embodiment, the power generator 150 may not be driven. In this case, the first enable signal EN1 can transition from a low level to a high level, and the second enable signal EN2 can transition from a high level to a low level. Furthermore, the third enable signal EN3 and the fourth enable signal EN4 can remain at a low level.
[0128] Figure 10 This is a diagram illustrating the operation of the first switching unit SU1 and the second switching unit SU2 when switching from the first mode to the second mode. Figure 11This is a diagram illustrating the operation of the first switching unit SU1 and the second switching unit SU2 when switching from the second mode to the first mode. Figure 12 This is a diagram illustrating the circuit configuration of the first switching unit SU1 and the second switching unit SU2 according to an embodiment of the present disclosure.
[0129] Reference Figures 10 to 12 The second switching unit SU2 according to an embodiment of the present disclosure may further include an eighth capacitor C8. One electrode of the eighth capacitor C8 may be connected to a seventh node SN7. The other electrode of the eighth capacitor C8 may be connected to a sixth node SN6. The first switching unit SU1 according to an embodiment of the present disclosure may further include a fourth capacitor C4. One electrode of the fourth capacitor C4 may be connected to a second node SN2. The other electrode of the fourth capacitor C4 may be connected to a third node SN3.
[0130] When switching from the second mode to the first mode, the (1_2) switching transistor ST1_2 can be turned off. That is, the first output section CVT1 can turn off the (1_2) switching transistor ST1_2 in response to the third enable signal EN3. On the other hand, when switching from the second mode to the first mode, the (2_2) switching transistor ST2_2 can be turned on. For example, in order to turn on the (2_2) switching transistor ST2_2, the second output section CVT2 can be driven and the second enable signal EN2 can be applied to the gate electrode of the (2_1) switching transistor ST2_1.
[0131] According to the comparison example, the first enable signal EN1 transitions from low to high, and then the second enable signal EN2 transitions from high to low, and the (2_1) switching transistor ST2_1 can be turned off. Therefore, the voltage VGS at the gate electrode of the (2_2) switching transistor ST2_2 may increase rapidly, and an electrical shock may be applied to the (2_2) switching transistor ST2_2.
[0132] On the other hand, according to an embodiment of the present invention, the second enable signal EN2 first transitions from a high level to a low level, allowing the voltage of the sixth node SN6 to transition from a low level to a high level. At this time, the first enable signal EN1 can remain low, and the voltages of the fourth node SN4 and the seventh node SN7 can remain high. Therefore, compared to the comparative example, the voltage VGS of the gate electrode of the (2_2) switching transistor ST2_2 (or the voltage difference between the sixth node SN6 and the seventh node SN7) can be relatively small. Subsequently, the first enable signal EN1 can transition from a low level to a high level, and the voltages of the fourth node SN4 and the seventh node SN7 can transition from a high level to a low level. Therefore, the voltage VGS of the gate electrode of the (2_2) switching transistor ST2_2 can rise relatively slowly, and the risk of electrical shocks being applied to the (2_2) switching transistor ST2_2 or the second switching unit SU2 can be prevented or mitigated.
[0133] Reference Figures 10 to 12 According to an embodiment of this disclosure, the second switching unit SU2 may further include a fifth resistor R5. One end of the fifth resistor R5 may be connected to a sixth node SN6. The other end of the fifth resistor R5 may be connected to a seventh node SN7. According to an embodiment, the resistance value of the fifth resistor R5 may be 10 kΩ, but is not limited to 10 kΩ.
[0134] The second switching unit SU2 may also include a parasitic capacitor CP1. For example, the parasitic capacitor CP1 may be connected to one electrode of the (2_2) switching transistor ST2_2 and the sixth node SN6.
[0135] According to the comparative example, without the fifth resistor R5, the predetermined voltage may flow into the gate electrode of the (2_2) switching transistor ST2_2 through the parasitic capacitor CP1. On the other hand, when the (2_2) switching transistor ST2_2 is turned off, the fifth resistor R5 can keep the voltage VGS applied to the gate electrode of the (2_2) switching transistor ST2_2 at 0V, and can improve the reliability of the drive of the second switching unit SU2.
[0136] When switching from the first mode to the second mode, the (1_2) switching transistor ST1_2 can be turned on. That is, the first output section CVT1 can turn on the (1_2) switching transistor ST1_2 in response to the third enable signal EN3. On the other hand, when switching from the first mode to the second mode, the (2_2) switching transistor ST2_2 can be turned off. For example, the second output section CVT2 can turn off the (2_2) switching transistor ST2_2 in response to the first enable signal EN1.
[0137] According to the comparative example, the first enable signal EN1 can be supplied to the second output section CVT2, after which the second enable signal EN2 can be applied to the gate electrode of the (2_1) switching transistor ST2_1. Therefore, the voltage VGS of the gate electrode of the (2_2) switching transistor ST2_2 may increase rapidly, and may apply an electrical shock to the (2_2) switching transistor ST2_2.
[0138] On the other hand, according to an embodiment of this disclosure, a second enable signal EN2 can be applied to the gate electrode of the (2_1) switching transistor ST2_1. Therefore, the voltage of the sixth node SN6 can transition from a low level to a high level. At this time, the first enable signal EN1 may not be supplied to the second output section CVT2. Therefore, the voltages of the fourth node SN4 and the seventh node SN7 can remain at a high level. Therefore, compared to the comparative example, the voltage VGS (or the voltage difference between the sixth node SN6 and the seventh node SN7) of the gate electrode of the (2_2) switching transistor ST2_2 can be relatively small. Then, the first enable signal EN1 is supplied to the second output section CVT2, and the voltages of the fourth node SN4 and the seventh node SN7 can transition from a high level to a low level. Therefore, the voltage VGS of the gate electrode of the (2_2) switching transistor ST2_2 can increase relatively gradually, and the risk of electrical shocks being applied to the (2_2) switching transistor ST2_2 can be prevented or mitigated.
[0139] Figure 13 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the present disclosure. Figure 14 It is shown Figure 13 The diagram illustrates an example of an electronic device 1000 implemented as a smartphone. Figure 15 It is shown Figure 13 The diagram shows an example of an electronic device 1000 implemented as a tablet PC.
[0140] Reference Figures 13 to 15 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 The display device 100. Furthermore, the electronic device 1000 may also include various ports capable of communicating with video cards, sound cards, memory cards, or Universal Serial Bus (USB) devices, or with other systems. In embodiments, such as Figure 14 As shown, the electronic device 1000 can be implemented as a smartphone. In an embodiment, as... Figure 15As shown, the electronic device 1000 can be implemented as a tablet PC. However, these embodiments are provided as examples and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a mobile phone, video phone, smart tablet, smartwatch, vehicle navigation system, computer monitor, laptop computer, or head-mounted display, etc.
[0141] Processor 1010 can perform specific calculations or tasks. According to embodiments, processor 1010 can be a microprocessor, a central processing unit, or an application processor, etc. Processor 1010 can be connected to other components via address buses, control buses, and data buses, etc. According to embodiments, processor 1010 can also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.
[0142] The memory device 1020 can store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices such as erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase-change random access memory (PRAM) devices, resistive random access memory, nano-floating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM) devices, or ferroelectric random access memory (FRAM) devices, and / or volatile memory devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, or mobile DRAM devices.
[0143] Storage device 1030 may include solid-state drives (SSDs), hard disk drives (HDDs), and read-only optical disc storage (CD-ROMs), etc.
[0144] Input / output device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, or mouse, and output devices such as a speaker or printer. According to an embodiment, display device 1060 may be included in input / output device 1040.
[0145] The power supply 1050 can supply the power required for the operation of the electronic device 1000. For example, the power supply 1050 can be a power management integrated circuit (PMIC).
[0146] Display device 1060 can display images corresponding to the visual information of electronic device 1000. Display device 1060 can be an organic light-emitting display device or a quantum dot light-emitting display device, but is not limited to either. Display device 1060 can be connected to other components via the aforementioned bus or other communication links. Figure 13 The display device 1060 can be connected with Figure 1 The display device 100 is described in the same manner.
[0147] Although specific embodiments and applications have been described herein, other embodiments and variations can be derived from the above description. Therefore, the spirit of this disclosure is not limited to these embodiments, but extends to the appended claims, various obvious modifications and equivalents.
[0148] According to the electronic device disclosed herein, by controlling the value of the second drive power according to the drive mode of the electronic device, the risk of electrical damage to the electronic device (or the circuitry inside the electronic device) can be prevented or mitigated.
[0149] However, the effects of the embodiments according to this disclosure are not limited to those described above, and a wider variety of effects are included herein.
Claims
1. An electronic device, wherein, The electronic device includes: The processor provides input image data to the display device; and The display device displays an image based on the input image. The display device includes: The display panel includes pixels connected to a first power line, a second power line, a scan line, and a data line; A power generator supplies a first driving power to the first power line and a second driving power to the second power line; and The timing controller generates a first enable signal, a second enable signal, a third enable signal, and a fourth enable signal for controlling the second drive power according to the drive mode. Wherein, the second driving power includes a second_1 driving power with a positive value and a second_2 driving power with a negative value, and The power generator includes: The second switching unit outputs the second_2 driving power to the second power line in the first mode; and The first switching unit outputs the second_1 driving power to the second power line in a second mode that is different from the first mode.
2. The electronic device according to claim 1, wherein, The power generator also includes: The first output section outputs the second_1 driving power based on the third enable signal; and The second output section outputs the second-second drive power based on the first enable signal.
3. The electronic device according to claim 2, wherein, The first switching unit includes: A first switch receives the second_1 driving power from the first output section; and A first switch controller, in response to the fourth enable signal, turns off the first switch in the first mode and turns the first switch on in the second mode. The second switching unit includes: A second switch receives the second_2 drive power from the second output section; and The second switch controller, in response to the second enable signal, turns the second switch on in the first mode and turns the second switch off in the second mode.
4. The electronic device according to claim 3, wherein, The first switch controller includes: The first switching transistor has a first electrode connected to ground, a second electrode connected to a second switching node, and a gate electrode connected to the first switching node. A second capacitor has a first electrode connected to the ground and a second electrode connected to the first switching node; and The second resistor has one end connected to the first switching node and the other end to which the fourth enable signal is supplied. The first switch includes: The first and second switching transistors have a first electrode connected to a third switching node, a second electrode connected to a fourth switching node, and a gate electrode connected to the second switching node. A third capacitor has a first electrode connected to the second switching node and a second electrode connected to the third switching node; and The third resistor has one end connected to the second switching node and the other end connected to the third switching node.
5. The electronic device according to claim 4, wherein, The first switching transistor is an N-type transistor and the first switching transistor is a P-type transistor.
6. The electronic device according to claim 5, wherein, The first switch further includes a fourth capacitor having a first electrode connected to the second switch node and a second electrode connected to the third switch node.
7. The electronic device according to any one of claims 4 to 6, wherein, The second switch controller includes: The second_1 switching transistor has a first electrode supplied by the first drive power, a second electrode connected to the sixth switching node, and a gate electrode connected to the fifth switching node; The fifth capacitor has a first electrode to which the first driving power is supplied and a second electrode connected to the fifth switching node; and The sixth capacitor has a first electrode connected to the ground and a second electrode connected to the fifth switching node. The second switch includes: The second switching transistor has a first electrode connected to the fourth switching node, a second electrode connected to the seventh switching node, and a gate electrode connected to the sixth switching node; A seventh capacitor has a first electrode connected to the seventh switching node and a second electrode connected to the sixth switching node; and The fourth resistor has one end connected to the seventh switch node and the other end connected to the sixth switch node.
8. The electronic device according to claim 7, wherein, The second-first switching transistor is a P-type transistor and the second-second switching transistor is an N-type transistor.
9. The electronic device according to claim 8, wherein, The second switch also includes: An eighth capacitor has a first electrode connected to the seventh switching node and a second electrode connected to the sixth switching node; and The fifth resistor has one end connected to the seventh switch node and the other end connected to the sixth switch node.
10. The electronic device according to claim 8, wherein, When switching from the first mode to the second mode, the second enable signal changes from low to high after a first time interval following the transition of the first enable signal from high to low.
11. The electronic device according to claim 10, wherein, When switching from the first mode to the second mode After a second time interval following the transition of the second enable signal to the high level, the third enable signal transitions from a low level to a high level, and After a third time interval following the transition of the third enable signal to the high level, the fourth enable signal transitions from the low level to the high level.
12. The electronic device according to claim 11, wherein, During the second time interval, the value of the second drive power changes from a low level to a middle level. After the third time interval, the value of the second driving power changes from the intermediate level to a high level.
13. The electronic device according to claim 11, wherein, In the second mode, the first_1 switching transistor and the first_2 switching transistor are turned on, and the second_1 switching transistor and the second_2 switching transistor are turned off.
14. The electronic device according to claim 8, wherein, When switching from the second mode to the first mode, the fourth enable signal changes from high to low after a fourth time interval following the change of the third enable signal from high to low.
15. The electronic device according to claim 14, wherein, When switching from the second mode to the first mode After a fifth time interval following the transition of the fourth enable signal to the low level, the second enable signal transitions from the high level to the low level, and Six time intervals after the second enable signal transitions to the low level, the first enable signal transitions from the low level to the high level. In the first mode, the first 1_1 switch transistor and the first 1_2 switch transistor are turned off, and the second 1 switch transistor and the second 2_2 switch transistor are turned on.