Display panel and display device

Abstract

This invention provides a display panel and display device, relating to the field of display technology, for reducing the length of a first gate driving circuit in a second direction and improving the screen-to-body ratio of the display panel. The display panel includes a display area and a non-display area; the display area includes multiple rows of pixel driving circuits, each row including multiple pixel driving circuits arranged along a first direction; the non-display area includes a first gate driving circuit, which includes multiple cascaded first gate driving units, each first gate driving unit being electrically connected to a first control terminal of one of the multiple pixel driving circuits in the row of pixel driving circuits; the multiple first gate driving units are arranged in at least two columns of first gate driving circuits, each column including multiple first gate driving units arranged along a second direction, and the two columns of first gate driving circuits are arranged along the first direction; the second direction intersects the first direction.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display panel and display device. Background Technology

[0002] Currently, display panels typically consist of multiple sub-pixels located in the display area, and driving circuitry located in the non-display area to illuminate the sub-pixels. The area containing the driving circuitry cannot be used for display, resulting in a larger bezel area for the display panel and limiting the improvement of its screen-to-body ratio. Summary of the Invention

[0003] This invention provides a display panel and display device for reducing the length of a first gate driving circuit in a second direction and increasing the screen-to-body ratio of the display panel.

[0004] In a first aspect, embodiments of the present invention provide a display panel, including a display area and a non-display area; The display area includes multiple rows of pixel driving circuits, and each row of pixel driving circuits includes multiple pixel driving circuits arranged along a first direction. The non-display area includes a first gate driving circuit, which includes multiple cascaded first gate driving units. The first gate driving units are electrically connected to the first control terminals of multiple pixel driving circuits in the pixel driving circuit row. The plurality of first gate driving units are arranged in at least two first gate driving circuit columns. Each first gate driving circuit column includes a plurality of first gate driving units arranged along a second direction. The two first gate driving circuit columns are arranged along a first direction. The second direction and the first direction intersect.

[0005] Secondly, embodiments of the present invention provide a display device, including the display panel described above.

[0006] The display panel and display device provided in this embodiment of the invention can reduce the number of first gate driving units included in a single first gate driving circuit column by arranging a plurality of first gate driving units into at least two first gate driving circuit columns. For example, the number of first gate driving units in a single first gate driving circuit column can be less than the number of pixel driving circuit rows. This arrangement helps to reduce the length of the first gate driving circuit in the second direction, thereby increasing the screen-to-body ratio of the display panel. Attached Figure Description

[0007] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present invention; Figure 2 A circuit diagram of a pixel driving circuit and a light-emitting unit provided for an embodiment of the present invention; Figure 3 This is a timing diagram of a pixel driving circuit provided in an embodiment of the present invention; Figure 4 An enlarged schematic diagram of a first gate driving circuit and a pixel driving circuit provided in an embodiment of the present invention; Figure 5 An enlarged schematic diagram of another first gate driving circuit and pixel driving circuit provided in an embodiment of the present invention; Figure 6 An enlarged schematic diagram of another first gate driving unit and pixel driving circuit provided in an embodiment of the present invention; Figure 7 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 8 for Figure 7 An enlarged schematic diagram of region A1 in the image; Figure 9 for Figure 7 Another enlarged schematic diagram of region A1 in the diagram; Figure 10 A circuit diagram of a first gate driving unit provided in an embodiment of the present invention; Figure 11 A wiring diagram of a first gate driving unit provided in an embodiment of the present invention; Figure 12 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 13 A schematic diagram of the working timing of two pixel driving circuit rows that are electrically connected to the same second gate driving unit; Figure 14 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0009] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0010] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0011] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0012] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0013] This invention provides a display panel, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. The display panel includes a display area AA and a non-display area NA; the display area AA includes a plurality of pixel driving circuits 10.

[0014] like Figure 1 As shown, multiple pixel driving circuits 10 are arranged in an array along a first direction h1 and a second direction h2, where the first direction h1 and the second direction h2 intersect. The multiple pixel driving circuits 10 can be arranged into multiple rows 1 of pixel driving circuits arranged along the second direction h2, and each row 1 of pixel driving circuits includes multiple pixel driving circuits 10 arranged along the first direction h1.

[0015] In this embodiment of the invention, the display area AA further includes a light-emitting unit ( Figure 1 (Not shown), the pixel driving circuit 10 is electrically connected to the light-emitting unit, and the pixel driving circuit 10 provides driving current to the light-emitting unit.

[0016] like Figure 1 As shown, the non-display area NA includes a first gate driving circuit 21, which includes multiple cascaded first gate driving units 210. Cascading means that the output terminal of a previous stage first gate driving unit 210 (e.g., the i-th stage first gate driving unit 210) is electrically connected to the input terminal of a subsequent stage first gate driving unit 210 (e.g., the (i+1)-th stage first gate driving unit 210). Here, i is an integer.

[0017] In this embodiment of the invention, the first gate driving unit 210 is electrically connected to a plurality of pixel driving circuits 10 in the pixel driving circuit row 1.

[0018] For example, the first gate driving unit 210 is electrically connected to the first control terminals of a plurality of pixel driving circuits 10 in row 1 of the pixel driving circuits. The first gate driving unit 210 can provide a first control signal to the first control terminal of the pixel driving circuit 10. For example, the first control signal can be used to control the pixel driving circuit 10 to receive a data signal, the data signal being related to the driving current generated by the pixel driving circuit 10.

[0019] In one alternative implementation, such as Figure 2 As shown, Figure 2 The present invention provides a schematic diagram of a pixel driving circuit and a light-emitting unit. The pixel driving circuit 10 includes a first light-emitting control transistor T11, a data writing transistor T12, a driving transistor T13, a threshold compensation transistor T14, a first reset transistor T15, a second light-emitting control transistor T16, and a second reset transistor T17.

[0020] like Figure 2 As shown, the gate of driving transistor T13 is electrically connected to the first node N11, the first terminal of driving transistor T13 is electrically connected to the second node N12, and the second terminal of driving transistor T13 is electrically connected to the second node N13. The first terminal of the first reset transistor T15 is electrically connected to the first reset signal terminal Vref1, and the second terminal is electrically connected to the first node N1. The first terminal of the data write transistor T12 is electrically connected to the data signal terminal Data, and the second terminal of the data write transistor T12 is electrically connected to the second node N12.

[0021] The first light-emitting control transistor T11 and the second light-emitting control transistor T16, in response to the light-emitting control signal provided by the light-emitting control signal terminal E, control the driving current to flow through the light-emitting unit 11. The first reset transistor T15, in response to the first scan signal provided by the first scan signal terminal S1, electrically connects the first reset signal terminal Vref1 and the first node N1. The data writing transistor T12, in response to the second scan signal provided by the second scan signal terminal S2, electrically connects the data signal terminal Data and the second node N12.

[0022] For example, such as Figure 2 As shown, the first terminal of the threshold compensation transistor T14 is electrically connected to the second node N13, and the second terminal of the threshold compensation transistor T14 is electrically connected to the gate of the driving transistor T13; the gate of the threshold compensation transistor T14 is electrically connected to the second scan signal terminal S2.

[0023] Optional, such as Figure 2As shown, the first electrode of the first light-emitting control transistor T11 is electrically connected to the power signal terminal PVDD; the second electrode of the first light-emitting control transistor T11 is electrically connected to the first electrode of the driving transistor T13, i.e., the second node N12; the first electrode of the second light-emitting control transistor T16 is electrically connected to the second electrode of the driving transistor T13, i.e., the second node N13; the second electrode of the second light-emitting control transistor T16 is electrically connected to the first electrode of the light-emitting unit 11; and the gates of both the first light-emitting control transistor T11 and the second light-emitting control transistor T16 are electrically connected to the light-emitting control signal terminal E. The second electrode of the light-emitting unit 11 is electrically connected to the power signal terminal PVEE.

[0024] The gate of the first reset transistor T15 is electrically connected to the first scan signal terminal S1, the first terminal of the first reset transistor T15 is electrically connected to the first reset signal terminal Vref1, and the second terminal of the first reset transistor T15 is electrically connected to the first node N1.

[0025] The gate of the data writing transistor T12 is electrically connected to the second scan signal terminal S2, the first terminal is electrically connected to the data signal terminal Data, and the second terminal is electrically connected to the second node N12.

[0026] For example, such as Figure 2 As shown, the pixel driving circuit 10 also includes a second reset transistor T17 and a storage capacitor Cst. The gate of the second reset transistor T17 is electrically connected to the first scan signal terminal S1, the first terminal of the second reset transistor T17 is electrically connected to the second reset signal terminal Vref2, and the second terminal of the second reset transistor T17 is electrically connected to the light-emitting unit 11. The first plate of the storage capacitor Cst is electrically connected to the power supply signal terminal PVDD, and the second plate of the storage capacitor Cst is electrically connected to the first node N1.

[0027] Optional, such as Figure 3 As shown, Figure 3 This is a timing diagram of a pixel driving circuit provided in an embodiment of the present invention. When the pixel driving circuit 10 is working, within one working cycle T: During the first time period t1, the first scan signal terminal S1 transmits a valid level signal, causing the first reset transistor T15 and the second reset transistor T17 to conduct. The first reset signal provided by the first reset signal terminal Vref1 is written to the first node N11 through the first reset transistor T15 to reset the potential of the first node N11. The second reset signal provided by the second reset signal terminal Vref2 is written to the fourth node N14 through the second reset transistor T17 to reset the potential of the fourth node N14.

[0028] During the second time period t2, the second scan signal terminal S2 transmits a valid level signal. Both the threshold compensation transistor T14 and the data writing transistor T12 are turned on. The data signal provided by the data signal terminal Data charges the first node N11 through the data writing transistor T12, the driving transistor T13, and the threshold compensation transistor T14 until the potential of the first node N11 reaches Vdata - |Vth|, completing the threshold capture. Here, Vth is the threshold voltage of the driving transistor T13.

[0029] During the third time period t3, the light-emitting control signal terminal E transmits an effective level signal, and the first light-emitting control transistor T11, the second light-emitting control transistor T16, and the driving transistor T13 are turned on, and the light-emitting current flows through the light-emitting unit 11, causing the light-emitting unit 11 to emit light.

[0030] For example, the first control terminal mentioned above includes Figure 2 The second scan signal terminal S2 is shown.

[0031] In this embodiment of the invention, the plurality of first gate driving units 210 are arranged in at least two first gate driving circuit columns 211. For example... Figure 1 As shown, Figure 1 The diagram illustrates the arrangement of multiple first gate driving units 210 into two first gate driving circuit columns 211, wherein one first gate driving circuit column 211 includes multiple first gate driving units 210 arranged along the second direction h2, and the two first gate driving circuit columns 211 are arranged along the first direction h1.

[0032] The display panel provided in this embodiment of the invention, by arranging a plurality of first gate driving units 210 into at least two first gate driving circuit columns 211, can reduce the number of first gate driving units 210 included in a single first gate driving circuit column 211. For example, the number of first gate driving units 210 in a single first gate driving circuit column 211 can be less than the number of pixel driving circuit rows 1. This arrangement helps to reduce the length of the first gate driving circuit 21 in the second direction h2, thereby increasing the screen-to-body ratio of the display panel.

[0033] For example, in this embodiment of the invention, the number of first gate driving units 210 in the first gate driving circuit 21 is greater than or equal to the number of pixel driving circuit rows 1. Therefore, when increasing the PPI of the display panel, the number of first gate driving units 210 in the first gate driving circuit 21 also needs to be increased accordingly. By arranging multiple first gate driving units 210 into at least two first gate driving circuit columns 211, this embodiment of the invention can reduce the number of first gate driving units 210 included in a single first gate driving circuit column 211. This arrangement helps to reduce the length of the first gate driving circuit 21 in the second direction h2, and can meet the design requirements of high pixel PPI while avoiding increasing the length of the first gate driving circuit 21 in the second direction h2.

[0034] Optional, such as Figure 4 and Figure 5 As shown, Figure 4 and Figure 5 This is an enlarged schematic diagram of two first gate driving circuits and pixel driving circuits provided in embodiments of the present invention. The length of the pixel driving circuit 10 in the second direction h2 is a, and the length of the first gate driving unit 210 in the second direction h2 is c. Optionally, in embodiments of the present invention, c > a, so as to make full use of the space freed up by reducing the first gate driving unit 210 in the first gate driving circuit array 211.

[0035] For example, in an optional embodiment, the present invention can arrange more devices, such as transistors, in the first gate driving unit 210 along the second direction h2 to reduce the width of the first gate driving unit 210 in the first direction h1. By adopting this arrangement, while reducing the length of the first gate driving circuit 21 in the second direction h2, it is also possible to avoid an excessive increase in the length m of the first gate driving circuit 21 in the first direction h1, thus ensuring that the non-display area NA has a small length in both the first and second directions h1 and h2.

[0036] In another alternative embodiment, the present invention may increase the width-to-length ratio of the channel of at least some of the transistors in the first gate driving unit 210 to increase the driving capability of the first gate driving unit 210.

[0037] Optional, such as Figure 4 and Figure 5As shown, in this embodiment of the invention, c ≤ 2a can also be set. Based on the above-mentioned setting c > a to increase the length of the first gate driving unit 210 in the second direction h2, this embodiment of the invention avoids setting the length of the first gate driving unit 210 in the second direction h2 to be too large by setting c ≤ 2a. The larger the length of the first gate driving unit 210 in the second direction h2, the fewer the number of first gate driving units 210 that can be set in the first gate driving circuit array 211 will be. Therefore, by adopting this setting method, within a limited space, the number of first gate driving units 210 in a single first gate driving array 211 can be avoided being too small. Given a fixed number of first gate driving units 210 in the first gate driving circuit 211, it is possible to avoid setting too many first gate driving circuit arrays 211 in the display panel, that is, to avoid increasing the number of first gate driving circuit arrays 211, thereby avoiding excessively increasing the length of the first gate driving circuit 21 in the first direction h1.

[0038] Optionally, in this embodiment of the invention, 2c ≤ 3a, that is, c ≤ 3a / 2. By adopting this setting, the length of the first gate driving unit 210 in the second direction h2 is not too large, which is beneficial to increase the number of first gate driving units 210 provided in a single first gate driving circuit column 211, thereby reducing the number of first gate driving circuit columns 211 and reducing the length of the first gate driving circuit 21 in the first direction h1.

[0039] For example, such as Figure 4 and Figure 5 As shown, in this embodiment of the invention, different first gate driving units 210 in the first gate driving circuit 21 can have the same shape.

[0040] In another alternative implementation, exemplarily, such as Figure 6 As shown, Figure 6 This is an enlarged schematic diagram of another first gate driving unit and pixel driving circuit provided in an embodiment of the present invention. The plurality of first gate driving units 210 include at least a first type of first gate driving unit 2101 and a second type of first gate driving unit 2102. The first type of first gate driving unit 2101 has a length of c in the second direction h2 and a length of b in the first direction h1. The second type of first gate driving unit 2102 has a length of e in the second direction h2 and a length of d in the first direction h1, where b > c and d < e. That is, the long side direction of the first type of first gate driving unit 2101 is the first direction h1, and the long side direction of the second type of first gate driving unit 2102 is the second direction h2. In other words, their long side directions are different.

[0041] For example, in the embodiments of the present invention, b > d and c < e. That is, the long side direction of the first type of first gate driving unit 2101 is parallel to the short side direction of the second type of first gate driving unit 2102, both parallel to the first direction h1; the short side direction of the first type of first gate driving unit 2101 is parallel to the long side direction of the second type of first gate driving unit 2102, both parallel to the second direction h2.

[0042] Optional, such as Figure 6 As shown, in this embodiment of the invention, the first type of first gate driving unit 2101 and the second type of first gate driving unit 2102 can be arranged along the first direction h1. That is, in the first direction h1, the two at least partially overlap. After the two types of first gate driving units 210 with different long side directions are arranged in this way, the space of the non-display area can be fully utilized. While the number of first gate driving units 210 that need to be set in the first gate driving circuit 21 is fixed, by adopting this arrangement, the length of the first gate driving circuit 21, which includes multiple first gate driving units 210, can be reduced in both the first direction h1 and the second direction h2.

[0043] Optional, such as Figure 6 As shown, along the first direction h1, in this embodiment of the invention, one second type of first gate driving unit 2102 may overlap at least partially with at least two first type of first gate driving units 2101. Figure 6 The diagram illustrates an overlap of one second-type first gate driving unit 2102 and two first-type first gate driving units 2101 along the first direction h1. This arrangement further improves the space utilization of the non-display area NA and helps to simultaneously reduce the width of the first gate driving circuit 21, which includes the first-type first gate driving unit 2101 and the second-type first gate driving unit 2102, along the first direction h1 and the second direction h2.

[0044] When configuring the second type of first gate driving unit 2102, for example, in this embodiment of the invention, 2a < e ≤ 3a can be set. By setting e > 2a, this embodiment of the invention ensures that the length e of the second type of first gate driving unit 2102 in the second direction h2 will not be too small. With a fixed area of ​​the second type of first gate driving unit 2102, it can prevent the length d of the second type of first gate driving unit 2102 in the first direction h1 from being too large, thus avoiding excessively increasing the length of a single second type of first gate driving unit 2102 in the first direction h1, and thereby avoiding excessively increasing the width of the first gate driving circuit 21 in the first direction h1.

[0045] Meanwhile, by setting e≤3a, the length e of the second type of first gate driving unit 2102 in the second direction h2 can be kept from being too large. This avoids reducing the number of first gate driving units 210 included in the column where the second type of first gate driving unit 2102 is located, thereby avoiding increasing the number of columns. While reducing the width of the first gate driving circuit 21 in the second direction h2, it is also beneficial to reduce the width of the first gate driving circuit 21 in the first direction h1.

[0046] When setting the first type of first gate driving unit 2101, for example, in this embodiment of the invention, 2a < 2c ≤ 3a can be set. By setting c > a, this embodiment of the invention can avoid the length c of the first type of first gate driving unit 2101 in the second direction h2 being too small. When the area of ​​the first type of first gate driving unit 2101 is constant, it is beneficial to reduce the width b of the first type of first gate driving unit 2101 in the second direction h2, avoiding b being too large. This is beneficial to reduce the width of the column where the first type of first gate driving unit 2101 is located in the first direction h1, thereby reducing the width of the first gate driving circuit 21 including the first type of first gate driving unit 2101 in the first direction h1.

[0047] Meanwhile, by setting 2c≤3a, the length c of the first type of first gate driving unit 2101 in the second direction h2 can be kept from being too large. This avoids reducing the number of first gate driving units 210 included in the column where the first type of first gate driving unit 2101 is located, thereby avoiding increasing the number of first gate driving circuit columns 211 included in the first gate driving circuit 21. While reducing the length of the first gate driving circuit 21 in the second direction h2, it is also beneficial to reduce the length of the first gate driving circuit 21 in the first direction h1.

[0048] Optional, such as Figure 6 As shown, the second type of first gate driving unit 2102 is electrically connected to the pixel driving circuit 10 via a first connecting line 31, at least a portion of which is located between two adjacent first type of first gate driving units 2101. This arrangement avoids the first connecting line 31 from overlapping with other first gate driving units 210 in the direction h3 perpendicular to the plane of the display panel, thus reducing the coupling between the first connecting line 31 and other first gate driving units 210.

[0049] For example, such as Figure 4 , Figure 5 and Figure 6As shown, the display panel may include repeating units U along a second direction h2. Multiple repeating units U may be arranged repeatedly along the second direction h2 to form multiple pixel driving circuit rows and a first gate driving circuit. The repeating unit U includes n1 pixel driving circuit rows, where n1 > 2. Figure 4 and Figure 6 The diagram illustrates a repeating unit U comprising three rows of pixel driving circuits. Figure 5 The diagram shows a repeating unit U consisting of four pixel driving circuits.

[0050] Optional, such as Figure 7 and Figure 8 As shown, Figure 7 This is a schematic diagram of yet another display panel provided in an embodiment of the present invention. Figure 8 for Figure 7 An enlarged schematic diagram of region A1 in the diagram shows that the display region AA includes an irregularly shaped display region AA1, where the irregularly shaped display region AA1 refers to a display region whose edges are not straight lines. Figure 7 The irregularly shaped display area AA1 has rounded edges at the corners of the display panel. In the display panel, two intersecting edges are connected by rounded corners as an illustration. The setting of the irregularly shaped display area AA1 can optimize the display effect of the display panel.

[0051] In the irregular display area AA1, such as Figure 8 As shown, at least some of the pixel driving circuits 10 are staggered relative to each other in the second direction h2. This arrangement is adopted to adapt to, for example, Figure 7 The design shown is of a display panel with non-rectangular irregular shapes such as rounded corners.

[0052] For example, such as Figure 7 As shown, the display area also includes a conventional display area AA2, where the conventional display area AA2 refers to a display area with straight edges. In the conventional display area AA2, the pixel driving circuit and the first gate driving unit 210 can be configured as described above. Figure 4 , Figure 5 and Figure 6 Configure it in this way.

[0053] Optional, such as Figure 8 As shown, at least a portion of the first gate driving unit 210 and at least a portion of the pixel driving circuit 10 overlap each other in the second direction h2. This arrangement allows full utilization of the space saved by the inward retraction of the pixel driving circuit 10 towards the display area AA to house the first gate driving unit 210, which helps reduce the length of the non-display area NA of the irregularly shaped display panel in the first direction h1.

[0054] Optional, such as Figure 8As shown, the plurality of first gate driving units 210 include at least a third type of first gate driving unit 2103, wherein, along the second direction h2, the third type of first gate driving unit 2103 and at least two other first gate driving units 210 at least partially overlap. This arrangement allows the plurality of first gate driving units 210 corresponding to the irregular display area AA1 to be arranged more closely, which helps to reduce the length of the plurality of first gate driving units 210 corresponding to the irregular display area AA1 in the first direction h1.

[0055] Optional, such as Figure 9 As shown, Figure 9 for Figure 7 Another enlarged schematic diagram of region A1 in the diagram shows that the plurality of first gate driving units 210 include at least a fourth type of first gate driving unit 2104. The fourth type of first gate driving unit 2104 includes a first part 21041 and a second part 21042. The first part 21041 and the second part 21042 are arranged along the second direction h2, and the length of the first part 21041 in the first direction h1 is f1, and the length of the second part 21042 in the first direction h1 is f2, wherein f1 < f2.

[0056] like Figure 9 As shown, the first part 21041 and the third type of first gate driving unit 2103 at least partially overlap in the first direction h1; the second part 21042 and the third type of first gate driving unit 2103 at least partially overlap in the second direction h2. This arrangement fully utilizes the space between the fourth type of first gate driving unit 2104 and the third type of first gate driving unit 2103, making their arrangement more compact. This improves the space utilization of the display panel and helps to further reduce the length of the first gate driving circuit 21, which includes multiple first gate driving units 210, in the first direction h1.

[0057] Optional, such as Figure 9 As shown, the plurality of first gate driving units 210 include at least a fifth type of first gate driving unit 2105. The fifth type of first gate driving unit 2105 includes a third part 21051 and a fourth part 21052. The third part 21051 and the fourth part 21052 are arranged along the first direction h1. The length of the third part 21051 in the second direction h2 is g1, and the length of the fourth part 21052 in the second direction h2 is g2, wherein g1 < g2.

[0058] like Figure 9As shown, the fourth part 21052 and the pixel driving circuit 10 at least partially overlap in the first direction h1; the third part 21051 and the pixel driving circuit 10 at least partially overlap in the second direction h2. This arrangement fully utilizes the space between the fifth type first gate driving unit 2105 and the pixel driving circuit 10, making their arrangement more compact and improving the space utilization of the display panel. It also simultaneously reduces the length of the first gate driving circuit 21 in both the first and second directions h1.

[0059] It should be noted that the first gate driving unit 210 includes multiple transistors and / or storage capacitors and other electronic devices. The length of the first gate driving unit 210 in a certain direction refers to the maximum length of the whole composed of multiple transistors and / or storage capacitors in a certain direction.

[0060] In one alternative implementation, such as Figure 10 As shown, Figure 10 This is a circuit diagram of a first gate driving unit provided in an embodiment of the present invention. The first gate driving unit 210 includes a control module 201 and an output module 202, which are electrically connected. The control module 201 provides signals to a control node in the first gate driving unit 210, and the output module 202 outputs a gate driving signal under the action of the control node.

[0061] For example, such as Figure 10 As shown, the first gate driving unit 210 includes a first control node N21 and a second control node N22. The control module 201 includes a first sub-control module 2011 and a second sub-control module 2012. The first sub-control module 2011 is electrically connected to the first control node N21 and is used to provide signals to the first control node N21. The second sub-control module 2012 is electrically connected to the second control node N22 and is used to provide signals to the second control node N22.

[0062] In one alternative implementation, such as Figure 10 As shown, the first sub-control module 2011 includes a first control transistor T21, a third control transistor T23, a fourth control transistor T24, and a sixth control transistor T26.

[0063] In this configuration, the gate of the fourth control transistor T24 receives the first clock signal CK, the first terminal receives the input signal IN, and the second terminal and the first terminal of the sixth control transistor T26 are electrically connected to the third control node N23. The gate of the sixth control transistor T26 receives the first level signal VGL, and the second terminal is electrically connected to the first control node N21.

[0064] The gate of the third control transistor T23 is electrically connected to the second control node N22, its first terminal receives the second level signal VGH, and its second terminal is electrically connected to the first terminal of the first control transistor T21. The gate of the first control transistor T21 receives the second clock signal XCK, and its second terminal is electrically connected to the second terminal of the fourth control transistor T24.

[0065] Optional, such as Figure 10 As shown, the second sub-control module 2012 includes a second control transistor T22 and a fifth control transistor T25. The gate of the fifth control transistor T25 receives a first clock signal CK, its first terminal receives a first level signal VGL, and its second terminal is electrically connected to the second control node N22.

[0066] The gate of the second control transistor T22 is electrically connected to the third control node N23, the first terminal receives the first clock signal CK, and the second terminal is electrically connected to the second control node N22.

[0067] For example, such as Figure 10 As shown, the output module 202 includes a first output transistor T27 and a second output transistor T28. The first output transistor T27 responds to the signal of the first control node N21 by providing a second clock signal XCK to the output terminal OUT. The second output transistor T28 responds to the signal of the second control node N22 by providing a second level signal VGH to the output terminal OUT.

[0068] like Figure 10 As shown, the first gate driving unit 210 includes a first capacitor C1 and a second capacitor C2.

[0069] In terms of having such Figure 10 When designing the layout of the first gate driving unit 210 of the circuit structure shown, the embodiments of the present invention can arrange the positions of the transistors and capacitors therein according to different requirements.

[0070] For example, when it is necessary to set the first gate drive unit 210 to Figure 6 When the first type of first gate driving unit 2101 is shown, the embodiments of the present invention can make the first gate driving unit 210 according to Figure 11 Configure it as shown. Figure 11 This is a wiring diagram of a first gate driving unit provided in an embodiment of the present invention, wherein the control module 201 and the output module 202 are arranged along a first direction h1. Figure 11 As shown, when setting the output module 202, the embodiment of the present invention can arrange the seventh transistor T27 and the eighth transistor T28 along the second direction h2.

[0071] based on Figure 11The arrangement shown allows the first gate driving unit 210 to be approximately rectangular in shape, with its length b in the first direction h1 greater than its length c in the second direction h2. The maximum distance between the fifth transistor T25 and the second capacitor C22 in the first direction h1 is equal to the length b of the first gate driving unit 210 in that direction. Similarly, the maximum distance between the fifth transistor T25 and the eighth transistor T27 in the first direction h2 is equal to the length c of the first gate driving unit 210 in the second direction h2.

[0072] It should be noted that the display panel also includes multiple drive signal lines. These drive signal lines include multiple lines used to provide the aforementioned input signal IN, first clock signal CK, second clock signal XCK, first level signal VGL, and second level signal VGH, respectively. To more clearly illustrate the electrical connections between the transistors in the first gate drive unit 210, Figure 11 The drive signal lines have been omitted.

[0073] In another optional embodiment, the present invention may also arrange the seventh transistor T27 and the fifth transistor T25 along the second direction h2, and arrange the eighth transistor T28 and the fifth transistor T25 along the second direction h2, to increase the length c of the first gate driving unit 210 in the second direction h2, so that the first gate driving unit is formed as follows: Figure 6 The second type of first gate drive unit 2102 shown has a shape in which the long side direction is parallel to the second direction h2.

[0074] For example, such as Figure 9 As shown, the area of ​​the first part 21041 is smaller than the area of ​​the second part 21042. When designing the fourth type of first gate driving unit 2104, by way of example, in the embodiment of the present invention, at least a portion of the control module 201 may be located in the first part 21041, and at least a portion of the output module 202 may be located in the second part 21042.

[0075] By adopting this configuration method, the settable space of the output module 202 can be increased, thereby increasing the channel width-to-length ratio of at least one of the transistors in the output module 202, such as the first output transistor T27 and the second output transistor T28, which is beneficial to increasing the driving capability of the output signal output by the output module 202.

[0076] For example, such as Figure 9As shown, the area of ​​the third part 21051 is smaller than the area of ​​the fourth part 21052. In designing the fifth type first gate drive unit 2105, by way of example, in embodiments of the present invention, at least a portion of the control module 201 may be located in the third part 21051, and at least a portion of the output module 202 may be located in the fourth part 21052.

[0077] By adopting this configuration method, the settable space of the output module 202 can be increased, thereby increasing the channel width-to-length ratio of at least one of the transistors in the output module 202, such as the first output transistor T27 and the second output transistor T28, which is beneficial to increasing the driving capability of the output signal output by the output module 202.

[0078] For example, the first gate driving circuit 21 described above can drive the pixel driving circuit row 1 in a one-to-one manner. Here, one-to-one means that one first gate driving unit 10 of the first gate driving circuit 21 is electrically connected to one pixel driving circuit row 1, and different pixel driving circuit rows 1 are electrically connected to different first gate driving units 10.

[0079] Optionally, the first gate drive circuit 21 can drive the gate to the gate as follows: Figure 2 The data writing transistor T12 of the pixel driving circuit 10 shown writes the control signal, that is, the first gate driving circuit 21 can provide the aforementioned second scan control signal S2. When the display panel is working, different pixel driving circuit rows 1 can sequentially receive signals provided by different first gate driving units 210 in the first gate driving circuit 21 to control the different pixel driving circuit rows 1 to sequentially receive data signals.

[0080] For example, such as Figure 12 As shown, Figure 12 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The non-display area NA further includes a second gate driving circuit 22. The second gate driving circuit 22 includes multiple cascaded second gate driving units 220. Each second gate driving unit 220 is electrically connected to the second control terminal of at least two pixel driving circuit rows 1. That is, the second gate driving circuit 22 can drive the pixel driving circuit rows 1 in a one-to-two or one-to-many manner. Here, one-to-two means that one second gate driving unit 220 of the second gate driving circuit 22 is electrically connected to two pixel driving circuit rows 1, and one-to-many means that one second gate driving unit 220 of the second gate driving circuit 22 is electrically connected to more than two pixel driving circuit rows 1.

[0081] By adopting this configuration, the number of second gate driving units 220 can be reduced, making the number of second gate driving units 220 less than the number of pixel driving circuit rows 1. This helps to reduce the space occupied by the second gate driving circuit 22 and can reduce the length of the non-display area NA in the first direction h1 and the second direction h2.

[0082] For example, the second control terminal mentioned above includes Figure 2 The light-emitting control signal terminal E is shown. That is, the second gate driving unit 220 can direct the light to the following terminal: Figure 2 The gates of the first light-emitting control transistor T11 and the second light-emitting control transistor T16 shown are written with light-emitting control signals. When the display panel is working, multiple pixel driving circuits 10 in at least two pixel driving circuit rows 1 that are electrically connected to a second gate driving unit 220 can receive the same light-emitting control signal.

[0083] As illustrated by the second gate driving unit 220 electrically connecting two pixel driving circuits in row 1, for example... Figure 13 As shown, Figure 13 This is a timing diagram of two pixel driving circuit rows electrically connected to the same second gate driving unit 220. E is the light emission control signal received by the two pixel driving circuit rows 1. S1_1 and S2_1 are the first scan signal and the second scan signal received by one of the two pixel driving circuit rows electrically connected to the same second gate driving unit 220, respectively. S1_2 and S2_2 are the first scan signal and the second scan signal received by the other pixel driving circuit row of the two pixel driving circuit rows electrically connected to the same second gate driving unit 220, respectively.

[0084] Based on the same inventive concept, embodiments of the present invention also provide a display device, such as... Figure 14 As shown, Figure 14 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes the display panel 100 described above. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Of course, Figure 14 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, in-vehicle display, tablet computer, laptop computer, e-reader or television.

[0085] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, Includes display area and non-display area; The display area includes multiple rows of pixel driving circuits, and each row of pixel driving circuits includes multiple pixel driving circuits arranged along a first direction. The non-display area includes a first gate driving circuit, which includes a plurality of cascaded first gate driving units, and the first gate driving units are electrically connected to the first control terminals of a plurality of pixel driving circuits in the pixel driving circuit row. The plurality of first gate driving units are arranged in at least two first gate driving circuit columns, one first gate driving circuit column includes a plurality of first gate driving units arranged along a second direction, and the two first gate driving circuit columns are arranged along the first direction; the second direction and the first direction intersect.

2. The display panel according to claim 1, characterized in that, The length of the pixel driving circuit in the second direction is a. The length of the first gate driving unit in the second direction is c, and the first direction and the second direction intersect; wherein... c > a.

3. The display panel according to claim 2, characterized in that, c≤2a.

4. The display panel according to claim 2, characterized in that, 2c≤3a.

5. The display panel according to claim 1, characterized in that, The plurality of first gate driving units include at least a first type of first gate driving unit and a second type of first gate driving unit, wherein the first type of first gate driving unit and the second type of first gate driving unit are arranged along the first direction; The length of the first gate driving unit of the first type is c in the second direction and b in the first direction. The second type of first gate driving unit has a length of e in the second direction and a length of d in the first direction. b > d, c < e.

6. The display panel according to claim 5, characterized in that, 2a<e≤3a,2a<2c≤3a。 7. The display panel according to claim 5, characterized in that, Along the first direction, one of the second type of first gate driving units overlaps at least partially with at least two of the second type of first gate driving units.

8. The display panel according to claim 5, characterized in that, The second type of first gate driving unit is electrically connected to the pixel driving circuit via a first connection line, and at least a portion of the first connection line is located between two adjacent first type of first gate driving units.

9. The display panel according to claim 1, characterized in that, At least some of the pixel driving circuits are staggered relative to each other in the second direction.

10. The display panel according to claim 9, characterized in that, At least a portion of the first gate driving unit and at least a portion of the pixel driving circuit overlap each other in the second direction.

11. The display panel according to claim 9, characterized in that, The plurality of first gate driving units include at least a third type of first gate driving unit, and along the second direction, the third type of first gate driving unit overlaps at least partially with the other two first gate driving units.

12. The display panel according to claim 11, characterized in that, The plurality of first gate driving units include at least a fourth type of first gate driving unit, the fourth type of first gate driving unit comprising a first portion and a second portion. The first part and the second part are arranged along the second direction, and the length of the first part in the first direction is less than the length of the second part in the first direction; The first portion and the third type of first gate driving unit overlap at least partially in the first direction; The second portion and the third type of first gate driving unit overlap at least partially in the second direction.

13. The display panel according to claim 12, characterized in that, The area of ​​the first part is smaller than the area of ​​the second part; The first gate driving unit includes a control module and an output module, with at least a portion of the control module located in the first portion and at least a portion of the output module located in the second portion.

14. The display panel according to claim 9, characterized in that, The plurality of first gate driving units include at least a fifth type of first gate driving unit, the fifth type of first gate driving unit comprising a third portion and a fourth portion. The third part and the fourth part are arranged along the first direction, and the length of the third part in the second direction is less than the length of the fourth part in the second direction; The fourth part and the pixel driving circuit overlap at least partially in the first direction; The third part and the pixel driving circuit overlap at least partially in the second direction.

15. The display panel according to claim 14, characterized in that, The area of ​​the third part is smaller than the area of ​​the fourth part; The first gate driving unit includes a control module and an output module, with at least a portion of the control module located in the third part and at least a portion of the output module located in the fourth part.

16. The display panel according to claim 1, characterized in that, The non-display area further includes a second gate driving circuit, which includes a plurality of cascaded second gate driving units, and one of the second gate driving units is electrically connected to at least the second control terminal of a plurality of pixel driving circuits in two rows of pixel driving circuits. The second gate driving unit is located on the side of the first gate driving unit away from the display area.

17. A display device, characterized in that, Includes the display panel as described in any one of claims 1-16.

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