Light signal generating circuit

Abstract

A light emission signal generation circuit. The light emission signal generation circuit includes a timing output circuit and a pulse width output circuit. The timing output circuit receives a first light emission timing signal, a first clock signal, a second clock signal, and a pulse width clock signal, and outputs the pulse width clock signal based on the first light emission timing signal, the first clock signal, the second clock signal to provide a second light emission timing signal. The pulse width output circuit is coupled to the timing output circuit to receive the second light emission timing signal, and receives a gate low voltage and a pulse width enable signal, and outputs the gate low voltage based on the second light emission timing signal and the pulse width enable signal to provide a light emission drive signal.

Description

Technical Field

[0001] This invention relates to a signal generation circuit, and more particularly to a self-emissive light-emitting signal generation circuit. Background Technology

[0002] Organic light-emitting diodes (OLEDs), mini LEDs, and micro LEDs are the main components used in self-emissive display panels today. However, the luminous efficacy curves of mini LEDs and micro LEDs are different from those of organic light-emitting diodes. That is, when operating at the same brightness, the luminous efficacy point of mini LEDs and micro LEDs will be different, resulting in poor luminous efficacy and high power consumption.

[0003] For micro LEDs (uLEDs), pulse width modulation (PWM) mode has better color shift and relatively better power consumption performance compared to pulse amplitude modulation (PAM) mode. The dimming method of pulse width modulation (PWM) is to use a fixed number of pulses of the light emission signal and adjust the pulse width of the light emission signal to meet the brightness requirements, while taking into account the display quality and power consumption.

[0004] When the pulse width of the predetermined light-emitting signal is greater than the period of the clock signal, the pulse width of the light-emitting signal is usually determined based on the DC level (e.g., enable level) output by the light-emitting start signal, making the pulse width of the light-emitting signal a multiple of the period of the clock signal. Alternatively, when the pulse width of the predetermined light-emitting signal is less than the period of the clock signal, the pulse width of the light-emitting signal is usually determined based on the adjustable width AC signal received based on the output of the light-emitting start signal. However, with the above dimming method, to improve the dimming flexibility, more clock signals with different phases but fixed pulse widths are needed, or an adjustable width AC signal with greater driving capability is needed. In other words, to improve the dimming flexibility of pulse width modulation, more circuit area is inevitably required for transmitting the clock signal / AC signal. Summary of the Invention

[0005] This invention provides a light-emitting signal generating circuit that can improve the dimming flexibility of pulse width modulation without increasing the circuit area used.

[0006] The light-emitting signal generation circuit of the present invention includes a timing output circuit and a pulse-width output circuit. The timing output circuit receives a first light-emitting timing signal, a first clock signal, a second clock signal, and a pulse-width clock signal, and outputs a pulse-width clock signal based on the first light-emitting timing signal, the first clock signal, and the second clock signal to provide a second light-emitting timing signal. The pulse-width output circuit is coupled to the timing output circuit to receive the second light-emitting timing signal, and receives a gate low voltage and a pulse-width enable signal, and outputs a gate low voltage based on the second light-emitting timing signal and the pulse-width enable signal to provide a light-emitting drive signal.

[0007] Based on the above, in the light-emitting signal generation circuit of this embodiment, the light-emitting driving signal can determine the start point of the pulse based on the light-emitting timing signal, and the light-emitting driving signal can determine the end point of the pulse based on the pulse width enable signal; that is, the pulse width of the light-emitting driving signal can be based on both the light-emitting timing signal and the pulse width enable signal. Therefore, the dimming flexibility of pulse width modulation can be improved. Furthermore, since the pulse width output circuit has a low output gate voltage (i.e., a low power supply voltage), there is no need to increase the signal / clock driving capability, i.e., no need to increase the additional circuit area.

[0008] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a light-emitting signal generation circuit according to an embodiment of the present invention.

[0010] Figure 2 This is a circuit diagram of a light-emitting signal generating circuit according to an embodiment of the present invention.

[0011] Figure 3 This is a schematic diagram of the driving waveform of a light-emitting signal generating circuit according to an embodiment of the present invention, where the pulse width of the light-emitting driving signal is less than the signal period of the clock signal.

[0012] Figure 4A This is a schematic diagram of the operation of a light-emitting signal generating circuit during pre-charging according to an embodiment of the present invention.

[0013] Figure 4B This is a schematic diagram of the operation of a light-emitting signal generating circuit during voltage pull-down according to an embodiment of the present invention.

[0014] Figure 4C This is a schematic diagram of the operation of a light-emitting signal generating circuit during voltage pull-up according to an embodiment of the present invention.

[0015] Figure 4DThis is a schematic diagram of the operation of a light-emitting signal generating circuit according to an embodiment of the present invention during a voltage stabilization period.

[0016] Figure 5 This is a schematic diagram of the driving waveform of a light-emitting signal generating circuit according to an embodiment of the present invention, where the pulse width of the light-emitting driving signal is greater than the period of the clock signal.

[0017] Figure 6 This is a circuit diagram of a light-emitting signal generating circuit according to another embodiment of the present invention.

[0018] Explanation of reference numerals in the attached figures: 100, 100a, 100b: Light emission signal generation circuit 110: Timing Output Circuit 111, 111a: Timing pull-down control circuit 112, 112a: Timing pull-down circuits 113, 113a: Timing pull-up control circuit 114, 114a: Sequential pull-up circuits 120: Pulse Width Output Circuit 121, 121a: Pulse Width Pull-Down Control Circuit 122, 122a: Pulse Width Pull-Down Circuits 123, 123a: Pulse width pull-up control circuit 124, 124a: Pulse Width Pull-Up Circuit BT1(n), BT2(n): Pull-down control voltages C1~C4, C3a: Capacitors CLK(n), CLK(n+1), CLK1, CLK2: Clock signals EM_AA(n), EM_AA(1): Light emission driving signals EM_STV: Light emission start signal EMT(n-1), EMT(n), EMT(1): Light emission timing signals ENA, ENB: Pulse Width Enable Signals H: During horizontal scanning H: High voltage level L: Low voltage level Ppd, Ppda: During voltage pull-down period Pph, Ppha: During voltage pull-up Ppr, Ppra: During pre-charging Pstb, Pstba: During voltage stabilization PWCK(n), PWCK1, PWCK2: Pulse width clock signals Q(n), X(n): Pull-up control voltage T1~T22: Transistors VGH: Gate High Voltage VGL: Gate Low Voltage Detailed Implementation

[0019] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and this invention, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0020] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the “first element,” “component,” “region,” “layer,” or “part” discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this document.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms “comprising” and / or “comprising” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0022] Figure 1 This is a system schematic diagram of a light-emitting signal generation circuit according to an embodiment of the present invention. Please refer to... Figure 1In this embodiment, the light emission signal generation circuit 100 includes a timing output circuit 110 and a pulse width output circuit 120. The timing output circuit 110 receives the light emission timing signal EMT(n-1) (corresponding to the first light emission timing signal), the clock signal CLK(n) (corresponding to the first clock signal) and CLK(n+1) (corresponding to the second clock signal), and the pulse width clock signal PWCK(n), and outputs the pulse width clock signal PWCK(n) based on the light emission timing signal EMT(n-1), the clock signal CLK(n), and CLK(n+1) to provide the light emission timing signal EMT(n) (corresponding to the second light emission timing signal), where n is a lead number.

[0023] The pulse width output circuit 120 is coupled to the timing output circuit 110 to receive the light emission timing signal EMT(n), and to receive the gate low voltage VGL and the pulse width enable signal ENA. Based on the light emission timing signal EMT(n) and the pulse width enable signal ENA, the circuit outputs the gate low voltage VGL to provide the light emission driving signal EM_AA(n).

[0024] Based on the above, the starting point of the pulse in the light-emitting drive signal EM_AA(n) can be determined based on the light-emitting timing signal EMT(n), and the pulse width of the light-emitting drive signal EM_AA(n) can be based on the starting point of the pulse, that is, the pulse width of the light-emitting drive signal EM_AA(n) can be based on the light-emitting timing signal EMT(n) and the pulse width enable signal ENA. Therefore, the dimming flexibility of pulse width modulation can be improved. Furthermore, since the pulse width output circuit 120 has a low gate voltage VGL (i.e., a low power supply voltage), there is no need to increase the signal / clock driving capability, that is, no need to increase the additional circuit area.

[0025] In this embodiment, the timing output circuit 110 includes a timing pull-down control circuit 111, a timing pull-down circuit 112, a timing pull-up control circuit 113, and a timing pull-up circuit 114. The timing pull-down control circuit 111 receives the light emission timing signal EMT(n-1) and the clock signal CLK(n) to provide a pull-down control voltage BT1(n) (corresponding to the first pull-down control voltage) based on the light emission timing signal EMT(n-1) and the clock signal CLK(n).

[0026] The timing pull-down circuit 112 is coupled to the timing pull-down control circuit 111 to receive the pull-down control voltage BT1(n), and to receive the clock signal CLK(n+1) and the pulse width clock signal PWCK(n), so as to output the pulse width clock signal PWCK(n) based on the pull-down control voltage BT1(n) and the clock signal CLK(n+1) to provide the light emission timing signal EMT(n).

[0027] The timing pull-up control circuit 113 is coupled to the timing pull-down control circuit 111 to receive the pull-down control voltage BT1(n), and to receive the light emission timing signal EMT(n-1), the clock signal CLK(n), and the gate high voltage VGH, so as to provide the pull-up control voltage Q(n) (corresponding to the first pull-up control voltage) based on the pull-down control voltage BT1(n), the light emission timing signal EMT(n-1), and the clock signal CLK(n).

[0028] The timing pull-up circuit 114 is coupled to the timing pull-up control circuit 113 to receive the pull-up control voltage Q(n), coupled to the light emission timing signal EMT(n), and receives the gate high voltage VGH, so as to pull the light emission timing signal EMT(n) up to the gate high voltage VGH based on the pull-up control voltage Q(n).

[0029] In this embodiment, the pulse width output circuit 120 includes a pulse width pull-down control circuit 121, a pulse width pull-down circuit 122, a pulse width pull-up control circuit 123, and a pulse width pull-up circuit 124. The pulse width pull-down control circuit 121 receives the light emission timing signal EMT(n) and provides a pull-down control voltage BT2(n) (corresponding to the second pull-down control voltage) based on the light emission timing signal EMT(n).

[0030] The pulse width pull-down circuit 122 is coupled to the pulse width pull-down control circuit 121 to receive the pull-down control voltage BT2(n) and the gate low voltage VGL, so as to output the gate low voltage VGL based on the pull-down control voltage BT2(n) to provide the light emission drive signal EM_AA(n).

[0031] The pulse width pull-up control circuit 123 is coupled to the pulse width pull-down control circuit 121 to receive the pull-down control voltage BT2(n), and to receive the light emission timing signal EMT(n), the pulse width enable signal ENA, and the gate high voltage VGH, so as to provide the pull-up control voltage X(n) (corresponding to the second pull-up control voltage) based on the pull-down control voltage BT2(n), the light emission timing signal EMT(n), and the pulse width enable signal ENA.

[0032] The pulse width pull-up circuit 124 is coupled to the pulse width pull-up control circuit 123 to receive the pull-up control voltage X(n), coupled to the light emission driving signal EM_AA(n), and receives the gate high voltage VGH, so as to pull the light emission driving signal EM_AA(n) up to the gate high voltage VGH based on the pull-up control voltage X(n).

[0033] Figure 2 This is a circuit diagram of a light-emitting signal generating circuit according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2In this embodiment, the light emission signal generation circuit 100 is exemplified by light emission signal generation circuit 100a, wherein the same or similar components are labeled with the same or similar reference numerals. Furthermore, the timing pull-down control circuit 111, timing pull-down circuit 112, timing pull-up control circuit 113, timing pull-up circuit 114, pulse width pull-down control circuit 121, pulse width pull-down circuit 122, pulse width pull-up control circuit 123, and pulse width pull-up circuit 124 can refer to the circuit structures shown in the timing pull-down control circuit 111a, timing pull-down circuit 112a, timing pull-up control circuit 113a, timing pull-up circuit 114a, pulse width pull-down control circuit 121a, pulse width pull-down circuit 122a, pulse width pull-up control circuit 123a, and pulse width pull-up circuit 124a, but the embodiments of the present invention are not limited thereto.

[0034] In this embodiment, the timing pull-down control circuit 111a includes a transistor T1 (corresponding to the first transistor), wherein the transistor T1 is, for example, a P-type transistor. The transistor T1 has a first terminal for receiving the light emission timing signal EMT(n-1), a control terminal for receiving the clock signal CLK(n), and a second terminal for providing the pull-down control voltage BT1(n).

[0035] In this embodiment, the timing pull-down circuit 112a includes transistors T2 and T3 (corresponding to the second and third transistors) and capacitor C1 (corresponding to the first capacitor), wherein transistors T2 and T3 are, for example, P-type transistors. Transistor T2 has a first terminal for receiving the pull-down control voltage BT1(n), a control terminal for receiving the gate low voltage VGL, and a second terminal. Transistor T3 has a first terminal for receiving the pulse width clock signal PWCK(n), a control terminal coupled to the second terminal of transistor T2, and a second terminal for providing the light emission timing signal EMT(n). Capacitor C1 is coupled between the clock signal CLK(n+1) and the control terminal of transistor T3.

[0036] In this embodiment, the timing pull-up control circuit 113a includes transistors T4 to T8 (corresponding to the fourth to eighth transistors) and capacitor C2 (corresponding to the second capacitor), wherein transistors T4 to T8 are, for example, P-type transistors. Transistor T4 has a first terminal, a control terminal for receiving the light emission timing signal EMT(n-1), and a second terminal. Transistor T5 has a first terminal coupled to the second terminal of transistor T4, a control terminal for receiving the light emission timing signal EMT(n-1), and a second terminal for receiving the gate high voltage VGH. Capacitor C2 is coupled between the clock signal CLK(n) and the first terminal of transistor T4.

[0037] Transistor T6 has a first terminal coupled to a low gate voltage VGL, a control terminal coupled to a first terminal of transistor T4, and a second terminal providing a pull-up control voltage Q(n). Transistor T7 has a first terminal coupled to the second terminal of transistor T6, a control terminal receiving a pull-down control voltage BT1(n), and a second terminal. Transistor T8 has a first terminal coupled to the second terminal of transistor T7, a control terminal receiving a pull-down control voltage BT1(n), and a second terminal receiving a high gate voltage VGH.

[0038] In this embodiment, the timing pull-up circuit 114a includes transistors T9 to T11 (corresponding to the ninth to eleventh transistors), wherein transistors T9 to T11 are, for example, P-type transistors. Transistor T9 has a first terminal coupled to the pull-down control voltage BT1(n), a control terminal receiving the pull-up control voltage Q(n), and a second terminal. Transistor T10 has a first terminal coupled to the second terminal of transistor T9, a control terminal receiving the pull-up control voltage Q(n), and a second terminal receiving the gate high voltage VGH. Transistor T11 has a first terminal coupled to the light emission timing signal EMT(n), a control terminal receiving the pull-up control voltage Q(n), and a second terminal receiving the gate high voltage VGH.

[0039] In this embodiment, the pulse width pull-down control circuit 121a includes transistor T12 (corresponding to the twelfth transistor), wherein transistor T12 is, for example, a P-type transistor. Transistor T12 has a first terminal for receiving the light emission timing signal EMT(n), a control terminal for receiving the light emission timing signal EMT(n), and a second terminal for providing the pull-down control voltage BT2(n).

[0040] In this embodiment, the pulse width modulation (PWM) pull-down circuit 122a includes transistors T13 and T14 (corresponding to the thirteenth and fourteenth transistors) and capacitor C3 (corresponding to the third capacitor), wherein transistors T13 and T14 are, for example, P-type transistors. Transistor T13 has a first terminal receiving the pull-down control voltage BT2(n), a control terminal receiving the gate low voltage VGL, and a second terminal. Transistor T14 has a first terminal receiving the gate low voltage VGL, a control terminal coupled to the second terminal of transistor T13, and a second terminal providing the light-emitting drive signal EM_AA(n). Capacitor C3 is coupled between the control terminal and the second terminal of transistor T14, that is, coupled between the light-emitting drive signal EM_AA(n) (corresponding to the reference signal) and the control terminal of transistor T14.

[0041] In this embodiment, the pulse width pull-up control circuit 123a includes transistors T15-T19 (corresponding to the fifteenth to nineteenth transistors) and capacitor C4 (corresponding to the fourth capacitor), wherein transistors T15-T19 are, for example, P-type transistors. Transistor T15 has a first terminal, a control terminal for receiving the light emission timing signal EMT(n), and a second terminal. Transistor T16 has a first terminal coupled to the second terminal of transistor T15, a control terminal for receiving the light emission timing signal EMT(n), and a second terminal for receiving the gate high voltage VGH. Capacitor C4 is coupled between the pulse width enable signal ENA and the first terminal of transistor T16.

[0042] Transistor T17 has a first terminal coupled to a gate low voltage VGL, a control terminal coupled to a first terminal of transistor T15, and a second terminal providing a pull-up control voltage X(n). Transistor T18 has a first terminal coupled to the second terminal of transistor T17, a control terminal receiving a pull-down control voltage BT2(n), and a second terminal. Transistor T19 has a first terminal coupled to the second terminal of transistor T18, a control terminal receiving a pull-down control voltage BT2(n), and a second terminal receiving a gate high voltage VGH.

[0043] In this embodiment, the pulse width modulation pull-up circuit 124a includes transistors T20 to T22 (corresponding to the twentieth to the twenty-second transistors), wherein transistors T20 to T22 are, for example, P-type transistors. Transistor T20 has a first terminal coupled to the pull-down control voltage BT2(n), a control terminal receiving the pull-up control voltage X(n), and a second terminal. Transistor T21 has a first terminal coupled to the second terminal of transistor T20, a control terminal receiving the pull-up control voltage X(n), and a second terminal receiving the gate high voltage VGH. Transistor T22 has a first terminal coupled to the light-emitting drive signal EM_AA(n), a control terminal receiving the pull-up control voltage X(n), and a second terminal receiving the gate high voltage VGH.

[0044] Figure 3 This is a schematic diagram of the driving waveform of a light-emitting signal generation circuit according to an embodiment of the present invention, where the pulse width of the light-emitting driving signal is less than the signal period of the clock signal. Please refer to... Figures 1 to 3 In this embodiment, for example, the pulse width of the light-emitting drive signal EM_AA(n) is less than the signal period of the clock signals CLK(n) and CLK(n+1), and the pulse width clock signal PWCK(n) is set as a pulse signal. The operation of the light-emitting signal generation circuit 100a is roughly divided into four periods: the pre-charge period Ppr, the voltage pull-down period Ppd, the voltage pull-up period Pph, and the voltage stabilization period Pstb.

[0045] The signal period of the pulse width enable signal ENA can be determined based on the expected pulse width of the light emission drive signal EM_AA(n), but it is greater than or equal to the signal periods of the clock signals CLK(n) and CLK(n+1).

[0046] In this embodiment, the pulse width of the light emission driving signal EM_AA(n) is, for example, less than the signal period of the clock signals CLK(n) and CLK(n+1) (e.g., 2H during two horizontal scan periods). Therefore, the signal period of the pulse width enable signal ENA can be set to 2H during two horizontal scan periods.

[0047] In this embodiment, the light emission timing signal EMT(n-1) is based on the light emission start signal EM_STV, the light emission timing signal EMT(n) is based on the light emission timing signal EMT(1), the clock signal CLK(n) is based on the clock signal CLK1, the clock signal CLK(n+1) is based on the clock signal CLK2, the pulse width clock signal PWCK(n) is based on the pulse width clock signal PWCK1, and the light emission drive signal EM_AA(n) is based on the light emission drive signal EM_AA(1). Furthermore, clock signals CLK1 and CLK2 have the same waveform but a phase difference of 180 degrees, pulse width clock signals PWCK1 and PWCK2 have the same waveform but a phase difference of 180 degrees, and pulse width enable signals ENA and ENB have the same waveform but a phase difference of 180 degrees.

[0048] Figure 4A This is a schematic diagram of the operation of a light-emitting signal generating circuit during pre-charging according to an embodiment of the present invention. Please refer to... Figures 1 to 3 and Figure 4A In this embodiment, during the pre-charge period Ppr, the light emission start signal EM_STV and the clock signal CLK1 are at a low voltage level L, causing the pull-down control voltage BT1(n) to be at a low voltage level L to turn on transistor T3. At this time, the clock signal CLK2 and the pulse width clock signal PWCK1 are at a high voltage level H. Therefore, the light emission timing signal EMT(1) will be at a high voltage level H.

[0049] The low voltage level L of the light-emitting start signal EM_STV turns on transistors T4 and T5, causing the gate high voltage VGH (considered as a high voltage level H) to be transmitted to the control terminal of transistor T6, thus turning off transistor T6. The low voltage level L of the pull-down control voltage BT1(n) turns on transistors T7 and T8, causing the gate high voltage VGH (considered as a high voltage level H) to be transmitted to the second terminal of transistor T6, that is, the pull-up control voltage Q(n) is a high voltage level H, so transistors T9~T11 are turned off.

[0050] The high voltage level H of the light emission timing signal EMT(1) turns off transistors T12, T15, and T16. Since the pulse width enable signal ENA changes from a high voltage level H to a low voltage level L, transistor T17 will turn on. At this time, the low gate voltage VGL (considered as a low voltage level L) is transmitted to the second terminal of transistor T17 via the turned-on transistor T17, thus the pull-up control voltage X(n) becomes a low voltage level L, thereby turning on transistors T20~T22. Therefore, under the influence of the high gate voltage VGH, the pull-down control voltage BT2(n) and the light emission driving signal EM_AA(1) will be at a high voltage level H.

[0051] Figure 4B This is a schematic diagram of the operation of a light-emitting signal generating circuit according to an embodiment of the present invention during voltage pull-down. Please refer to... Figures 1 to 3 and Figure 4B In this embodiment, during the voltage pull-down period Ppd, the light emission start signal EM_STV and the clock signal CLK1 are at a high voltage level H, causing transistor T1 to be cut off. Furthermore, the clock signal CLK2 changes from a high voltage level H to a low voltage level L, causing the voltage at the control terminal of transistor T3 to be a low voltage level L followed by another low voltage level L (denoted as L--). At this time, the pulse width clock signal PWCK1 is at a low voltage level L, which means the light emission timing signal EMT(1) is at a low voltage level L.

[0052] The high voltage level H of the light emission start signal EM_STV turns off transistors T4 and T5, keeping the voltage at the control terminal of transistor T6 at a high voltage level H, meaning transistor T6 remains off. Meanwhile, transistors T7 and T8 remain on, keeping the pull-up control voltage Q(n) at a high voltage level H, thus turning off transistors T9 to T11.

[0053] The low voltage level L of the light emission timing signal EMT(1) turns on transistor T12, making the pull-down control voltage BT2(n) low voltage level L, that is, transistor T14 will be turned on, so the light emission driving signal EM_AA(1) will be low voltage level L.

[0054] The low voltage level L of the light emission timing signal EMT(1) also turns on transistors T15 and T16, transmitting the high gate voltage VGH to the control terminal of transistor T17. Furthermore, the pulse width enable signal ENA is at a high voltage level H, thus transistor T17 is turned off. Additionally, transistors T18 and T19 are turned on by the low voltage level L of the pull-down control voltage BT2(n), thus transistors T20~T22 are turned off.

[0055] Figure 4C This is a schematic diagram of the operation of a light-emitting signal generating circuit during voltage pull-up according to an embodiment of the present invention. Please refer to... Figures 1 to 3 and Figure 4C In this embodiment, during the voltage pull-up period Pph, the light emission start signal EM_STV is at a high voltage level H, and the clock signal CLK1 changes from a high voltage level H to a low voltage level L, causing transistor T1 to turn on. Therefore, the pull-down control voltage BT1(n) is at a high voltage level H to turn off transistor T3.

[0056] The high voltage level H of the light emission start signal EM_STV cuts off transistors T4 and T5, and the high voltage level H of the pull-down control voltage BT1(n) cuts off transistors T7 and T8. However, the low voltage level L of the clock signal CLK1 turns on transistor T6, so the pull-up control voltage Q(n) is affected by the low gate voltage VGL and is at a low voltage level L. Therefore, transistors T9~T11 are turned on, making the pull-down control voltage BT1(n) and the light emission timing signal EMT(1) at a high voltage level H.

[0057] The high voltage level H of the light emission timing signal EMT(1) turns off transistors T12, T15, and T16. Since the pulse width enable signal ENA changes from a high voltage level H to a low voltage level L, transistor T17 will turn on. At this time, influenced by the low gate voltage VGL, the pull-up control voltage X(n) becomes a low voltage level L, thus turning on transistors T20~T22. Therefore, influenced by the high gate voltage VGH, the pull-down control voltage BT2(n) and the light emission driving signal EM_AA(1) will be at a high voltage level H.

[0058] Figure 4D This is a schematic diagram of the operation of a light-emitting signal generating circuit according to an embodiment of the present invention during a voltage stabilization period. Please refer to... Figures 1 to 3 and Figure 4D In this embodiment, Pstb during the voltage stabilization period is approximately the same as Pph during the voltage pull-up period, which will not be elaborated further here.

[0059] Figure 5 This is a schematic diagram of the driving waveform of a light-emitting signal generation circuit according to an embodiment of the present invention, where the pulse width of the light-emitting driving signal is greater than the period of the clock signal. Please refer to... Figures 1 to 3 and Figure 5In this embodiment, for example, the pulse width of the light-emitting drive signal EM_AA(n) is greater than the signal period of the clock signals CLK(n) and CLK(n+1), and the pulse width clock signal PWCK(n) is set to a DC signal whose level corresponds to the gate low voltage VGL (considered as low voltage level L). The operation of the light-emitting signal generation circuit 100a is roughly divided into four periods: a pre-charge period Ppra, a voltage pull-down period Ppda, a voltage pull-up period Ppha, and a voltage stabilization period Pstba. The operation of the pre-charge period Ppra, the voltage pull-down period Ppda, the voltage pull-up period Ppha, and the voltage stabilization period Pstba can be referred to... Figures 4A to 4D The diagram shows the pre-charge period Ppr, the voltage pull-down period Ppd, the voltage pull-up period Pph, and the voltage stabilization period Pstb. The difference is that the pre-charge period Ppra and the voltage pull-down period Ppda overlap.

[0060] Figure 6 This is a circuit diagram of a light-emitting signal generating circuit according to another embodiment of the present invention. Please refer to... Figure 1 , Figure 2 and Figure 6 In this embodiment, the light emission signal generation circuit 100b is largely the same as the light emission signal generation circuit 100a, except that the capacitor C3a in the pulse width pull-down circuit 122b is coupled between the pulse width enable signal ENB (corresponding to the second pulse width enable signal / reference signal) and the control terminal of the transistor T14.

[0061] In summary, the light-emitting signal generation circuit of this embodiment of the invention, as described above, allows the light-emitting driving signal to determine the pulse start point based on the light-emitting timing signal, and the light-emitting driving signal to determine the pulse end point based on the pulse width enable signal. That is, the pulse width of the light-emitting driving signal can be based on both the light-emitting timing signal and the pulse width enable signal. Therefore, the dimming flexibility of pulse width modulation can be improved. Furthermore, since the pulse width output circuit has a low output gate voltage (i.e., a low power supply voltage), there is no need to increase the signal / clock driving capability, i.e., no need to increase the additional circuit area.

[0062] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A light-emitting signal generating circuit, comprising: A timing output circuit receives a first light emission timing signal, a first clock signal, a second clock signal, and a pulse width clock signal, and outputs the pulse width clock signal based on the first light emission timing signal, the first clock signal, and the second clock signal to provide a second light emission timing signal; as well as A pulse width output circuit is coupled to the timing output circuit to receive the second light emission timing signal, and to receive a gate low voltage and a pulse width enable signal, and to output the gate low voltage based on the second light emission timing signal and the pulse width enable signal to provide a light emission driving signal.

2. The light-emitting signal generating circuit as described in claim 1, wherein when the pulse width of the light-emitting driving signal is less than the signal period of the first clock signal and the second clock signal, the pulse width clock signal is a pulse signal. When the pulse width of the light-emitting driving signal is greater than the signal period of the first clock signal and the second clock signal, the pulse width clock signal is a DC signal.

3. The light-emitting signal generating circuit as described in claim 1, wherein the timing output circuit comprises: A timing pull-down control circuit receives the first light emission timing signal and the first clock signal, and provides a first pull-down control voltage based on the first light emission timing signal and the first clock signal; A timing pull-down circuit is coupled to the timing pull-down control circuit to receive the first pull-down control voltage, and to receive the second clock signal and the pulse width clock signal, so as to output the pulse width clock signal based on the first pull-down control voltage and the second clock signal to provide the second light emission timing signal; A timing pull-up control circuit is coupled to the timing pull-down control circuit to receive the first pull-down control voltage, and to receive the first light emission timing signal and the first clock signal, so as to provide a first pull-up control voltage based on the first pull-down control voltage, the first light emission timing signal and the first clock signal; as well as A timing pull-up circuit is coupled to the timing pull-up control circuit to receive the first pull-up control voltage, coupled to the second light emission timing signal, and receives a gate high voltage to pull the second light emission timing signal up to the gate high voltage based on the first pull-up control voltage.

4. The light-emitting signal generating circuit as described in claim 3, wherein the timing pull-down control circuit comprises: A first transistor has a first terminal for receiving the first light emission timing signal, a control terminal for receiving the first clock signal, and a second terminal for providing the first pull-down control voltage.

5. The light-emitting signal generating circuit as described in claim 3, wherein the timing pull-down circuit comprises: A second transistor has a first terminal for receiving the first pull-down control voltage, a control terminal for receiving the gate low voltage, and a second terminal; A third transistor has a first terminal for receiving the pulse width clock signal, a control terminal coupled to the second terminal of the second transistor, and a second terminal for providing the second light emission timing signal; and A first capacitor is coupled between the second clock signal and the control terminal of the third transistor.

6. The light-emitting signal generating circuit as described in claim 3, wherein the timing pull-up control circuit comprises: A fourth transistor has a first terminal, a control terminal for receiving the first light emission timing signal, and a second terminal; A fifth transistor has a first terminal coupled to the second terminal of the fourth transistor, a control terminal for receiving the first light emission timing signal, and a second terminal for receiving the gate high voltage; A second capacitor is coupled between the first clock signal and the first terminal of the fourth transistor; A sixth transistor has a first terminal coupled to the gate low voltage, a control terminal coupled to the first terminal of the fourth transistor, and a second terminal providing the first pull-up control voltage; A seventh transistor, having a first terminal coupled to the second terminal of the sixth transistor, a control terminal receiving the first pull-down control voltage, and a second terminal; and An eighth transistor has a first terminal coupled to the second terminal of the seventh transistor, a control terminal receiving the first pull-down control voltage, and a second terminal receiving the gate high voltage.

7. The light-emitting signal generating circuit as described in claim 3, wherein the timing pull-up circuit comprises: A ninth transistor has a first terminal coupled to the first pull-down control voltage, a control terminal receiving the first pull-up control voltage, and a second terminal; A tenth transistor has a first terminal coupled to the second terminal of the ninth transistor, a control terminal receiving the first pull-up control voltage, and a second terminal receiving the gate high voltage; and An eleventh transistor has a first terminal coupled to the second light emission timing signal, a control terminal receiving the first pull-up control voltage, and a second terminal receiving the gate high voltage.

8. The light-emitting signal generating circuit as described in claim 1, wherein the pulse width output circuit comprises: A pulse width pull-down control circuit receives the second light emission timing signal and provides a second pull-down control voltage based on the second light emission timing signal; A pulse width pull-down circuit is coupled to the pulse width pull-down control circuit to receive the second pull-down control voltage and the gate low voltage, so as to output the gate low voltage based on the second pull-down control voltage to provide the light emission driving signal; A pulse width pull-up control circuit is coupled to the pulse width pull-down control circuit to receive the second pull-down control voltage, and to receive the second light emission timing signal and the pulse width enable signal, so as to provide a second pull-up control voltage based on the second pull-down control voltage, the second light emission timing signal and the pulse width enable signal; as well as A pulse width pull-up circuit is coupled to the pulse width pull-up control circuit to receive the second pull-up control voltage, coupled to the light emission driving signal, and receives a gate high voltage to pull the light emission driving signal up to the gate high voltage based on the second pull-up control voltage.

9. The light-emitting signal generating circuit as described in claim 8, wherein the pulse width pull-down control circuit comprises: A twelfth transistor has a first terminal for receiving the second light emission timing signal, a control terminal for receiving the second light emission timing signal, and a second terminal for providing the second pull-down control voltage.

10. The light-emitting signal generating circuit as described in claim 8, wherein the pulse width pull-down circuit comprises: A thirteenth transistor has a first terminal for receiving the second pull-down control voltage, a control terminal for receiving the gate low voltage, and a second terminal; A fourteenth transistor has a first terminal receiving the low gate voltage, a control terminal coupled to the second terminal of the thirteenth transistor, and a second terminal providing the light-emitting drive signal; and A third capacitor is coupled between a reference signal and the control terminal of the fourteenth transistor.

11. The light emission signal generating circuit of claim 8, wherein the reference signal is one of the light emission driving signal and a second pulse width enable signal.

12. The light-emitting signal generating circuit as described in claim 8, wherein the pulse width pull-up control circuit comprises: A fifteenth transistor has a first terminal, a control terminal for receiving the second light emission timing signal, and a second terminal; A sixteenth transistor has a first terminal coupled to the second terminal of the fifteenth transistor, a control terminal for receiving the second light emission timing signal, and a second terminal for receiving the gate high voltage; A fourth capacitor is coupled between the pulse width enable signal and the first terminal of the sixteenth transistor; A seventeenth transistor has a first terminal coupled to the gate low voltage, a control terminal coupled to the first terminal of the fifteenth transistor, and a second terminal providing the second pull-up control voltage; An eighteenth transistor has a first terminal coupled to the second terminal of the seventeenth transistor, a control terminal receiving the second pull-down control voltage, and a second terminal; and A nineteenth transistor has a first terminal coupled to the second terminal of the eighteenth transistor, a control terminal receiving the second pull-down control voltage, and a second terminal receiving the gate high voltage.

13. The light-emitting signal generating circuit as described in claim 8, wherein the pulse width pull-up circuit comprises: A twentieth transistor has a first terminal coupled to the second pull-down control voltage, a control terminal receiving the second pull-up control voltage, and a second terminal; A twenty-first transistor has a first terminal coupled to the second terminal of the twentyth transistor, a control terminal receiving the second pull-up control voltage, and a second terminal receiving the gate high voltage; and A 22nd transistor has a first terminal coupled to the light-emitting drive signal, a control terminal receiving the second pull-up control voltage, and a second terminal receiving the gate high voltage.

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