Organic light emitting diode display panel and driving circuit thereof

Abstract

The application discloses an organic light emitting diode display panel and a driving circuit thereof. The display panel is provided with a pixel array and a shared data and sensing dual-function line. Each pixel unit adopts a structure in which a driving circuit is integrated with a time sequence controller, a mode switching switch, a voltage driving path, a current integration path and a mixed signal processor. The shared data and sensing dual-function line architecture eliminates the influence of parasitic capacitance, reduces the sensing path time constant to less than 0.5 microseconds, calculates the threshold voltage by using a double-level integration ratio method, realizes threshold voltage compensation error of less than or equal to ±3%, eliminates the hysteresis effect by inserting a zero bias voltage relaxation stage, effectively reduces the dynamic residual image gray scale difference, and reduces power consumption by using differential predictive coding. The application realizes wide-range, high-precision and row-by-row real-time threshold voltage and mobility double-parameter compensation in a compact pixel structure, significantly improves display uniformity and reduces power consumption.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to an organic light-emitting diode display panel, a driving circuit for the display panel, and a display device. Background Technology

[0002] Active-Matrix Organic Light-Emitting Diode (AMOLED) displays have become a mainstream advanced display technology due to their advantages such as high contrast, fast response, wide viewing angle, and flexibility. The core light-emitting element of an AMOLED display is the organic light-emitting diode (OLED), which is a current-driven device whose brightness is precisely controlled by the current flowing through the driving thin-film transistor (TFT). Theoretically, under the same data voltage, each pixel should exhibit consistent brightness. However, in actual manufacturing and long-term operation, AMOLED display panels face serious image quality problems such as uneven brightness and image retention caused by the non-uniformity and drift of the electrical parameters of the driving TFT.

[0003] To overcome the threshold voltage drift problem of driving thin-film transistors, the industry has mainly developed two types of technical solutions: internal compensation pixel circuits and external compensation pixel circuits.

[0004] Internal compensation schemes are represented by the 7T1C structure, which integrates seven thin-film transistors and a storage capacitor within the pixel. Before emission, the threshold voltage is pre-stored in the gate-source capacitance of the driving transistor using diode connections or capacitive coupling. The compensation current formula for this scheme can be expressed as:

[0005] in, The luminous current of an organic light-emitting diode (OLED) For carrier mobility, The capacitance per unit area of ​​the gate oxide layer. To drive the aspect ratio of thin-film transistors, For data voltage, The reference voltage is used. Although this formula eliminates the threshold voltage term in form, this scheme has the following inherent limitations in practical applications: First, the range of threshold voltage drift that can be compensated is limited by the voltage swing of the storage capacitor and the charge injection effect of the switching transistor. When the threshold voltage drift is large... First, the compensation error increases rapidly to over 10%, leading to color cast at low grayscale levels. Second, the seven transistors and one capacitor occupy a large pixel area, significantly reducing the aperture ratio in products with a pixel density higher than 500 PPI, directly affecting the luminous lifespan and peak brightness of the organic light-emitting diode. Third, the above compensation formula still includes mobility. First, the mobility difference between different pixels can reach ±15%, which cannot be compensated, resulting in uneven brightness at high gray levels. Second, the solution cannot eliminate the hysteresis effect of driving thin-film transistors, which makes the current-voltage characteristic curve dependent on the historical bias state, producing visible dynamic afterimages in fast-moving scenes, with gray level differences of 3 to 5 gray levels.

[0006] External compensation schemes are typically represented by a 3T1C structure with an independent sensing line. This structure uses three thin-film transistors (TFTs) and a storage capacitor, with an additional sensing line independent of the data lines. The electrical parameters of the driving TFTs are routed to the driving circuit via this sensing line, where analog-to-digital conversion and compensation calculations are performed internally. While this scheme improves compensation accuracy, its most serious inherent problem lies in the parasitic capacitance in the sensing path. Unavoidable overlapping parasitic capacitance exists between the independent sensing line, the data lines, and the gate lines. This parasitic capacitance, together with the sensing line resistance, constitutes a low-pass filtering effect, with an equivalent time constant typically ranging from 3 to 5 microseconds. At a 120Hz refresh rate, the single-line scan cycle is only about 7.4 microseconds, and the sensing signal setup time requires 3 to 5 microseconds, occupying the majority of the line cycle. This makes it impossible to complete the entire sampling, calculation, and writing process within a single line cycle. Therefore, existing external compensation schemes can only employ a slower inter-frame compensation strategy and cannot achieve real-time line-by-line compensation. Furthermore, the independent sensing line occupies panel wiring space, increasing manufacturing complexity and the risk of line breakage. Meanwhile, parasitic capacitance on the data line leads to dynamic power consumption. As the refresh rate increases quadratically with the resolution, at 4K resolution and 240Hz refresh rate, the dynamic power consumption of the data drive circuit can reach 2 to 3 watts, becoming the main heat source of the display module.

[0007] In summary, existing organic light-emitting diode (OLED) driving technologies suffer from four interconnected and mutually restrictive technical drawbacks: the incompatibility between compensation capability and pixel complexity, the limitation of real-time compensation due to parasitic capacitance in the sensing path, motion blur caused by hysteresis, and significant dynamic power consumption at high refresh rates. Therefore, there is an urgent need in this field for a driving circuit and display device for OLED display panels that can simultaneously address the aforementioned problems. Summary of the Invention

[0008] The purpose of this invention is to provide a driving circuit, display panel, and display device for an organic light-emitting diode display panel, so as to solve the technical problems existing in the prior art, such as the inability to simultaneously achieve compensation capability and pixel complexity, the limitation of real-time compensation by parasitic capacitance of the sensing path, dynamic image retention caused by hysteresis effect, and the prominent dynamic power consumption at high refresh rates.

[0009] To achieve the above objectives, the present invention provides the following technical solution.

[0010] A driving circuit for an organic light-emitting diode display panel includes: a data line, a timing controller, a mode switching switch, and a mixed signal processor; Each of the data lines is connected to a column of pixel units in the pixel array of the display panel. The data lines have dual functions of shared data and sensing, and are time-division multiplexed in the time domain into voltage drive mode and current integration mode. In the voltage-driven mode, the compensation voltage is written into the storage capacitor in the pixel unit via the data line; In the current integration mode, the source current of the driving thin-film transistor of the pixel unit is integrated and measured through the data line; The timing controller is used to control the mode switching switch to switch the data line between voltage drive mode and current integration mode. The mixed signal processor is configured to perform the following steps: Step S1: In the first sampling phase, the first drain current of the driving thin-film transistor in the pixel unit under the first applied gate-source voltage is measured; Step S2: In the second sampling stage, the second drain current of the driving thin-film transistor in the pixel unit is measured under the second gate-source voltage; Step S3: Calculate the measured threshold voltage of the driving thin-film transistor using the dual-level integral ratio method.

[0011] Furthermore, the mixed signal processor uses the dual-level integral ratio method to calculate the measured threshold voltage of the driving thin-film transistor using the following formula:

[0012] in: The measured threshold voltage, The first applied gate-source voltage, For the second applied gate-source voltage, For the corresponding The measured drain current of the driving thin-film transistor, For the corresponding The measured drain current of the driving thin-film transistor.

[0013] Furthermore, the driving circuit also includes a current integration path, through which the drain current of the driving thin-film transistor under the gate-source voltage is measured.

[0014] Furthermore, the current integration path includes a transimpedance amplifier and an adjustable integrating capacitor; during the first sampling phase and the second sampling phase, the change in the output voltage of the transimpedance amplifier and the drain current of the driving thin-film transistor satisfy the following voltage-current relationship formula:

[0015] in: This represents the change in output voltage of the transimpedance amplifier. To drive the drain current of the thin-film transistor, For the integration time window, It is an adjustable integrating capacitor. The mixed signal processor is based on the measured voltage and current relationship formula. Reverse calculation of the drain current and .

[0016] Furthermore, the driving circuit also includes a voltage driving path, and the mixed signal processor is further configured to perform the following steps: Step S4: Based on the calculated measured threshold voltage, synthesize a compensation voltage, and output the compensation voltage to the data line through the voltage drive path during the data writing stage; Step S5: After calculating the measured threshold voltage, calculate the measured mobility of the driving thin-film transistor according to the following formula. :

[0017] in: This represents the measured mobility. The channel length of the driving thin-film transistor. To drive the gate oxide capacitance per unit area of ​​the thin-film transistor, The channel width of the driving thin-film transistor; Step S6: Synthesize the compensation voltage according to the following formula :

[0018] in: To compensate for the data voltage, The ideal data voltage corresponding to the target brightness. This is the threshold voltage compensation coefficient. The factory-calibrated reference threshold voltage, This is the mobility compensation coefficient. This is the factory-calibrated reference migration rate. Step S7: Introduce a temperature compensation term and synthesize the compensation voltage according to the following formula. :

[0019] in: This is the temperature compensation coefficient. The current temperature. For reference temperature; Step S8: Introduce an organic light-emitting diode aging compensation term for the pixel unit, and synthesize the compensation voltage according to the following formula. :

[0020] in: This is the aging compensation coefficient for organic light-emitting diodes. The aging factor for organic light-emitting diodes. For time.

[0021] Furthermore, the drive circuit is also configured to perform the following steps: Differential predictive coding is used to reduce dynamic power consumption during data drive. During the data writing phase, the actual voltage jump amplitude output by the voltage drive path is:

[0022] in: This represents the actual voltage jump amplitude. This is the current row compensation voltage. This is the predicted compensation voltage value from the previous row. For row number, The predicted value of the previous row compensation voltage is calculated based on the inter-frame variation trend of the previous row compensation voltage and the threshold voltage:

[0023] in: This is the compensation voltage for the previous line, in volts (V). The threshold voltage shows the inter-frame variation trend, and... The dynamic power consumption reduction ratio meets the following conditions:

[0024] in: For dynamic power consumption ratio, For mathematical expectation operators, This represents the voltage jump amplitude in the traditional solution.

[0025] Furthermore, the drive circuit is also configured to perform the following steps: Compensation sampling is performed at inter-frame intervals, with one frame designated as a compensation frame every 30 frames. In this compensation frame, steps S1 to S4 are performed on each row of pixels. Furthermore, if and only if the current frame is a normal frame, the measured threshold voltage calculated from the previous compensation frame is directly reused in the remaining 29 frames. and the measured mobility It only performs hysteresis elimination and data writing.

[0026] Furthermore, the signal establishment time of the data line in the current integration mode does not exceed 0.5 microseconds; and the maximum refresh rate supported by the driving circuit is not less than 120Hz only when the driving circuit is operating in the line-by-line real-time compensation mode.

[0027] The present invention also provides an organic light-emitting diode (OLED) display panel containing the aforementioned driving circuit, wherein each pixel unit in the pixel array includes: a driving thin-film transistor (TFT), a data writing transistor, a sensing control transistor, an anode reset transistor, and a storage capacitor; the drain of the driving TFT is connected to a first power supply voltage, and the source is connected to the lower end of the storage capacitor and the anode of the OLED device; the source of the data writing transistor is connected to the data line, the drain is connected to the gate of the driving TFT and the upper end of the storage capacitor, and the gate is connected to the nth row scan signal; the source of the sensing control transistor is connected to a reference voltage, the drain is connected to the source of the driving TFT, and the gate is connected to a sensing control signal; the source of the anode reset transistor is connected to a reset level, the drain is connected to the anode of the OLED device, and the gate is connected to a light emission control signal.

[0028] Compared with the prior art, the present invention has the following beneficial effects: First, this invention employs a shared data and sensing dual-function line architecture, integrating data writing and current sensing functions onto the same physical trace, physically eliminating the parasitic capacitance coupling path between the independent sensing line and data line in traditional external compensation schemes. The equivalent time constant of the sensing path is reduced from 3 to 5 microseconds in the prior art to less than 0.5 microseconds, and the establishment time of a single-line sensing signal does not exceed 1.0 microsecond. At a refresh rate of 120Hz, this invention can complete all stages of pre-reset, threshold voltage sampling, mobility sampling, compensation calculation, hysteresis elimination, data writing, and organic light-emitting diode emission within a single line cycle, achieving for the first time real-time line-by-line compensation of the electrical parameters of the driving thin-film transistor.

[0029] No separate sensing lines are required; all compensation sampling operations are completed through shared data and sensing dual-function lines. Compared to existing external compensation solutions, the number of traces on the panel is reduced by approximately 30%, lowering the wiring complexity and manufacturing cost of the display panel. Simultaneously, it reduces the risk of trace breakage due to bending in flexible display panels, improving product reliability.

[0030] Secondly, this invention employs a dual-level integral ratio method to determine the threshold voltage of the driving thin-film transistor. By measuring the current under two different gate-source voltages, the influence of process parameters such as mobility, oxide capacitance, and aspect ratio is eliminated through ratio calculation, directly obtaining the accurate value of the threshold voltage. Based on this method, this invention can accurately measure the threshold voltage drift. High linearity compensation within the range, with compensation error controlled within... Within. In contrast, existing internal compensation schemes can only compensate... And the compensation error is as high as Therefore, this invention effectively solves the technical defects of narrow compensation range and low compensation accuracy in the prior art.

[0031] Third, this invention employs a 4T1C compact pixel structure, requiring only four thin-film transistors and one storage capacitor to achieve dual-parameter compensation of threshold voltage and mobility. Compared to existing internal compensation schemes (7T1C), the number of transistors is reduced by 43%, significantly reducing pixel area occupancy. This is particularly beneficial at high pixel densities (PPI). In display products, the pixel aperture ratio can be increased to over 50%, thereby extending the luminous life of organic light-emitting diodes and increasing peak brightness.

[0032] Fourth, after obtaining the threshold voltage, this invention further solves for the mobility and incorporates the mobility compensation term into the compensation voltage calculation formula, which can eliminate mobility differences between different pixels (up to...). The effect on driving current. In high grayscale display scenarios, brightness uniformity is significantly improved, avoiding the high grayscale mura problem caused by the inability of existing internal compensation schemes to compensate for mobility.

[0033] Fifth, this invention introduces a temperature sensor and a temperature compensation coefficient. The current temperature information is dynamically incorporated into the compensation voltage calculation formula. to It can automatically compensate for changes in threshold voltage with temperature over a wide temperature range (typical value). to (mV / °C), maintaining the stability of compensation accuracy, overcoming the deficiency of existing technologies in lacking temperature adaptability.

[0034] Sixth, this invention calculates the aging factor by periodically detecting the equivalent resistance of organic light-emitting diode devices. Furthermore, by incorporating an aging compensation term into the compensation voltage calculation formula, this invention unifies the threshold drift compensation of the driving thin-film transistor and the luminous efficiency decay compensation of the organic light-emitting diode into the same mathematical model, avoiding the mismatch problem of compensation parameters caused by the separate treatment of the two in existing technologies. Even after prolonged use (e.g., 10,000 hours), this invention can still maintain more than 90% of the initial brightness level, and color deviation is minimal. .

[0035] Seventh, this invention employs differential predictive coding technology, utilizing the time correlation of compensation voltages between adjacent rows to predictively encode the data voltage before outputting it. The actual output voltage jump amplitude... Significantly smaller than traditional solutions Dynamic power consumption is proportional to the square of the voltage jump amplitude. This invention reduces the average voltage jump amplitude by more than 40%, thereby reducing dynamic power consumption by more than 40%. At 4K resolution and 240Hz refresh rate, the power consumption of the data drive circuit is reduced from 2 to 3 watts in the prior art to less than 1.5 watts, effectively alleviating the heat generation problem of the display module.

[0036] Eighth, the driving circuit of this invention supports configurable compensation frame intervals (typically 30 frames) and adjustable parameters such as integration time and hysteresis elimination time. In scenarios requiring high refresh rates, the integration time and hysteresis elimination time can be reduced, or the compensation frame interval can be increased, achieving a balance between compensation accuracy and refresh rate. This invention supports a maximum progressive real-time compensation refresh rate of not less than 120Hz and a maximum uncompensated frame refresh rate of not less than 200Hz.

[0037] Ninth, the present invention inserts a zero-bias relaxation stage before each frame of data is written, forcibly setting the gate-source voltage of the driving thin-film transistor to zero and maintaining it. (Typical value 3 microseconds) This invention utilizes the physical relaxation effect to erase interface trapping charges caused by historical bias, restoring the driving thin-film transistor to an electrically neutral state. Experiments show that, after adopting this invention, the dynamic image retention grayscale difference is reduced from 3 to 5 grayscale levels in the prior art to below 0.5 grayscale levels, essentially eliminating image retention in fast-moving scenes. Furthermore, this mechanism requires no additional transistors or complex timing, and can be implemented within a 4T1C structure. Attached Figure Description

[0038] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. It should be noted that the drawings are only schematic representations and are not drawn strictly according to actual dimensions and scale, wherein the same or similar reference numerals represent the same or similar elements.

[0039] Figure 1 is a system architecture block diagram of the organic light-emitting diode display panel provided in an embodiment of the present invention.

[0040] Figure 2 is a circuit structure diagram of a pixel unit provided in an embodiment of the present invention.

[0041] Figure 3 is a row scan timing diagram provided in an embodiment of the present invention.

[0042] The above-described drawings constitute a part of this specification and are used to explain and illustrate the technical solutions of this invention in conjunction with specific embodiments, rather than limiting the scope of protection of this invention.

[0043] The reference numerals in the attached figures are explained as follows: Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in further detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the scope of protection of the invention.

[0045] Example 1: Basic Structure and Function of Organic Light Emitting Diode Display Panel and its Driving Circuit Referring to Figure 1, this embodiment provides an organic light-emitting diode (OLED) display panel 10 and its driving circuit 200. The driving circuit 200 integrates a timing controller 250, a mode switching switch 210, a voltage driving path 220, a current integration path 230, and a mixed signal processor 240. The timing controller 250 outputs Scan[n], Sense[n], and Emit[n] signals and controls the mode switching switch 210 to switch the OLED between voltage driving mode, current integration mode, and reset mode. The driving circuit also includes several data lines, each corresponding to a column of pixel units in the pixel array of the display panel 10. These data lines have shared data and sensing functions, and are time-division multiplexed in the time domain for voltage driving mode and current integration mode, wherein: In the voltage-driven mode, the compensation voltage is written into the storage capacitor in the pixel unit via the data line; In the current integration mode, the source current of the driving thin-film transistor of the pixel unit is integrated and measured through the data line; The timing controller 250 is used to control the mode switching switch 210 to switch the data line between voltage drive mode and current integration mode. The mixed signal processor 240 is configured to perform the following steps: Step S1: In the first sampling phase, the first drain current of the driving thin-film transistor in the pixel unit under the first applied gate-source voltage is measured; Step S2: In the second sampling stage, the second drain current of the driving thin-film transistor in the pixel unit is measured under the second gate-source voltage; Step S3: Calculate the measured threshold voltage of the driving thin-film transistor using the dual-level integral ratio method, as shown in the following formula:

[0046] in: The measured threshold voltage is expressed in volts (V). The first applied gate-source voltage is expressed in volts (V). The second applied gate-source voltage, in volts (V), and , For the corresponding The measured drain current of the driving thin-film transistor is expressed in amperes (A). For the corresponding The measured drain current of the driving thin-film transistor is expressed in amperes (A).

[0047] The driving circuit 200 measures the gate-source voltage of the driving thin-film transistor through the current integration path 230. , Drain current , The current integration path includes a transimpedance amplifier and an adjustable integrating capacitor; during the first and second sampling phases, the change in the output voltage of the transimpedance amplifier and the drain current of the driving thin-film transistor satisfy the following voltage-current relationship formula:

[0048] in: This represents the change in output voltage of the transimpedance amplifier, expressed in volts (V). The drain current that drives the thin-film transistor is measured in amperes (A). This is the integration time window, measured in seconds (s). This is an adjustable integrating capacitor, measured in farads (F). Furthermore, the mixed signal processor, based on the voltage and current relationship formula, calculates the measured voltage and current. Reverse calculation of the drain current and .

[0049] The mixed signal processor is further configured to perform the following steps S4-S8: Step S4: Based on the calculated measured threshold voltage, synthesize a compensation voltage, and output the compensation voltage to the data line through the voltage drive path during the data writing stage; Step S5: After calculating the measured threshold voltage, calculate the measured mobility of the driving thin-film transistor according to the following formula. :

[0050] in: The measured mobility is expressed in square centimeters per volt-second (cm² / V·s). The channel length of the driving thin-film transistor is expressed in centimeters (cm). The capacitance per unit area of ​​the gate oxide layer driving a thin-film transistor is expressed in farads per square centimeter (F / cm²). The channel width of the driving thin-film transistor is expressed in centimeters (cm). Step S6: Synthesize the compensation voltage according to the following formula :

[0051] in: The voltage after compensation is expressed in volts (V). The ideal data voltage corresponding to the target brightness is expressed in volts (V). This is the threshold voltage compensation coefficient, dimensionless. The factory-calibrated reference threshold voltage is expressed in volts (V). This is the mobility compensation coefficient, dimensionless. The reference mobility is the factory calibration rate, and the unit is square centimeters per volt-second (cm² / V·s). Step S7: Introduce a temperature compensation term and synthesize the compensation voltage according to the following formula. :

[0052] in: This is the temperature compensation coefficient, measured in volts per degree Celsius (V / °C). The current temperature is in degrees Celsius (°C). This is a reference temperature, in degrees Celsius (°C). Step S8: Introduce an organic light-emitting diode aging compensation term for the pixel unit, and synthesize the compensation voltage according to the following formula. :

[0053] in: This is the aging compensation coefficient for organic light-emitting diodes, dimensionless. The aging factor for organic light-emitting diodes is dimensionless. Time is measured in seconds (s).

[0054] The driving circuit 200 is further configured to perform the following steps: perform compensation sampling at inter-frame intervals, setting one frame out of every 30 frames as a compensation frame, and performing steps S1 to S4 for each row of pixels in the compensation frame; and, if and only if the current frame is a normal frame, the remaining 29 frames directly reuse the calculated measured threshold voltage buffered in the previous compensation frame. and the measured mobility Only hysteresis cancellation and data writing are performed. The signal setup time of the data line in the current integration mode does not exceed 0.5 microseconds; and, only when the drive circuit operates in line-by-line real-time compensation mode, its maximum supported refresh rate is not less than 120Hz.

[0055] The display panel 10 is also equipped with a display array, which is a pixel array composed of M rows × N columns of pixel units, where M and N are both integers greater than 1. Each data column is configured with a shared data and sensing dual-function line (hereinafter referred to as DSL), which is time-division multiplexed in the time domain into voltage drive mode and current integration mode.

[0056] Referring to Figure 2, each pixel unit adopts a 4T1C structure, specifically including: a driving thin film transistor DTFT, a data writing transistor T1, a sensing control transistor T2, an anode reset transistor T3, and a storage capacitor Cst.

[0057] The connection relationships and functions of each transistor are described below: The drain of the driving thin-film transistor (DTFT) is connected to the first power supply voltage VDD (typically 5V), and the source is connected to the lower end of the storage capacitor Cst and the anode of the organic light-emitting diode (OLED) device. The DTFT is the core component of the pixel circuit, which generates the current that drives the OLED to emit light based on the gate-source voltage.

[0058] The source of the data writing transistor T1 is connected to the shared data and sensing dual-function line DSL, and the drain is connected to the gate of the driving thin-film transistor DTFT and the upper end of the storage capacitor Cst. The gate is connected to the nth row scan signal Scan[n]. T1 is used to control the writing of data voltage to the storage capacitor Cst.

[0059] The source of the sensing control transistor T2 is connected to the reference voltage. (Typical value 0V or 1V), the drain is connected to the source of the driving thin-film transistor DTFT, and the gate is connected to the nth row sensing control signal Sense[n]. T2 is used to lead the source current of the DTFT to DSL during the compensation sampling phase, or to connect the source of the DTFT to the reference potential during the hysteresis elimination phase.

[0060] The source of the anode reset transistor T3 is connected to the reset level. (Typical value -1V or 0V), the drain is connected to the anode of the organic light-emitting diode (OLED) device, and the gate is connected to the nth row light emission control signal Emit[n] (in this embodiment, Emit[n] is active high). T3 is used to clear the residual charge of the previous frame of the OLED anode during the pre-reset phase, or to cooperate with the OLED resistance measurement during the aging detection phase.

[0061] The upper end of the storage capacitor Cst is connected to the gate of the DTFT, and the lower end is connected to the source of the DTFT. Cst is used to maintain the gate-source voltage of the DTFT after data writing is completed, so that the OLED maintains a stable current during the light emission phase.

[0062] The timing controller outputs the Scan[n], Sense[n], and Emit[n] signals and controls the mode switch to switch the data line between three modes: voltage-driven mode, current-integrated mode, and reset mode. The timing controller is also configured to perform the following steps: Before the data writing phase of each frame, a hysteresis cancellation phase is inserted. In this hysteresis cancellation phase, the timing controller controls the Scan[n] signal and the Sense[n] signal to be high simultaneously, causing the data writing transistor and the sensing control transistor to be turned on simultaneously, and switching the data line to a reset mode with a zero potential, thereby reducing the gate-source voltage of the driving thin-film transistor. And the duration of maintaining this state The following conditions must be met:

[0063] in: The duration of the hysteresis elimination phase is expressed in microseconds (μs). The minimum hysteresis elimination time is expressed in microseconds (μs).

[0064] Further preferred minimum hysteresis elimination time The value of the hysteresis cancellation time is determined by the process characteristics of the driving thin-film transistor and ranges from 2 microseconds to 5 microseconds; furthermore, the hysteresis cancellation time is determined only if the current frame is a compensation frame. The value is 3 microseconds; the hysteresis cancellation time is 3 microseconds if and only if the current frame is a normal frame. The value is 2.5 microseconds.

[0065] This embodiment also provides an organic light-emitting diode display device, which includes the above-described driving circuit or display panel.

[0066] Example 2: Driving Method and Detailed Workflow This embodiment describes in detail the driving method based on the above-described organic light-emitting diode display panel. The method is organized in a frame-level pipeline manner, with different processes executed within each frame period depending on whether it is a compensation frame.

[0067] (I) Overall Process Referring to the row scan timing diagram in Figure 3, the system executes the following six stages sequentially within one row cycle: pre-reset stage, compensation sampling stage (including threshold voltage sampling and mobility sampling), compensation calculation stage, hysteresis elimination stage, data writing stage, and organic light-emitting diode emission stage.

[0068] (II) Detailed Process of Compensation Frame Single Line The following describes the single-line processing flow in detail, taking the compensation frame (1 frame out of every 30 frames) as an example. In this embodiment, it is assumed that the current processing line is row 'row', and the parameters are taken with typical values.

[0069] Step 1: Pre-reset phase (t = 0 ~ 1.0 μs) The timing controller 250 outputs Emit[row]=1 (high level), Scan[row]=0, and Sense[row]=0. Transistor T3 is turned on, and the OLED anode is connected to... The potential (-1V in this embodiment) is used to clear the residual charge on the OLED anode after the previous frame ends. The DSL is in a high-resistivity state. This stage lasts for [duration missing]. .

[0070] Step 2: Threshold voltage sampling phase (t = 1.0 ~ 1.8 μs) The timing controller 250 outputs Sense[row]=1, turning on transistor T2. The mixed-signal processor 240 sets the first gate-source voltage. The current is applied to the gate of the DTFT. The mode switch 210 switches the DSL to current integration mode and is connected to the input of the transimpedance amplifier TIA 230.

[0071] The TIA 230 integrates the source current of the DTFT, and the integrating capacitor... Integral time Record the change in TIA output voltage. .

[0072] According to Formula 7 above, the DTFT current... Calculated by the following formula:

[0073] in, The first measurement shows the drain current of the DTFT (in A). The change in output voltage of the TIA during the first integration (unit: V). The integrating capacitor (unit: F). This is the first integration time window (unit: seconds). In this embodiment, , , Calculated .Will Stored in the registers of the mixed signal processor 240.

[0074] Step 3: Mobility sampling phase (t = 1.8 ~ 2.6 μs) Sense[row] remains 1, and T2 remains on. The mixed-signal processor 240 sets the second gate-source voltage. The TIA 230 is applied to the DTFT gate. The integration time is... ,Record Similarly, calculate according to Formula 7. :

[0075] In this embodiment, Calculated .Will Stored in the registers of the mixed signal processor 240.

[0076] Step 4: Compensation Solution Stage (t = 2.6 ~ 3.8 μs) This phase executes in parallel with the pre-reset phase of the next row, without consuming additional row time. Scan[row]=0, Sense[row]=0, Emit[row]=0, all TFTs are turned off. DSL switches to internal processing mode. Mixed signal processor 240 executes the following calculation sub-steps.

[0077] Sub-step 4.1: Calculate the measured threshold voltage The dual-level integral ratio method using Formula 1 above is adopted:

[0078] in, , , , Calculated:

[0079] Sub-step 4.2: Calculate the measured mobility Formula 2 above is used:

[0080] in, Carrier mobility (unit: cm² / V·s) The length of the DTFT channel is in cm. DTFT channel width (unit: cm). This refers to the capacitance per unit area of ​​the gate oxide layer (unit: F / cm²). In this embodiment, (4μm) (8μm) Calculated:

[0081] Sub-step 4.3: Synthesize the compensation voltage This embodiment uses Formula 3 above, which includes threshold compensation and mobility compensation:

[0082] in, The final compensated data voltage (unit: V) is written. The ideal data voltage (unit: V) corresponds to the target brightness. This is the threshold voltage compensation coefficient (dimensionless). The measured threshold voltage (unit: V) The factory-calibrated reference threshold voltage (unit: V). This is the mobility compensation coefficient (dimensionless). The migration rate is the factory-calibrated reference rate (unit: cm² / V·s). The measured mobility is expressed in cm² / V·s. In this embodiment, , , , , , Calculations show that:

[0083] Will Store it in the row buffer for use in step 6.

[0084] Step 5: Hysteresis elimination phase (t = 3.8 ~ 6.8 μs) The timing controller 250 outputs Scan[row]=1, Sense[row]=1, and Emit[row]=0. Transistors T1 and T2 are simultaneously turned on. The mode switch 210 switches DSL to reset mode, outputting 0V. The gate of the DTFT is connected to DSL=0V through T1, and the source is connected to Vref≈0V through T2. Therefore, the gate-source voltage of the DTFT is... Maintain this state. .

[0085] The conditions for hysteresis elimination are:

[0086] in, The duration of the relaxation phase (in μs). This is the minimum hysteresis elimination time (unit: μs). In this embodiment, , When the conditions are met, the hysteresis effect is effectively eliminated.

[0087] Step 6: Data writing phase (t = 6.8 ~ 8.3 μs) The timing controller 250 outputs Scan[row]=1, Sense[row]=0, and Emit[row]=0. Transistor T1 is turned on, and T2 and T3 are turned off. The mode switch 210 switches the DSL to voltage drive mode and is connected to the output of the voltage drive path 220. The voltage drive path 220 outputs a compensation voltage. To DSL. The storage capacitor Cst is charged via T1, and the DTFT gate voltage stabilizes at 3.8767V. This phase continues. .

[0088] This invention employs differential predictive coding to reduce data-driven dynamic power consumption, and the actual voltage jump amplitude output by the voltage drive path 220 is... Given by the following formula:

[0089] in: This represents the actual voltage jump amplitude, measured in volts (V). This is the current line compensation voltage, in volts (V). This is the predicted compensation voltage value from the previous row, in volts (V). The row number is a positive integer. Among them, the predicted value of the compensation voltage in the previous row Calculated based on the inter-frame variation trend of the compensation voltage and threshold voltage in the previous row:

[0090] in: This is the compensation voltage for the previous line, in volts (V). The threshold voltage shows the inter-frame variation trend, with the unit being volts (V). Furthermore, the dynamic power consumption reduction ratio meets the following conditions:

[0091] in: The dynamic power consumption ratio is dimensionless. For mathematical expectation operators, The data voltage jump amplitude in the traditional scheme is expressed in volts (V).

[0092] Specifically, in this embodiment, the actual voltage jump amplitude It can be represented as:

[0093] in, This is the current row compensation voltage. This is the predicted compensation voltage value from the previous row. Assume the compensation voltage from the previous row... Threshold voltage variation trend Then the predicted value , The jump amplitude of the traditional solution The voltage is approximately 0.5~1.0V, and the power consumption is significantly reduced in this embodiment.

[0094] Step 7: Organic Light Emitting Diode (OLED) emission phase (t = 8.3μs to pre-reset of the next frame) The timing controller 250 outputs Scan[row]=0, Sense[row]=0, and Emit[row]=0. Transistors T1, T2, and T3 are all turned off. DSL switches to a high-impedance state. The storage capacitor Cst maintains the gate voltage of the DTFT at [value missing]. The DTFT generates a driving current based on the gate-source voltage, which flows through the OLED to make it emit light.

[0095] The drive current is determined by the following formula:

[0096] Calculate the OLED driving current in this embodiment:

[0097] The current is consistent with the ideal current corresponding to the target brightness, indicating that the compensation is effective.

[0098] (III) Simplified Procedure for Ordinary Frames Normal frames (the remaining 29 frames out of every 30 frames) are not sampled and calculated in real time; the threshold voltage buffered in the previous compensation frame is directly reused. and mobility The process is simplified to: Step 1: Pre-reset stage ( ).

[0099] Step 2: Rapid Hysteresis Elimination Phase ( ).

[0100] Step 3: Data writing stage ( ), calculate using cached compensation parameters .

[0101] Step 4: Organic light-emitting diode (OLED) emission stage.

[0102] The total time for a single line of a normal frame is approximately 5.0μs, and higher refresh rates (≥200Hz) are supported.

[0103] (iv) Special process for aging test frames An aging detection frame is executed every 1000 frames. Based on the compensation frame process, after step 3 (μ sampling) and before step 4 (compensation calculation), the following additional steps 3A to 3C are inserted.

[0104] Additional step 3A: Preparation for aging factor detection of organic light-emitting diodes (t = 2.6 ~ 2.8 μs) The timing controller outputs Sense[row]=1 and Emit[row]=1, turning on T2 and T3. DSL switches to current integration mode.

[0105] Additional step 3B: Leakage current measurement (t = 2.8 ~ 3.4 μs) Apply test voltage Leakage current is measured through a current integration path. In this embodiment, it is assumed that... .

[0106] Additional step 3C: Aging factor update (t = 3.4 ~ 3.8 μs, in parallel with compensation solution) Calculate and update the aging factor according to Formulas 11 and 12 above. :

[0107]

[0108] renew The data is transferred to a register for use in Formula 5 in subsequent step 4 (compensation solution).

[0109] Step 4: Compensation calculation (executed in parallel with the above additional step 3C, t = 2.6 ~ 3.8 μs) During the compensation calculation phase, the mixed signal processor simultaneously reads the updated aging factor. Formula 5 is used to synthesize a compensation voltage that includes an aging compensation term.

[0110]

[0111] in The aging compensation factor for organic light-emitting diodes is set to 0.2 in this embodiment. After compensation The corresponding increase.

[0112] III. Example 3: Parameter Configuration and Performance Optimization This embodiment provides parameter configuration schemes for different application scenarios.

[0113] (a) High refresh rate scenario (240Hz)

[0114] (ii) Ultra-high resolution scene (4K@120Hz)

[0115] (III) Low power consumption scenario (60Hz)

[0116] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A driving circuit for an organic light-emitting diode (OLED) display panel, characterized in that, include: Data cable, timing controller, mode switch, and mixed signal processor; Each of the data lines is connected to a column of pixel units in the pixel array of the display panel. The data lines have dual functions of shared data and sensing, and are time-division multiplexed in the time domain into voltage drive mode and current integration mode. In the voltage-driven mode, the compensation voltage is written into the storage capacitor in the pixel unit via the data line; In the current integration mode, the source current of the driving thin-film transistor of the pixel unit is integrated and measured through the data line; The timing controller is used to control the mode switching switch to switch the data line between voltage drive mode and current integration mode. The mixed signal processor is configured to perform the following steps: Step S1: In the first sampling phase, the first drain current of the driving thin-film transistor in the pixel unit under the first applied gate-source voltage is measured; Step S2: In the second sampling stage, the second drain current of the driving thin-film transistor in the pixel unit is measured under the second gate-source voltage; Step S3: Calculate the measured threshold voltage of the driving thin-film transistor using the dual-level integral ratio method.

2. The driving circuit for the organic light-emitting diode display panel according to claim 1, characterized in that, The mixed signal processor uses the following formula to calculate the measured threshold voltage of the driving thin-film transistor using the dual-level integral ratio method: ； in: For the measured threshold voltage, The first applied gate-source voltage, For the second applied gate-source voltage, For the corresponding The measured drain current of the driving thin-film transistor, For the corresponding The measured drain current of the driving thin-film transistor.

3. The driving circuit for the organic light-emitting diode display panel according to claim 1 or 2, characterized in that, The driving circuit also includes a current integration path, through which the drain current of the driving thin-film transistor under the gate-source voltage is measured.

4. The driving circuit for the organic light-emitting diode display panel according to claim 3, characterized in that, The current integration path includes a transimpedance amplifier and an adjustable integrating capacitor; during the first sampling phase and the second sampling phase, the change in the output voltage of the transimpedance amplifier and the drain current of the driving thin-film transistor satisfy the following voltage-current relationship formula: ； in: This represents the change in output voltage of the transimpedance amplifier. To drive the drain current of the thin-film transistor, For the integration time window, It is an adjustable integrating capacitor. The mixed signal processor is based on the measured voltage and current relationship formula. Reverse calculation of the drain current and .

5. The driving circuit for an organic light-emitting diode display panel according to claim 1 or 2, characterized in that, The driving circuit further includes a voltage driving path, and the mixed signal processor is further configured to perform the following steps: Step S4: Based on the calculated measured threshold voltage, synthesize a compensation voltage, and output the compensation voltage to the data line through the voltage drive path during the data writing stage; Step S5: After calculating the measured threshold voltage, calculate the measured mobility of the driving thin-film transistor according to the following formula. : ； in: This represents the measured mobility. The channel length of the driving thin-film transistor. To drive the gate oxide capacitance per unit area of ​​the thin-film transistor, The channel width of the driving thin-film transistor; Step S6: Synthesize the compensation voltage according to the following formula : ； in: To compensate for the data voltage, The ideal data voltage corresponding to the target brightness. This is the threshold voltage compensation coefficient. The factory-calibrated reference threshold voltage, This is the mobility compensation coefficient. This is the factory-calibrated reference migration rate. Step S7: Introduce a temperature compensation term and synthesize the compensation voltage according to the following formula. : ； in: This is the temperature compensation coefficient. The current temperature. For reference temperature; Step S8: Introduce an organic light-emitting diode aging compensation term for the pixel unit, and synthesize the compensation voltage according to the following formula. : ； in: This is the aging compensation coefficient for organic light-emitting diodes. The aging factor for organic light-emitting diodes. For time.

6. The driving circuit for the organic light-emitting diode display panel according to claim 5, characterized in that, The drive circuit is also configured to perform the following steps: Differential predictive coding is used to reduce dynamic power consumption during data drive. During the data writing phase, the actual voltage jump amplitude output by the voltage drive path is: ； in: This represents the actual voltage jump amplitude. This is the current row compensation voltage. This is the predicted compensation voltage value from the previous row. For row number, The predicted value of the previous row compensation voltage is calculated based on the inter-frame variation trend of the previous row compensation voltage and the threshold voltage: ； in: This is the compensation voltage for the previous line, in volts (V). The threshold voltage shows the inter-frame variation trend, and... The dynamic power consumption reduction ratio meets the following conditions: ； in: For dynamic power consumption ratio, For mathematical expectation operators, This represents the voltage jump amplitude in the traditional solution.

7. The driving circuit for the organic light-emitting diode display panel according to claim 6, characterized in that, The drive circuit is also configured to perform the following steps: Compensation sampling is performed at inter-frame intervals, with one frame designated as a compensation frame every 30 frames. In this compensation frame, steps S1 to S4 are performed on each row of pixels. Furthermore, if and only if the current frame is a normal frame, the measured threshold voltage calculated from the previous compensation frame is directly reused in the remaining 29 frames. and the measured mobility It only performs hysteresis elimination and data writing.

8. The driving circuit for the organic light-emitting diode display panel according to claim 1, characterized in that, The signal establishment time of the data line in the current integration mode shall not exceed 0.5 microseconds; and the maximum refresh rate supported by the driving circuit shall not be less than 120Hz if and only if the driving circuit is operating in the line-by-line real-time compensation mode.

9. An organic light-emitting diode display panel, comprising the driving circuit according to any one of claims 1-8, characterized in that, Each pixel unit in the pixel array includes: a driving thin-film transistor, a data writing transistor, a sensing control transistor, an anode reset transistor, and a storage capacitor; the drain of the driving thin-film transistor is connected to a first power supply voltage, and the source is connected to the lower end of the storage capacitor and the anode of the organic light-emitting diode (OLED); the source of the data writing transistor is connected to the data line, the drain is connected to the gate of the driving thin-film transistor and the upper end of the storage capacitor, and the gate is connected to the nth row scan signal; the source of the sensing control transistor is connected to a reference voltage, the drain is connected to the source of the driving thin-film transistor, and the gate is connected to a sensing control signal; the source of the anode reset transistor is connected to a reset level, the drain is connected to the anode of the OLED, and the gate is connected to a light emission control signal.

10. An organic light-emitting diode display device, characterized in that, Includes the display panel as described in claim 9.

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