Sub-pixel, display device including the same, electronic device including the same, and driving method of the electronic device

Abstract

A sub-pixel, a display device including the same, an electronic device including the same, and a driving method of the electronic device are provided. The sub-pixel includes a first capacitor maintaining a potential difference between a first node and a third node, a second capacitor maintaining a potential difference between a second node and a power line to which a constant voltage is applied, and a third capacitor maintaining a potential difference between the first node and the second node.

Description

[0001] This application claims priority to and all benefits arising therefrom of Korean Patent Application No. 10-2025-0005437, filed on January 14, 2025, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The disclosed embodiments relate to a sub-pixel, a display device including the sub-pixel, an electronic device including the display device, and a driving method for the electronic device. Background Technology

[0003] With the development of information technology, the importance of display devices as the connection medium between users and information is becoming increasingly prominent. Therefore, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) is increasing.

[0004] Display devices can display images of varying brightness by allowing an appropriate amount of drive current to flow through the light-emitting elements within the device. Easier control over the magnitude of the drive current improves visibility. Summary of the Invention

[0005] The technical problem to be solved is to provide a sub-pixel whose driving current can be easily controlled, a display device including the sub-pixel, an electronic device including the display device, and a driving method for the electronic device.

[0006] In the disclosed embodiments, the sub-pixel includes: a first transistor including a gate electrode electrically connected to a first node, the first transistor being connected between a second node and a third node, the third node being electrically connected to a first power line; a light-emitting element connected between the second node and the second power line; a second transistor switching the electrical connection between the first node and a data line; a third transistor switching the electrical connection between the second node and the third power line; a fourth transistor switching the electrical connection between the first power line and the third node; a first capacitor maintaining the potential difference between the first node and the third node; a second capacitor maintaining the potential difference between the second node and a power line to which a constant voltage is applied; and a third capacitor maintaining the potential difference between the first node and the second node.

[0007] In one embodiment, the second capacitor may include a first electrode electrically connected to the second node and a second electrode electrically connected to a power line to which a constant voltage is applied.

[0008] In this embodiment, a second power supply voltage may be applied to a second power line. A constant voltage may be the same as the second power supply voltage.

[0009] In this embodiment, a third power supply voltage may be applied to a third power line. A constant voltage may be the same as the third power supply voltage.

[0010] In an embodiment, the electric field line to which a constant voltage is applied may be different from the first, second, and third electric field lines.

[0011] In an embodiment, the first electrode of the second capacitor and the second electrode of the second capacitor can be disposed on the same layer.

[0012] In an embodiment, the capacitance of the second capacitor may be greater than the capacitance between the anode and cathode electrodes of the light-emitting element.

[0013] In this embodiment, the first transistor, the second transistor, and the fourth transistor may include P-type semiconductors. The third transistor may include N-type semiconductors.

[0014] In this embodiment, a first power supply voltage may be applied to a first power line. A third power supply voltage may be applied to a third power line. The first power supply voltage may be applied to the respective body electrodes of the first transistor, the second transistor, and the fourth transistor. The third power supply voltage may be applied to the body electrode of the third transistor.

[0015] In the disclosed embodiments, the display device includes: a display panel having a plurality of sub-pixels disposed therein, and a plurality of data lines, a plurality of first gate lines, a plurality of second gate lines, and a plurality of light emission control lines electrically connected to the plurality of sub-pixels disposed therein; a data driver supplying data voltage to the plurality of data lines; and a gate drive circuit supplying signals to the plurality of first gate lines, the plurality of second gate lines, and the plurality of light emission control lines, wherein at least one of the plurality of sub-pixels includes: a first transistor including a gate electrode electrically connected to a first node, the first transistor being connected between a second node and a third node, the third node being electrically connected to a first power line; a light-emitting element connected between the second node and the second power line; a second transistor switching the electrical connection between the first node and a corresponding data line among the plurality of data lines; a third transistor switching the electrical connection between the second node and the third power line; a fourth transistor switching the electrical connection between the first power line and the third node; a first capacitor maintaining a potential difference between the first node and the third node; a second capacitor maintaining a potential difference between the second node and a power line to which a constant voltage is applied; and a third capacitor maintaining a potential difference between the first node and the second node.

[0016] In one embodiment, the second transistor may include a gate electrode electrically connected to a corresponding first gate line among a plurality of first gate lines.

[0017] In one embodiment, the second transistor may be turned on in response to a first scan signal having a low level applied to the gate electrode.

[0018] In one embodiment, the third transistor may include a gate electrode electrically connected to a corresponding second gate line among a plurality of second gate lines.

[0019] In one embodiment, the third transistor may be turned on in response to a second scan signal having a high level applied to the gate electrode.

[0020] In the disclosed embodiments, the electronic device includes: a processor for outputting input image data; a controller for converting the input image data to output image data; a display panel having a plurality of sub-pixels disposed therein, and having a plurality of data lines, a plurality of first gate lines, a plurality of second gate lines, and a plurality of light emission control lines electrically connected to the plurality of sub-pixels disposed therein; a data driver for supplying a data voltage corresponding to the image data to the plurality of data lines; and a gate driving circuit for supplying signals to the plurality of first gate lines, the plurality of second gate lines, and the plurality of light emission control lines, wherein at least one of the plurality of sub-pixels includes: a first transistor, including a transistor electrically connected to a first node. A gate electrode; a first transistor connected between a second node and a third node, the third node being electrically connected to a first power line; a light-emitting element connected between the second node and the second power line; a second transistor switching the electrical connection between the first node and a corresponding data line among multiple data lines; a third transistor switching the electrical connection between the second node and the third power line; a fourth transistor switching the electrical connection between the first power line and the third node; a first capacitor maintaining the potential difference between the first node and the third node; a second capacitor maintaining the potential difference between the second node and a power line to which a constant voltage is applied; and a third capacitor maintaining the potential difference between the first node and the second node.

[0021] In one embodiment, the controller may generate image data based on the capacitance of the first capacitor and the capacitance of the third capacitor.

[0022] In a disclosed embodiment, a method for driving an electronic device including a first transistor and a light-emitting element electrically connected to the first transistor is provided. The method includes the steps of: applying a data voltage to a first electrode of a first capacitor electrically connected to the gate electrode of the first transistor, and applying a first power supply voltage to a second electrode of the first capacitor electrically connected to the source electrode of the first transistor; applying a data voltage to the gate electrode of the first transistor and storing a first threshold voltage of the first transistor in the first capacitor; applying the first power supply voltage to a second electrode of a second capacitor; and reflecting the voltage fluctuation of the second electrode of the first capacitor to the first electrode at a ratio corresponding to the capacitance of the first capacitor; and causing voltage fluctuation of a second electrode of a third capacitor electrically connected to the drain electrode of the first transistor by a drive current flowing through the first transistor, and reflecting the voltage fluctuation of the second electrode of the third capacitor to the first electrode of the third capacitor at a ratio corresponding to the capacitance of the third capacitor, wherein the first electrode of the third capacitor is electrically connected to the gate electrode of the first transistor.

[0023] In one embodiment, the ratio corresponding to the capacitance of the first capacitor can be calculated by dividing the capacitance of the first capacitor by the value obtained by adding the capacitances of the first capacitor and the third capacitor.

[0024] In one embodiment, the ratio corresponding to the capacitance of the third capacitor can be calculated by dividing the capacitance of the third capacitor by the value obtained by adding the capacitances of the first capacitor and the third capacitor.

[0025] In one embodiment, the electronic device may further include a second capacitor, which includes a first electrode electrically connected to the drain electrode of the first transistor and a second electrode to which a constant voltage is applied. A ripple voltage may be applied to the first electrode of the second capacitor to reflect the voltage fluctuation of the second electrode of the first capacitor in the first electrode in a ratio corresponding to the capacitance of the first capacitor. Attached Figure Description

[0026] The above and other features will become more apparent from the description of the disclosed embodiments with reference to the accompanying drawings.

[0027] Figure 1 This is a system block diagram based on an embodiment of a disclosed display device.

[0028] Figure 2 It is shown Figure 1 A block diagram of an embodiment of any of the sub-pixels.

[0029] Figure 3 This is an equivalent circuit diagram based on a disclosed embodiment of a subpixel.

[0030] Figure 4 This is an equivalent circuit diagram based on a disclosed embodiment of a subpixel.

[0031] Figure 5 This is an equivalent circuit diagram based on a disclosed embodiment of a subpixel.

[0032] Figure 6 This is an embodiment of the first capacitor.

[0033] Figure 7 This is an embodiment of the second capacitor.

[0034] Figure 8 This is an embodiment of the disclosed subpixel driving method.

[0035] Figures 9 to 12 It is used for explanation Figure 8 About Figure 3 A diagram of the driving method for sub-pixels.

[0036] Figure 13This is an embodiment of the disclosed subpixel driving method.

[0037] Figures 14 to 17 It is used for explanation Figure 13 About Figure 3 A diagram of the driving method for sub-pixels.

[0038] Figure 18 It is shown Figure 1 A plan view of an embodiment of the display panel.

[0039] Figure 19 It is shown Figure 18 An exploded perspective view of a portion of the display panel.

[0040] Figure 20 It is shown Figure 19 A plan view of any one of the pixels in the embodiment.

[0041] Figure 21 It is based on the publicly available information along Figure 20 A cross-sectional view taken along line I-I' of an embodiment.

[0042] Figure 22 It is based on the publicly available information along Figure 20 A cross-sectional view taken along line I-I' of an embodiment.

[0043] Figure 23 It is shown Figure 22 A magnified view of region A.

[0044] Figure 24 It is shown that it includes Figure 21 The first light-emitting element to the third light-emitting element and Figure 22 A cross-sectional view of an embodiment of a portion of the light-emitting structure in any one of the first to third light-emitting elements.

[0045] Figure 25 It is shown that it includes Figure 21 The first light-emitting element to the third light-emitting element and Figure 22 A cross-sectional view of another embodiment of a portion of the light-emitting structure in any one of the first to third light-emitting elements.

[0046] Figure 26 It is shown Figure 19 A plan view of another embodiment of any of the pixels.

[0047] Figure 27 It is shown Figure 19 A plan view of another embodiment of any of the pixels.

[0048] Figure 28 This is a block diagram illustrating an embodiment of the display system.

[0049] Figure 29 It is shown Figure 28 A perspective view of an embodiment of the application of the display system.

[0050] Figure 30 It shows the product worn by the user. Figure 29 A diagram of a head-mounted display device. Detailed Implementation

[0051] In the following, various embodiments of the disclosure will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement these embodiments. The disclosure may be implemented in many different forms and is not limited to the embodiments described herein.

[0052] To ensure clarity of the disclosure, parts irrelevant to the description may be omitted, and throughout the specification, identical or similar components are indicated by the same reference numerals. Therefore, the aforementioned reference numerals may also be used in other figures.

[0053] Furthermore, for ease of description, the dimensions and thicknesses of each component shown in the figures are arbitrarily illustrated; therefore, the disclosure is not limited to what is shown. Thicknesses may be exaggerated to clearly represent multiple layers and regions in the figures.

[0054] Furthermore, the term "identical" in the instruction manual can mean "substantially identical." In other words, it can mean sufficiently identical that a person with ordinary knowledge can understand that they are the same. Other expressions may omit the word "substantially."

[0055] The terms first, second, etc., can be used to describe various components, but components should not be limited by the terms. The terms above are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of disclosure, a first component can be named a second component, and similarly, a second component can be named a first component. Unless the context clearly requires otherwise, the singular forms “a,” “an,” and “the” include plural references.

[0056] The terms "below," "under," "above," and "on" are used to describe the relationship between the components shown in the accompanying drawings. These terms are relative concepts and are interpreted with reference to the directions indicated in the drawings.

[0057] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0058] It will be understood that the terms “comprising” or “having” are intended to specify the presence of the features, quantities, steps, operations, components, parts or combinations thereof described in the specification, and do not exclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof.

[0059] The disclosed embodiments will be described in detail below with reference to the accompanying drawings.

[0060] Figure 1 This is a system block diagram based on an embodiment of the disclosed display device 100.

[0061] Reference Figure 1 The display device 100 in the disclosed embodiments may include a display panel 110, a gate driving circuit 120, a data driver 130, a voltage generator 140, a controller 150, and a temperature sensor 160, etc.

[0062] The display panel 110 may include a plurality of sub-pixels SP. First gate lines GL1 to m-th gate lines GLm (where m is an integer of 2 or greater) connected to the plurality of sub-pixels SP may be provided in the display panel 110. First data lines DL1 to n-th data lines DLn (where n is an integer of 2 or greater) connected to the plurality of sub-pixels SP may be provided in the display panel 110.

[0063] Multiple sub-pixels SP can be connected to the gate driving circuit 120 via the first gate line GL1 to the m-th gate line GLm. Multiple sub-pixels SP can be connected to the data driver 130 via the first data line DL1 to the n-th data line DLn.

[0064] Each of the plurality of sub-pixels SP may include at least one light-emitting element for generating light. Each of the plurality of sub-pixels SP may generate light of a color such as red, green, blue, cyan, magenta, yellow, etc. (e.g., a specific color or a specific wavelength). Two or more sub-pixels of the plurality of sub-pixels SP may constitute a pixel PXL. In an embodiment, as... Figure 1 As shown, for example, three sub-pixels can form a pixel PXL.

[0065] The gate driving circuit 120 can be connected to a plurality of sub-pixels SP (e.g., a plurality of sub-pixels SP arranged as a whole on a first direction DR1) via each of the first gate lines GL1 to the m-th gate line GLm. For example, the first direction DR1 can be a direction from one side of the display panel 110 to the opposite side (e.g., from left to right). For example, the first direction DR1 can be a row direction.

[0066] The gate drive circuit 120 can output a gate signal (e.g., a gate signal at an on or off level) to the first gate line GL1 through the m-th gate line GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame and a horizontal synchronization signal for outputting the gate signal in timing synchronization with the applied data signal.

[0067] In an embodiment, first light emission control lines EL1 to m-th light emission control lines ELm, connected to multiple sub-pixels SP, may also be disposed in the display panel 110. The first light emission control lines EL1 to m-th light emission control lines ELm may be arranged to extend in the row direction within the display panel 110. Multiple sub-pixels SP may be connected to the first light emission control lines (also referred to as emission control lines) EL1 to m-th light emission control lines ELm. In the above embodiment, the gate driving circuit 120 may include a light emission control driver that controls the first light emission control lines EL1 to m-th light emission control lines ELm. The light emission control driver may operate under the control of the controller 150.

[0068] The gate driving circuit 120 may be disposed on one side of the display panel 110. However, the embodiments are not limited thereto. In embodiments, for example, the gate driving circuit 120 may be divided into two or more driving circuits that are physically and / or logically separated, and such driving circuits may be disposed on one side and opposite sides of the display panel 110 (e.g., the opposite side of the display panel 110 to said side). Thus, the gate driving circuit 120 may be disposed in various forms within the display panel 110 or in the periphery of the display panel 110.

[0069] The data driver 130 can be connected to a plurality of sub-pixels SP (e.g., a plurality of sub-pixels SP arranged as a whole on a second direction DR2) via each of the first data lines DL1 to the nth data line DLn. For example, the second direction DR2 can be a direction from one side (e.g., the lower side) of the display panel 110 to the opposite side (e.g., the upper side). For example, the second direction DR2 can be a column direction.

[0070] The data driver 130 can receive image data DATA and data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0071] The data driver 130 can apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn using a voltage (e.g., a gamma voltage Vgamma) from the voltage generator 140. When a gate signal (e.g., an on-level gate signal) is applied to each of the first gate lines GL1 to the mth gate line GLm, the data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLn. In response to the gate signal (e.g., a gate signal at an on-level), each of the plurality of sub-pixels SP can receive the data signal applied in a corresponding timing sequence. The plurality of sub-pixels SP can generate light corresponding to the received data signal. Therefore, an image can be displayed on the display panel 110.

[0072] In an embodiment, the gate drive circuit 120 and the data driver 130 may each include complementary metal-oxide-semiconductor (“CMOS”) circuit elements.

[0073] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 can generate multiple voltages and provide the generated voltages to components of display device 100. In an embodiment, for example, voltage generator 140 can receive an input voltage from outside display device 100. Voltage generator 140 can adjust (e.g., reduce) the level of the received voltage and regulate the adjusted voltage. Voltage generator 140 can generate multiple voltages.

[0074] Voltage generator 140 can generate, for example, a first power supply voltage VDD, a second power supply voltage VSS, and a gamma voltage Vgamma. The generated first power supply voltage VDD and second power supply voltage VSS can be applied (e.g., applied commonly) to a plurality of sub-pixels SP. The first power supply voltage VDD can have a relatively high voltage level. The second power supply voltage VSS can have a lower voltage level than the first power supply voltage VDD. The generated gamma voltage Vgamma can be provided to data driver 130. In some other embodiments, the first power supply voltage VDD and / or the second power supply voltage VSS can be provided by an external device of display device 100 (e.g., a power management integrated circuit (“PMIC”)).

[0075] According to embodiments, voltage generator 140 can generate different voltages. In one embodiment, for example, voltage generator 140 can generate an initialization voltage that is applied (e.g., commonly applied) to multiple sub-pixels SP. In another embodiment, for example, during a sensing operation that senses the electrical characteristics of the light-emitting elements and / or transistors of multiple sub-pixels SP, a preset reference voltage can be applied to the first data lines DL1 to the nth data lines DLn, and voltage generator 140 can generate such a reference voltage.

[0076] The controller 150 can control various operations of the display device 100. The controller 150 can receive input image data IMG and control signals CTRL for controlling its display from the outside. In response to the received control signals CTRL, the controller 150 can provide gate control signals GCS, data control signals DCS, and voltage control signals VCS, etc.

[0077] The controller 150 can output image data DATA by converting the input image data IMG into a format suitable for the display device 100 or display panel 110. In one embodiment, the controller 150 can output image data DATA by aligning the input image data IMG into rows of sub-pixels SP.

[0078] Two or more components of the data driver 130, voltage generator 140, and controller 150 can be configured (e.g., mounted) in a single integrated circuit. Figure 1 As shown, data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). In this case, data driver 130, voltage generator 140, and controller 150 may be functionally different components within a single driver integrated circuit (DIC). In some other embodiments, at least one of data driver 130, voltage generator 140, and controller 150 may be configured (e.g., mounted) in the driver integrated circuit (DIC), and the remainder may be configured (e.g., mounted) and placed in an integrated circuit different from the driver integrated circuit (DIC). Controller 150 may be a hardware component such as a circuit that performs a predetermined function. For example, the hardware component may include a field-programmable gate array (“FPGA”) or an application-specific integrated circuit (“ASIC”).

[0079] Temperature sensor 160 senses temperature (e.g., temperature around temperature sensor 160) and generates temperature data TEP indicating the sensed temperature. In an embodiment, temperature sensor 160 may be disposed on display panel 110. In an embodiment, temperature sensor 160 may be disposed adjacent to (near) display panel 110 and / or driver integrated circuit DIC. In an embodiment, display device 100 may include two or more temperature sensors 160.

[0080] The controller 150 can control various operations of the display device 100 in response to temperature data TEP. In one embodiment, the controller 150 can adjust the brightness of the image output from the display panel 110 in response to the temperature data TEP. In another embodiment, for example, the controller 150 can adjust at least one of the data signal input to the display panel 110, the first power supply voltage VDD, and the second power supply voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0081] Figure 2 It is shown Figure 1 A block diagram of an embodiment of any of the sub-pixels SP.

[0082] exist Figure 2 In, it is shown that in Figure 1 The sub-pixel SPij is set in the i-th row (i is an integer greater than or equal to 1) and j-th column (j is an integer greater than or equal to 1) of the sub-pixel SP.

[0083] Reference Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0084] The light-emitting element (LD) is connected between the first power supply voltage node VDDN and the second power supply voltage node VSSN. In this case, the first power supply voltage node VDDN is the transmission... Figure 1 The first power supply voltage node is VDD, and the second power supply voltage node is VSSN for transmission. Figure 1 The node of the second power supply voltage VSS.

[0085] The anode electrode AE ​​of the light-emitting element LD is connected to the first power supply voltage node VDDN via a sub-pixel circuit SPC, and the cathode electrode CE of the light-emitting element LD can be connected to the second power supply voltage node VSSN. In an embodiment, for example, the anode electrode AE ​​of the light-emitting element LD can be connected to the first power supply voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0086] Sub-pixel circuits (SPCs) can be connected to Figure 1 The i-th gate line GLi from the first gate line GL1 to the m-th gate line GLm Figure 1 The first optical emission control line EL1 to the m-th optical emission control line ELm, and the i-th optical emission control line ELi and Figure 1 The first data line DL1 to the nth data line DLn, specifically the j-th data line DLj. The sub-pixel circuit SPC controls the light-emitting element LD based on the signals received through these signal lines.

[0087] The sub-pixel circuit (SPC) can operate in response to a gate signal (or scan signal) received via the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines.

[0088] The sub-pixel circuit SPC can operate in response to the light emission control signal received via the i-th light emission control line ELi.

[0089] The sub-pixel circuit SPC can receive data signals via the j-th data line DLj. In response to the light emission control signal received via the i-th light emission control line ELi, the sub-pixel circuit SPC can adjust the current flowing from the first power supply voltage node VDDN through the light-emitting element LD to the second power supply voltage node VSSN according to the stored voltage. Therefore, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0090] Figure 3 This is an equivalent circuit diagram based on an embodiment of the disclosed subpixel SPij.

[0091] The sub-pixel SPij in the disclosed embodiments may include a sub-pixel circuit SPC and a light-emitting element LD.

[0092] The subpixel circuit (SPC) may include two or more switching elements and one or more storage elements. In one embodiment, the switching elements may be implemented as transistors. In another embodiment, the storage elements may be implemented as capacitors.

[0093] Reference Figure 3 The sub-pixel circuit SPC in the disclosed embodiments may include four transistors and three capacitors. In an embodiment, for example, the sub-pixel circuit SPC in the disclosed embodiments may include first transistors TR1 to fourth transistors TR4 and first capacitors C1 to third capacitors C3.

[0094] The first transistor TR1 may include a gate electrode electrically connected to a first node N1, a first electrode electrically connected to a second node N2, and a second electrode electrically connected to a third node N3. The first transistor TR1 may also include a body electrode electrically connected to a first power line PL1. The first electrode may be a source electrode or a drain electrode (e.g., a drain electrode). The second electrode may be the other of the source and drain electrodes (e.g., a source electrode). The first transistor TR1 can control the magnitude of the current flowing through the light-emitting element LD based on the voltage applied to the first node N1.

[0095] The second transistor TR2 can switch the electrical connection between the j-th data line DLj and the first node N1 in response to a first scan signal GW[i] applied to the i-th first gate line GL1i. The second transistor TR2 may include a body electrode electrically connected to the first power line PL1. When the second transistor TR2 is turned on in response to the first scan signal GW[i] at an on level (e.g., a relatively low level), a data voltage Vdata or a voltage corresponding to the data voltage Vdata may be applied to the first node N1. The i-th gate line GL1i may include the i-th first gate line GL1i.

[0096] The third transistor TR3 can switch the electrical connection between the second node N2 and the third power line PL3 in response to a second scan signal GB[i] applied to the i-th second gate line GL2i. The third transistor TR3 may include a body electrode electrically connected to the third power line PL3. When the third transistor TR3 is turned on in response to the second scan signal GB[i] at an on level (e.g., a relatively high level), the third power supply voltage VINT or a voltage corresponding to the third power supply voltage VINT can be applied to the second node N2. In an embodiment, the voltage can be generated from the voltage generator 140 described above (see reference 140). Figure 1 The third power supply voltage VINT is supplied. The i-th gate line GLi may include the i-th second gate line GL2i.

[0097] The fourth transistor TR4 can switch the electrical connection between the first power line PL1 and the third node N3 in response to the i-th light emission control signal EM[i] applied to the i-th light emission control line ELi. The fourth transistor TR4 may include a body electrode electrically connected to the first power line PL1. When the fourth transistor TR4 is turned on in response to the i-th light emission control signal EM[i] at an on-level (e.g., a relatively low level), a first power supply voltage VDD can be applied to the third node N3. The fourth transistor TR4 can be electrically connected to the first power line PL1 via the first power supply voltage node VDDN. The first power supply voltage VDD can be applied to the first power line PL1.

[0098] The first capacitor C1 can maintain the potential difference between the first node N1 and the third node N3. The first capacitor C1 may include a first electrode E11 electrically connected to the first node N1 and a second electrode E12 electrically connected to the third node N3. In some embodiments, the first electrode E11 and the second electrode E12 may be disposed on the same layer. In other embodiments, the first electrode E11 and the second electrode E12 may be disposed on different layers.

[0099] The second capacitor C2 can mitigate (e.g., minimize) voltage variations at the second node N2. In an embodiment, the second capacitor C2 can be configured to be connected in parallel with the light-emitting element LD. The second capacitor C2 may include a first electrode E21 electrically connected to the second node N2 and a second electrode E22 electrically connected to the second electric field line (also referred to as the electric field line) PL2. The second capacitor C2 can maintain the potential difference between the second node N2 and the electric field line to which a constant voltage is applied (e.g., the second electric field line PL2 to which a second power supply voltage VSS is applied). The first electrode E21 and the second electrode E22 may be disposed in the same layer. The second capacitor C2 can be physically distinguished from the parasitic capacitance of the light-emitting element LD itself, which is formed by the anode electrode AE ​​and the cathode electrode CE disposed in different layers, with the light-emitting structure EMS disposed between the anode electrode AE ​​and the cathode electrode CE. In the disclosed embodiment, the capacitance of the second capacitor C2 may be greater than the capacitance between the anode electrode AE ​​and the cathode electrode CE of the light-emitting element LD.

[0100] The third capacitor C3 can maintain the potential difference between the first node N1 and the second node N2. The third capacitor C3 may include a first electrode E31 electrically connected to the first node N1 and a second electrode E32 electrically connected to the second node N2. In one embodiment, the first electrode E31 and the second electrode E32 of the third capacitor C3 may be disposed on the same layer as each other. In another embodiment, the first electrode E31 and the second electrode E32 of the third capacitor C3 may be disposed on different layers.

[0101] The light-emitting element (LD) may include a first electrode (e.g., an anode electrode AE) electrically connected to a second node N2, a second electrode (e.g., a cathode electrode CE) electrically connected to a second power line PL2, and a light-emitting structure EMS disposed between the anode electrode AE ​​and the cathode electrode CE. The cathode electrode CE may be electrically connected to the second power line PL2 via a second power supply voltage node VSSN. The second power supply voltage (also known as a constant voltage) VSS may be applied to the second power line PL2.

[0102] Each of the first transistor TR1 to the fourth transistor TR4 can be a transistor comprising a P-type semiconductor or a transistor comprising an N-type semiconductor. In an embodiment, the first transistor TR1, the second transistor TR2, and the fourth transistor TR4 can be implemented as transistors comprising a P-type semiconductor. In the above embodiment, the third transistor TR3 can be implemented as a transistor comprising an N-type semiconductor. However, the disclosed embodiments are not limited thereto. In an embodiment, for example, at least one of the first transistor TR1, the second transistor TR2, and the fourth transistor TR4 can be implemented as a transistor comprising an N-type semiconductor, or the third transistor TR3 can be implemented as a transistor comprising a P-type semiconductor.

[0103] A transistor containing a P-type semiconductor can turn on in response to a low-level signal and turn off in response to a high-level signal. A transistor containing an N-type semiconductor can turn on in response to a high-level signal and turn off in response to a low-level signal.

[0104] In one embodiment, each of the first transistor TR1 to the fourth transistor TR4 may be implemented as a transistor including a body electrode. However, in another embodiment, at least one of the first transistor TR1 to the fourth transistor TR4 may be implemented as a transistor without a body electrode.

[0105] Figure 4 This is an equivalent circuit diagram based on an embodiment of the disclosed subpixel SPij.

[0106] and Figure 3 In contrast, the second electrode E22 of the second capacitor C2 can be electrically connected to the third power line (also called the power line) PL3, which is supplied with the third power supply voltage (also called the constant voltage) VINT. The second capacitor C2 can perform the function of maintaining the voltage of the second node N2.

[0107] Figure 5 This is an equivalent circuit diagram based on an embodiment of the disclosed subpixel SPij.

[0108] and Figure 3 and Figure 4 In contrast, the second electrode E22 of the second capacitor C2 can be electrically connected to the fourth power line (also called the power line) PL4, which is subjected to the fourth power supply voltage (also called the constant voltage) Vhold. The second capacitor C2 can perform the function of maintaining the voltage of the second node N2.

[0109] The fourth power supply voltage Vhold can be applied to the fourth power line PL4. This can be obtained from the aforementioned voltage generator 140 (see reference). Figure 1 A fourth power supply voltage Vhold is supplied. In an embodiment, the fourth power supply voltage Vhold may be the same as the first power supply voltage VDD. The fourth power line PL4 may be the same as or electrically connected to the first power line PL1.

[0110] In an embodiment, the fourth power supply voltage Vhold can be different from all of the first power supply voltage VDD, the second power supply voltage VSS, and the third power supply voltage VINT.

[0111] Figure 6 This is an embodiment of the first capacitor C1.

[0112] Reference Figure 6The first electrode E11 and the second electrode E12 of the first capacitor C1 may include the same electrode layer SD. Each of the first electrode E11 and the second electrode E12 of the first capacitor C1 may be disposed in the same plane formed by the first direction DR1 and the second direction DR2.

[0113] The first electrode E11 of the first capacitor C1 can be electrically connected to the first node N1. The second electrode E12 can be electrically connected to the third node N3.

[0114] Figure 7 This is an embodiment of the second capacitor C2.

[0115] Reference Figure 7 The first electrode E21 and the second electrode E22 of the second capacitor C2 may include the same electrode layer SD. Each of the first electrode E21 and the second electrode E22 of the second capacitor C2 may be disposed in the same plane formed by the first direction DR1 and the second direction DR2.

[0116] The first electrode E21 of the second capacitor C2 can be electrically connected to the second node N2.

[0117] Further refer to the above Figure 6 Each of the first electrode E11 and the second electrode E12 of the first capacitor C1 can be disposed on the same layer as each of the first electrode E21 and the second electrode E22 of the second capacitor C2. However, the disclosed embodiments are not limited thereto, and each of the first electrode E11 and the second electrode E12 of the first capacitor C1 can be disposed on a different layer from each of the first electrode E21 and the second electrode E22 of the second capacitor C2.

[0118] Figure 8 This is an embodiment of the disclosed subpixel driving method 800.

[0119] The subpixel driving method 800 can also be called the display device driving method 800 or the electronic device driving method 800.

[0120] Reference Figure 8 During the horizontal time period 1H (or a predetermined horizontal time period) during which the subpixels are driven, the time period can be divided into a first time period T1, a second time period T2, a third time period T3, and a fourth time period T4.

[0121] Data drive 130 (reference) Figure 1 During the first time period T1 to the third time period T3, the data voltage Vdata[i] supplied to the i-th pixel row can be supplied to the j-th data line DLj.

[0122] Gate drive circuit 120 (reference) Figure 1The first scan signal GW[i] at the on level can be supplied to the i-th first gate line GL1i during the first time period T1 and the second time period T2. The gate drive circuit 120 can supply the first scan signal GW[i] at the off level to the i-th first gate line GL1i during the third time period T3 and the fourth time period T4. In the embodiment, the first scan signal GW[i] at the on level can be at a relatively low level. The first scan signal GW[i] at the off level can be at a relatively high level.

[0123] Gate drive circuit 120 (reference) Figure 1 The second scan signal GB[i] at the on level can be supplied to the i-th second gate line GL2i during the first time period T1 to the third time period T3. The gate drive circuit 120 can supply the second scan signal GB[i] at the off level to the i-th second gate line GL2i during the fourth time period T4. In the embodiment, the second scan signal GB[i] at the on level can be at a relatively high level. The second scan signal GB[i] at the off level can be at a relatively low level.

[0124] Gate drive circuit 120 (reference) Figure 1 The i-th optical emission control signal EM[i], which is at the off level, can be supplied to the i-th optical emission control line ELi during the second time period T2. The gate drive circuit 120 can supply the i-th optical emission control signal EM[i], which is at the on level, to the i-th optical emission control line ELi during the first time period T1, the third time period T3, and the fourth time period T4. The i-th optical emission control signal EM[i], which is at the on level, can be at a relatively low level. The i-th optical emission control signal EM[i], which is at the off level, can be at a relatively high level.

[0125] The first time period T1 can also be referred to as the "initialization period". The second time period T2 can also be referred to as the "data writing and threshold voltage compensation period". The third time period T3 can also be referred to as the "brightness control period". The fourth time period T4 can also be referred to as the "transmission period". The first time period T1 to the fourth time period T4 will be described in detail below.

[0126] Figures 9 to 12 It is used for explanation Figure 8 About Figure 3 A diagram showing the driving method for subpixel SPij.

[0127] For ease of description, refer to Figure 3 The sub-pixel SPij is described in the driving method 800. However, the disclosed embodiments are not limited thereto, and Figure 8 The driving method 800 can be similarly applied to Figure 4 sub-pixels SPij and Figure 5 The sub-pixel SPij.

[0128] Figure 9 This is a diagram showing the first time period T1 of the driving method 800.

[0129] Reference Figure 9 The first scan signal GW[i] at the on level can be supplied to the i-th first gate line GL1i during the first time period T1. The second scan signal GB[i] at the on level can be supplied to the i-th second gate line GL2i. During the first time period T1, the on level of the i-th optical emission control signal (also known as the emission control signal) EM[i] can be supplied to the i-th optical emission control line ELi. The first transistor TR1, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4 can be turned on.

[0130] When the first scan signal GW[i], which is at the on level, is supplied to the i-th first gate line GL1i, the second transistor TR2 can be turned on. When the second transistor TR2 is turned on, the data voltage Vdata[i] can be supplied from the j-th data line DLj to the first node N1.

[0131] The first capacitor C1 can be initialized using the data voltage Vdata[i] and the first power supply voltage VDD. During the first time period T1, the first capacitor C1 can be charged with a voltage corresponding to the voltage difference between the data voltage Vdata[i] and the first power supply voltage VDD, regardless of the voltage charged in the previous time period (or previous frame period).

[0132] When the second scan signal GB[i], which is at the on level, is supplied to the i-th second gate line GL2i, the third transistor TR3 can be turned on. When the third transistor TR3 is turned on, the third power supply voltage VINT can be supplied to the second node N2. When the third power supply voltage VINT is supplied to the second node N2, the light-emitting element LD can be initialized. When the third power supply voltage VINT is supplied to the second node N2, the voltage of the anode electrode of the light-emitting element LD can be initialized to the third power supply voltage VINT.

[0133] The second capacitor C2 can be initialized by the third power supply voltage VINT. In an embodiment, for example, during a first time period T1, the second capacitor C2 can be charged with a voltage corresponding to the voltage difference between the third power supply voltage VINT and the second power supply voltage VSS, regardless of the voltage charged in a previous time period (or previous frame period).

[0134] The third capacitor C3 can be initialized by the data voltage Vdata[i] supplied to the first node N1 and the third power supply voltage VINT supplied to the second node N2. In an embodiment, for example, during the first time period T1, the third capacitor C3 can be charged with voltages corresponding to the data voltage Vdata[i] and the third power supply voltage VINT, regardless of the voltage charged in the previous time period (or previous frame period).

[0135] During the first time period T1, the current supplied from the first transistor TR1 can flow through the third transistor TR3 in the direction of the third electric field line PL3. During the first time period T1, the light-emitting element LD can remain in a non-light-emitting state.

[0136] The voltage of the first node N1 in the first time period T1 can be equal to the data voltage Vdata[i]. The voltage of the second node N2 can be equal to the third power supply voltage VINT. The voltage of the third node N3 can be equal to the first power supply voltage VDD.

[0137] Figure 10 This is a diagram showing the second time period T2 of the driving method 800.

[0138] Reference Figure 10 During the second time period T2, the second transistor TR2 can remain in the on state in response to the first scan signal GW[i] supplied to the i-th first gate line GL1i which is at the on level, and the third transistor TR3 can remain in the on state in response to the second scan signal GB[i] supplied to the i-th second gate line GL2i which is at the on level.

[0139] During the second time period T2, the fourth transistor TR4 can be turned off in response to the light emission control signal EM[i] at the off level supplied to the i-th light emission control line ELi. When the fourth transistor TR4 is turned off, the first power line PL1 and the third node N3 can be electrically isolated.

[0140] When the second transistor TR2 is set to the on state during the second time period T2, the first node N1 can be electrically connected to the j-th data line DLj to supply the data voltage Vdata[i]. During the second time period T2, the third node N3 can be in a floating state, dropping from the first power supply voltage VDD to the voltage shown in Equation 1 below.

[0141] Equation 1

[0142] In Equation 1, “VN(3)” refers to the voltage of the third node N3. “Vdata[i]” represents the data voltage Vdata[i]. “|Vth_TR1|” represents the absolute value of the threshold voltage of the first transistor TR1.

[0143] During the second time period T2, the voltage corresponding to the threshold voltage of the first transistor TR1 can be stored in the first capacitor C1.

[0144] During the second time period T2, the fourth transistor TR4 is set to the off state, and the current supplied from the third node N3 to the second node N2 via the first transistor TR1 can flow through the third transistor TR3 in the direction of the third electric field line PL3. During the second time period T2, the light-emitting element LD can remain in a non-light-emitting state.

[0145] The voltage of the first node N1 in the second time period T2 can be the data voltage Vdata[i]. The voltage of the second node N2 can be the third power supply voltage VINT.

[0146] Figure 11 This is a diagram showing the third time period T3 of the driving method 800.

[0147] Reference Figure 11 During the third time period T3, the i-th optical emission control line ELi is supplied with the i-th optical emission control signal EM[i] at the on level, and the fourth transistor TR4 can be set to the on state. During the third time period T3, the first scan signal GW[i] at the off level is applied to the i-th first gate line GL1i, and the second transistor TR2 can be set to the off state. During the third time period T3, the second scan signal GB[i] at the on level is supplied to the i-th second gate line GL2i, and the third transistor TR3 can remain in the on state.

[0148] When the third transistor TR3 is turned on during the third time period T3, the first transistor TR1 can control the amount of current supplied from the first power line PL1 to the second node N2 in response to the voltage of the first node N1. When the third transistor TR3 is set to the on state, the current supplied to the second node N2 can be guided to the third power line PL3. During the third time period T3, the light-emitting element LD is set to the non-light-emitting state, thereby improving the display device 100 (refer to...). Figure 1 ( ) grayscale representation.

[0149] Specifically, the voltage of the second node N2 can be increased to a higher voltage than desired during the second time period T2, thus allowing excess current to be supplied to the light-emitting element LD. In embodiments, for example, the light-emitting element LD may emit light temporarily even when black grayscale is achieved in sub-pixel SPij. Therefore, in the disclosed embodiment, during the third time period T3, the current supplied from the first transistor TR1 is supplied to the third power line PL3, thereby improving the display device 100 (see reference). Figure 1 The grayscale representation of ).

[0150] During the third time period T3, the voltage at the first node N1 can rise to the first power supply voltage VDD. Therefore, the voltage change at the first node N1 can be expressed as Equation 2.

[0151] Equation 2

[0152] In Equation 2, “VN(1)” refers to the voltage of the first node N1. “Vdata[i]” represents the data voltage Vdata[i]. “ΔVs” can represent the voltage change of the third node N3. “α” refers to the ratio by which the voltage change of the third node N3 is reflected in the voltage change of the first node N1.

[0153] ΔVs can be calculated as shown in Equation 3 below.

[0154] Equation 3

[0155] "α" can be calculated as shown in Equation 4 below.

[0156] Equation 4

[0157] In Equation 4, "c1" refers to the storage capacity of the first capacitor C1. "c3" represents the storage capacity of the third capacitor C3.

[0158] The voltage at the second node N2 during the third time period T3 can be equal to the third power supply voltage VINT.

[0159] As the level of the first scan signal GW[i] transitions from on to off during the transition from the second time period T2 to the third time period T3, and voltage fluctuations are applied to the j-th data line DLj, ripple voltage can be applied to the second node N2. The second capacitor C2 can mitigate (e.g., minimize) the voltage variation of the second node N2 from the third supply voltage VINT due to the ripple voltage. Therefore, the voltage of the second node N2 can be maintained at the third supply voltage VINT.

[0160] Figure 12 This is a diagram showing the fourth time period T4 of the driving method 800.

[0161] Reference Figure 12 During the fourth time period T4, the second scan signal GB[i] at the cutoff level is applied to the i-th second gate line GL2i, and the third transistor TR3 can be turned off. During the fourth time period T4, the first scan signal GW[i] at the cutoff level is applied to the i-th first gate line GL1i, and the second transistor TR2 can be turned off. During the fourth time period T4, the i-th transmit control signal EM[i] at the conduction level is applied to the i-th light emission control line ELi, and the fourth transistor TR4 can be turned on.

[0162] During the fourth time period T4, the first transistor TR1 can control the amount of current supplied from the first power supply voltage node VDDN to the second power supply voltage node VSSN via the light-emitting element LD in response to the voltage of the first node N1. During the fourth time period T4, the light-emitting element LD can generate light with a brightness corresponding to the amount of drive current supplied from the first transistor TR1.

[0163] During the fourth time period T4, the voltage of the second node N2 can be changed from the third power supply voltage VINT to a predetermined voltage. The amount of voltage change of the second node N2 during the fourth time period T4 is shown in Equation 5 below.

[0164] Equation 5

[0165] In Equation 5, “ΔV A "V" refers to the amount of voltage change at the second node N2. A' "VINT" refers to the voltage of the second node N2 in the fourth time period T4. "VINT" refers to the third power supply voltage VINT, and can correspond to the voltage of the second node N2 in the third time period T3.

[0166] Due to the coupling phenomenon of the third capacitor C3, the voltage of the first node N1 can fluctuate as shown in Equation 6 below.

[0167] Equation 6

[0168] In Equation 6, “VN(1)” refers to the voltage of the first node N1. “Vdata[i]+αΔVs” corresponds to the voltage of the first node N1 in the third time period T3. “β” refers to the ratio by which the voltage change of the second node N2 is reflected in the voltage change of the first node N1. “ΔV A "The same as the calculation in Equation 5."

[0169] “β” can be calculated as shown in Equation 7 below.

[0170] Equation 7

[0171] In Equation 7, "c1" refers to the storage capacity of the first capacitor C1. "c3" represents the storage capacity of the third capacitor C3.

[0172] Rewriting Equation 6 using Equations 3, 4, 5, and 7, the voltage at the first node N1 can be expressed as Equation 8 below.

[0173] Equation 8

[0174] The voltage difference between the source electrode and the gate electrode of the first transistor TR1 in the fourth time period T4 can be expressed as Equation 9 below.

[0175] Equation 9

[0176] In Equation 9, “Vsg” can correspond to the voltage difference between the source and gate electrodes of the first transistor TR1. The voltage of the source electrode can be equal to the first power supply voltage VDD. The voltage of the gate electrode can be the same as “VN(1)”, which is the voltage of the first node N1 in Equation 8.

[0177] The threshold voltage of the first transistor TR1 can be set differently depending on the voltage difference between the body electrode voltage and the source electrode voltage of the first transistor TR1. Assuming the first power supply voltage VDD is set to 8 volts (V), the body electrode voltage of the first transistor TR1 can be set to 8V during the second time period T2. The voltage of the source electrode (or the third node N3) of the first transistor TR1 can be set to a voltage lower than the body electrode voltage. In an embodiment, for example, assuming the voltage of the third node N3 is set to 4V, the voltage difference between the body electrode voltage and the source electrode voltage of the first transistor TR1 can be set to 4V. Therefore, the first transistor TR1 can have a first threshold voltage during the second time period T2. During the second time period T2, the first threshold voltage can be compensated. The absolute value of the first threshold voltage can be represented by |Vth_TR1| as described in Equation 1.

[0178] Next, the voltage of the third node N3 during the fourth time period T4 can be the first power supply voltage VDD. During the fourth time period T4, the voltage at the body electrode and the voltage at the source electrode of the first transistor TR1 can be set to be the same, and the threshold voltage of the first transistor TR1 during the fourth time period T4 can be the second threshold voltage. The second threshold voltage can be different from the first threshold voltage. The absolute value of the second threshold voltage can be represented by |Vth_TR1'|.

[0179] In the fourth time period T4, the magnitude of the driving current flowing through the light-emitting element LD in the first transistor TR1 is shown in Equation 10 below.

[0180] Equation 10

[0181] In Equation 10, "I" LD "" refers to the magnitude of the driving current flowing through the light-emitting element LD. "μ" refers to the electron mobility of the first transistor TR1. "Cox" refers to the oxide capacitance of the first transistor TR1. "W" refers to the channel width of the first transistor TR1. "L" refers to the channel length of the first transistor TR1. "Vsg" is the same as calculated in Equation 9. "|Vth_TR1'|" can refer to the threshold voltage of the first transistor TR1, which is the second threshold voltage, in the fourth time period T4.

[0182] When solving equation 10, it is as shown in equation 11 below.

[0183] Equation 11

[0184] Referring to Equation 11, the data voltage Vdata[i] can be driven by the current (e.g., I in Equation 11). LD The value reflected in the equation is the ratio of the capacitances of the first capacitor C1 and the third capacitor C3 (e.g., c3 / (c1+c3) in Equation 11). When the ratio of the data voltage Vdata[i] to the capacitance of the capacitors is reflected in the drive current, the range of the data voltage can be relatively wide.

[0185] Further reference Figure 1 When the input image data IMG is converted into image data DATA, the controller 150 can generate the image data DATA based on the capacitance of the first capacitor C1 (e.g., c1 in Equation 11) and the capacitance of the third capacitor C3 (e.g., c3 in Equation 11). The data driver 130 can generate a data voltage Vdata[i] corresponding to the image data DATA.

[0186] In the embodiments, when the data voltage Vdata[i] is directly reflected in the drive current (or the coefficient by which the data voltage Vdata[i] is multiplied is equal to or greater than 1), the range of the data voltage is set to be relatively small. In this case, it is relatively difficult to achieve various gray levels and thus stably achieve the predetermined gray level using a relatively small range of data voltages. When the range of data voltages that can be set is widened, as in the application, by multiplying the data voltage by a smaller coefficient, the preset gray level can be stably achieved.

[0187] Furthermore, the absolute value of the threshold voltage of the first transistor TR1 (e.g., |Vth_TR1| in Equation 11) can be reflected in the drive current in correspondence with the ratio of the capacitances of the first capacitor C1 and the third capacitor C3 (e.g., c1 / (c1+c3) in Equation 11). In this case, the influence of the threshold voltage of the first transistor TR1 can be mitigated.

[0188] The difference between the voltage at the second node N2 and the third power supply voltage VINT (e.g., V in Equation 11) A' -VINT) can be reflected in the drive current in a manner corresponding to the ratio of the capacitances of the first capacitor C1 and the third capacitor C3 (e.g., c3 / (c1+c3) in Equation 11). In this case, the effects of voltage fluctuations at the second node N2 are mitigated, thereby improving visibility.

[0189] Figure 13 This is an embodiment of the disclosed subpixel driving method 1300.

[0190] The subpixel driving method 1300 can also be called the display device driving method 1300 or the electronic device driving method 1300.

[0191] Reference Figure 13 During this period, the horizontal time period 1H (or predetermined horizontal time period) during which sub-pixel SPij is driven may include a first time period T1a, a second time period T2, and a third time period T3.

[0192] When with Figure 8 Compared to the driving method 800, Figure 13 The driving method 1300 can further compensate the threshold voltage of the first transistor TR1 in the first time period T1a.

[0193] Figures 14 to 17 It is used for parallel explanation Figure 13 About Figure 3 The driving method of sub-pixel SPij is shown in Figure 1300.

[0194] For ease of description, refer to Figure 3The driving method 1300 is described by sub-pixels SPij. However, the disclosed embodiments are not limited thereto, and Figure 13 The driving method 1300 can be similarly applied to Figure 4 sub-pixels SPij and Figure 5 The sub-pixel SPij.

[0195] Figure 14 This is a diagram showing the first time period T1a of the driving method 1300.

[0196] Reference Figure 14 The first scan signal GW[i], which is at the on level, can be supplied to the i-th first gate line GL1i during the first time period T1a. The second scan signal GB[i], which is at the on level, can be supplied to the i-th second gate line GL2i. During the first time period T1a, the i-th transmit control signal EM[i], which is at the off level, can be supplied to the i-th light emission control line ELi. The first transistor TR1, the second transistor TR2, and the third transistor TR3 can be turned on.

[0197] When the first scan signal GW[i], which is at the on level, is supplied to the i-th first gate line GL1i, the second transistor TR2 can be turned on. When the second transistor TR2 is turned on, the data voltage Vdata[i] can be supplied from the j-th data line DLj to the first node N1.

[0198] The first capacitor C1 can be charged with a voltage corresponding to the voltage difference between the data voltage Vdata[i] and the first power supply voltage VDD by the first power supply voltage VDD applied to the third node N3 in the fourth time period T4 of the immediately preceding frame and the data voltage Vdata[i] applied during the first time period T1a.

[0199] When the second scan signal GB[i], which is at the on level, is supplied to the i-th second gate line GL2i, the third transistor TR3 can be turned on. When the third transistor TR3 is turned on, the third power supply voltage VINT can be supplied to the second node N2. When the third power supply voltage VINT is supplied to the second node N2, the light-emitting element LD can be initialized. When the third power supply voltage VINT is supplied to the second node N2, the voltage of the anode electrode of the light-emitting element LD can be initialized to the third power supply voltage VINT.

[0200] The second capacitor C2 can be initialized by the third power supply voltage VINT. In an embodiment, for example, during the first time period T1a, the second capacitor C2 can be charged with a voltage corresponding to the voltage difference between the third power supply voltage VINT and the second power supply voltage VSS, regardless of the voltage charged in the previous time period (or previous frame period).

[0201] The third capacitor C3 can be initialized by the data voltage Vdata[i] supplied to the first node N1 and the third power supply voltage VINT supplied to the second node N2. During the first time period T1a, the third capacitor C3 can be charged with the voltages corresponding to the data voltage Vdata[i] and the third power supply voltage VINT, regardless of the voltages charged in the previous time period (or previous frame period).

[0202] During the first time period T1a, the current supplied from the first transistor TR1 can flow through the third transistor TR3 in the direction of the third electric field line PL3. During the first time period T1a, the light-emitting element LD can remain in a non-light-emitting state.

[0203] The voltage of the first node N1 in the first time period T1a can be equal to the data voltage Vdata[i]. The voltage of the second node N2 can be equal to the third power supply voltage VINT.

[0204] Figure 15 This is a diagram showing the second time period T2 of the driving method 1300.

[0205] Reference Figure 15 During the second time period T2, the second transistor TR2 can remain in the on state in response to the first scan signal GW[i] supplied to the i-th first gate line GL1i which is at the on level, and the third transistor TR3 can remain in the on state in response to the second scan signal GB[i] supplied to the i-th second gate line GL2i which is at the on level.

[0206] During the second time period T2, the fourth transistor TR4 can remain in the off state in response to the off-level i-th optical emission control signal EM[i] supplied to the i-th optical emission control line ELi.

[0207] When the second transistor TR2 is set to the on state during the second time period T2, the first node N1 can be electrically connected to the j-th data line DLj to supply the data voltage Vdata[i]. During the second time period T2, the third node N3 can be in a floating state and drop from the first power supply voltage VDD to the voltage shown in Equation 12 below.

[0208] Equation 12

[0209] In Equation 12, “VN(3)” refers to the voltage of the third node N3. “Vdata[i]” represents the data voltage Vdata[i]. “|Vth_TR1|” represents the absolute value of the threshold voltage of the first transistor TR1. Equation 12 is the same as Equation 1.

[0210] During the second time period T2, the voltage corresponding to the threshold voltage of the first transistor TR1 can be stored in the first capacitor C1.

[0211] During the second time period T2, the third transistor TR3 is set to the on state, and the current supplied from the third node N3 to the second node N2 via the first transistor TR1 can flow through the third transistor TR3 in the direction of the third electric field line PL3. During the second time period T2, the light-emitting element LD can remain in a non-light-emitting state.

[0212] The voltage of the first node N1 in the second time period T2 can be the data voltage Vdata[i]. The voltage of the second node N2 can be the third power supply voltage VINT.

[0213] Figure 16 This is a diagram showing the third time period T3 of the driving method 1300.

[0214] Reference Figure 16 During the third time period T3, the i-th optical emission control line ELi is supplied with the i-th optical emission control signal EM[i] at the on level, and the fourth transistor TR4 can be set to the on state. During the third time period T3, the first scan signal GW[i] at the off level is applied to the i-th first gate line GL1i, and the second transistor TR2 can be set to the off state. During the third time period T3, the second scan signal GB[i] at the on level is supplied to the i-th second gate line GL2i, and the third transistor TR3 can remain in the on state.

[0215] When the third transistor TR3 is turned on during the third time period T3, the first transistor TR1 can control the amount of current supplied from the first power line PL1 to the second node N2 in response to the voltage of the first node N1. When the third transistor TR3 is set to the on state, the current supplied to the second node N2 can be guided to the third power line PL3. During the third time period T3, the light-emitting element LD is set to the non-light-emitting state, thereby improving the display device 100 (refer to...). Figure 1 The grayscale representation of ).

[0216] In detail, the voltage of the second node N2 can be increased to a higher voltage than desired during the second time period T2, so excess current may be supplied to the light-emitting element LD. In embodiments, for example, the light-emitting element LD may emit light temporarily even when black grayscale is achieved in sub-pixel SPij. Therefore, in the disclosed embodiment, during the third time period T3, the current supplied from the first transistor TR1 is supplied to the third power line PL3, thereby improving the display device 100 (see...). Figure 1 The grayscale representation of ).

[0217] During the third time period T3, the voltage of the first node N1 can rise to the first power supply voltage VDD. Therefore, the voltage change of the first node N1 can be expressed as Equation 13.

[0218] Equation 13

[0219] In Equation 13, “VN(1)” refers to the voltage of the first node N1. “Vdata[i]” represents the data voltage Vdata[i]. “ΔVs” can represent the voltage change of the third node N3. “α” refers to the ratio in which the voltage change of the third node N3 is reflected in the voltage change of the first node N1. Equation 13 is the same as Equation 2 above.

[0220] "ΔVs" can be calculated as shown in Equation 14 below.

[0221] Equation 14

[0222] Equation 14 is the same as Equation 3 above.

[0223] "α" can be calculated as shown in Equation 15 below.

[0224] Equation 15

[0225] In Equation 15, "c1" refers to the storage capacity of the first capacitor C1. "c3" represents the storage capacity of the third capacitor C3. Equation 15 is the same as Equation 4 above.

[0226] The voltage at the second node N2 during the third time period T3 can be equal to the third power supply voltage VINT.

[0227] As the level of the first scan signal GW[i] transitions from on to off during the transition from the second time period T2 to the third time period T3, and voltage fluctuations are applied to the j-th data line DLj, ripple voltage can be applied to the second node N2. The second capacitor C2 can mitigate (e.g., minimize) the voltage variation of the second node N2 from the third supply voltage VINT due to the ripple voltage. Therefore, the voltage of the second node N2 can be maintained at the third supply voltage VINT.

[0228] Figure 17 This is a diagram showing the fourth time period T4 of the driving method 1300.

[0229] Reference Figure 17During the fourth time period T4, the second scan signal GB[i] at the cutoff level is applied to the i-th second gate line GL2i, and the third transistor TR3 can be turned off. During the fourth time period T4, the first scan signal GW[i] at the cutoff level is applied to the i-th first gate line GL1i, and the second transistor TR2 can be turned off. During the fourth time period T4, the i-th optical emission control signal EM[i] at the on level is applied to the i-th optical emission control line ELi, and the fourth transistor TR4 can be on.

[0230] During the fourth time period T4, the first transistor TR1 can control the amount of current supplied from the first power supply voltage node VDDN to the second power supply voltage node VSSN via the light-emitting element LD in response to the voltage of the first node N1. During the fourth time period T4, the light-emitting element LD can generate light with a brightness corresponding to the amount of drive current supplied from the first transistor TR1.

[0231] During the fourth time period T4, the voltage of the second node N2 can be changed from the third power supply voltage VINT to a predetermined voltage. The amount of voltage change of the second node N2 during the fourth time period T4 is shown in Equation 16 below.

[0232] Equation 16

[0233] In Equation 16, “ΔV A "V" refers to the amount of voltage change at the second node N2. A' "VINT" refers to the voltage of the second node N2 in the fourth time period T4. "VINT" refers to the third power supply voltage VINT, and can correspond to the voltage of the second node N2 in the third time period T3. Equation 16 is the same as Equation 5 above.

[0234] Due to the coupling phenomenon of the third capacitor C3, the voltage of the first node N1 can fluctuate as shown in Equation 17 below.

[0235] Equation 17

[0236] In Equation 17, “VN(1)” refers to the voltage of the first node N1. “Vdata[i]+αΔVs” corresponds to the voltage of the first node N1 in the third time period T3. “β” refers to the ratio by which the voltage change of the second node N2 is reflected in the voltage change of the first node N1. “ΔV A "As calculated in Equation 16. Equation 17 is the same as Equation 6 above."

[0237] “β” can be calculated as shown in Equation 18 below.

[0238] Equation 18

[0239] In Equation 18, "c1" refers to the storage capacity of the first capacitor C1. "c3" represents the storage capacity of the third capacitor C3. Equation 18 is the same as Equation 7 above.

[0240] Using equations 14, 15, 16, and 18 to rewrite equation 17, the voltage at the first node N1 can be expressed as equation 19 below.

[0241] Equation 19

[0242] Equation 19 is the same as Equation 8 above.

[0243] The voltage difference between the source electrode and the gate electrode of the first transistor TR1 in the fourth time period T4 can be expressed as Equation 20 below.

[0244] Equation 20

[0245] In Equation 20, “Vsg” can correspond to the voltage difference between the source and gate electrodes of the first transistor TR1. The voltage of the source electrode can be equal to the first power supply voltage VDD. The voltage of the gate electrode can be the same as “VN(1)”, which is the voltage of the first node N1 in Equation 19. Equation 20 is the same as Equation 9 above.

[0246] In the fourth time period T4, the magnitude of the driving current flowing through the light-emitting element LD in the first transistor TR1 is shown in Equation 21 below.

[0247] Equation 21

[0248] In equation 21, “I LD "" refers to the magnitude of the driving current flowing through the light-emitting element LD. "μ" refers to the electron mobility of the first transistor TR1. "Cox" refers to the oxide capacitance of the first transistor TR1. "W" refers to the channel width of the first transistor TR1. "L" refers to the channel length of the first transistor TR1. "Vsg" is the same as calculated in Equation 20. "|Vth_TR1'|" can refer to the threshold voltage of the first transistor TR1, which is the second threshold voltage, in the fourth time period T4. Equation 21 is the same as Equation 10 above.

[0249] When solving equation 21, it is as shown in equation 22 below.

[0250] Equation 22

[0251] Equation 22 is the same as Equation 11 above.

[0252] Referring to Equation 22, the data voltage Vdata[i] can be driven by the current (e.g., I in Equation 22). LD The value reflected in the equation is the ratio of the capacitances of the first capacitor C1 and the third capacitor C3 (e.g., c3 / (c1+c3) in Equation 22). When the ratio of the data voltage Vdata[i] to the capacitors is reflected in the drive current, the range of the data voltage can be relatively wide.

[0253] Further reference Figure 1 When the input image data IMG is converted into image data DATA, the controller 150 can generate the image data DATA based on the capacitance of the first capacitor C1 (e.g., c1 in Equation 22) and the capacitance of the third capacitor C3 (e.g., c3 in Equation 22). The data driver 130 can generate a data voltage Vdata[i] corresponding to the image data DATA.

[0254] In the embodiments, when the data voltage Vdata[i] is directly reflected in the drive current (or the coefficient by which the data voltage Vdata[i] is multiplied is equal to or greater than 1), the range of the data voltage is set to be relatively small. In this case, it is relatively difficult to achieve various gray levels and thus stably achieve the preset gray level using a relatively small range of data voltages. When the range of the data voltage that can be set is widened, as in the application, the preset gray level can be stably achieved.

[0255] Furthermore, the absolute value of the threshold voltage of the first transistor TR1 (e.g., |Vth_TR1| in Equation 22) can be reflected in the drive current in correspondence with the ratio of the capacitances of the first capacitor C1 and the third capacitor C3 (e.g., c1 / (c1+c3) in Equation 22). In this case, the influence of the threshold voltage of the first transistor TR1 can be mitigated.

[0256] The difference between the voltage at the second node N2 and the third power supply voltage VINT (e.g., V in Equation 22) A' -VINT) can be reflected in the drive current in a manner corresponding to the ratio of the capacitances of the first capacitor C1 and the third capacitor C3 (e.g., c3 / (c1+c3) in Equation 22). In this case, the effects of voltage fluctuations at the second node N2 are mitigated, thereby improving visibility.

[0257] Figure 18 It is shown Figure 1 A plan view of an embodiment of the display panel 110.

[0258] Reference Figure 18 , Figure 1 The embodiment of the display panel 110 can correspond to Figure 18 The display panel DP shown may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA is positioned around the display area DA.

[0259] Display panel DP can include substrate SUB, subpixel SP, and pad (or "soldering pad") PD.

[0260] When the display panel DP is used as a display for a head-mounted display (“HMD”) device, a virtual reality (“VR”) device, a mixed reality (“MR”) device, or an augmented reality (“AR”) device, the display panel DP can be positioned substantially close to the user's eyes. In this case, sub-pixels SP with a relatively high degree of integration are desirable. In embodiments where the substrate SUB is set as a silicon substrate, the integration of the sub-pixels SP can be increased. The sub-pixels SP and / or the remaining components of the display panel DP can be formed on the substrate SUB, which is the silicon substrate in the above embodiments. A display device 100 including a display panel DP formed on a substrate SUB, which is a silicon substrate (see reference 100). Figure 1 It can also be referred to as an organic light-emitting diode (OLED) (“OLEDoS”) display device on silicon.

[0261] Subpixels SP can be disposed on the substrate SUB in the display area DA. Subpixels SP can be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiments are not limited to this. In an embodiment, for example, subpixels SP can be arranged in a zigzag shape along the first direction DR1 and the second direction DR2. In an embodiment, for example, subpixels SP can be arranged in a pentiline shape. ® The layout is in the form of a row. The first direction DR1 can be the row direction, and the second direction DR2 can be the column direction.

[0262] Two or more sub-pixels in a plurality of sub-pixels SP can form a pixel PXL.

[0263] In the non-display area NDA on the substrate SUB, components for controlling the sub-pixel SP can be provided. In an embodiment, for example, wiring connected to the sub-pixel SP (such as...) Figure 1 The first gate line GL1 to the m gate line GLm and the first data line DL1 to the nth data line DLn can be set in the non-display area NDA.

[0264] Figure 1At least one of the gate drive circuit 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 can be integrated into the non-display area NDA of the display panel DP. In an embodiment, Figure 1 The gate drive circuit 120 may be disposed (e.g., mounted) to the display panel DP and located in the non-display area NDA. In some other embodiments, the gate drive circuit 120 may be implemented as an integrated circuit separate from the display panel DP. In one embodiment, the temperature sensor 160 may be located in the non-display area NDA to sense the temperature of the display panel DP or the area surrounding the display panel DP.

[0265] The pad PD can be disposed in the non-display area NDA. The pad PD can be electrically connected to the sub-pixel SP via wiring. In an embodiment, for example, the pad PD can be connected to the sub-pixel SP via the first data line DL1 to the nth data line DLn.

[0266] The pad PD can connect the display panel DP to the display device 100 (see reference). Figure 1 Other components. In an embodiment, the voltage and signals required for the operation of components included in the display panel DP can be transmitted from the pad PD via... Figure 1 The driver integrated circuit (DIC) is provided. In an embodiment, for example, first data lines DL1 to nth data lines DLn can be connected to the driver integrated circuit (DIC) via a pad PD. In an embodiment, for example, a first power supply voltage VDD and a second power supply voltage VSS can be received from the driver integrated circuit (DIC) via the pad PD. In an embodiment, for example, when the gate drive circuit 120 is disposed (e.g., mounted) on the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit (DIC) to the gate drive circuit 120 via the pad PD.

[0267] In this embodiment, the circuit board can be electrically connected to the pad PD using a conductive adhesive such as an anisotropic conductive film. In this case, the circuit board can be a flexible circuit board (“FPCB”) or a flexible film with a flexible material. The driver integrated circuit (DIC) can be disposed (e.g., mounted) to the circuit board and electrically connected to the pad PD.

[0268] In embodiments, the display area DA can have various shapes. The display area DA can have a closed loop shape including straight edges and / or curved edges. In embodiments, for example, the display area DA can have shapes such as polygons, circles, semicircles, ellipses, etc.

[0269] In some embodiments, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially circular (rounded). In some embodiments, the display panel DP may be flexible, foldable, rollable, or stretchable. In this case, the display panel DP and / or the substrate SUB may comprise a material with flexible properties.

[0270] Figure 19 It is shown Figure 18 An exploded perspective view of a portion of the display panel DP.

[0271] exist Figure 19 For clarity and conciseness, the diagram illustrates the relationship between the display panel DP and... Figure 18 The portion corresponding to pixels PXL1 and PXL2 within pixel PXL in the display panel can be similarly constructed for the portion corresponding to the remaining pixels in the display panel DP.

[0272] Reference Figure 18 and Figure 19 Each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the disclosure is not limited thereto. In embodiments, for example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels, or may include two sub-pixels.

[0273] exist Figure 19 In the example, when viewed on a third direction DR3 intersecting the first direction DR1 and the second direction DR2, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are shown as having a square shape and the same size as each other. However, the embodiment is not limited to this. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be modified to have various shapes.

[0274] The display panel (DP) may include a substrate (SUB), a pixel circuit layer (PCL), a light-emitting element layer (LDL), a sealing layer (TFE), an optical functional layer (OFL), a coating layer (OC), and a cover window (CW).

[0275] In some embodiments, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. In some embodiments, for example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (“SeOI”) layer, etc. In some other embodiments, the substrate SUB may include a glass substrate. In still other embodiments, the substrate SUB may include a polyimide (“PI”) substrate.

[0276] A pixel circuit layer (PCL) is disposed on a substrate (SUB). The substrate (SUB) and / or the pixel circuit layer (PCL) may include an insulating layer and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may be used as at least some of the circuit elements and / or at least some of the wiring, etc. The conductive patterns may include copper, but the disclosure is not limited thereto.

[0277] The circuit elements may include a sub-pixel circuit SPC for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (see [link to circuit diagram]). Figure 2 The sub-pixel circuit (SPC) may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion comprising a source region, a drain region, and a channel region, and a gate electrode superimposed on the semiconductor portion. In an embodiment, when the substrate SUB is a silicon substrate, the semiconductor portion is included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, when the substrate SUB is a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. In an embodiment, for example, each capacitor may include electrodes spaced apart from each other in a planar view defined by a first direction DR1 and a second direction DR2. In an embodiment, for example, each capacitor may include electrodes spaced apart from each other on a third direction DR3, and an insulating layer is disposed between the electrodes.

[0278] The wiring of the pixel circuit layer (PCL) may include signal lines connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, such as gate lines, light emission control lines, and data lines. The wiring may also include connections to... Figure 2 The wiring for the first power supply voltage node VDDN. Additionally, the wiring may include connections to... Figure 2 Wiring of the second power supply voltage node VSSN.

[0279] The light-emitting element layer (LDL) may include an anode electrode (AE), a pixel-defining layer (PDL), a light-emitting structure (EMS), and a cathode electrode (CE).

[0280] The anode electrode AE ​​can be disposed on the pixel circuit layer PCL. The anode electrode AE ​​can contact the circuit elements of the pixel circuit layer PCL. The anode electrode AE ​​can include an opaque conductive material capable of reflecting light, but the disclosure is not limited thereto.

[0281] A pixel defining layer (PDL) is disposed on the anode electrode AE. The PDL may define an opening OP that exposes a portion of each of the anode electrodes AE. The opening OP of the PDL may define light-emitting regions corresponding to the first sub-pixels SP1 through SP3, respectively. In an alternative embodiment, it is understood that the light-emitting regions corresponding to the first sub-pixels SP1 through SP3 are defined according to the anode electrode AE. In regions adjacent to the boundaries of mutually adjacent sub-pixels, the PDL may include separators that cause discontinuities to be formed in the light-emitting structure EMS. In this case, it is understood that the light-emitting regions corresponding to the first sub-pixels SP1 through SP3 are defined according to the separators of the PDL.

[0282] In an embodiment, the pixel defining layer (PDL) may include an inorganic material. In this case, the pixel defining layer (PDL) may include multiple stacked inorganic layers. For example, in an embodiment, the pixel defining layer (PDL) may include silicon oxide (SiO2). x (x is a positive number) and silicon nitride (SiN) x In some other embodiments, the pixel defining layer (PDL) may include an organic material. However, the material of the pixel defining layer (PDL) is not limited to this.

[0283] The light-emitting structure (EMS) can be disposed on the anode electrode (AE) exposed by the opening (OP) of the pixel-defining layer (PDL). The light-emitting structure (EMS) may include a light-emitting layer for generating light, an electron transport layer for transporting electrons, and a hole transport layer for transporting holes, etc.

[0284] In an embodiment, the light-emitting structure EMS fills the opening OP of the pixel-defining layer PDL, but may be disposed entirely on top of the pixel-defining layer PDL. In other words, the light-emitting structure (also called the luminescent structure) EMS may extend above the first sub-pixels SP1 to the third sub-pixels SP3. In this case, at least some layers in the light-emitting structure EMS may be broken or bent at the boundary between the first sub-pixels SP1 and the third sub-pixels SP3. However, the embodiment is not limited to this. In an embodiment, for example, the portions of the light-emitting structure EMS corresponding to the first sub-pixels SP1 to the third sub-pixels SP3 are separated from each other, and each of them may be disposed in the opening OP of the pixel-defining layer PDL.

[0285] The cathode electrode CE can be disposed on the light-emitting structure EMS. The cathode electrode CE can extend from the first sub-pixel SP1 to the third sub-pixel SP3. In this way, the cathode electrode CE can be configured as a common electrode for the first sub-pixel SP1 to the third sub-pixel SP3.

[0286] The cathode electrode CE can be a thin metal layer with a thickness sufficient to transmit light emitted from the light-emitting structure EMS. The cathode electrode CE can comprise, or be composed of, a metallic material or a transparent conductive material to have a relatively small thickness. In embodiments, the cathode electrode CE can comprise at least one of a variety of transparent conductive materials, including indium tin oxide (“ITO”), indium zinc oxide (“IZO”), indium tin zinc oxide (“ITZO”), zinc aluminum oxide (“AZO”), zinc gallium oxide (“GZO”), zinc tin oxide (“TZO”), or tin gallium oxide (“GTO”). In some other embodiments, the cathode electrode CE can comprise at least one of silver (Ag), magnesium (Mg), and combinations thereof. However, the material of the cathode electrode CE is not limited thereto.

[0287] Any one of the anode electrodes AE, the portion of the light-emitting structure EMS superimposed on the anode electrode AE, and the portion of the cathode electrode CE superimposed on the anode electrode AE ​​can be understood as constituting a light-emitting element LD (refer to...). Figure 2 In other words, the light-emitting elements of the first sub-pixel SP1 to the third sub-pixel SP3 may each include an anode electrode, a portion of the light-emitting structure EMS superimposed on the anode electrode, and a portion of the cathode electrode CE superimposed on the anode electrode. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transferred to the light-emitting layer of the light-emitting structure EMS to form excitons, and light can be generated when the excitons transition from the excited state to the ground state. The brightness of the light can be determined based on the amount of current flowing through the light-emitting layer. The wavelength range of the generated light can be determined based on the structure of the light-emitting layer.

[0288] A sealing layer (also called an encapsulation layer) TFE is disposed on the cathode electrode CE. The encapsulation layer TFE may cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE prevents oxygen or moisture from penetrating into the light-emitting element layer LDL. In embodiments, the encapsulation layer TFE may comprise a structure of one or more inorganic films and one or more organic films stacked alternately. In embodiments, for example, the inorganic films may comprise silicon nitride, silicon oxide, or silicon oxynitride (SiO2). x N y (x and y are positive numbers), etc. In embodiments, for example, the organic film may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polymethylene sulfide resin, or benzocyclobutene (“BCB”) resin. However, the materials of the organic and inorganic films of the encapsulation layer TFE are not limited thereto.

[0289] To improve the encapsulation efficiency of the TFE encapsulation layer, the TFE encapsulation layer may also include aluminum oxide (AlO2). x A thin film, including aluminum oxide, can be disposed on the upper surface of the encapsulation layer TFE facing the optical functional layer OFL and / or on the lower surface of the encapsulation layer TFE facing the light-emitting element layer LDL.

[0290] Thin films comprising or composed of alumina can be formed by atomic layer deposition (“ALD”). However, embodiments are not limited thereto. The encapsulation layer TFE may also comprise a thin film comprising or composed of at least one of a variety of materials suitable for improving encapsulation efficiency.

[0291] The optical functional layer (OFL) is disposed on the encapsulation layer (TFE). The optical functional layer (OFL) may include a color filter layer (CFL) and a lens array (LA).

[0292] A color filter layer (CFL) is disposed between the encapsulation layer (TFE) and the lens array (LA). The CFL filters light emitted from the light-emitting structure (EMS) to selectively output light of a wavelength range or color corresponding to each sub-pixel. The CFL includes color filters (CFs) corresponding to first sub-pixels SP1 through third sub-pixels SP3, each of which allows light within its corresponding wavelength range to pass through. In an embodiment, for example, the color filter corresponding to the first sub-pixel SP1 allows red light to pass through, the color filter corresponding to the second sub-pixel SP2 allows green light to pass through, and the color filter corresponding to the third sub-pixel SP3 allows blue light to pass through. Depending on the light emitted from the light-emitting structure (EMS) of each sub-pixel, at least a portion of the color filters (CFs) may be omitted.

[0293] A lens array LA is disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first sub-pixels SP1 through SP3, respectively. Each of the lenses LS can output light emitted from the light-emitting structure EMS in the intended path, thereby improving light emission efficiency. The lens array LA may have a relatively high refractive index. In an embodiment, for example, the lens array LA may have a higher refractive index than the coating layer OC. In an embodiment, the lenses LS may include organic materials. In an embodiment, the lenses LS may include acrylic materials. However, the materials of the lenses LS are not limited to these.

[0294] In an embodiment, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA may be offset in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2, relative to the opening OP of the pixel defining layer PDL. Specifically, in the central region of the display area DA, when viewed in the third direction DR3, the center of the color filter and the center of the lens may be aligned with or superimposed on the center of the opening OP of the corresponding pixel defining layer PDL. In an embodiment, for example, in the central region of the display area DA, the opening OP of the pixel defining layer PDL may be completely superimposed on the corresponding color filter of the color filter layer CFL and the corresponding lens of the lens array LA. In the region of the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3, the center of the color filter and the center of the lens may be offset from the center of the opening OP of the corresponding pixel defining layer PDL in a planar direction. In an embodiment, for example, in a region immediately adjacent to (near) the non-display region NDA within the display region DA, the opening OP of the pixel defining layer PDL can be partially superimposed with the corresponding color filter of the color filter layer CFL and the corresponding lens of the lens array LA. Therefore, at the center of the display region DA, light emitted from the light-emitting structure EMS can be effectively output in a direction perpendicular to the display surface. Outside the display region DA, light emitted from the light-emitting structure EMS can be effectively output in a direction tilted at a predetermined angle relative to the normal direction of the display surface.

[0295] A coating layer OC can be disposed on the lens array LA. The coating layer OC can cover the optical functional layer OFL, the encapsulation layer TFE, the light-emitting structure EMS, and / or the pixel circuit layer PCL. The coating layer OC can include various materials suitable for protecting the underlying layers from foreign matter such as dust and moisture. In embodiments, for example, the coating layer OC can include at least one of inorganic and organic insulating films. In embodiments, for example, the coating layer OC can include, but is not limited to, epoxy resin. The coating layer OC can have a lower refractive index than the lens array LA.

[0296] A cover window (CW) may be disposed on the coating layer (OC). The cover window (CW) protects the layer beneath it. The cover window (CW) may have a higher refractive index than the coating layer (OC). The cover window (CW) may include glass, but the disclosure is not limited thereto. In embodiments, for example, the cover window (CW) may be encapsulation glass protecting components disposed beneath it. In some other embodiments, the cover window (CW) may be omitted.

[0297] Figure 20 It is shown Figure 19 A plan view of any one of the pixels in the embodiment.

[0298] exist Figure 20 For clarity and conciseness, the diagram is shown schematically. Figure 19 The first pixel PXL1 is one of the first pixels PXL1 and the second pixel PXL2. The remaining pixels can be constructed similarly to the first pixel PXL1.

[0299] Reference Figure 19 and Figure 20 The first pixel PXL1 may include the first sub-pixel SP1 to the third sub-pixel SP3 arranged on the first direction DR1.

[0300] The first sub-pixel SP1 may include a first light-emitting region EMA1 and a non-light-emitting region NEA surrounding the first light-emitting region EMA1. The second sub-pixel SP2 may include a second light-emitting region EMA2 and a non-light-emitting region NEA surrounding the second light-emitting region EMA2. The third sub-pixel SP3 may include a third light-emitting region EMA3 and a non-light-emitting region NEA surrounding the third light-emitting region EMA3.

[0301] The first luminescent region EMA1 can be derived from the luminescent structure EMS (see reference). Figure 19 The first light-emitting region EMA2 can be the region of the light-emitting structure EMS that emits light corresponding to the second sub-pixel SP1. The second light-emitting region EMA2 can be the region of the light-emitting structure EMS that emits light corresponding to the second sub-pixel SP2. The third light-emitting region EMA3 can be the region of the light-emitting structure EMS that emits light corresponding to the third sub-pixel SP3.

[0302] Figure 21 It is based on the publicly available information along Figure 20 A cross-sectional view taken along line I-I' of an embodiment.

[0303] Reference Figure 21 Set up a base SUB and a pixel circuit layer PCL set on the base SUB.

[0304] The substrate SUB may include a silicon wafer substrate formed using semiconductor processes. In embodiments, for example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0305] A pixel circuit layer (PCL) is disposed on a substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the first sub-pixels SP1 to the third sub-pixels SP3. In an embodiment, for example, the substrate SUB and the pixel circuit layer PCL may include transistor T_SP1 for the first sub-pixel SP1, transistor T_SP2 for the second sub-pixel SP2, and transistor T_SP3 for the third sub-pixel SP3. Transistor T_SP1 for the first sub-pixel SP1 may be a sub-pixel circuit SPC (see reference) included in the first sub-pixel SP1. Figure 2The transistor T_SP2 of the second sub-pixel SP2 can be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 can be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 21 For clarity and brevity, only one transistor of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0306] The transistor T_SP1 of the first sub-pixel SP1 may include the source region SRA, the drain region DRA, and the gate electrode GE.

[0307] The source region (SRA) and drain region (DRA) can be disposed within the substrate (SUB). A well (WL) formed by ion implantation is disposed within the substrate (SUB), and the source region (SRA) and drain region (DRA) can be spaced apart from each other within the well (WL). The region between the source region (SRA) and drain region (DRA) within the well (WL) can be defined as a channel region. The gate electrode (GE) is stacked with the channel region between the source region (SRA) and drain region (DRA) and can be disposed within the pixel circuit layer (PCL). The gate electrode (GE) can be spaced apart from the well (WL) or channel region by an insulating material such as a gate insulating layer (GI). The gate electrode (GE) can include a conductive material.

[0308] The multiple layers included in the pixel circuit layer PCL include insulating layers and conductive patterns disposed between the insulating layers, and such conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 can be electrically connected to the drain region DRA via a drain connector DRC through one or more insulating layers. The second conductive pattern CP2 can be electrically connected to the source region SRA via a source connector SRC through one or more insulating layers.

[0309] In this embodiment, the first conductive pattern CP1 and the second conductive pattern CP2 may include the above-described... Figure 6 and Figure 7 The electrode layer SD.

[0310] When the gate electrode GE and the first conductive pattern CP1 and the second conductive pattern CP2 are connected to other circuit elements and / or wiring, the transistor T_SP1 of the first sub-pixel SP1 can be set to any one of the transistors of the first sub-pixel SP1.

[0311] The transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 can be constructed similarly to the transistor T_SP1 of the first sub-pixel SP1.

[0312] Thus, the substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the first sub-pixels SP1 to the third sub-pixels SP3.

[0313] A via layer (VIAL) is disposed on the pixel circuit layer (PCL). The via layer (VIAL) covers the pixel circuit layer (PCL) but can have an overall flat surface. The via layer (VIAL) flattens the steps on the pixel circuit layer (PCL). The via layer (VIAL) can be, but is not limited to, silicon oxide (SiO2). x Silicon nitride (SiN) x At least one of silicon carbonitride (SiCN).

[0314] The light-emitting element layer (LDL) is disposed on the via layer (VIAL). The light-emitting element layer (LDL) may include a first reflective electrode (RE1) to a third reflective electrode (RE3), a planarization layer (PLNL), a first anode electrode (AE1) to a third anode electrode (AE3), a pixel definition layer (PDL), a light-emitting structure (EMS), and a cathode electrode (CE).

[0315] On the via layer VIAL, the first reflective electrode RE1 to the third reflective electrode RE3 are respectively arranged in the first sub-pixel SP1 to the third sub-pixel SP3. Each of the first reflective electrode RE1 to the third reflective electrode RE3 can contact a circuit element disposed in the pixel circuit layer PCL through a via (not shown) penetrating the via layer VIAL.

[0316] The first reflecting electrodes RE1 to the third reflecting electrodes RE3 can be used as total reflection mirrors to reflect light emitted from the light-emitting structure EMS toward the display surface (or the cover window CW). The first reflecting electrodes RE1 to the third reflecting electrodes RE3 may include metallic materials suitable for reflecting light. The first reflecting electrodes RE1 to the third reflecting electrodes RE3 may include, but are not limited to, at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more materials selected from them.

[0317] In an embodiment, a connecting electrode (not shown) may be disposed below each of the first to third reflective electrodes RE1 to RE3. The connecting electrode can improve the electrical connection characteristics between the reflective electrode and the circuit elements of the pixel circuit layer PCL. The connecting electrode may have a multilayer structure. The multilayer structure may include, but is not limited to, titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN). In an embodiment, the corresponding reflective electrode may be disposed between multiple layers of the connecting electrode.

[0318] A buffer pattern BFP may be disposed below at least one of the first reflective electrodes RE1 to the third reflective electrode RE3. The buffer pattern BFP may include, but is not limited to, inorganic materials such as, but not limited to, silicon carbonitride. By arranging the buffer pattern BFP, the height of the reflective electrode on the third-direction DR3 can be adjusted. In an embodiment, for example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0319] The first reflecting electrodes RE1 to the third reflecting electrodes RE3 can be used as total reflection mirrors, and the cathode electrode CE can be used as a half-reflection mirror. In an embodiment, for example, each of the first reflecting electrodes RE1 to the third reflecting electrodes RE3 and the cathode electrode CE can provide a resonant structure in the sub-pixel. Light emitted from the light-emitting layer of the light-emitting structure EMS can be amplified by reciprocating between the corresponding reflecting electrode and the cathode electrode CE, and the amplified light can be output through the cathode electrode CE. Thus, the distance between each reflecting electrode and the cathode electrode CE can be understood as the resonant distance of the light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0320] Due to the buffer pattern BFP, the first sub-pixel SP1 can have a shorter resonant distance than other sub-pixels. This adjusted resonant distance allows light within a specific wavelength range (e.g., red) to be effectively and efficiently amplified. Therefore, the first sub-pixel SP1 can effectively and efficiently output light within the corresponding wavelength range.

[0321] Although the buffer pattern BFP is in Figure 21 The buffer pattern BFP is shown as being disposed in the first sub-pixel SP1 but not in the second sub-pixels SP2 and SP3, but the disclosure is not limited thereto. The buffer pattern BFP may also be disposed in at least one of the second sub-pixels SP2 and SP3 to adjust the resonant distance of at least one of the second sub-pixels SP2 and SP3. In an embodiment, for example, the first sub-pixels SP1 to SP3 correspond to red, green, and blue, respectively; the distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE; and the distance between the second reflective electrode RE2 and the cathode electrode CE may be smaller than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0322] To planarize the step between the first reflective electrode RE1 and the third reflective electrode RE3, a planarization layer PLNL can be provided on the via layer VIAL and the first reflective electrode RE1 to the third reflective electrode RE3. The planarization layer PLNL typically covers the first reflective electrode RE1 to the third reflective electrode RE3 and the via layer VIAL, but can have a flat surface. In this embodiment, the planarization layer PLNL can be omitted.

[0323] On the planarization layer PLNL, first anode electrodes AE1 to third anode electrodes AE3 are respectively stacked with first reflective electrodes RE1 to third reflective electrodes RE3. When viewed on a third-direction DR3, the first anode electrodes AE1 to third anode electrodes AE3 can have the same characteristics as... Figure 20 The first light-emitting regions EMA1 to the third light-emitting regions EMA3 have similar shapes. The first anode electrode AE1 to the third anode electrode AE3 are respectively connected to the first reflective electrode RE1 to the third reflective electrode RE3. The first anode electrode AE1 can be connected to the first reflective electrode RE1 via a first via VIA1 through the planarization layer PLNL. The second anode electrode AE2 can be connected to the second reflective electrode RE2 via a second via VIA2 through the planarization layer PLNL. The third anode electrode AE3 can be connected to the third reflective electrode RE3 via a third via VIA3 through the planarization layer PLNL.

[0324] In embodiments, the first anode electrode AE1 to the third anode electrode AE3 may comprise at least one of a transparent conductive material such as indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium gallium zinc oxide (“IGZO”), and indium tin zinc oxide (“ITZO”). However, the materials of the first anode electrode AE1 to the third anode electrode AE3 are not limited thereto. In embodiments, for example, the first anode electrode AE1 to the third anode electrode AE3 may comprise titanium nitride.

[0325] A pixel-defining layer (PDL) is disposed on a portion of the first anode electrode AE1 to the third anode electrode AE3 and the planarization layer PLNL. The PDL defines an opening OP that exposes a portion of each of the first anode electrode AE1 to the third anode electrode AE3. The region superimposed on the PDL can be understood as the boundary region BDA between adjacent (neighboring) subpixels.

[0326] In an embodiment, the pixel defining layer (PDL) may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO2). x ) and silicon nitride (SiN) xAt least one of the following. In an embodiment, for example, the pixel defining layer PDL may include a first inorganic insulating layer ISL1, a second inorganic insulating layer ISL2, and a third inorganic insulating layer ISL3 stacked sequentially. The first inorganic insulating layer ISL1 to the third inorganic insulating layer ISL3 may include, but are not limited to, silicon nitride and silicon oxide. The first inorganic insulating layer ISL1 to the third inorganic insulating layer ISL3 may have a stepped profile in the region immediately adjacent to (near) the opening OP.

[0327] The pixel-defined layer (PDL) may include separators (SPRs) in the boundary regions (BDAs) between adjacent (nearby) subpixels. In other words, the separators (SPRs) can be set... Figure 18 In each of the boundary regions between sub-pixels SP.

[0328] The separator SPR can cause discontinuities to form in the light-emitting structure EMS within the boundary region BDA. In embodiments, for example, the light-emitting structure EMS can be broken or bent within the boundary region BDA by means of the separator SPR. Therefore, the boundary region PDL can be defined according to the separator SPR. Figure 20 The first light-emitting area EMA1 to the third light-emitting area EMA3 respectively correspond to the first sub-pixel SP1 to the third sub-pixel SP3.

[0329] The separator SPR can be disposed in or on the pixel-defining layer PDL. The pixel-defining layer PDL can include one or more trenches TRCH1 and TRCH2 as separator SPRs in the boundary region BDA. In an embodiment, as... Figure 21 As shown, one or more trenches TRCH1 and TRCH2 can penetrate the pixel defining layer PDL and partially penetrate the planarization layer PLNL. In some other embodiments, one or more trenches TRCH1 and TRCH2 can penetrate the pixel defining layer PDL and the planarization layer PLNL, and partially penetrate the via layer VIAL. In some other embodiments, one or more trenches TRCH1 and TRCH2 at least partially penetrate the planarization layer PLNL and / or the via layer VIAL, and a portion of the pixel defining layer PDL can be disposed within one or more of the trenches TRCH1 and TRCH2.

[0330] exist Figure 21 The diagram illustrates two trenches, TRCH1 and TRCH2, within the boundary region BDA. However, the disclosure is not limited thereto. In one embodiment, for example, the pixel-defining layer PDL may include one trench within the boundary region BDA. In an alternative embodiment, the pixel-defining layer PDL may include three or more trenches within the boundary region BDA.

[0331] Due to the first trench TRCH1 and the second trench TRCH2, discontinuous portions such as the first aperture VD1 and the second aperture VD2 in the boundary region BDA can be defined within the light-emitting structure EMS. Some of the multiple layers stacked in the light-emitting structure EMS can be broken or bent due to the first aperture VD1 and the second aperture VD2. In an embodiment, for example, at least one charge-generating layer and at least one hole-injecting layer included in the light-emitting structure EMS can be broken at the first aperture VD1 and the second aperture VD2. Thus, due to the first trench TRCH1 and the second trench TRCH2, a portion of the light-emitting structure EMS included in the first sub-pixel SP1 to the third sub-pixel SP3 can be at least partially separated.

[0332] Depending on the shape of the first trench TRCH1 and the second trench TRCH2, the discontinuous portions formed in the light-emitting structure EMS can vary.

[0333] In this embodiment, the light-emitting structure EMS can be formed by processes such as vacuum deposition or inkjet printing. In this case, the same material as the light-emitting structure EMS can be disposed on the bottom surface of the via layer VIAL adjacent to the first trench TRCH1 and the second trench TRCH2.

[0334] The pixel defining layer (PDL) may include additional separators, such that the light-emitting structure (EMS) also includes discontinuous portions adjacent to the boundary region (BDA). In an embodiment, although not shown, the uppermost of the first inorganic insulating layers (ISL1) to the third inorganic insulating layers (ISL3) of the pixel defining layer (PDL), the third inorganic insulating layer (ISL3), may have a width wider than the second inorganic insulating layer (ISL2) directly below it. In an embodiment, for example, the pixel defining layer (PDL) may have a "T"-shaped or "I"-shaped cross-section in the boundary region (BDA). Depending on the shape of the pixel defining layer (PDL), the multiple layers included in the light-emitting structure (EMS) may be at least partially broken or bent in the boundary region (BDA) or in a region adjacent to the boundary region (BDA).

[0335] The light-emitting structure EMS can be disposed on the anode electrodes AE1, AE2, and AE3 exposed by the opening OP of the pixel-defining layer PDL. The light-emitting structure EMS fills the opening OP of the pixel-defining layer PDL and can be disposed throughout the entire first sub-pixel SP1 to the third sub-pixel SP3. As explained above, the light-emitting structure EMS can be at least partially broken or bent in the boundary region BDA by the separator SPR. Therefore, during the operation of the display panel DP, the current flowing from each of the first sub-pixels SP1 to the third sub-pixel SP3 through the layer included in the light-emitting structure EMS to the immediately adjacent (neighboring) sub-pixel can be reduced. Therefore, the first light-emitting elements LD1 to the third light-emitting elements LD3 can operate with relatively high reliability.

[0336] The cathode electrode CE can be disposed on the light-emitting structure EMS. The cathode electrode CE can be disposed in common for the first sub-pixel SP1 to the third sub-pixel SP3. The cathode electrode CE can be used as a semi-reflective mirror to partially transmit and partially reflect light emitted from the light-emitting structure EMS.

[0337] The first anode electrode AE1, the portion of the light-emitting structure EMS superimposed on the first anode electrode AE1, and the portion of the cathode electrode CE superimposed on the first anode electrode AE1 can constitute the first light-emitting element LD1. The second anode electrode AE2, the portion of the light-emitting structure EMS superimposed on the second anode electrode AE2, and the portion of the cathode electrode CE superimposed on the second anode electrode AE2 can constitute the second light-emitting element LD2. The third anode electrode AE3, the portion of the light-emitting structure EMS superimposed on the third anode electrode AE3, and the portion of the cathode electrode CE superimposed on the third anode electrode AE3 can constitute the third light-emitting element LD3.

[0338] The TFE encapsulation layer is disposed on the cathode electrode CE. The TFE encapsulation layer prevents oxygen and / or moisture from penetrating into the light-emitting element layer LDL.

[0339] An optical functional layer (OFL) is disposed on the encapsulation layer TFE. In one embodiment, the optical functional layer OFL can be attached to the encapsulation layer TFE via an adhesive layer APL. In another embodiment, for example, the optical functional layer OFL can be manufactured separately and attached to the encapsulation layer TFE via the adhesive layer APL. The adhesive layer APL can also be used to protect the underlying layers including the encapsulation layer TFE.

[0340] The optical functional layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include first color filters CF1 to third color filters CF3, respectively, corresponding to first sub-pixels SP1 to third sub-pixels SP3. The first color filters CF1 to third color filters CF3 can allow light of different wavelength ranges to pass through. In an embodiment, for example, the first color filters CF1 to third color filters CF3 can allow red, green, and blue light to pass through, respectively.

[0341] In one embodiment, the first color filter CF1 to the third color filter CF3 may be partially stacked in the boundary region BDA. In other embodiments, the first color filter CF1 to the third color filter CF3 are spaced apart from each other, and the black matrix may be disposed between the first color filter CF1 to the third color filter CF3.

[0342] A lens array LA is disposed on the color filter layer CFL. The lens array LA may include a first lens LS1 to a third lens LS3 corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. Each of the first lens LS1 to the third lens LS3 outputs light emitted from the first light-emitting element LD1 to the third light-emitting element LD3 along a predetermined path, thereby improving light emission efficiency.

[0343] The coating layer OC can be placed on the lens array LA. The coating layer OC protects its underlying layer from foreign matter such as dust and moisture. The cover window CW can be placed on the coating layer OC.

[0344] Figure 22 It is based on the publicly available information along Figure 20 A cross-sectional view taken along line I-I' of an embodiment. Figure 23 It is shown Figure 22 A magnified view of region A.

[0345] Reference Figure 22 The pixel circuit layer PCL and the via layer VIAL are set on the substrate SUB. Figure 22 The substrate SUB, pixel circuit layer PCL, and via layer VIAL are respectively connected to... Figure 21 The substrate SUB, pixel circuit layer PCL, and via layer VIAL are constructed similarly. Repeated descriptions will be omitted below.

[0346] The light-emitting element layer LDL' is disposed on the via layer VIAL. The light-emitting element layer LDL' may include a first reflective electrode RE1' to a third reflective electrode RE3', a first buffer pattern BFP1' and a second buffer pattern BFP2', a first cover pattern CVP1 to a third cover pattern CVP3, a first anode electrode AE1' to a third anode electrode AE3', a pixel defining layer PDL', a light-emitting structure EMS', and a cathode electrode CE.

[0347] On the via layer VIAL, the first reflective electrode RE1' to the third reflective electrode RE3' are respectively arranged in the first sub-pixel SP1 to the third sub-pixel SP3. Each of the first reflective electrode RE1' to the third reflective electrode RE3' can contact a circuit element disposed in the pixel circuit layer PCL through a via (not shown) penetrating the via layer VIAL.

[0348] The first reflective electrodes RE1' to the third reflective electrodes RE3' reflect light emitted from the light-emitting structure EMS' toward the display surface (or the cover window CW). The first reflective electrodes RE1' to the third reflective electrodes RE3' may include metallic materials suitable for reflecting light. The first reflective electrodes RE1' to the third reflective electrodes RE3' may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more materials selected from them, but are not limited thereto.

[0349] In an embodiment, a connecting electrode (not shown) may also be provided between each of the first reflective electrode RE1' to the third reflective electrode RE3' and the via layer VIAL. The connecting electrode can improve the electrical connection characteristics between the reflective electrode and the circuit elements of the pixel circuit layer PCL. The connecting electrode can have a multilayer structure. The multilayer structure may include, but is not limited to, titanium (Ti), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), etc. In an embodiment, the corresponding reflective electrode can be disposed between multiple layers of the connecting electrode.

[0350] A buffer pattern can be disposed on at least one of the first reflective electrode RE1' to the third reflective electrode RE3'. In an embodiment, the first buffer pattern BFP1' and the second buffer pattern BFP2' can be disposed on the first reflective electrode RE1' and the third reflective electrode RE3', respectively. The heights of the first anode electrode AE1' and the third anode electrode AE3' on the third-direction DR3 can be adjusted by the first buffer pattern BFP1' and the second buffer pattern BFP2'. The first buffer pattern BFP1' and the second buffer pattern BFP2' may include, but are not limited to, silicon oxide (SiO2). x ) and silicon nitride (SiN) x Inorganic materials.

[0351] First cover patterns CVP1 to third cover patterns CVP3 can be respectively disposed on first reflective electrodes RE1' to third reflective electrodes RE3'. In the first sub-pixel SP1, the first cover pattern CVP1 is disposed on the first reflective electrode RE1' and the first buffer pattern BFP1'. In the second sub-pixel SP2, the second cover pattern CVP2 is disposed on the second reflective electrode RE2'. In the third sub-pixel SP3, the third cover pattern CVP3 is disposed on the third reflective electrode RE3' and the second buffer pattern BFP2'. The first cover patterns CVP1 to third cover patterns CVP3 can be formed during the manufacturing process after the formation of the first buffer pattern BFP1' and the second buffer pattern BFP2'. The first cover patterns CVP1 to third cover patterns CVP3 can include the same material as the first buffer pattern BFP1' and the second buffer pattern BFP2'. In embodiments, for example, the first cover patterns CVP1 to third cover patterns CVP3 can include silicon oxide (SiO2). x ) and silicon nitride (SiN) x ( ) inorganic materials, but the disclosure is not limited to this.

[0352] The first anode electrode AE1' to the third anode electrode AE3' are respectively disposed on the first cover pattern CVP1 to the third cover pattern CVP3. In an embodiment, the first anode electrode AE1' may cover the first cover pattern CVP1, the first buffer pattern BFP1', and the first reflective electrode RE1'. The second anode electrode AE2' may cover the second cover pattern CVP2 and the second reflective electrode RE2'. The third anode electrode AE3' may cover the third cover pattern CVP3, the second buffer pattern BFP2', and the third reflective electrode RE3'.

[0353] The first anode electrode AE1' to the third anode electrode AE3' can be electrically connected to the first reflective electrode RE1' to the third reflective electrode RE3', respectively. In an embodiment, for example, each anode electrode can be connected to an end (or edge) of the reflective electrode. However, the embodiment is not limited to this. To improve the electrical connection characteristics between the anode electrode and the reflective electrode, the anode electrode can be connected to the reflective electrode in various ways.

[0354] In the embodiments, the first anode electrode AE1' to the third anode electrode AE3' may include, for example, indium tin oxide (“ITO”), indium zinc oxide (“IZO”), and zinc oxide (ZnO). x At least one of the following transparent conductive materials: indium gallium zinc oxide (“IGZO”), indium tin zinc oxide (“ITZO”), and zinc oxide (“ZnO”). xThe anode material can be ZnO. However, the materials of the first anode electrode AE1' to the third anode electrode AE3' are not limited thereto. In embodiments, for example, the first anode electrode AE1' to the third anode electrode AE3' may include titanium nitride.

[0355] When viewed on a third-party DR3, the first anode electrode AE1' to the third anode electrode AE3' can have the same characteristics as... Figure 20 The first luminous region EMA1 to the third luminous region EMA3 have similar shapes.

[0356] The first anode electrodes AE1' to the third anode electrodes AE3' and the cathode electrode CE can partially reflect the incident light. Light emitted from the light-emitting layer of the light-emitting structure EMS' is amplified by circling back and forth between the corresponding anode electrode and the cathode electrode CE, and can be output through the cathode electrode CE. In an embodiment, for example, each anode electrode and cathode electrode CE can provide a resonant structure in the sub-pixel. In this case, the distance between each anode electrode and the cathode electrode CE can be understood as the resonant distance of the light emitted from the light-emitting layer of the corresponding light-emitting structure EMS'.

[0357] The first sub-pixel SP1 to the third sub-pixel SP3 can correspond to red, green, and blue, respectively. In this case, by means of the first buffer pattern BFP1' and the second buffer pattern BFP2', the heights of the first anode electrode AE1' and the third anode electrode AE3' on the third-direction DR3 can be higher than those of the second anode electrode AE2'. Therefore, the first sub-pixel SP1 and the third sub-pixel SP3 can have shorter resonant distances than the second sub-pixel SP2 due to the first buffer pattern BFP1' and the second buffer pattern BFP2'. In this way, the resonant distance of each sub-pixel can be adjusted so that light in the wavelength range of the corresponding color is effectively and efficiently amplified.

[0358] exist Figure 22In the diagram, the first buffer pattern BFP1' and the second buffer pattern BFP2' are shown as being disposed below the first anode electrode AE1' and the third anode electrode AE3', respectively, but the disclosure is not limited thereto. In one embodiment, for example, one of the first buffer pattern BFP1' and the second buffer pattern BFP2' may be omitted. In another embodiment, both the first buffer pattern BFP1' and the second buffer pattern BFP2' may be omitted. In this case, the resonant distances between the respective anode electrodes and the cathode electrode CE may be equal to each other. In another embodiment, the buffer patterns may be disposed below each of the first anode electrodes AE1' to the third anode electrodes AE3'. In this case, the buffer patterns disposed at the bottom of each anode electrode may have different thicknesses, so the resonant distances between the respective anode electrodes and the cathode electrode CE may be different from each other. In this way, by providing buffer patterns for adjusting the height of at least one of the first anode electrodes AE1' to the third anode electrodes AE3', the resonant distance in each sub-pixel can be optimized.

[0359] A pixel defining layer PDL' is disposed on a portion of the first anode electrode AE1' to the third anode electrode AE3' and the via layer VIAL. The pixel defining layer PDL' defines an opening OP' that exposes a portion of each of the first anode electrode AE1' to the third anode electrode AE3'. The area superimposed on the pixel defining layer PDL' can be understood as the boundary region BDA between adjacent (neighboring) subpixels.

[0360] The pixel-defining layer (PDL) may include multiple inorganic insulating layers stacked sequentially. Each of the multiple inorganic insulating layers may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x At least one of the following. However, the embodiments are not limited thereto. In an embodiment, for example, the pixel defining layer PDL' may include an organic insulating layer.

[0361] In an embodiment, the pixel defining layer PDL' may include a first inorganic insulating layer ISL1' to a fourth inorganic insulating layer ISL4'. The first inorganic insulating layer ISL1' may cover a portion of the first anode electrode AE1' to the third anode electrode AE3' and the via layer VIAL. A second inorganic insulating layer ISL2' is disposed on the first inorganic insulating layer ISL1', a third inorganic insulating layer ISL3' is disposed on the second inorganic insulating layer ISL2', and a fourth inorganic insulating layer ISL4' is disposed on the third inorganic insulating layer ISL3'. The first inorganic insulating layer ISL1' and the third inorganic insulating layer ISL3' may include silicon nitride (SiN). x The second inorganic insulating layer ISL2' and the fourth inorganic insulating layer ISL4' may include silicon oxide (SiO2). xHowever, the disclosure is not limited thereto. In the embodiments, the first inorganic insulating layer ISL1' may be omitted.

[0362] The pixel-defining layer (PDL) may include separators (SPRs) in the boundary regions (BDAs) between adjacent (nearby) subpixels. The separators (SPRs) may result in discontinuous portions, such as apertures (VDs), defined within the light-emitting structure (EMS). Due to these discontinuous portions, at least some of the multiple layers included in the light-emitting structure (EMS) may be broken or bent.

[0363] The fourth inorganic insulating layer ISL4' may have a width wider than the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3'. In this case, the side of the adjacent (proximate) opening OP' between the second inorganic insulating layer ISL2' and the fourth inorganic insulating layer ISL4' may be configured as a separator SPR'.

[0364] and Figure 22 Refer to together Figure 23 The fourth inorganic insulating layer ISL4' may include a first portion P1 to a third portion P3. A second portion P2 may completely overlap with the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3'. The first portion P1 protrudes from the second portion P2 in a direction opposite to the first direction DR1. The third portion P3 protrudes from the second portion P2 in the first direction DR1. Thus, the width of the fourth inorganic insulating layer ISL4' may be wider than the widths of the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3'. In embodiments, for example, during the manufacturing process, the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' may be undercut to exclude the portions overlapping with the first portion P1 and the third portion P3. In embodiments, for example, each of the first portion P1 and the third portion P3 of the fourth inorganic insulating layer ISL4' may have an overhang shape on the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3'.

[0365] In the boundary region BDA, the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' may have the same width. However, the disclosure is not limited thereto, and the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' may have different widths. In one embodiment, for example, the second inorganic insulating layer ISL2' may have a wider width than the third inorganic insulating layer ISL3'. In another embodiment, the third inorganic insulating layer ISL3' may have a wider width than the second inorganic insulating layer ISL2'.

[0366] In the second sub-pixel SP2, the first portion P1 of the fourth inorganic insulating layer ISL4' and the first side SSF1 of the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' can be configured as a separator SPR'. Therefore, a first aperture VD1' can be defined in the light-emitting structure EMS' adjacent to the first portion P1 of the fourth inorganic insulating layer ISL4'. In the third sub-pixel SP3, the third portion P3 of the fourth inorganic insulating layer ISL4' and the second side SSF2 of the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' can be configured as another separator SPR'. Therefore, a second aperture VD2' can be defined in the light-emitting structure EMS' adjacent to the third portion P3 of the fourth inorganic insulating layer ISL4'.

[0367] Some of the multiple layers stacked in the light-emitting structure EMS' may be broken or bent due to the first aperture VD1' and the second aperture VD2'. In an embodiment, for example, at least one charge-generating layer and at least one hole-injecting layer included in the light-emitting structure EMS' may be interrupted by the first aperture VD1' and the second aperture VD2'. Thus, due to the separator SPR', portions of the light-emitting structure EMS' included in the first sub-pixel SP1 to the third sub-pixel SP3 can be at least partially separated from each other.

[0368] The pixel-defining layer (PDL) may include additional spacers, such that the light-emitting structure (EMS) may also include discontinuous portions in the boundary region (BDA). In an embodiment, the pixel-defining layer (PDL) may include one or more trenches as spacers in the boundary region (BDA). The trenches may penetrate one or more of the first inorganic insulating layers (ISL1) to the fourth inorganic insulating layers (ISL4). Due to the trenches, some of the multiple layers stacked in the light-emitting structure (EMS) (e.g., at least one charge-generating layer and at least one hole-injecting layer) may be broken or bent. In an embodiment, the light-emitting structure (EMS) may have a structure in which three light-emitting portions, each including a light-emitting layer, are stacked and two charge-generating layers may be disposed between the three light-emitting portions. In such an embodiment, the pixel-defining layer (PDL) may include one or more trenches in the boundary region (BDA).

[0369] Return to reference Figure 22The light-emitting structure EMS' can be disposed on the anode electrodes AE1', AE2', and AE3' exposed by the opening OP' of the pixel-defining layer PDL'. The light-emitting structure EMS' fills the opening OP' of the pixel-defining layer PDL' and can be disposed integrally across the first sub-pixels SP1 to the third sub-pixels SP3. As explained above, the light-emitting structure EMS' can be broken or bent in the boundary region BDA or in the region immediately adjacent to the boundary region BDA by the separator SPR'. Therefore, during the operation of the display panel DP, the current flowing from each of the first sub-pixels SP1 to the third sub-pixels SP3 through the layer included in the light-emitting structure EMS' to the immediately adjacent sub-pixel can be reduced. Therefore, the first light-emitting elements LD1' to the third light-emitting elements LD3' can operate with relatively high reliability.

[0370] In one embodiment, the light-emitting structure EMS' may include two sequentially stacked light-emitting portions, each of which includes a light-emitting layer that generates light according to an applied current. In other embodiments, the light-emitting structure EMS' may include three sequentially stacked light-emitting portions, each of which includes a light-emitting layer that generates light according to an applied current. In such embodiments, a charge-generating layer may be disposed between the light-emitting portions.

[0371] In the embodiments, the light-emitting structure EMS' can be formed by processes such as vacuum deposition, inkjet printing, etc.

[0372] The cathode electrode CE can be disposed on the light-emitting structure EMS'. The cathode electrode CE can be disposed in common for the first sub-pixel SP1 to the third sub-pixel SP3.

[0373] The first anode electrode AE1', the portion of the light-emitting structure EMS' superimposed on the first anode electrode AE1', and the portion of the cathode electrode CE superimposed on the first anode electrode AE1' can constitute the first light-emitting element LD1'. The second anode electrode AE2', the portion of the light-emitting structure EMS' superimposed on the second anode electrode AE2', and the portion of the cathode electrode CE superimposed on the second anode electrode AE2' can constitute the second light-emitting element LD2'. The third anode electrode AE3', the portion of the light-emitting structure EMS' superimposed on the third anode electrode AE3', and the portion of the cathode electrode CE superimposed on the third anode electrode AE3' can constitute the third light-emitting element LD3'.

[0374] The TFE encapsulation layer is disposed on the cathode electrode CE. The TFE encapsulation layer can prevent oxygen, moisture, etc. from penetrating into the light-emitting element layer LDL'.

[0375] The adhesive layer APL, the optical functional layer OFL, the coating layer OC, and the cover window CW are disposed on the encapsulation layer TFE. The adhesive layer APL, the optical functional layer OFL, the coating layer OC, and the cover window CW are respectively bonded to… Figure 21 The adhesive layer APL, optical functional layer OFL, coating layer OC, and cover window CW are constructed similarly. Further description of these is omitted.

[0376] Figure 24 It is shown that it includes Figure 21 The first light-emitting element LD1 to the third light-emitting element LD3 and Figure 22 A cross-sectional view of an embodiment of a portion of the light-emitting structure in any one of the first light-emitting elements LD1' to the third light-emitting element LD3'.

[0377] Reference Figure 24 The light-emitting structure can have a series structure in which a first light-emitting unit EU1 and a second light-emitting unit EU2 are stacked. Figure 21 The light-emitting structures of each of the first light-emitting elements LD1 to the third light-emitting element LD3 can be constructed in a substantially identical manner.

[0378] Each of the first light-emitting unit EU1 and the second light-emitting unit EU2 may include at least one light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0379] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer, and may also include a hole buffer layer or an electron blocking layer as needed. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same structure or different structures.

[0380] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and may also include an electron buffer layer or a hole blocking layer as needed. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same structure or different structures from each other.

[0381] A connecting layer, which can be configured in the form of a charge generation layer CGL, can be disposed between the first light-emitting unit EU1 and the second light-emitting unit EU2 to connect the first light-emitting unit EU1 and the second light-emitting unit EU2 to each other. In an embodiment, the charge generation layer CGL can have a stacked structure of a p-doped layer and an n-doped layer. In an embodiment, for example, the p-doped layer can include p-type dopants such as HAT-CN, TCNQ, NDP-9, etc., and the n-doped layer can include alkali metals, alkaline earth metals, lanthanide-based metals, or combinations thereof. However, the disclosure is not limited thereto.

[0382] In an embodiment, the first emissive layer EML1 and the second emissive layer EML2 can generate light of different colors from each other. Light emitted from each of the first emissive layer EML1 and the second emissive layer EML2 can be mixed and visually perceived as white light. In an embodiment, for example, the first emissive layer EML1 can generate blue light, and the second emissive layer EML2 can generate yellow light. In an embodiment, the second emissive layer EML2 may include a structure in which a first sub-emissive layer generating red light and a second sub-emissive layer generating green light are stacked. Red light and green light can be mixed to provide yellow light. In this case, an intermediate layer that performs the function of transporting holes and / or blocking electron transport can be further provided between the first sub-emissive layer and the second sub-emissive layer.

[0383] In some other embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 can generate light of the same color.

[0384] The light-emitting structure can be formed by vacuum deposition or inkjet printing, but the disclosure is not limited to these methods.

[0385] Figure 25 It is shown that it includes Figure 21 The first light-emitting element LD1 to the third light-emitting element LD3 and Figure 22 A cross-sectional view of another embodiment of a portion of the light-emitting structure in any one of the first light-emitting elements LD1' to the third light-emitting element LD3'.

[0386] Reference Figure 25 The light-emitting structure can have a series structure in which the first light-emitting unit EU1' to the third light-emitting unit EU3' are stacked. Figure 21 The light-emitting structures of each of the first light-emitting elements LD1 to the third light-emitting element LD3 can be constructed in a substantially identical manner.

[0387] Each of the first light-emitting units EU1' to the third light-emitting units EU3' may include a light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1' may include a first light-emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting unit EU2' may include a second light-emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting unit EU3' may include a third light-emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light-emitting layer EML3' may be disposed between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0388] Each of the first hole transport unit HTU1' to the third hole transport unit HTU3' may include at least one of a hole injection layer and a hole transport layer, and may also include a hole buffer layer or an electron blocking layer as needed. The first hole transport unit HTU1' to the third hole transport unit HTU3' may have the same structure or different structures.

[0389] Each of the first electron transport units ETU1' to the third electron transport units ETU3' may include at least one of an electron injection layer and an electron transport layer, and may also include an electron buffer layer or a hole blocking layer as needed. The first electron transport units ETU1' to the third electron transport units ETU3' may have the same structure or different structures from each other.

[0390] The first charge generation layer CGL1' is disposed between the first light-emitting unit EU1' and the second light-emitting unit EU2'. The second charge generation layer CGL2' is disposed between the second light-emitting unit EU2' and the third light-emitting unit EU3'.

[0391] In an embodiment, the first light-emitting layer EML1' to the third light-emitting layer EML3' can generate light of different colors from each other. The light emitted by each of the first light-emitting layer EML1' to the third light-emitting layer EML3' can be mixed and regarded as white light. In an embodiment, for example, the first light-emitting layer EML1' can generate blue light, the second light-emitting layer EML2' can generate green light, and the third light-emitting layer EML3' can generate red light.

[0392] In some other embodiments, two or more of the first light-emitting layers EML1' to the third light-emitting layers EML3' can generate light of the same color.

[0393] and Figure 24 and Figure 25 The difference shown Figure 21 The light-emitting structure EMS can include one light-emitting unit in each of the first light-emitting element LD1 to the third light-emitting element LD3. In an optional embodiment, with Figure 24 and Figure 25 The difference shown Figure 22 The light-emitting structure EMS' can include one light-emitting unit in each of the first light-emitting element LD1' to the third light-emitting element LD3'. In this case, it includes... Figure 21 Each of the first light-emitting elements LD1 to the third light-emitting element LD3 is included in or is contained in the first light-emitting element LD1 to the third light-emitting element LD3. Figure 22 Each of the first to third light-emitting elements LD1' can emit light of a different color. In an embodiment, for example, as... Figure 21 As shown, the light-emitting unit of the first light-emitting element LD1 can emit red light, the light-emitting unit of the second light-emitting element LD2 can emit green light, and the light-emitting unit of the third light-emitting element LD3 can emit blue light. In this case, the light-emitting units of the first sub-pixel SP1 to the third sub-pixel SP3 are separated from each other, and each of them can be disposed in the pixel defining layer (see reference). Figure 21 PDL and Figure 22 The opening of the PDL' (refer to) Figure 21 OP and Figure 22 In the OP'), at least some of the color filters CF1 to CF3 can be omitted.

[0394] Figure 26 It is shown Figure 19 A plan view of another embodiment of any of the pixels.

[0395] Reference Figure 26 The first pixel PXL1' may include the first sub-pixel SP1' to the third sub-pixel SP3'.

[0396] The first sub-pixel SP1' may include a first luminous region EMA1' and a non-luminous region NEA' surrounding the first luminous region EMA1'. The second sub-pixel SP2' may include a second luminous region EMA2' and a non-luminous region NEA' surrounding the second luminous region EMA2'. The third sub-pixel SP3' may include a third luminous region EMA3' and a non-luminous region NEA' surrounding the third luminous region EMA3'.

[0397] The first sub-pixel SP1' and the second sub-pixel SP2' can be arranged on the second direction DR2. The third sub-pixel SP3' can be set on the first direction DR1 relative to each of the first sub-pixel SP1' and the second sub-pixel SP2'.

[0398] The second sub-pixel SP2' can have a larger area than the first sub-pixel SP1', and the third sub-pixel SP3' can have a larger area than the second sub-pixel SP2'. Therefore, the second light-emitting region EMA2' can have a larger area than the first light-emitting region EMA1', and the third light-emitting region EMA3' can have a larger area than the second light-emitting region EMA2'. However, the embodiments are not limited to this. In embodiments, for example, the first sub-pixel SP1' and the second sub-pixel SP2' can have substantially the same area as each other, and the third sub-pixel SP3' can have an area larger than each of the first sub-pixel SP1' and the second sub-pixel SP2'. Thus, the areas of the first sub-pixel SP1' to the third sub-pixel SP3' can be modified differently.

[0399] Figure 27 It is shown Figure 19 A plan view of another embodiment of any of the pixels.

[0400] Reference Figure 27 The first sub-pixel SP1 of the first pixel PXL1” may include a first light-emitting region EMA1” and a non-light-emitting region NEA surrounding the first light-emitting region EMA1”. The second sub-pixel SP2 of the first pixel PXL1” may include a second light-emitting region EMA2” and a non-light-emitting region NEA surrounding the second light-emitting region EMA2”. The third sub-pixel SP3 of the first pixel PXL1” may include a third light-emitting region EMA3” and a non-light-emitting region NEA surrounding the third light-emitting region EMA3”.

[0401] When viewed on a third-party DR3, the first sub-pixel SP1” to the third sub-pixel SP3” can have a polygonal shape. In an embodiment, for example, the shape of the first sub-pixel SP1” to the third sub-pixel SP3” can be as follows: Figure 27 The hexagon shown.

[0402] When viewed on a third-party DR3, the first light-emitting area EMA1” to the third light-emitting area EMA3” may have a circular shape. However, the embodiments are not limited to this. In an embodiment, for example, each of the first light-emitting area EMA1” to the third light-emitting area EMA3” may have a polygonal shape.

[0403] The first sub-pixel SP1” and the third sub-pixel SP3” can be arranged on the first direction DR1. The second sub-pixel SP2” can be arranged relative to the first sub-pixel SP1” in a direction that is tilted at an acute angle (or diagonal) relative to the second direction DR2.

[0404] Figure 20 , Figure 26 and Figure 27 The arrangement of subpixels shown is illustrative and not limited thereto. Each pixel may include two or more subpixels, and the subpixels may be arranged in various ways. Each of the subpixels may have various shapes, and each of its luminous regions may have various shapes.

[0405] Figure 28 This is a block diagram illustrating an embodiment of the display system 2800.

[0406] Reference Figure 28 The display system 2800 may include a processor 2810 and one or more display devices 2822 and 2824. The display system 2800 in the disclosed embodiments may also be referred to as electronic device 2800.

[0407] Processor 2810 can perform various tasks and calculations. In embodiments, processor 2810 may include an application processor (“AP”), a graphics processing unit (“GPU”), a microprocessor, a central processing unit (“CPU”), etc. Processor 2810 can be connected to other components of display system 2800 via a bus system to control them.

[0408] exist Figure 28 In the diagram, display system 2800 is shown to include a first display device 2822 and a second display device 2824. Processor 2810 is connected to the first display device 2822 via a first channel CH1 and to the second display device 2824 via a second channel CH2.

[0409] Through the first channel CH1, the processor 2810 can transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 2822. The first display device 2822 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 2822 can be used with a reference... Figure 1 The described display device 100 is similarly constructed. In this case, the first image data IMG1 and the first control signal CTRL1 can respectively serve as... Figure 1 The input image data IMG and the control signal CTRL are provided.

[0410] Through the second channel CH2, the processor 2810 can transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 2824. The second display device 2824 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 2824 can be used with a reference... Figure 1 The described display device 100 is similarly constructed. In this case, the second image data IMG2 and the second control signal CTRL2 can respectively serve as... Figure 1 The input image data IMG and the control signal CTRL are provided.

[0411] Display system 2800 may include portable computers, mobile phones, smartphones, tablet personal computers (“PCs”), and computer systems that provide image display capabilities, such as smartwatches, watch phones, portable multimedia players (“PMPs”), navigation devices, or ultra-mobile personal computers (“UMPCs”). Additionally, display system 2800 may include at least one of HMD devices, VR devices, MR devices, and AR devices.

[0412] Figure 29 It is shown Figure 28 A perspective view of an embodiment of the application of the display system 2800.

[0413] Reference Figure 29 , Figure 28 The display system 2800 can be applied to the HMD device 2900. The HMD device 2900 can be a wearable electronic device that can be worn on the user's head.

[0414] HMD device 2900 may include a headband 2910 and a display device storage housing 2920. The headband 2910 may be connected to the display device storage housing 2920. The headband 2910 may include a horizontal strap and / or a vertical strap for securing the HMD device 2900 to a user's head. The horizontal strap may surround the side of the user's head, and the vertical strap may be configured to surround the upper part of the user's head. However, the disclosure is not limited thereto. In embodiments, for example, the headband 2910 may be implemented in the form of an eyeglass frame or a helmet, etc.

[0415] The display device storage housing 2920 can store... Figure 28 The first display device 2822 and the second display device 2824. The display device storage housing 2920 can also store... Figure 28 The processor is 2810.

[0416] Figure 30 This is to show the device worn by the user USR. Figure 29 A diagram of the HMD device 2900.

[0417] Reference Figure 30 First display device 2822 (see Figure 28 The first display panel DP1 and the second display device 2824 (see) Figure 28 The second display panel DP2 is disposed in the HMD device 2900. The HMD device 2900 may also include one or more left eye lenses LLNS and / or one or more right eye lenses RLNS.

[0418] In the display device storage housing 2920, the right eye lens RLNS can be disposed between the first display panel DP1 and the right eye of the user USR. In the display device storage housing 2920, the left eye lens LLNS can be disposed between the second display panel DP2 and the left eye of the user USR.

[0419] The image output from the first display panel DP1 can be displayed to the user's right eye via the right eye lens RLNS. The right eye lens RLNS can refract light from the first display panel DP1 toward the user's right eye. The right eye lens RLNS can perform optical functions to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0420] The image output from the second display panel DP2 can be displayed on the user's left eye via the left eye lens LLNS. The left eye lens LLNS refracts light from the second display panel DP2 toward the user's left eye. The left eye lens LLNS performs an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0421] In one embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens with a pancake-shaped profile. In another embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens comprising sub-regions with different optical properties. In this case, each display panel outputs an image corresponding to a sub-region of the multi-channel lens, and the output image can be displayed to the user through the corresponding sub-region.

[0422] Visibility can be improved according to the sub-pixel, the display device including the sub-pixel, the electronic device including the display device, and the driving method of the electronic device in the disclosed embodiments.

[0423] The accompanying drawings and detailed descriptions mentioned so far are merely exemplary disclosures, intended only for illustrative purposes and not for limiting the scope of the disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent embodiments can be made therefrom. Consequently, the true scope of protection of the disclosure should be determined by the technical concept of the appended claims.

Claims

1. A sub-pixel, the sub-pixel comprising: A first transistor includes a gate electrode electrically connected to a first node, the first transistor being connected between a second node and a third node, the third node being electrically connected to a first electric field line; A light-emitting element is connected between the second node and the second electric field line; The second transistor is configured to switch the electrical connection between the first node and the data line; The third transistor is configured to switch the electrical connection between the second node and the third power line; A fourth transistor is configured to switch the electrical connection between the first power line and the third node; A first capacitor is configured to maintain a potential difference between the first node and the third node; The second capacitor is configured to maintain the potential difference between the second node and the electric field line to which a constant voltage is applied; as well as The third capacitor is configured to maintain the potential difference between the first node and the second node.

2. The sub-pixel according to claim 1, wherein, The second capacitor includes a first electrode electrically connected to the second node and a second electrode electrically connected to the power line to which the constant voltage is applied.

3. The sub-pixel according to claim 2, wherein, A second power supply voltage is applied to the second power line, and The constant voltage is the same as the second power supply voltage.

4. The sub-pixel according to claim 2, wherein, A third power supply voltage is applied to the third electric field line, and The constant voltage is the same as the third power supply voltage.

5. The sub-pixel according to claim 2, wherein, The electric field line to which the constant voltage is applied is different from the first electric field line, the second electric field line, and the third electric field line.

6. The sub-pixel according to claim 2, wherein, The first electrode of the second capacitor and the second electrode of the second capacitor are disposed on the same layer.

7. The sub-pixel according to claim 6, wherein, The capacitance of the second capacitor is greater than the capacitance between the anode and cathode electrodes of the light-emitting element.

8. The sub-pixel according to claim 1, wherein, The first transistor, the second transistor, and the fourth transistor comprise P-type semiconductors, and The third transistor includes an N-type semiconductor.

9. The sub-pixel according to claim 8, wherein, A first power supply voltage is applied to the first electric field line, and a third power supply voltage is applied to the third electric field line. Wherein, the first power supply voltage is applied to the respective body electrodes of the first transistor, the second transistor, and the fourth transistor, and The third power supply voltage is applied to the body electrode of the third transistor.

10. A display device, the display device comprising: The display panel includes multiple data lines, multiple first gate lines, multiple second gate lines, multiple light emission control lines, and multiple sub-pixels electrically connected to the multiple data lines, the multiple first gate lines, the multiple second gate lines, and the multiple light emission control lines. At least one of the multiple sub-pixels includes: a first transistor including a gate electrode electrically connected to a first node, the first transistor being connected between a second node and a third node, the third node being electrically connected to a first power line; a light-emitting element connected between the second node and the second power line; a second transistor configured to switch the electrical connection between the first node and a corresponding data line among the multiple data lines; a third transistor configured to switch the electrical connection between the second node and the third power line; a fourth transistor configured to switch the electrical connection between the first power line and the third node; a first capacitor configured to maintain a potential difference between the first node and the third node; a second capacitor configured to maintain a potential difference between the second node and a power line to which a constant voltage is applied; and a third capacitor configured to maintain a potential difference between the first node and the second node. A data driver is configured to supply data voltage to the plurality of data lines; and The gate driving circuit is configured to supply signals to the plurality of first gate lines, the plurality of second gate lines, and the plurality of light emission control lines.

11. The display device according to claim 10, wherein, The second transistor includes a gate electrode electrically connected to a corresponding first gate line among the plurality of first gate lines.

12. The display device according to claim 11, wherein, The second transistor turns on in response to a first scan signal with a low level applied to the gate electrode.

13. The display device according to claim 10, wherein, The third transistor includes a gate electrode electrically connected to a corresponding second gate line among the plurality of second gate lines.

14. The display device according to claim 13, wherein, The third transistor is turned on in response to a second scan signal with a high level applied to the gate electrode.

15. An electronic device, the electronic device comprising: Processor, outputs input image data; The controller converts the input image data to output image data; The display panel includes multiple data lines, multiple first gate lines, multiple second gate lines, multiple light emission control lines, and multiple sub-pixels electrically connected to the multiple data lines, the multiple first gate lines, the multiple second gate lines, and the multiple light emission control lines. At least one of the multiple sub-pixels includes: a first transistor including a gate electrode electrically connected to a first node, the first transistor being connected between a second node and a third node, the third node being electrically connected to a first power line; a light-emitting element connected between the second node and the second power line; a second transistor configured to switch the electrical connection between the first node and a corresponding data line among the multiple data lines; a third transistor configured to switch the electrical connection between the second node and the third power line; a fourth transistor configured to switch the electrical connection between the first power line and the third node; a first capacitor configured to maintain a potential difference between the first node and the third node; a second capacitor configured to maintain a potential difference between the second node and a power line to which a constant voltage is applied; and a third capacitor configured to maintain a potential difference between the first node and the second node. A data driver is configured to supply a data voltage corresponding to the image data to the plurality of data lines; and The gate driving circuit is configured to supply signals to the plurality of first gate lines, the plurality of second gate lines, and the plurality of light emission control lines.

16. The electronic device according to claim 15, wherein, The controller generates the image data based on the capacitance of the first capacitor and the capacitance of the third capacitor.

17. A method for driving an electronic device including a first transistor and a light-emitting element electrically connected to the first transistor, the method comprising the steps of: The first electrode of the first capacitor, to which the data voltage is applied, is electrically connected to the gate electrode of the first transistor, and the second electrode of the first capacitor, to which the first power supply voltage is applied, is electrically connected to the source electrode of the first transistor. The data voltage is applied to the gate electrode of the first transistor, and the first threshold voltage of the first transistor is stored in the first capacitor; The first power supply voltage is applied to the second electrode of the first capacitor, and the voltage fluctuation of the second electrode of the first capacitor is reflected to the first electrode in a ratio corresponding to the capacitance of the first capacitor. as well as The voltage fluctuation of the second electrode of the third capacitor, which is electrically connected to the drain electrode of the first transistor, is caused by the drive current flowing through the first transistor, and the amount of voltage fluctuation of the second electrode of the third capacitor is reflected to the first electrode of the third capacitor in a ratio corresponding to the capacitance of the third capacitor, wherein the first electrode of the third capacitor is electrically connected to the gate electrode of the first transistor.

18. The method according to claim 17, wherein, The ratio corresponding to the capacitance of the first capacitor is calculated by dividing the capacitance of the first capacitor by the value obtained by adding the capacitance of the first capacitor and the capacitance of the third capacitor.

19. The method of claim 17, wherein, The ratio corresponding to the capacitance of the third capacitor is calculated by dividing the capacitance of the third capacitor by the value obtained by adding the capacitance of the first capacitor and the capacitance of the third capacitor.

20. The method of claim 17, wherein, The electronic device further includes a second capacitor, the second capacitor comprising a first electrode electrically connected to the drain electrode of the first transistor and a second electrode to which a constant voltage is applied, and The ripple voltage is applied to the first electrode of the second capacitor to reflect the voltage fluctuation of the second electrode of the first capacitor in the first electrode of the first capacitor at a ratio corresponding to the capacitance of the first capacitor.

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