A pre-stored pixel driving circuit for double array substrate of VA / TN panel
By using a pre-stored pixel driving circuit on a dual-array substrate, and by combining pre-stored capacitors and transistors, the problem of inconsistent image quality under high refresh rates and long lamp durations in traditional circuits is solved, thus achieving efficient and low-power display.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHENGDU JIUTIAN HUAXIN TECH CO LTD
- Filing Date
- 2024-08-21
- Publication Date
- 2026-07-14
Smart Images
Figure CN122392454A_ABST
Abstract
Description
[0001] This invention is a divisional application filed on August 21, 2024, with application number "202411148272.6" and titled "A pre-stored pixel driving circuit for a dual-array substrate of a VA / TN panel". Technical Field
[0002] This invention relates to the field of pixel driving technology, and more specifically to a pre-stored pixel driving circuit for a dual-array substrate of a VA / TN panel. Background Technology
[0003] Field sequential or color sequential display driving technology leverages the persistence of vision to directly mix RGB three-color light sources, achieving full-color display effects. It eliminates the need for color filters, thus improving light source utilization and reducing power consumption.
[0004] Traditional 1T2C pixel circuits, lacking a reset circuit, leave residual charge from the previous frame on the pixel capacitors. This has a minor impact at lower refresh rates (backlighting can only be activated after all frame data has been written and the liquid crystal has reached a stable state; otherwise, image distortion will occur, requiring ample time for liquid crystal deflection before backlighting). However, at higher refresh rates (in field-sequence display technology, a traditional color frame is divided into three RGB subframes, resulting in a refresh rate typically three times that of traditional displays), sufficient liquid crystal deflection time cannot be allowed to accommodate the lamp-on time (final light output brightness is positively correlated with lamp-on time), leading to inaccurate pixel grayscale. This makes it difficult to achieve high brightness and high frequency display over an average time, while increasing the requirements for backlight brightness specifications and lifespan, thus raising costs.
[0005] Furthermore, to prevent liquid crystal polarization, the data lines need to repeatedly switch between positive and negative frame polarity voltages. To ensure display quality, neighboring pixels and the data line itself need to be driven in reverse to reduce flicker and other issues. Methods include column inversion, row inversion, dot inversion, and combinations thereof. Dot inversion achieves the best display quality. However, because the data lines in the same column repeatedly invert the COM signal voltage within a single frame, power consumption is the highest. Moreover, the power consumption of the data lines is proportional to the square of the driving frequency, making it difficult to achieve under the higher frequency driving requirements of field-sequence displays. Therefore, implementing low-power dot inversion based on field-sequence displays is beneficial for improving display quality and enhancing competitiveness.
[0006] In summary, traditional pixel driving circuits cannot simultaneously achieve high refresh rates, long lamp duration, and high image quality consistency. Summary of the Invention
[0007] In view of this, the present invention provides a pre-stored pixel driving circuit for a dual-array substrate of a VA / TN panel. By improving the circuit structure and driving timing, the problem that traditional pixel driving circuits cannot simultaneously achieve high refresh rate, long lamp duration and high image quality consistency is solved.
[0008] To solve the above problems, the technical solution of the present invention is to use a pre-stored pixel driving circuit for a dual-array substrate of a VA / TN panel, comprising: a first sub-circuit disposed on an upper substrate and a second sub-circuit disposed on a lower substrate, wherein both the upper substrate and the lower substrate are array substrates; the first sub-circuit is configured such that: the first source-drain of a first transistor is coupled to a first data signal line, and the second source-drain of a second transistor is coupled to the first source-drain of a second transistor and one end of the first pre-stored capacitor; the second source-drain of the second transistor is coupled to one end of the pixel capacitor; the second sub-circuit is configured such that: the first source-drain of a fourth transistor is coupled to a second data signal line, and the second source-drain of a fourth transistor is coupled to the first source-drain of a third transistor and one end of the second pre-stored capacitor; the second source-drain of the third transistor is coupled to the other end of the pixel capacitor.
[0009] Optionally, when the first transistor, the second transistor, the third transistor, and the fourth transistor are all N-type MOS transistors, the gate of the first transistor is coupled to the first control signal line, the gate of the second transistor is coupled to the first transfer signal line, the gate of the third transistor is coupled to the second transfer signal line, and the gate of the fourth transistor is coupled to the second control signal line.
[0010] Optionally, when the first transistor and the fourth transistor are both N-type MOS transistors, and the second transistor and the third transistor are P-type MOS transistors, the gates of the first transistor and the second transistor are both coupled to the first control signal line, and the gates of the third transistor and the fourth transistor are coupled to the second control signal line.
[0011] Optionally, the ends of the first and second pre-storage capacitors furthest from the transistor are both coupled to a common signal line.
[0012] Optionally, the driving timing of the pixel driving circuit is configured as follows: during the backlight-on stage of the Nth frame, both the first control signal and the second control signal jump to a high potential line by line, the first transistor and the fourth transistor are turned on synchronously, the first data signal line stores the first data signal containing the grayscale voltage into the first pre-storage capacitor through the first transistor, and the second data signal line stores the second data signal containing the reference voltage into the second pre-storage capacitor through the fourth transistor, thus entering the backlight-off stage of the Nth frame.
[0013] Optionally, during the backlight off phase of the Nth frame, the second transfer signal jumps to a high potential, the third transistor turns on, and after the second pre-storage capacitor transmits a second data signal containing a reference voltage to one end of the pixel capacitor through the third transistor, the second transfer signal jumps back to a normal potential, and the third transistor turns off; the first transfer signal jumps to a high potential, the second transistor turns on, and after the first pre-storage capacitor transmits a first data signal containing a grayscale voltage to the other end of the pixel capacitor through the second transistor, the first transfer signal jumps back to a normal potential, the second transistor turns off, and the backlight on phase of the N+1th frame begins.
[0014] Optionally, during the backlight-on phase of the (N+1)th frame, both the first and second control signals transition to high potentials line by line, the first and fourth transistors turn on synchronously, the first data signal line stores the first data signal containing the reference voltage into the first pre-storage capacitor through the first transistor, and the second data signal line stores the second data signal containing the grayscale voltage into the second pre-storage capacitor through the fourth transistor, thus entering the backlight-off phase of the (N+1)th frame; during the backlight-off phase of the (N+1)th frame, the first transfer signal transitions to high potentials, the second transistor turns on, and after the first pre-storage capacitor transmits the first data signal containing the reference voltage to one end of the pixel capacitor through the second transistor, the first transfer signal transitions back to normal potentials, and the second transistor turns off; the second transfer signal transitions to high potentials, the third transistor turns on, and after the second pre-storage capacitor transmits the second data signal containing the grayscale voltage to the other end of the pixel capacitor through the third transistor, the second transfer signal transitions back to normal potentials, and the third transistor turns off, thus entering the backlight-on phase of the (N+2)th frame.
[0015] Optionally, the driving timing of the pixel driving circuit is configured as follows: during the backlight-on stage of the Nth frame, the first control signal and the second control signal synchronously transition to a high potential line by line, the first transistor and the fourth transistor are synchronously turned on, the first data signal line stores the first data signal containing the grayscale voltage into the first pre-storage capacitor through the first transistor, and the second data signal line stores the second data signal containing the reference voltage into the second pre-storage capacitor through the fourth transistor, thus entering the backlight-off stage of the Nth frame.
[0016] Optionally, during the backlight off phase of the Nth frame, the second control signal jumps to a low potential, the third transistor turns on, and after the second pre-storage capacitor transmits a second data signal containing a reference voltage to one end of the pixel capacitor through the third transistor, the second control signal jumps to a normal potential. After the third transistor turns off, the first control signal jumps to a low potential, the second transistor turns on, and after the first pre-storage capacitor transmits a first data signal containing a grayscale voltage to the other end of the pixel capacitor through the second transistor, the first control signal jumps back to a normal potential, the second transistor turns off, and the backlight on phase of the N+1th frame begins.
[0017] Optionally, during the backlight-on phase of the N+1th frame, the first control signal and the second control signal synchronously transition to a high potential line by line, the first transistor and the fourth transistor synchronously turn on, the first data signal line stores the first data signal containing the reference voltage into the first pre-storage capacitor through the first transistor, and the second data signal line stores the second data signal containing the grayscale voltage into the second pre-storage capacitor through the fourth transistor, thus entering the backlight-off phase of the N+1th frame; during the backlight-off phase of the N+1th frame, the first control signal transitions to a low potential, the second transistor turns on, the first pre-storage capacitor transmits the first data signal containing the reference voltage to one end of the pixel capacitor through the second transistor, the first control signal transitions back to a normal potential, the second transistor turns off, the second control signal transitions to a low potential, the third transistor turns on, the second pre-storage capacitor transmits the second data signal containing the grayscale voltage to the other end of the pixel capacitor through the third transistor, the second control signal transitions back to a normal potential, the third transistor turns off, thus entering the backlight-on phase of the N+2th frame.
[0018] The primary improvement of this invention is the provision of a pre-storage pixel driving circuit for a dual-array substrate of a VA / TN panel. By setting a pre-storage capacitor in conjunction with a transistor, the grayscale voltage of the next frame is stored in the pre-storage capacitor during the backlight illumination time of the current frame. This enables all pixels to synchronously transfer grayscale voltage when the backlight is off, greatly reducing the pixel voltage writing time and relatively increasing the backlight illumination time.
[0019] Furthermore, by utilizing the characteristic of field-sequence display technology that eliminates the need for a CF filter on the liquid crystal display device, and by setting up upper and lower dual-array substrates, data signals can be written through either substrate in any frame while being reset through the other substrate, eliminating the influence of residual data signals from the previous frame. This effectively reduces the time required for liquid crystal deflection to complete in a frame, solving the problem that traditional pixel driving circuits cannot simultaneously achieve high refresh rates, long lamp times, and high image quality consistency. Moreover, since the upper and lower substrates overlap in the direction of pixel light emission, and the first and second sub-circuits are respectively set on the upper and lower substrates, the aperture ratio of the pixel driving circuit can be significantly improved, ensuring high light transmittance while solving the aforementioned technical problems.
[0020] Furthermore, since the present invention can simultaneously write data signals through any substrate and reset through another substrate in any frame, the IC voltage range of the pixel driving circuit is [0, Vop-max] regardless of whether the frame is a positive or negative frame, while the IC voltage range of the traditional IT2C circuit is [-Vop-max, Vop-max]. Therefore, the present invention can also significantly reduce power consumption and reduce driving difficulty. Attached Figure Description
[0021] Figure 1 This is a simplified circuit diagram of the pre-stored pixel driving circuit for a dual-array substrate of a VA / TN panel according to the present invention; Figure 2 This is a simplified driving timing diagram of the pre-stored pixel driving circuit for a dual-array substrate of a VA / TN panel according to the present invention; Figure 3 This is an example diagram of the pixel structure used in the pixel driving circuit of the present invention; Figure 4 This is a simplified driving timing diagram of a preferred embodiment of the present invention; Figure 5 This is a GOA driving circuit diagram of a preferred embodiment of the present invention. Detailed Implementation
[0022] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0024] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0025] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.
[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.
[0027] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.
[0028] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0029] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0030] Specifically, such as Figure 1As shown, a pre-stored pixel driving circuit for a dual-array substrate of a VA / TN panel includes: a first sub-circuit disposed on an upper substrate and a second sub-circuit disposed on a lower substrate, wherein both the upper substrate and the lower substrate are array substrates; the first sub-circuit is configured such that: the first source-drain of a first transistor T1 is coupled to a first data signal line Data1, and its second source-drain is coupled to the first source-drain of a second transistor T2 and one end of the first pre-stored capacitor Cst1; the second source-drain of the second transistor T2 is coupled to one end of the pixel capacitor Clc; the second sub-circuit is configured such that: the first source-drain of a fourth transistor T4 is coupled to a second data signal line Data2, and its second source-drain is coupled to the first source-drain of a third transistor T3 and one end of the second pre-stored capacitor Cst2; the second source-drain of the third transistor T3 is coupled to the other end of the pixel capacitor Clc. The ends of the first pre-stored capacitor Cst1 and the second pre-stored capacitor Cst2 furthest from the transistors are both coupled to a common signal line Com.
[0031] Furthermore, when the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all N-type MOS transistors, the gate of the first transistor T1 is coupled to the first control signal line ScanT, the gate of the second transistor T2 is coupled to the first transfer signal line TranT, the gate of the third transistor T3 is coupled to the second transfer signal line TranC, and the gate of the fourth transistor T4 is coupled to the second control signal line ScanC.
[0032] Furthermore, such as Figure 2 As shown, the driving timing of the pixel driving circuit is configured as follows: During the backlight activation phase of the Nth frame (N=1 in the diagram), the first control signal and the second control signal ( Figure 2 In the sequence `scanN`, both the first and second control signals in the Nth row transition to a high level sequentially. The first transistor T1 and the fourth transistor T4 are simultaneously turned on. The first data signal line `Data1` stores the first data signal containing the grayscale voltage into the first pre-storage capacitor `Cst1` via the first transistor T1, and the second data signal line `Data2` stores the second data signal containing the reference voltage into the second pre-storage capacitor `Cst2` via the fourth transistor T4, thus entering the backlight-off phase of the Nth frame. This completes the pre-storage of the grayscale voltage and reference voltage for each pixel in the next frame during the backlight-on phase. The reference voltage can be equal to the common signal.
[0033] During the backlight-off phase of frame N, the second transfer signal jumps to a high potential, the third transistor T3 turns on, and the second pre-storage capacitor Cst2 transmits a second data signal containing the reference voltage to one end of the pixel capacitor Clc through the third transistor T3. Then, the second transfer signal jumps back to a normal potential, and the third transistor T3 turns off. The first transfer signal jumps to a high potential, the second transistor T2 turns on, and the first pre-storage capacitor Cst1 transmits a first data signal containing the grayscale voltage to the other end of the pixel capacitor Clc through the second transistor T2. Then, the first transfer signal jumps back to a normal potential, and the second transistor T2 turns off, entering the backlight-on phase of frame N+1. Thus, the writing of the grayscale voltage and reference voltage for each pixel in the next frame is completed during the backlight-off phase.
[0034] During the backlight-on phase of frame N+1, both the first and second control signals transition to high levels line by line. The first transistor T1 and the fourth transistor T4 are simultaneously turned on. The first data signal line Data1 stores the first data signal, including the reference voltage, into the first pre-storage capacitor Cst1 via the first transistor T1. The second data signal line Data2 stores the second data signal, including the grayscale voltage, into the second pre-storage capacitor Cst2 via the fourth transistor T4, thus entering the backlight-off phase of frame N+1. This completes the pre-storage of the grayscale voltage and reference voltage for each pixel in the next frame during the backlight-on phase.
[0035] During the backlight-off phase of frame N+1, the first transfer signal jumps to a high potential, the second transistor T2 turns on, and the first pre-storage capacitor Cst1 transmits a first data signal containing the reference voltage to one end of the pixel capacitor Clc through the second transistor T2. Then, the first transfer signal jumps back to a normal potential, and the second transistor T2 turns off. The second transfer signal then jumps to a high potential, the third transistor T3 turns on, and the second pre-storage capacitor Cst2 transmits a second data signal containing the grayscale voltage to the other end of the pixel capacitor Clc through the third transistor T3. Then, the second transfer signal jumps back to a normal potential, and the third transistor T3 turns off, entering the backlight-on phase of frame N+2. The purpose of resetting the pixel capacitor Clc before performing grayscale voltage transfer is to reduce the influence of charge sharing on the grayscale voltage and avoid inaccurate grayscale voltage on the pixel capacitor Clc during the backlight-on phase. This allows the writing of the grayscale voltage and reference voltage for each pixel in the next frame to be completed during the backlight-off phase.
[0036] It should be noted that in this embodiment, a high potential is defined as a potential higher than the reference voltage (common signal) that ensures the N-type MOS transistor is turned on after being written.
[0037] It should be noted that N is an odd number and a positive integer, which can be configured as 1, 3, 5, 7... in the above embodiments. It should be noted here that the pixel driving circuit claimed in this invention can be used in VA / TN panels, for example, in... Figure 3 The diagram illustrates a simplified single-domain pixel TN display structure, using a positive liquid crystal as an example. During a positive frame, the electric field direction is along the Y-axis, trending from the high-voltage ITO1 electrode towards the reset ITO2 electrode. In the (N+1)th frame, the electrode potential reverses, thus the electric field signal also reverses. During this electric field reversal, the polarity of the liquid crystal electron cloud reverses, preventing display failure caused by liquid crystal polarity aging.
[0038] Furthermore, to facilitate understanding of how the pixel driving circuit claimed in this invention reduces the data range, the data range during its operation is quantitatively explained below: In a traditional 1T2C circuit, the data range is [Vcom-Vop_max, Vcom+Vop_max], with an overall amplitude of 2Vop_max, which will not be elaborated further. However, in this embodiment, there are two types of charge sharing: Reset charge sharing. This is achieved by sharing the charge of Clc to the reset Cst. Let the pixel electrode voltage be Vpixel_N-1, the reset voltage be Vreset, and the reference electrode be Vcom. When the charge stored in Clc is shared to Cst2: Clc(Vpixel-Vcom) = (Clc+Cst2)(Vreset-Vcom). Vreset = Clc / (Clc+Cst2)*(Vpixel-Vcom)+Vcom. When Cst2 >> Clc, Vreset ≈ Vcom. This can also be visualized as a small capacitor charging a large capacitor, causing the charge in the small capacitor to decrease.
[0039] Data charge sharing. The pixel electrode voltage after sharing at one pole of the pixel capacitor Clc connected to the second transistor T2 is set to Vpixel_N, and the pre-stored signal Cst1 is Vdata. When T2 is turned on, Cst1 and Clc share charge: Cst1(Vdata-Vcom)=(Cst1+Clc)(Vpixel_N-Vcom); Vdata=(1+Clc / Cst1)(Vpixel_N-Vcom)+Vcom. When Cst1>>Clc, Vdata=Vpixel. It can be seen that Vpixel's maximum value is Vop_max, and due to electrode reversal, Vdata_range=Vop_max. Compared to the traditional scheme, the data range is reduced by 1 / 2.
[0040] Furthermore, to reduce the difficulty of driving the process, Cst1 can be set to Cst2, and Data1 and Data2 can be controlled separately by dual ICs. This drives the writing of data signals for the Nth and N+1th frames respectively, while simultaneously writing reset signals for the N-1th and Nth frames. In this case, the data output of the ICs will be halved. Because the display and data writing stages are separated, full-field illumination can be achieved, separating computation and display, and making it easier to achieve high resolution.
[0041] Accordingly, the present invention provides a preferred embodiment, such as... Figure 4 As shown, using the LPTO process, the first transistor T1 and the second transistor T2 on the same layer are fabricated as N-type MOSFETs and P-type MOSFETs, respectively. Similarly, the third transistor T3 and the fourth transistor T4 on the same layer are fabricated as N-type MOSFETs and P-type MOSFETs, respectively. Thus, when the first transistor T1 and the fourth transistor T4 are both N-type MOSFETs, and the second transistor T2 and the third transistor T3 are P-type MOSFETs, the gates of the first transistor T1 and the second transistor T2 are coupled to the first control signal line ScanT, and the gates of the third transistor T3 and the fourth transistor T4 are coupled to the second control signal line ScanC. With this process, compared to... Figure 1 The pixel driving circuit shown in this embodiment reduces two signal lines and corresponding via traces by multiplexing control signal lines, thereby further improving the pixel aperture ratio.
[0042] Furthermore, such as Figure 5 As shown, the driving timing of the pixel driving circuit in this embodiment is configured as follows: During the backlight-on phase of the Nth frame, the first and second control signals synchronously transition to a high level line by line. The first transistor T1 and the fourth transistor T4 are simultaneously turned on. The first data signal line Data1 stores the first data signal, containing the grayscale voltage, into the first pre-storage capacitor Cst1 via the first transistor T1. The second data signal line Data2 stores the second data signal, containing the reference voltage, into the second pre-storage capacitor Cst2 via the fourth transistor T4. Then, the backlight-off phase of the Nth frame begins. This completes the pre-storage of the grayscale voltage and reference voltage for each pixel in the next frame during the backlight-on phase.
[0043] During the backlight-off phase of frame N, the second control signal transitions to a low level, the third transistor T3 turns on, and the second pre-storage capacitor Cst2 transmits a second data signal containing the reference voltage to one end of the pixel capacitor Clc via the third transistor T3. Afterward, the second control signal returns to a normal level. When the third transistor T3 turns off, the first control signal transitions to a low level, the second transistor T2 turns on, and the first pre-storage capacitor Cst1 transmits a first data signal containing the grayscale voltage to the other end of the pixel capacitor Clc via the second transistor T2. Then, the first control signal returns to a normal level, the second transistor T2 turns off, and the backlight-on phase of frame N+1 begins. This completes the writing of the grayscale voltage and reference voltage for each pixel in the next frame during the backlight-off phase.
[0044] During the backlight-on phase of frame N+1, the first and second control signals synchronously transition to a high level line by line. The first transistor T1 and the fourth transistor T4 are simultaneously turned on. The first data signal line Data1 stores the first data signal, including the reference voltage, into the first pre-storage capacitor Cst1 via the first transistor T1. The second data signal line Data2 stores the second data signal, including the grayscale voltage, into the second pre-storage capacitor Cst2 via the fourth transistor T4, thus entering the backlight-off phase of frame N+1. This completes the pre-storage of the grayscale voltage and reference voltage for each pixel in the next frame during the backlight-on phase.
[0045] During the backlight-off phase of frame N+1, the first control signal transitions to a low level, the second transistor T2 turns on, and the first pre-storage capacitor Cst1 transmits a first data signal containing the reference voltage to one end of the pixel capacitor Clc via the second transistor T2. Then, the first control signal transitions back to its normal potential. After the second transistor T2 turns off, the second control signal transitions to a low level, and the third transistor T3 turns on. The second pre-storage capacitor Cst2 transmits a second data signal containing the grayscale voltage to the other end of the pixel capacitor Clc via the third transistor T3. Then, the second control signal transitions back to its normal potential, and the third transistor T3 turns off, entering the backlight-on phase of frame N+2. Thus, the writing of the grayscale voltage and reference voltage for each pixel in the next frame is completed during the backlight-off phase.
[0046] It should be noted that in this embodiment, a high potential is defined as a potential higher than the reference voltage that ensures the N-type MOSFET is in the on state after writing; a low potential is defined as a potential lower than the reference voltage that ensures the P-type MOSFET is in the on state after writing; and a normal potential is defined as a potential that ensures both the N-type MOSFET and the P-type MOSFET are in the off state.
[0047] Furthermore, in traditional pixel driving circuits, data signals are written through the T side, while the C side continuously displays the Vcom signal. Polarity reversal is achieved by adjusting the Vdata voltage to (Vcom ± Vop_max), resulting in a data range of 2Vop_max. However, in the dual-TFT structure claimed in this application, since polarity reversal is achieved by alternating writing of upper and lower data signals frame by frame, the upper and lower plate pixels alternately act as the com electrode, resulting in a data range of Vop_max. Reducing the data range decreases the heat generated by the IC and signal lines, thereby lowering power consumption. Moreover, this overlapping structure incorporates signal line metal and shielding line metal for light shielding, achieving light shielding in the non-aperture area and avoiding the reduction in aperture ratio caused by the increased width of the BM film after photolithography.
[0048] It should be noted that in the various embodiments of this application, R, G, and B three-color light are emitted frame by frame by backlight, and the visual persistence effect of the human eye is used to realize the display of color images. The order of R, G, and B backlight can be interchanged.
[0049] The above describes a pre-stored pixel driving circuit for a dual-array substrate of a VA / TN panel, provided by embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.
[0050] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can implement the described functions using different methods for each specific application, but such implementation should not be considered beyond the scope of the invention. The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be implemented directly in hardware, software modules executed by a processor, or a combination of both. Software modules can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.
Claims
1. A pre-stored pixel driving circuit for a dual-array substrate of a VA / TN panel, characterized in that, include: A first sub-circuit is disposed on the upper substrate and a second sub-circuit is disposed on the lower substrate, wherein... Both the upper substrate and the lower substrate are array substrates; The first sub-circuit is configured such that: the first source and drain of the first transistor (T1) are coupled to the first data signal line (Data1), and the second source and drain are coupled to the first source and drain of the second transistor (T2) and one end of the first pre-storage capacitor (Cst1); the second source and drain of the second transistor (T2) are coupled to one end of the pixel capacitor (Clc); The second sub-circuit is configured such that: the first source-drain of the fourth transistor (T4) is coupled to the second data signal line (Data2), and the second source-drain is coupled to the first source-drain of the third transistor (T3) and one end of the second pre-storage capacitor (Cst2); the second source-drain of the third transistor (T3) is coupled to the other end of the pixel capacitor (Clc); When the first transistor (T1) and the fourth transistor (T4) are both N-type MOSFETs, and the second transistor (T2) and the third transistor (T3) are P-type MOSFETs, The gates of the first transistor (T1) and the second transistor (T2) are both coupled to the first control signal line (ScanT), and the gates of the third transistor (T3) and the fourth transistor (T4) are coupled to the second control signal line (ScanC). The driving timing of the pixel driving circuit is configured as follows: During the backlight-on phase of the Nth frame, the first control signal and the second control signal synchronously transition to a high potential line by line, the first transistor (T1) and the fourth transistor (T4) are synchronously turned on, the first data signal line (Data1) stores the first data signal containing the grayscale voltage into the first pre-storage capacitor (Cst1) through the first transistor (T1), and the second data signal line (Data2) stores the second data signal containing the reference voltage into the second pre-storage capacitor (Cst2) through the fourth transistor (T4), thus entering the backlight-off phase of the Nth frame; During the backlight off phase of frame N, the second control signal jumps to a low potential, the third transistor (T3) turns on, and the second pre-storage capacitor (Cst2) transmits the second data signal containing the reference voltage to one end of the pixel capacitor (Clc) through the third transistor (T3). Then, the second control signal jumps to a normal potential. After the third transistor (T3) turns off, the first control signal jumps to a low potential, the second transistor (T2) turns on, and the first pre-storage capacitor (Cst1) transmits the first data signal containing the grayscale voltage to the other end of the pixel capacitor (Clc) through the second transistor (T2). Then, the first control signal jumps back to a normal potential, the second transistor (T2) turns off, and the backlight on phase of frame N+1 begins.
2. The pixel driving circuit according to claim 1, characterized in that, The ends of the first pre-storage capacitor (Cst1) and the second pre-storage capacitor (Cst2) furthest from the transistor are both coupled to the common signal line (Com).
3. The pixel driving circuit according to claim 1, characterized in that, During the backlight-on phase of the N+1th frame, the first control signal and the second control signal synchronously transition to a high potential line by line, the first transistor (T1) and the fourth transistor (T4) are synchronously turned on, the first data signal line (Data1) stores the first data signal containing the reference voltage into the first pre-storage capacitor (Cst1) through the first transistor (T1), and the second data signal line (Data2) stores the second data signal containing the grayscale voltage into the second pre-storage capacitor (Cst2) through the fourth transistor (T4), and then enters the backlight-off phase of the N+1th frame; During the backlight off phase of frame N+1, the first control signal jumps to a low potential, the second transistor (T2) turns on, and the first pre-storage capacitor (Cst1) transmits a first data signal containing a reference voltage to one end of the pixel capacitor (Clc) through the second transistor (T2). After that, the first control signal jumps back to the normal potential, the second transistor (T2) turns off, the second control signal jumps to a low potential, the third transistor (T3) turns on, and the second pre-storage capacitor (Cst2) transmits a second data signal containing a grayscale voltage to the other end of the pixel capacitor (Clc) through the third transistor (T3). After that, the second control signal jumps back to the normal potential, the third transistor (T3) turns off, and the backlight on phase of frame N+2 begins.