Memory device generating per-pin reference voltage

Abstract

A memory device is provided, including: a plurality of reference voltage generators each corresponding to a plurality of data pins and generating a reference voltage for each of the respective data pins, wherein each of the plurality of reference voltage generators includes: a voltage divider dividing a supply voltage into a plurality of divided voltages; control logic receiving a first code indicative of internal reference voltage level information and a second code indicative of offset voltage information of the respective data pin, and generating a control code based on the first code and the second code; and a reference voltage selector including a tree structure of transmission gates selecting one of the plurality of divided voltages in response to the control code and outputting the selected divided voltage as the reference voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0004660, filed on January 13, 2025, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a memory device that generates a per-pin (PER-PIN) reference voltage. Background Technology

[0004] The memory device can receive data signals through multiple channels. The memory device has multiple receive buffers, and these receive buffers can be used to determine the logic level of the received data signal. The receive buffers can determine whether the logic level of the received data signal is "1" or "0" based on a reference voltage.

[0005] If the reference voltage is inaccurate, the error rate in determining the logic level of the data signal will increase, and the performance of the entire system will degrade. Typically, as data rates increase, the setup and hold times for latching data signals by comparing them to a reference voltage become shorter, thus requiring a more precise reference voltage. Therefore, a method has been proposed to set the reference voltage differently for each pin by considering the characteristics of the data signal and the characteristics of the channel through which the data signal is transmitted. Summary of the Invention

[0006] Embodiments of this disclosure may provide a memory device for generating a PER-PIN reference voltage.

[0007] The purposes of the embodiments disclosed herein are not limited to those mentioned in this specification, and other purposes not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] Embodiments of this disclosure may provide a memory device including a plurality of reference voltage generators, each reference voltage generator corresponding to a plurality of data pins and generating a reference voltage for each of the corresponding data pins, wherein each of the plurality of reference voltage generators includes: a voltage divider for dividing a power supply voltage into a plurality of divided voltages; control logic for receiving a first code indicating internal reference voltage level information and a second code indicating offset voltage information of the corresponding data pin, and generating control code based on the first code and the second code; and a reference voltage selector including a plurality of tree-structured transmission gates, the transmission gates selecting one of the plurality of divided voltages in response to the control code, and outputting the selected divided voltage as the reference voltage.

[0009] Embodiments of this disclosure may provide a memory device including a plurality of input / output circuit regions, each corresponding to a plurality of data pins, wherein each of the plurality of input / output circuit regions includes a receive buffer region and a reference voltage generator region, the reference voltage generator region providing a reference voltage to the receive buffer region, and wherein the reference voltage generator region includes: a voltage divider region for dividing a power supply voltage into a plurality of voltage dividers; a control logic region for receiving a first code indicating internal reference voltage level information and a second code indicating offset voltage information of the corresponding data pin, and generating control code based on the first code and the second code; and a reference voltage selector region for selecting one of the plurality of voltage dividers in response to the control code, and outputting the selected voltage divider as the reference voltage.

[0010] According to embodiments of the present disclosure, a memory device for generating a PER-PIN reference voltage can be provided, which can shorten the settling time of the reference voltage.

[0011] According to embodiments of this disclosure, a memory device that generates a PER-PIN reference voltage can be provided, which improves area efficiency.

[0012] The advantages of the embodiments disclosed herein are not limited to those described above. Other advantages not mentioned will be readily apparent to those skilled in the art from the description of the claims. Attached Figure Description

[0013] This disclosure will be more fully understood from the following detailed description and accompanying drawings, which are provided for illustrative purposes only and do not limit the scope of this disclosure.

[0014] Figure 1 This is a block diagram illustrating a system including a memory device according to an embodiment of the present disclosure.

[0015] Figure 2 This is a block diagram illustrating a data driver according to an embodiment of the present disclosure.

[0016] Figure 3 It is shown Figure 2 Block diagram of the first reference voltage generator.

[0017] Figure 4 yes Figure 3 An exemplary circuit diagram of a voltage divider.

[0018] Figure 5 yes Figure 3 An exemplary circuit diagram of the control logic.

[0019] Figure 6 yes Figure 3 The configuration diagram of the reference voltage selector.

[0020] Figure 7 It is a graph showing how the reference voltage level of the DQ0 pin changes according to the offset enable signal, the first code, and the second code in the memory device, according to an embodiment of the present disclosure.

[0021] Figure 8 This is a schematic diagram illustrating the arrangement of a receive buffer and a reference voltage generator according to an embodiment of the present disclosure.

[0022] Figures 9 to 11 It is shown Figure 8 A schematic diagram of the layout structure of the first input / output circuit area. Detailed Implementation

[0023] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. When assigning reference numerals to components in each drawing, the same components may be assigned the same reference numerals even if shown in different drawings. Details of known technology or function may be omitted if it is thought that they would obscure the subject matter of the present disclosure. As used herein, terms such as “comprising,” “having,” or “consisting of” related to components allow for the inclusion of additional components, unless a term such as “only” is explicitly used. Furthermore, singular expressions such as “a,” “an,” and “the” are intended to include their plural forms unless the context clearly indicates otherwise.

[0024] Representations such as “first,” “second,” “A,” “B,” “(a),” and “(b)” may be used to describe components of this disclosure. These representations are merely for distinguishing one component from another and are not for limiting the nature, order, sequence, or number of components.

[0025] Regarding the description of the positional relationship between components, when two or more components are described as "connected," "linked," or "linked," it should be understood that they may be directly "connected," "linked," or "linked," or they may have an intermediate component. Here, the intermediate component may be included in one or more of the two or more components that are "connected," "linked," or "linked" to each other.

[0026] When using terms such as “after,” “next,” “following,” or “before,” to describe the temporal or sequential relationship between components, methods of operation, or methods of manufacture, they may also include discontinuous cases unless explicitly used with terms such as “immediately” or “directly.”

[0027] When a component is associated with a value or its corresponding information (e.g., level), such value or information can be interpreted as including tolerances due to various factors (e.g., process variation, internal or external shocks or noise), even without an explicit separate description.

[0028] In the following, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0029] Figure 1 This is a block diagram illustrating a system including a memory device according to an embodiment of the present disclosure.

[0030] Reference Figure 1 The system 10 includes a memory device 100 and a memory controller 200.

[0031] The memory device 100 can store data. The memory device 100 can operate in response to the control of the memory controller 200.

[0032] The memory device 100 can receive data signals from the memory controller 200. The memory controller 200 can output data signals to the memory device 100, or it can receive data signals from the memory device 100 or the host. Data signals include commands, addresses, and data.

[0033] Memory device 100 may include multiple memory cells. Memory device 100 includes a data drive unit 110 (hereinafter referred to as the "DQ drive unit") and multiple data pins (not shown, referred to as "DQ pins"). Data signals from memory controller 200 are input to the DQ pins of memory device 100 through multiple channels. The DQ drive unit 110 can generate a reference voltage for each DQ pin, and the received data signal can be determined using the PER-PIN reference voltage.

[0034] The PER-PIN reference voltage can be set to an appropriate voltage level by taking into account the characteristics of the data signal and the characteristics of the channel through which the data signal is transmitted. Therefore, the reference voltage can be a different value for each DQ pin.

[0035] Information relating to the reference voltage for each of the multiple DQ pins can be stored in the form of code in a separate memory circuit, such as a mode register. The DQ drive unit 110 can generate a reference voltage based on the reference voltage-related code. The reference voltage-related code can be determined during the training process of the memory device 100.

[0036] The memory device 100 can support termination modes by connecting a termination resistor to the end of the transmission line. The end of the transmission line can be terminated by the termination resistor at a constant voltage level. The memory device 100 can support a first termination mode and a second termination mode. For example, the first termination mode can be an LTT (Low Tap Termination) mode, and the second termination mode can be a PI-LTT (Power Isolation LTT) mode. Depending on the termination mode, the reference voltage can have different voltage ranges. For example, the range of the reference voltage in the LTT mode can be different from the range of the reference voltage in the PI-LTT mode.

[0037] Figure 2 This is a block diagram illustrating a data driver according to an embodiment of the present disclosure.

[0038] For ease of description below, the DQ drive unit 110 will be described as a receiver for reading input data, but the embodiments are not limited thereto. For example, the DQ drive unit 110 may include a transmitter for transmitting data to an external device.

[0039] Reference Figure 2 The DQ drive unit 110 includes a first reference voltage generator 121 to an eighth reference voltage generator 128, which correspond to the first receive buffer 111 to the eighth receive buffer 118, respectively.

[0040] The first receive buffer 111 to the eighth receive buffer 118 can receive the first input data signal (DIN0) to the eighth input data signal (DIN7) respectively through the first DQ pin (DQ0) to the eighth DQ pin (DQ7). For example, the first receive buffer 111 can receive the first input data signal (DIN0) through the first DQ pin (DQ0), and the second receive buffer 112 can receive the second input data signal (DIN1) through the second DQ pin (DQ1). Similarly, the third receive buffer 113 to the eighth receive buffer 118 can receive the third input data signal (DIN2) to the eighth input data signal (DIN7) respectively through the third DQ pin (DQ2) to the eighth DQ pin (DQ7).

[0041] Each of the first reference voltage generator 121 to the eighth reference voltage generator 128 can receive an offset enable signal (EN_OFS), a first code (VREF_CODE<6:0>), and a second code (DQ#_OFS<3:0>), where # is an integer between 0 and 7, including both 0 and 7.

[0042] The offset enable signal (EN_OFS) and the first code (VREF_CODE<6:0>) can be jointly provided to the first reference voltage generator 121 through the eighth reference voltage generator 128. The second code (DQ#_OFS<3:0>) can be provided individually to the first reference voltage generator 121 through the eighth reference voltage generator 128. For example, DQ0_OFS<3:0> can be provided to the first reference voltage generator 121, and DQ1_OFS<3:0> can be provided to the second reference voltage generator 122. Similarly, DQ2_OFS<3:0> through DQ7_OFS<3:0> can be provided to the third reference voltage generator 123 through the eighth reference voltage generator 128, respectively.

[0043] The first reference voltage generator 121 to the eighth reference voltage generator 128 can generate reference voltages (VREF_DQ0 to VREF_DQ7) based on the first code (VREF_CODE<6:0>) and the second code (DQ0_OFS<3:0> to DQ7_OFS<3:0>).

[0044] The first code (VREF_CODE<6:0>) indicates the level information of the internal reference voltage, and the second code (DQ#_OFS<3:0>) indicates the offset voltage information used to adjust the reference voltage used in the current determination operation.

[0045] In the second code (DQ#_OFS<3:0>), the most significant bit is DQ#_OFS. <3> Indicates a positive or negative sign ("+" or "-"), except for DQ#_OFS <3> The remaining bits (i.e., DQ#_OFS<2:0>) can represent the offset voltage value. That is, the second code (DQ#_OFS<3:0>) can represent a positive offset voltage value or a negative offset voltage value. For example, if the level of the internal reference voltage indicated by the first code (VREF_CODE<6:0>) is Vref, and if the second code (DQ0_OFS<3:0>) input to the first reference voltage generator 121 represents +Voffset, then the first reference voltage (VREF_DQ0) output from the first reference voltage generator 121 can have a voltage level of Vref + Voffset.

[0046] The reference voltages (VREF_DQ0 to VREF_DQ7) generated by the first reference voltage generator 121 to the eighth reference voltage generator 128 can be different from each other. Optionally, the reference voltage generated by one of the first reference voltage generator 121 to the eighth reference voltage generator 128 can be different from the reference voltage generated by any other reference voltage generator.

[0047] The first receive buffer 111 through the eighth receive buffer 118 can each receive a reference voltage from a corresponding reference voltage generator, and can determine the logic level of the data signal input through the corresponding DQ pin based on the received reference voltage. For example, the first receive buffer 111 can receive a first reference voltage (VREF_DQ0) from the first reference voltage generator 121, determine the logic level of the first input data signal (DIN0) based on the first reference voltage (VREF_DQ0), and generate a first data signal (D0). The second receive buffer 112 can receive a second reference voltage (VREF_DQ1) from the second reference voltage generator 122, determine the logic level of the second input data signal (DIN1) based on the second reference voltage (VREF_DQ1), and generate a second data signal (D1). The description of the first receive buffer 111 and the second receive buffer 112 also applies to the third receive buffer 113 through the eighth receive buffer 118.

[0048] exist Figure 2 In this embodiment, the memory device includes eight receive buffers and eight reference voltage generators, but other embodiments are not limited to this. The number of receive buffers and voltage generators included in the memory device can vary depending on the number of DQ pins.

[0049] Figure 3 It is shown Figure 2 Block diagram of the first reference voltage generator.

[0050] The following description of the first reference voltage generator 121 is similarly applicable to... Figure 2 The second to eighth reference voltage generators (122 to 128).

[0051] Reference Figure 3 The first reference voltage generator 121 includes a voltage divider 121A, control logic 121B, and a reference voltage selector 121C.

[0052] Voltage divider 121A can divide the power supply voltage to generate multiple voltage dividers (Vout<127:0>).

[0053] The reference voltage selector 121C can receive multiple divided voltages (Vout<127:0>) from the voltage divider 121A; receive control code (CODE0<6:0>) and inverting control code (CODEB0<6:0>) from the control logic 121B; select one of the multiple divided voltages (Vout<127:0>) based on the control code (CODE0<6:0>) and the inverting control code (CODEB0<6:0>); and output the divided voltage as the first reference voltage (VREF_DQ0).

[0054] Control logic 121B is enabled by the offset signal ( Figure 2 EN_OFS is enabled to generate control code (CODE0<6:0>) and inverted control code (CODEB0<6:0>) based on the first code (VREF_CODE<6:0>) and the second code (DQ0_OFS<3:0>).

[0055] Figure 3 This shows 128 voltage dividers (Vout<127:0>) and a 7-bit control code, but the number of bits in the control code can vary depending on the number of voltage dividers. For example, when the number of voltage dividers is 2... n When n is an integer greater than or equal to 2, the control code can be n bits (where n is an integer greater than or equal to 2).

[0056] Figure 4 yes Figure 3 An exemplary circuit diagram of a voltage divider.

[0057] Reference Figure 4 The voltage divider 121A generates multiple voltage dividers (Vout<127:0>) in response to an inverting enable signal (ENB_VREF). The voltage divider 121A includes a switch 410, a first resistor (R1), and a resistor ladder 420.

[0058] Switch 410 can be connected between power supply voltage terminal 430 and the first node (N1), and can respond to an offset enable signal ( Figure 2 The EN_OFS terminal is activated. Power supply voltage terminal 430 can be a power supply voltage pin.

[0059] Switch 410 may include a PMOS transistor. The drain electrode of the PMOS transistor may be connected to the power supply voltage terminal 430, the source electrode of the PMOS transistor may be connected to the first node (N1), and an inverting enable signal (ENB_VREF) may be input to the gate electrode of the PMOS transistor. Switch 410 may be turned on in response to the low-level inverting enable signal (ENB_VREF) to transfer the power supply voltage supplied to the power supply voltage terminal 430 to the first node (N1).

[0060] The level of the power supply voltage supplied to the power supply voltage terminal 430 can vary depending on the termination mode. In a first termination mode, the power supply voltage can have a first level voltage value, and in a second termination mode, the power supply voltage can have a second level voltage value, which is different from the first level. For example, the first termination mode can be an LTT mode, the second termination mode can be a PI-LTT mode, and the power supply voltage in the LTT mode can be 1.2 [V], and the power supply voltage in the PI-LTT mode can be 0.6 [V].

[0061] Voltage divider 121A can distribute the power supply voltage at different levels according to the termination mode to generate a divided voltage (Vout<127:0>). Therefore, the reference voltage can have different voltage ranges depending on the termination mode.

[0062] The first resistor (R1) is connected between the first node (N1) and the second node (N2). The resistor ladder 420 includes a plurality of second resistors (R2) connected in series between the second node (N2) and the ground node (VSS).

[0063] The voltage level of the second node (N2) can be determined by a standard. For example, the voltage level of the second node (N2) can be K times the supply voltage (where K is a positive number less than 1), and the value of K can be determined by a standard. The first resistor (R1) and the second resistor (R2) can have different resistivities. The resistivity of the first resistor (R1) can be greater than the resistivity of the second resistor (R2). Because the first resistor (R1) has a higher resistivity than the second resistor (R2), the area occupied by the first resistor (R1) can be reduced compared to the case where the resistivity of the first resistor R1 is equal to or less than the resistivity of the second resistor (R2).

[0064] The resistor ladder 420 distributes the potential difference between the second node (N2) and the ground voltage terminal (VSS) in a voltage divider manner to generate multiple divided voltages (Vout<127:0>).

[0065] Figure 5 yes Figure 3 An exemplary circuit diagram of the control logic.

[0066] Reference Figure 5 The control logic 121B includes the first XOR gate 51A to the seventh XOR gate 51G, the first decrementer 52A to the seventh decrementer 52G, and the first inverter 53A to the seventh inverter 53G.

[0067] In each of the first subtractors 52A to the seventh subtractors 52G, IN1 and IN2 are input terminals, CI is the terminal for inputting the carry value, S is the output terminal, and CO is the terminal for outputting the carry value. Based on the exemplary inputs and outputs, the operation of each of the first subtractors 52A to the seventh subtractors 52G is shown in Table 1 below.

[0068] Table 1

[0069]

[0070] The most significant bit of the second code (DQ0_OFS) <3> The first XOR gate 51A is provided as the setting value for the first subtractor 52A and as the first input for the first XOR gate 51A to the seventh XOR gate 51G. The remaining bits of the second code (DQ0_OFS<2:0>) are provided as the second inputs for the first XOR gate 51A to the third XOR gate 51C, respectively. A low-level voltage (VSSI) is provided as the second input for the fourth XOR gate 51D to the seventh XOR gate 51G.

[0071] If the most significant bit of the second code (DQ0_OFS) <3> If the most significant bit (DQ0_OFS<2:0>) is "0", then control logic 121B performs the operation of adding the remaining bits of the second code (excluding the most significant bit) to the first code (REF_CODE<6:0>) to generate control code (CODE0<6:0>). If the most significant bit (DQ0_OFS) of the second code is "0", then... <3> If the value is "1", then control logic 121B performs the operation of subtracting the remaining bits of the second code (excluding the most significant bit) (DQ0_OFS<2:0>) from the first code (REF_CODE<6:0>) to generate the control code (CODE0<6:0>).

[0072] The input terminals of the first inverter 53A to the seventh inverter 53G are respectively connected to the output terminals (S) of the first subtractor 52A to the seventh subtractor 52G. The control code (CODE<6:0>) output from the output terminals (S) of the first subtractor 52A to the seventh subtractor 52G is inverted to generate an inverted control code (CODEB0<6:0>).

[0073] Figure 5 The illustration shows a case where the number of voltage dividers (Vout<127:0>) is 128, and the number of inverters and subtractors are both 7. However, in other embodiments, the number of inverters and subtractors can vary depending on the number of voltage dividers. For example, when the number of voltage dividers is 2... n At this time, the number of inverters and the number of subtractors can be n respectively.

[0074] Figure 6 yes Figure 3 The configuration diagram of the reference voltage selector.

[0075] Reference Figure 6 The reference voltage selector 121C includes multiple transmission gates. These transmission gates can be layered into multiple layers (L1 to L7). In this embodiment, the multiple layers include layers one through seven (L1 to L7).

[0076] The voltage divider voltages (Vout<127:0>) are input from voltage divider 121A to the input terminals of the transmission gates in the first layer (L1). The number of transmission gates in the first layer (L1) can be equal to the number of voltage divider voltages (Vout<127:0>). For example... Figure 6 As shown, when the number of voltage dividers (Vout<127:0>) is 128, the number of transmission gates in the first layer (L1) can be 128.

[0077] In each of the first layer (L1) to the seventh layer (L7), the transmission gates have a binary tree structure. In each of the first layer (L1) to the seventh layer (L7), two transmission gates are paired and connected to a common output terminal.

[0078] The output terminals of layer K are connected to the input terminals of the transmission gates in layer (K+1). The number of transmission gates in layer (K+1) can be half the number of transmission gates in layer K. Figure 6 As shown, the number of transmission gates included in the first layer (L1), the second layer (L2), the third layer (L3), the fourth layer (L4), the fifth layer (L5), the sixth layer (L6), and the seventh layer (L7) are 128, 64, 32, 16, 8, 4, and 2, respectively.

[0079] The transmission gate can have a CMOS structure. That is, the transmission gate can include an NMOS transistor and a PMOS transistor connected in parallel between the input terminal and the output terminal, and when both the NMOS transistor and the PMOS transistor are turned on, the signal at the input terminal can be output to the output terminal.

[0080] One bit of the control code and its inverse phase are input to each of the first to seventh layers (L1). Based on this single bit of the control code and its inverse phase, one of the two transmission gates in a pair within the k-th layer can be turned on, while the other can be turned off. For example, when two transmission gates (TG1, TG2) in a pair in the seventh layer (L7) are referred to as the first transmission gate (TG1) and the second transmission gate (TG2), one of them can be turned on, while the other can be turned off.

[0081] The gate electrode of the NMOS transistor (NMOS1) of the first transmission gate (TG1) and the gate electrode of the PMOS transistor (PMOS2) of the second transmission gate (TG2) can be connected together to the first line (W1), and the gate electrode of the PMOS transistor (PMOS1) of the first transmission gate (TG1) and the gate electrode of the NMOS transistor (NMOS2) of the second transmission gate (TG2) can be connected together to the second line (W2). <6> and CODEB0 <6> The inputs are respectively connected to the first line (W1) and the second line (W2). Therefore, one of the first transmission gate (TG1) and the second transmission gate (TG2) can be turned on, and the other can be turned off, allowing one of the voltage dividers input to the first transmission gate (TG1) or the second transmission gate (TG2) to be output. For example, when a "logic high" is input to the first line (W1) and a "logic low" is input to the second line (W2), the first transmission gate (TG1) is turned on and the second transmission gate (TG2) is turned off, causing the voltage divider input to the first transmission gate (TG1) to be output. Conversely, when a "logic low" is input to the first line (W1) and a "logic high" is input to the second line (W2), the first transmission gate (TG1) is turned off and the second transmission gate (TG2) is turned on, causing the voltage divider input to the second transmission gate (TG2) to be output.

[0082] The transmission gates included in layers 1 (L1) to 6 (L6) can also operate in a similar manner to the transmission gates included in layer 7 (L7).

[0083] exist Figure 6 In this embodiment, the number of voltage dividers is 128, the reference voltage selector (121C) comprises 7 layers, and the control code has 7 bits. However, in other embodiments, the number of layers included in the reference voltage selector (121C) can vary depending on the number of voltage dividers. For example, when the number of voltage dividers is 2... n In this case, the number of layers included in the reference voltage selector (121C) can be n, and the control code can be n bits.

[0084] Figure 7 It is a graph showing how the reference voltage level of the DQ0 pin changes according to the offset enable signal, the first code, and the second code in the memory device, according to an embodiment of the present disclosure.

[0085] Reference Figure 7 When the offset enable signal (EN_OFS) is at a "high" level, the DQ driver generates a reference voltage for each DQ pin.

[0086] When the offset enable signal (EN_OFS) is at a "high" level and when the most significant bit (DQ0_OFS) of the second code (DQ0_OFS<3:0>) is... <3> When the offset enable signal (EN_OFS) is at a "high" level, the first reference voltage generator of the DQ driver generates the reference voltage (VREF_DQ0) for the DQ0 pin by adding the internal reference voltage (0 offset) corresponding to the first code (VREF_CODE<6:0>) and the offset voltage corresponding to DQ0_OFS<2:0>. For example, when the offset enable signal (EN_OFS) is at a "high" level, DQ0_OFS <3> When at a “high” level, and when DQ0_OFS<2:0> is at “4”, the first reference voltage generator generates the reference voltage (VREF_DQ0) of the DQ0 pin by adding the internal reference voltage (0 offset) and the offset voltage corresponding to level “4”.

[0087] When the offset enable signal (EN_OFS) is at a "high" level, and when the most significant bit (DQ0_OFS) of the second code (DQ0_OFS<3:0>) is... <3> When the offset enable signal (EN_OFS) is at a "low" level, the first reference voltage generator subtracts the offset voltage corresponding to DQ0_OFS<2:0> from the internal reference voltage (0 offset) to generate the reference voltage (VREF_DQ0) for the DQ0 pin. For example, when the offset enable signal (EN_OFS) is at a "low" level, when DQ0_OFS... <3> When at a "low" level, and when DQ0_OFS<2:0> is "4", the first reference voltage generator subtracts the offset voltage corresponding to level "4" from the internal reference voltage (0 offset) to generate the reference voltage (VREF_DQ0) for the DQ0 pin. Figure 7 In this configuration, when the offset enable signal (EN_OFS) transitions from a "low" level to a "high" level, DQ0_OFS<2:0> is "0". Therefore, the offset voltage is 0, and the reference voltage (VREF_DQ0) of the DQ0 pin has the same value as the internal reference voltage (0 offset).

[0088] When the offset enable signal (EN_OFS) is low, the DQ driver sets the reference voltage of all DQ pins to the internal reference voltage (0 offset). Figure 7 When the offset enable signal (EN_OFS) transitions from a "high" level to a "low" level, the DQ0 reference voltage (VREF_DQ0) changes from the value OFS+2 to the internal reference voltage (0 offset). While the offset enable signal (EN_OFS) is at a "low" level, the DQ0 reference voltage (VREF_DQ0) remains at the internal reference voltage (0 offset).

[0089] The advantages of embodiments according to this disclosure include the following.

[0090] Unlike this disclosure, a configuration 2 may exist. n A method with one transmission gate, each transmission gate input 2. n A voltage divider, making 2 n One of the transmission gates is turned on and the other transmission gates are turned off, in order to select 2. n One of the voltage dividers is used as the reference voltage. In this case, because 2... n Bit control code to control 2 n Because it requires a large number of transmission gates, a large number of components are needed to configure the circuitry for generating the control code, and the size of the circuitry for generating the control code can be relatively large. This is because the reference voltage selector (121C) according to this disclosure uses only n-bit control codes to select 2... n One of the voltage dividers, so the control logic that generates the control code can be configured with a small number of components in a small size. Therefore, area efficiency can be improved.

[0091] Figure 8 This is a schematic diagram illustrating the arrangement of a receive buffer and a reference voltage generator according to an embodiment of the present disclosure.

[0092] Reference Figure 8 The memory device includes a first input / output circuit region (R-IO0) to an eighth input / output circuit region (R-IO7) corresponding to a first DQ pin to an eighth DQ pin, respectively. Although not shown, the first DQ pin to the eighth DQ pin may be arranged in the first input / output circuit region (R-IO0) to the eighth input / output circuit region (R-IO7), respectively. Figure 8 It includes eight input / output circuitry areas, but this is just an example; in other embodiments, the number of input / output circuitry areas may vary depending on the number of DQ pins.

[0093] The first input / output circuit area (R-IO0) to the eighth input / output circuit area (R-IO7) can be arranged in a row along the first horizontal direction (HD1).

[0094] Each of the first input / output circuit regions (R-IO0) to the eighth input / output circuit regions (R-IO7) includes a receive buffer and a reference voltage generator. In each of the first input / output circuit regions (R-IO0) to the eighth input / output circuit regions (R-IO7), a reference voltage output from the reference voltage generator is input to the receive buffer. For example, a first receive buffer 111 and a first reference voltage generator 121 are arranged in the first input / output circuit region (R-IO0). A first reference voltage (VREF_DQ0) output from the first reference voltage generator 121 is input to the first receive buffer 111. The description of the first input / output circuit region (R-IO0) is similarly applicable to the second input / output circuit regions (R-IO1) to the eighth input / output circuit regions (R-IO7).

[0095] Unlike this disclosure, in the comparative device, the reference voltage generator can be arranged in an area separate from the receiving buffer. In this case, the wiring for transmitting the reference voltage output from the reference voltage generator to the receiving buffer becomes longer, and the time delay during the transmission of the reference voltage increases, which may cause the establishment time of the reference voltage to exceed a preset threshold, and the signal characteristics may deteriorate.

[0096] According to this disclosure, because the reference voltage generator and the receiving buffer to which the reference voltage output from the reference voltage generator is input are arranged in a single input / output circuit area, the wiring used to transmit the reference voltage can be configured to have a shorter length. Furthermore, the time delay occurring during the transmission of the reference voltage from the reference voltage generator to the receiving buffer can be reduced, and the settling time of the reference voltage can be shortened.

[0097] Figures 9 to 11 It is shown Figure 8 A schematic diagram of the layout structure of the first input / output circuit area.

[0098] Reference Figure 9 The first input / output circuit region (R_IO0) includes a first region (R1) and a reference voltage generator region (R-121A, R-121B and R-121C).

[0099] The first region (R1) includes a DQ pin region (R-DQ0), a transmit buffer region (R-Tx), and a receive buffer region (R-Rx). The DQ pins can be arranged in the DQ pin region (R-DQ0), the transmit buffer can be arranged in the transmit buffer region (R-Tx), and the receive buffer can be arranged in the receive buffer region (R-Rx).

[0100] In this embodiment, the reference voltage generator regions (R-121A, R-121B, and R-121C) may be arranged outside the first region (R1). The reference voltage generator regions (R-121A, R-121B, and R-121C) may be arranged adjacent to the receive buffer region (R-Rx) and the transmit buffer region (R-Tx) in the second horizontal direction (HD2).

[0101] The reference voltage generator area includes the voltage divider area (R-121A), the control logic area (R-121B), and the reference voltage selector area (R-121C). Figure 3 The voltage divider (121A), control logic (121B), and reference voltage selector (121C) are respectively arranged in the voltage divider area (R-121A), control logic area (R-121B), and reference voltage selector area (R-121C).

[0102] The receive buffer region (R-Rx) is positioned closer to the reference voltage selector region (R-121C) than the DQ pin region (R-DQ0). At least a portion of the reference voltage selector region (R-121C) may overlap with the receive buffer region (R-Rx) in the second horizontal direction (HD2). The voltage divider region (R-121A) and the control logic region (R-121B) may be positioned on either side of the reference voltage selector region (R-121C) in the first horizontal direction (HD1), respectively.

[0103] In the first region (R1), the pull-up driver region (R-PUD) and the pull-down driver region (R-PDD) can be arranged on both sides of the first horizontal direction (HD1) of the DQ pin region (R-DQ0). The pull-up driver is arranged in the pull-up driver region (R-PUD), and the pull-down driver is arranged in the pull-down driver region (R-PDD).

[0104] According to this disclosure, the reference voltage selector region (R-121C) is adjacent to the receive buffer region (R-Rx), and at least a portion of the reference voltage selector region (R-121C) overlaps with the receive buffer region (R-Rx) in the second horizontal direction (HD2). Therefore, when the reference voltage selector region (R-121C) and the receive buffer region (R-Rx) are connected, the wiring for transmitting the reference voltage output from the reference voltage selector to the receive buffer can be configured to have a shorter length and can extend in the second horizontal direction (HD2).

[0105] Reference Figure 10 The reference voltage generator regions (R-121A, R-121B, and R-121C) can be arranged adjacent to the first region (R1) in the first horizontal direction (HD1). For example... Figure 10 As shown, the reference voltage generator regions (R-121A, R-121B, and R-121C) can be arranged to the left of the first region (R1). Although not shown, the reference voltage generator regions (R-121A, R-121B, and R-121C) can also be arranged to the right of the first region (R1).

[0106] At least a portion of the reference voltage selector region (R-121C) may overlap with the receive buffer region (R-Rx) in the first horizontal direction (HD1). The voltage divider region (R-121A) and the control logic region (R-121B) are respectively arranged on both sides of the reference voltage selector region (R-121C) in the second horizontal direction (HD2).

[0107] Reference Figure 11 The voltage divider area (R-121A) and the reference voltage selector area (R-121C) can be arranged between the transmit buffer area (R-Tx) and the receive buffer area (R-Rx).

[0108] The reference voltage selector region (R-121C) can be arranged closer to the receive buffer region (R-Rx) than the voltage divider region (R-121A). The reference voltage selector region (R-121C) can be arranged in the first horizontal direction (HD1) between the voltage divider region (R-121A) and the receive buffer region (R-Rx). The voltage divider region (R-121A) can be arranged in the first horizontal direction (HD1) between the reference voltage selector region (R-121C) and the transmit buffer region (R-Tx).

[0109] The control logic region (R-121B) may overlap with the reference voltage selector region (R-121C) in the second horizontal direction (HD2). For example, the control logic region (R-121B) may be arranged adjacent to the voltage divider region (R-121A), the reference voltage selector region (R-121C), and the receive buffer region (R-Rx) in the second horizontal direction (HD2).

[0110] The above description is merely an illustrative explanation of this disclosure. Therefore, those skilled in the art to which this disclosure pertains can make various modifications and variations without departing from the essential characteristics of this disclosure. Furthermore, the embodiments disclosed herein are not intended to limit the scope of this disclosure, but rather to explain it. Therefore, the scope of this disclosure should not be limited by the embodiments.

Claims

1. A memory device, comprising: Multiple reference voltage generators, each corresponding to multiple data pins, generate a reference voltage for each of the corresponding data pins. Each of the plurality of reference voltage generators includes: A voltage divider divides the power supply voltage into multiple voltage dividers. The control logic receives a first code and a second code, and generates control code based on the first code and the second code. The first code indicates internal reference voltage level information, and the second code indicates the offset voltage information of the corresponding data pin. A reference voltage selector includes a plurality of tree-structured transmission gates, which selects one of the plurality of voltage dividers in response to the control code and outputs the selected voltage divider as the reference voltage.

2. The memory device according to claim 1, wherein, The multiple tree-structured transmission gates are grouped into multiple layers. In each of the multiple layers, two transmission gates share a single output terminal, and In response to the control code, one of the two transmission gates is turned on, and the other is turned off.

3. The memory device according to claim 1, wherein, The number of the plurality of voltage dividers is 2. n The control code is n bits, where n is an integer greater than or equal to 2.

4. The memory device according to claim 1, wherein, In the first termination mode, the voltage of the first level is provided to the voltage divider as the power supply voltage, and In the second termination mode, a second voltage level is provided to the voltage divider as the power supply voltage, and the second voltage level is different from the first voltage level.

5. The memory device according to claim 1, wherein, The voltage divider includes: A switch is connected between the power supply voltage terminal and the first node, and is turned on in response to an inverting enable signal; A first resistor is connected between the first node and the second node; and A resistance ladder includes a plurality of second resistors connected in series between the second node and the ground voltage terminal, and The resistivity of the first resistor is different from that of the second resistor.

6. The memory device according to claim 5, wherein, The resistivity of the first resistor is higher than that of the second resistor.

7. The memory device according to claim 1, wherein, The control logic includes multiple subtractors that add or subtract the remaining bits of the second code, excluding the most significant bit of the second code, from the first code.

8. The memory device according to claim 1, wherein, The first code is provided to the plurality of reference voltage generators, and The second code provided to the first reference voltage generator among the plurality of reference voltage generators is different from the second reference voltage generator provided to the second reference voltage generator among the plurality of reference voltage generators.

9. A memory device, comprising: Multiple input / output circuit regions, each of which corresponds to multiple data pins. in, Each of the plurality of input / output circuit regions includes: Receive buffer area; and The reference voltage generator region provides a reference voltage to the receive buffer region. The reference voltage generator region includes: In the voltage divider area, the power supply voltage is divided into multiple voltage dividers; The control logic area receives a first code and a second code, and generates control code based on the first code and the second code. The first code indicates internal reference voltage level information, and the second code indicates the offset voltage information of the corresponding data pin. The reference voltage selector region, in response to the control code, selects one of the plurality of voltage dividers and outputs the selected voltage divider as the reference voltage.

10. The memory device according to claim 9, wherein, Each of the plurality of input / output circuit regions further includes a data pin region and a transmit buffer region. The data pin area, the receive buffer area, and the transmit buffer area are included in the first area, and The reference voltage generator region is located outside the first region.

11. The memory device according to claim 10, wherein, The plurality of input / output circuit regions are arranged in a row along the first horizontal direction. The reference voltage generator region is arranged adjacent to the first region in the second horizontal direction, and The second horizontal direction is perpendicular to the first horizontal direction.

12. The memory device according to claim 11, wherein, The receive buffer region is positioned closer to the reference voltage generator region than the data pin region.

13. The memory device according to claim 11, wherein, At least a portion of the reference voltage selector region overlaps with the receive buffer region in the second horizontal direction.

14. The memory device according to claim 11, wherein, The voltage divider region and the control logic region are respectively arranged on both sides of the reference voltage selector region in the first horizontal direction.

15. The memory device according to claim 10, wherein, The plurality of input / output circuit regions are arranged in a row along a first horizontal direction, and The reference voltage generator region is arranged adjacent to the first region in the first horizontal direction.

16. The memory device according to claim 15, wherein, At least a portion of the reference voltage selector region overlaps with the receive buffer region in the first horizontal direction.

17. The memory device according to claim 15, wherein, The voltage divider region and the control logic region are respectively arranged on both sides of the reference voltage selector region in a second horizontal direction, which is perpendicular to the first horizontal direction.

18. The memory device according to claim 10, wherein, The plurality of input / output circuit regions are arranged in a row along a first horizontal direction, and The voltage divider region and the receiving buffer region are respectively arranged on both sides of the reference voltage selector region in the first horizontal direction.

19. The memory device according to claim 18, wherein, The receiving buffer region and the transmitting buffer region are arranged along the first horizontal direction, and The voltage divider region and the reference voltage selector region are respectively located between the receive buffer region and the transmit buffer region.

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