Nonvolatile memory control system with dynamic threshold voltage adjustment

Abstract

The application relates to the technical field of nonvolatile storage control, and discloses a nonvolatile storage control system with dynamic threshold voltage adjustment, which comprises a read interference monitoring unit, a temperature acquisition unit, a threshold calibration control module and a read circuit.The read interference monitoring unit is used for acquiring read interval duration data of a target storage unit; the temperature acquisition unit is used for acquiring real-time temperature data; the threshold calibration control module is used for determining an attenuation coefficient of charge detrapping characteristics of a storage medium according to the duration data, carrying out attenuation calculation on an initial interference cumulative value to determine a dynamic interference cumulative value, and then generating a target voltage offset and outputting a reference adjustment signal in combination with the real-time temperature data; and the read circuit is used for adjusting a reference end potential of a sensing amplifier according to the signal.The application corrects an interference model based on the physical law of charge detrapping characteristics, effectively offsets threshold voltage rollback caused by physical relaxation, widens a read window of a multi-level storage architecture, and guarantees data read reliability of the system in a high-frequency access environment.

Description

Technical Field

[0001] This invention relates to the field of non-volatile memory control technology, and more specifically, to a non-volatile memory control system with dynamic threshold voltage adjustment. Background Technology

[0002] As a core support for modern intensive computing architectures, non-volatile memory technology plays a crucial role as a data carrier in high-frequency concurrent access scenarios such as cloud platforms and IoT data centers. In multi-level memory cell architecture, memory cells represent multi-bit information through charge trapping states of different magnitudes. This requires high accuracy in the distribution of threshold voltage. In order to maintain the accuracy of data reading, existing memory control systems usually adopt interference monitoring methods based on the accumulation of reading counts. By recording the access history of specific word lines and querying a preset offset table, the sensing amplifier is driven to adjust the reading reference voltage.

[0003] However, in actual large-scale concurrent read operations, the charge trapping layer of the storage medium exhibits significant temporal relaxation hysteresis. This physical characteristic means that the charge trapping and escape process does not increase monotonically and linearly with the number of reads. When the physical word line is subjected to high-frequency burst reads, the charge traps generate a sharp accumulation of electrons and induce a threshold voltage shift. However, during the physical rest interval between two read operations, the trapped electrons will spontaneously detrap due to the intrinsic thermal excitation of the material, resulting in a nonlinear physical drop in the threshold voltage. Since traditional controllers lack physical awareness of the word line rest duration, their fixed linear accumulation model cannot distinguish between acute interference and long-term slow-release interference. When faced with read requests with long-tailed intervals, they often output an excessive reference voltage offset based on the total number of historical reads. This rigid overcompensation directly compresses the read window margin of the storage cell, which in turn induces uncorrectable errors.

[0004] Therefore, how to construct a read bias adjustment mechanism that can sense the charge relaxation effect and realize dynamic offsetting of interference to eliminate the overcompensation phenomenon in irregular access mode has become the technical problem to be solved by this invention. Summary of the Invention

[0005] This invention provides a non-volatile memory control system for dynamic threshold voltage adjustment, the system comprising: The read interference monitoring unit is used to acquire the read operation history information of the target storage unit and its adjacent storage units, and to calculate the read interval duration data between two adjacent read operations based on the read operation history information. Temperature acquisition unit, used to acquire real-time temperature data of the current system environment; The threshold calibration control module is connected to the read interference monitoring unit and the temperature acquisition unit, respectively. It is used to determine the attenuation coefficient in the corresponding time domain based on the read interval duration data and the preset medium physical charge de-trapping characteristic curve. It also uses the attenuation coefficient to perform a reduction calculation on the initial interference accumulation value extracted from the non-volatile register at the previous moment to obtain the dynamic interference accumulation value at the current moment. The threshold calibration control module is also used to map and convert the real-time temperature data and the dynamic interference accumulation value to generate the target voltage offset corresponding to the target storage unit and output the corresponding reference adjustment signal to the read circuit. The readout circuit is connected to the threshold calibration control module. The readout circuit includes a sensing amplifier and a digital-to-analog converter module. The digital-to-analog converter module is used to adjust the input level of the reference terminal of the sensing amplifier according to the reference adjustment signal so that the input level of the reference terminal is locked at the target reference voltage that matches the target voltage offset.

[0006] Preferably, when determining the cumulative value of dynamic interference, the threshold calibration control module retrieves the target attenuation factor corresponding to the reading interval duration data by searching a preset attenuation mapping table; the threshold calibration control module determines the product of the initial cumulative value of interference and the target attenuation factor as the existing interference correction component, and sums the existing interference correction component with the transient interference increment generated by this reading operation to complete the numerical update of the cumulative value of dynamic interference.

[0007] Preferably, the read interference monitoring unit includes a timestamp memory, which records the current count value of the system clock to generate a current timestamp each time a read instruction for the target storage unit is received; the read interference monitoring unit calculates the difference between the current timestamp and the previous read timestamp in the historical record to generate read interval duration data.

[0008] Preferably, when generating the target voltage offset, the threshold calibration control module determines the voltage regulation gain for the corresponding temperature range based on real-time temperature data; if the real-time temperature data exceeds the preset temperature alarm threshold, the threshold calibration control module linearly increases the conversion ratio coefficient between the cumulative dynamic interference value and the target voltage offset to compensate for the shrinkage of the read margin caused by the increased charge movement activity under high temperature conditions.

[0009] Preferably, the read interference monitoring unit further includes an adjacent state sensor for identifying the logical state distribution of stored charges in adjacent storage cells; the threshold calibration control module determines the spatial coupling capacitance strength factor based on the logical state distribution and uses the spatial coupling capacitance strength factor to adjust the gain of the dynamic interference accumulation value.

[0010] Preferably, the reading circuit further includes an error rate statistics module, which is used to obtain the bit error rate during the data reading process after the target reference voltage is adjusted; if the bit error rate is higher than the preset safety limit, the error rate statistics module feeds back the adjustment step correction command to the threshold calibration control module so that the threshold calibration control module reduces the single adjustment span of the target voltage offset.

[0011] Preferably, when the threshold calibration control module receives the system shutdown signal, it synchronously stores the current dynamic interference accumulation value into a non-volatile register; in the first reading cycle after the system is powered on again, the threshold calibration control module extracts the interference record before shutdown from the non-volatile register, determines the charge loss based on the power outage duration, and completes the initial alignment of the dynamic interference accumulation value.

[0012] Preferably, the digital-to-analog conversion module consists of a voltage divider resistor chain and a switching matrix. The switching matrix switches the physical node of the voltage divider resistor chain connected to the sensing amplifier according to the decoding level of the reference adjustment signal, so as to change the absolute potential of the input level at the reference terminal.

[0013] Preferably, the threshold calibration control module is also connected to a cycle lifetime statistician to obtain the cumulative erase / write count data of the storage array; the threshold calibration control module performs linear slope correction on the mapping function of the target voltage offset based on the cumulative erase / write count data to offset the degradation of charge retention performance of the target storage cell caused by the aging of the tunnel oxide layer.

[0014] The embodiments of the present invention have at least the following beneficial effects: 1. In the control of non-volatile memory with dynamic threshold voltage adjustment, a dynamic adjustment mechanism that senses the charge relaxation effect of the storage medium is constructed by introducing a hardware-level timestamp parameter. Traditional technical solutions usually rely only on the linear accumulation of read counts to evaluate the degree of interference, ignoring the physical characteristics of spontaneous charge de-trapping of multi-level memory cells after intensive access. This invention extracts the physical rest interval between two adjacent accesses of the target word line and uses this interval to perform nonlinear attenuation calculation on the basic value of interference accumulation, so that the output voltage offset is kept synchronized with the real charge distribution state inside the memory cell in real time. This dynamic hedging method based on material physical properties eliminates the overcompensation phenomenon caused by blind accumulation counting.

[0015] 2. The system achieves multi-dimensional collaborative compensation for spatial topology interference, ambient temperature, and temporal relaxation effects. By coupling the read history of adjacent cells, the real-time sampling value of the temperature sensor, and the net interference residue calculated based on timestamps, the calibration engine can output a more accurate read comparator reference voltage. This deep integration of multiple mechanisms not only solves the problem of overlapping storage state distribution of multi-level cells, but also distinguishes between acute charge drift and long-term slow-release interference through accurate perception of physical rest intervals. When the system faces complex operating conditions of high-concurrency burst read / write and long-term idle alternation, this collaborative mechanism can dynamically narrow the fluctuation range of the threshold voltage and maintain the read window budget of the storage cell, thereby reducing the probability of uncorrectable errors without changing the underlying hardware structure.

[0016] 3. The system enhances the operational stability of the storage module under irregular access modes through the logical linkage of hardware-level registers and arithmetic units. The closed-loop feedback path formed between the read interference monitoring unit and the threshold voltage calibration engine ensures that the physical execution of each read instruction is based on an accurate assessment of the current charge escape state of the medium. When the system detects a long resting interval in the physical word line, the attenuation factor automatically corrects historical accumulated errors, avoiding decision failures triggered by excessively high reference voltage settings during the cold data wake-up phase. This dynamic leaky bucket model with physical material lifecycle awareness improves the adaptive adjustment capability of the storage control system under extreme conditions and effectively expands the reliable operating boundary of the storage array under deep submicron processes. Attached Figure Description

[0017] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings, in which several embodiments of the invention are illustrated by way of example and not limitation, wherein: Figure 1 This is a schematic diagram of the overall architecture of the dynamic threshold voltage adjustment non-volatile memory control system of the present invention; Figure 2 This is a diagram showing the internal core components and dynamic interference calculation logic of the threshold calibration control module and reading circuit of the present invention. Detailed Implementation

[0018] The principles and spirit of the present invention will now be described with reference to several exemplary embodiments in conjunction with the accompanying drawings. It should be understood that these embodiments are provided merely to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0019] A non-volatile memory control system with dynamic threshold voltage adjustment, the system comprising: The read interference monitoring unit is used to acquire the read operation history information of the target storage unit and its adjacent storage units, and to calculate the read interval duration data between two adjacent read operations based on the read operation history information. Temperature acquisition unit, used to acquire real-time temperature data of the current system environment; The threshold calibration control module is connected to the read interference monitoring unit and the temperature acquisition unit, respectively. It is used to determine the attenuation coefficient in the corresponding time domain based on the read interval duration data and the preset medium physical charge de-trapping characteristic curve. It also uses the attenuation coefficient to perform a reduction calculation on the initial interference accumulation value extracted from the non-volatile register at the previous moment to obtain the dynamic interference accumulation value at the current moment. The threshold calibration control module is also used to map and convert the real-time temperature data and the dynamic interference accumulation value to generate the target voltage offset corresponding to the target storage unit and output the corresponding reference adjustment signal to the read circuit. The readout circuit is connected to the threshold calibration control module. The readout circuit includes a sensing amplifier and a digital-to-analog converter module. The digital-to-analog converter module is used to adjust the input level of the reference terminal of the sensing amplifier according to the reference adjustment signal so that the input level of the reference terminal is locked at the target reference voltage that matches the target voltage offset.

[0020] Preferably, when determining the cumulative value of dynamic interference, the threshold calibration control module retrieves the target attenuation factor corresponding to the reading interval duration data by searching a preset attenuation mapping table; the threshold calibration control module determines the product of the initial cumulative value of interference and the target attenuation factor as the existing interference correction component, and sums the existing interference correction component with the transient interference increment generated by this reading operation to complete the numerical update of the cumulative value of dynamic interference.

[0021] Preferably, the read interference monitoring unit includes a timestamp memory, which records the current count value of the system clock to generate a current timestamp each time a read instruction for the target storage unit is received; the read interference monitoring unit calculates the difference between the current timestamp and the previous read timestamp in the historical record to generate read interval duration data.

[0022] Preferably, the threshold calibration control module determines the cumulative value of dynamic interference based on the exponential decay law of physical charge escape. The quantization calculation logic used by the threshold calibration control module is as follows: ,in, This represents the cumulative value of dynamic disturbance at the current moment. The initial cumulative interference value is given, Δt is the data reading interval, and λ is the preset medium attenuation constant. This represents the amount of interference per unit to the target storage unit caused by a single read operation.

[0023] Preferably, when generating the target voltage offset, the threshold calibration control module determines the voltage regulation gain for the corresponding temperature range based on real-time temperature data; if the real-time temperature data exceeds the preset temperature alarm threshold, the threshold calibration control module linearly increases the conversion ratio coefficient between the cumulative dynamic interference value and the target voltage offset to compensate for the shrinkage of the read margin caused by the increased charge movement activity under high temperature conditions.

[0024] Preferably, the read interference monitoring unit further includes an adjacent state sensor for identifying the logical state distribution of stored charges in adjacent storage cells; the threshold calibration control module determines the spatial coupling capacitance strength factor based on the logical state distribution and uses the spatial coupling capacitance strength factor to adjust the gain of the dynamic interference accumulation value.

[0025] Preferably, the reading circuit further includes an error rate statistics module, which is used to obtain the bit error rate during the data reading process after the target reference voltage is adjusted; if the bit error rate is higher than the preset safety limit, the error rate statistics module feeds back the adjustment step correction command to the threshold calibration control module so that the threshold calibration control module reduces the single adjustment span of the target voltage offset.

[0026] Preferably, when the threshold calibration control module receives the system shutdown signal, it synchronously stores the current dynamic interference accumulation value into a non-volatile register; in the first reading cycle after the system is powered on again, the threshold calibration control module extracts the interference record before shutdown from the non-volatile register, determines the charge loss based on the power outage duration, and completes the initial alignment of the dynamic interference accumulation value.

[0027] Preferably, the digital-to-analog conversion module consists of a voltage divider resistor chain and a switching matrix. The switching matrix switches the physical node of the voltage divider resistor chain connected to the sensing amplifier according to the decoding level of the reference adjustment signal, so as to change the absolute potential of the input level at the reference terminal.

[0028] Preferably, the threshold calibration control module is also connected to a cycle lifetime statistician to obtain the cumulative erase / write count data of the storage array; the threshold calibration control module performs linear slope correction on the mapping function of the target voltage offset based on the cumulative erase / write count data to offset the degradation of charge retention performance of the target storage cell caused by the aging of the tunnel oxide layer.

[0029] Example 1: When the system faces concurrent access conditions of cloud platform intensive computing architecture, the multi-level non-volatile memory module is subjected to an access mode that alternates between extremely high frequency burst reads and long period cold data idle. When physical blocks encounter dense burst reads in a short period of time, charge traps generate electron accumulation and cause threshold voltage drift. During the physical rest interval of several hours or days between two burst reads, the trapped electrons generate a spontaneous de-trapping effect due to the intrinsic thermal excitation of the material, causing the threshold voltage to drop nonlinearly. Traditional memory control systems use a fixed-period read interference monitoring mechanism and rely on a linear superposition model of absolute read counts. Due to the lack of recording of physical word line access timestamps and perception of time-domain rest duration, they cannot distinguish between acute interference and long-term slow-release interference. When processing read requests with long-tail intervals, they output an excessive reference voltage offset based on the historical total number of reads. This rigid overcompensation cuts off the remaining read window budget of the memory unit, inducing uncorrectable read errors.

[0030] When a read command is received for the target memory cell, the read interference monitoring unit uses the hardware-level physical block timestamp register to synchronously extract the initial cumulative interference value of the target physical word line and the system clock count value of the most recent applied read on-state voltage. It then drives the main control logic arithmetic unit to calculate the difference between the current system time and this count value, generating read interval duration data. The threshold calibration control module, based on the charge detrapping characteristic curve of the storage medium, calls a preset attenuation factor to perform a reduction calculation on the initial cumulative interference value. The specific calculation formula is as follows: ,in, This represents the cumulative value of dynamic disturbance at the current moment. The initial cumulative interference value is given, Δt is the data reading interval, and λ is the preset medium attenuation constant. This represents the unit interference amount caused to the target storage unit by a single read operation. This operation converts the read interval duration data into a negative exponential multiplier to cancel the trap removal effect, and combines it with the real-time temperature data obtained by the temperature acquisition unit to generate the voltage regulation gain corresponding to the temperature range. Then, it outputs the target voltage offset corresponding to the target storage unit, and outputs the corresponding reference adjustment signal to the read circuit to switch the physical node of the switching matrix in the digital-to-analog converter module connected to the sensing amplifier, so that the input level of the reference terminal is locked at the target reference voltage that matches the target voltage offset and the data read is completed. When the main control logic arithmetic unit performs the dynamic interference accumulation value update operation, the main control chip pre-builds a two-dimensional attenuation factor mapping table in the non-volatile firmware area. The construction process is to divide the time segment interval based on the system clock beat, calculate the discretized negative exponential constant corresponding to each time segment interval in combination with the preset medium physical charge trap removal characteristic curve, and quantize the discretized negative exponential constant into an eight-bit wide unsigned integer format and write it into the non-volatile firmware area.

[0031] Within the actual cycle of the system receiving the read command, the main control logic arithmetic unit extracts the read interval duration data as an index address to obtain the corresponding fixed-point attenuation multiplier from the image table. The hardware multiplier-adder multiplies the initial cumulative interference value from the previous moment with the fixed-point attenuation multiplier, triggering the shift register to shift to the right by a preset number of bits to complete the value reduction. The integer adder adds the reduced value to the unit interference amount, and directly outputs the current dynamic interference cumulative value by replacing the multi-cycle floating-point series expansion operation with table lookup and hardware shift physical link. The read interval duration data provides a time constraint input for the reduction operation, and the dynamic interference cumulative value output by the reduction operation enables the adjustment of the target reference voltage. The range of the section is controlled by the degree of physical relaxation decay. The two work together to solve the technical problem of the mutual constraint between rigid superposition compensation and material time-domain hysteresis characteristics under the alternating conditions of high-frequency burst read and write and long-term cold data idle. The system reconstructs the threshold voltage adjustment benchmark from the cumulative statistical index of access count to the physical material charge state tracking index based on rest interval decay. The arithmetic logic flow of hardware-level registers and arithmetic units eliminates the physical loss of the sensing circuit caused by excessive reference voltage bias, so that the reference voltage applied to the comparator is adapted to the charge trapping state inside the floating gate layer in real time, forming a dynamic leaky bucket control architecture based on the physical material charge retention characteristics.

[0032] Example 2: The current configuration uses a non-volatile memory wafer-level verification platform to test the dynamic threshold voltage adjustment mechanism under complex thermal fields and non-uniform read interference conditions. This platform includes a signal source supporting timing programming and a physical block-level voltage probe. Its heat flow generator outputs random temperature fluctuations with an amplitude of 2.5°C on the surface of the test chip and cyclically applies thermal stress between 30°C and 80°C. Gaussian white noise with a signal-to-noise ratio of 15dB is mixed into the test signal source to reproduce crosstalk disturbances in the motherboard wiring. When establishing the dielectric decay constant, the thickness of the floating gate layer oxide film of the target physical block is analyzed. Combined with the statistical distribution of offline charge retention force tests, the engineering value range for the arithmetic logic unit to output a reduced amplitude calculation result within 10μs with an error rate of less than 3% is established as 0.045 to 0.055. A physical block with an aging degree of 10,000 erase / write cycles is selected. 100,000 burst read operations were continuously applied to accumulate initial charge traps. The initial interference accumulation value at this time was extracted, and the original bit error rate carrying background noise was measured to be 0.012 at 25°C. The high-stress initial physical state benchmark was established. The value range of this project was determined based on the normalization of the system clock. Specifically, the read interval duration data was normalized to milliseconds. Based on the charge release slope of this batch of wafers under accelerated aging conditions at 85°C, the theoretical reduction coefficient of the natural exponent under a single clock cycle was derived. Since a value of λ below 0.045 would result in a high amount of compensation and failure to eliminate long-tail resting error, while a value above 0.055 would cause excessive erasure of interference accumulation in the short term, inducing read errors, this range was locked to ensure that the time-domain reduction model matches the actual charge release rate of the physical medium.

[0033] The experiment was divided into three groups: a control group 1 using a linear superposition model of absolute read counts; a control group 2 lacking temperature-voltage mapping conversion; a control group 3 with the dielectric attenuation constant set to an out-of-range boundary value of 0.150; and an experimental group with a fully implemented dynamic threshold voltage adjustment mechanism. Each group initiated a second read operation after a 72-hour physical rest period, and the timestamp memory output the read interval duration data to the main control logic arithmetic unit. The voltage probe captured a fixed reference voltage offset of 125mV from the output of control group 1. The experimental group followed the formula... Calculate the cumulative value of dynamic interference, where, This represents the cumulative value of dynamic disturbance at the current moment. The initial cumulative interference value is given, Δt is the data reading interval, and λ is the preset medium attenuation constant. This represents the unit interference caused to the target memory cell by a single read operation. The cumulative dynamic interference output of the test group decreased to 42.5% of the original value. Combined with the real-time temperature data of 75℃ output by the temperature acquisition unit, a mapping transformation was performed, and the output target voltage offset was 56mV. During this test cycle, a nonlinear material response inflection point was observed. When the physical resting interval exceeded the 48-hour threshold, the decay rate of the cumulative dynamic interference slowed down and entered the flat region, indicating that the high-energy trap charge inside the floating gate layer had dissipated and the remaining low-energy charge remained stable. In the control group three, due to the excessive setting of the dielectric decay constant, the cumulative dynamic interference value fell into the zero range within 12 hours. The calculated compensation amount could not offset the residual read interference, causing distortion of the reference adjustment signal.

[0034] The sensing amplifier switches the switching matrix nodes of the digital-to-analog converter module according to the reference adjustment signal, and outputs the final read physical parameters. The overcompensation action of control group 1 cuts off the read window budget, and the measured bit error rate rises to 0.038. Control group 2 lacks voltage adjustment gain under high temperature heat flow disturbance, and the measured bit error rate is 0.021. Control group 3 has a measured bit error rate of 0.025 due to compensation failure caused by the mismatch of dielectric attenuation parameters. The experimental group filters out 15dB background random voltage drift by co-mapping dynamic interference accumulation value and real-time temperature data, and locks the reference input level of the sensing amplifier at the target reference voltage, and the measured bit error rate is 0.004. The hardware-level read interval duration data is used as a time constraint input, and the adjustment range of the target reference voltage is limited by the charge decay characteristic curve. The system switches the threshold voltage adjustment reference to the physical material charge state tracking index, so that the reference voltage applied to the comparator is adapted to the charge trapping state inside the floating gate layer in real time, and solves the read error problem under the alternating conditions of high-frequency burst read and write and long-term cold data idle.

[0035] Example 3: When the system faces the condition that the solid-state drive storage module has been in service for a long time and the wear of each physical block is uneven, the number of erase and write cycles of the target storage unit continues to increase, resulting in physical damage to the oxide film of the floating gate layer; the damage at the material level causes a nonlinear shift in the escape rate of trapped electrons, making the static dielectric decay constant set for healthy physical blocks unable to adapt to the charge loss dynamics of aged physical blocks; if the system maintains the factory-set decay constant, the cumulative value of dynamic interference output by the threshold calibration control module lags behind the physical degradation process, causing inaccurate reference voltage compensation and data reading failure.

[0036] The threshold calibration control module triggers the attenuation parameter calibration logic based on the number of erase / write cycles of the physical block. When the number of erase / write cycles of the target physical block reaches a preset wear node, the main control logic arithmetic unit sends a programming instruction to the reserved reference word line in the target physical block to write test data, and uses a voltage probe to record the initial threshold voltage at the moment the reference word line is written. The timestamp memory starts a resting timer, and after the timer value reaches the 24-hour calibration interval, the reading circuit senses the reference word line again to obtain the resting threshold voltage. The main control logic arithmetic unit calculates the difference between the initial threshold voltage and the resting threshold voltage to determine the absolute charge loss, and divides the absolute charge loss by... The calibration interval is used to calculate the leakage current drift slope, which characterizes the material properties of the current physical block. The main control logic arithmetic unit applies a multiplier mapping to the initially set attenuation parameters based on the division quotient of the leakage current drift slope and the factory reference slope, generating a dielectric attenuation constant suitable for the current wear state. During the calibration interval of up to 24 hours, the reference word line is in a logically isolated state. The system main control will reset the normal high-frequency read and write business flow to the working word line in the same physical block that is not in the calibration state, or schedule it across blocks through the wear leveling mechanism to ensure that the long physical rest measurement only runs independently in the background, thereby completing the seamless extraction of the drift slope without blocking the concurrent data throughput of the foreground.

[0037] The threshold calibration control module will use the medium attenuation constant Substitute into the formula In the process, the cumulative dynamic interference value of the target storage unit is updated, where, This represents the cumulative value of dynamic disturbance at the current moment. The initial cumulative interference value is given, Δt is the data reading interval, and λ is the medium attenuation constant. This represents the unit interference amount caused to the target storage cell by a single read operation; the updated output dynamic interference accumulation value is combined with the real-time temperature data obtained by the temperature acquisition unit and mapped to the target voltage offset, driving the digital-to-analog converter module to lock the input level of the sensing amplifier at the target reference voltage; the system converts the static attenuation constant into a dynamic parameter determined based on the measured physical drift slope of the reference word line, so that the adjustment logic of the reference voltage covers the physical decay law of the entire life cycle of the material, suppressing read errors in the later stages of the storage system's service life.

[0038] Example 4: When the system faces the baseline calibration condition before the solid-state drive storage module leaves the factory, the calibration equipment selects a test physical block of the same batch of wafers as the test carrier. The test carrier is placed in an ambient heat flow chamber, and multiple temperature nodes are set with a fixed test gradient of 5°C within the range of 0°C to 85°C. When each temperature node is reached, the test excitation circuit writes the preset highest level data to the target physical word line of the test carrier to inject saturated charge trap, cuts off the write voltage, and starts the system clock timing. During the rest period, the voltage probe continuously detects the actual threshold voltage of the test carrier with a sampling period of 2 hours. The main control logic arithmetic unit collects the actual threshold voltage and the corresponding rest duration data of each sampling period, and uses the least squares method to fit the aforementioned data set to calculate the fitting exponential decay slope corresponding to each temperature node. The main control logic arithmetic unit determines the slope as the reference value of the dielectric decay constant under specific temperature conditions and quantifies and extracts the underlying physical leakage current characteristics of the batch of storage media.

[0039] The calibration equipment uses the extracted reference values ​​of all dielectric attenuation constants as the basic physical characteristic benchmark. Based on the orthogonal combination dimension of temperature nodes and resting time intervals, it writes and solidifies a two-dimensional grid-shaped attenuation mapping table in the non-volatile firmware area of ​​the main control chip. After the solid-state drive storage module is put into actual field service, the threshold calibration control module uses the real-time temperature data obtained by the temperature acquisition unit and the read interval duration data calculated by the timestamp memory as a joint index to address the attenuation mapping table, extracts the corresponding target attenuation factor, and substitutes it into the calculation logic of the dynamic interference accumulation value. The material intrinsic characteristics obtained offline... The parameters are transformed into a reference for on-site operation, so that the target reference voltage output by the threshold calibration control module is controlled by the charge retention test reference of a specific batch of materials. This establishes an initial data baseline for the non-volatile storage control system to cope with the challenges of cross-batch material differences and cross-temperature range fluctuations. When the real-time temperature data exceeds the preset temperature alarm threshold, the internal temperature slope compensator of the threshold calibration control module establishes the conversion ratio coefficient according to the quantitative calibration procedure. During the factory verification stage, the test physical block is placed in a high and low temperature test chamber, and the temperature is gradually increased to the maximum working environment limit in five-degree Celsius temperature steps, starting from the temperature alarm threshold.

[0040] At each temperature verification node, the actual threshold voltage offset of the target storage unit after a uniform rest period is extracted. The voltage drift difference between two adjacent temperature nodes is calculated, and the arithmetic mean of the drift differences of all test nodes is established as the reference temperature compensation factor and fixed in the internal read-only register. Under field service operation, in response to the condition that the real-time temperature data is greater than the temperature alarm threshold, the subtractor in the arithmetic logic unit calculates the difference between the real-time temperature data and the temperature alarm threshold. The hardware multiplier multiplies the difference with the reference temperature compensation factor and outputs the linear compensation component. The adder superimposes the linear compensation component onto the basic conversion ratio coefficient to generate the updated conversion ratio coefficient. According to the updated conversion ratio coefficient, the dynamic interference accumulation value is mapped to the target voltage offset and the corresponding drive voltage is output. In the specific execution path of this mapping conversion, the main control logic integrates a two-dimensional hardware lookup table. The row address lines of the lookup table are connected to the digitized real-time temperature data bus, and the column address lines are connected to the quantized dynamic interference accumulation value data bus. The reference voltage gain word pre-programmed at the corresponding cross node is output through cross addressing, thereby completing the hardware-level mapping conversion from two variables to a single target voltage offset.

[0041] Example 5: When the system faces high-density read / write mixed conditions of a multi-level memory cell array, adjacent threshold voltage state distribution intervals are squeezed together. When multi-state memory particles are subjected to read interference, the parasitic coupling electric field strength experienced by memory cells in the high-voltage state is greater than that of memory cells in the low-voltage state. If the system applies a static unit interference constant to all target memory cells, the dynamic interference accumulation value output by the main control logic arithmetic unit deviates from the physical energy level transition law. The target voltage offset generated by subsequent conversion cannot adapt to the charge trapping change degree of the current programming state. In order to reconstruct the physical mapping path of the unit interference, the threshold calibration control module starts the extraction mechanism based on programming state recognition, reads the current logical page encoding data of the target memory cell obtained by the interference monitoring unit, and finds the interference weight coefficient corresponding to the logical page encoding data according to the state weight mapping matrix solidified in the non-volatile firmware area. The main control logic arithmetic unit multiplies the basic interference base with the interference weight coefficient to generate the unit interference for the current programming state. and substitute it into the formula In, among them, This represents the cumulative value of dynamic disturbance at the current moment. Here, Δt is the initial cumulative interference value, λ is the read interval duration, and λ is the dielectric attenuation constant. This extraction mechanism converts a single interference base into a dynamic weight sequence that covers all physical programming energy levels, eliminating the risk of physical parameter mismatch caused by single constant compensation. Extending from this mechanism, the adjacent state sensor configured inside the read interference monitoring unit does not need to apply a complete time-consuming read voltage sequence to adjacent word lines. Instead, it directly listens to the accompanying address latch signal left by the main memory controller on the internal data bus when it refreshes in the background or writes back to the cache. This allows for the analysis of the rough distribution of charge logic states in adjacent memory cells, thereby obtaining the spatial coupling capacitance strength factor without increasing the foreground access latency.

[0042] After the threshold calibration control module generates the target voltage offset by mapping the updated dynamic disturbance accumulation value with real-time temperature data, the driver node of the digital-to-analog converter (DAC) faces the engineering anomaly risk of adjacent voltage state reversal caused by the physical input range exceeding the limit. To establish hardware constraints for the DAC link, the threshold calibration control module incorporates a hardware-level boundary limiting comparator. This boundary limiting comparator acquires the maximum physical sensing margin corresponding to the parasitic capacitance of the flash array bit lines and calculates the hardware limit offset threshold. The boundary limiting comparator receives the target voltage offset output by the main control logic arithmetic unit and determines the numerical relationship between the target voltage offset and the hardware limit offset threshold. In response to the condition that the target voltage offset is greater than the hardware limit offset threshold, the threshold calibration control module intercepts the original adjustment command and outputs a value carrying the hardware limit offset threshold to the read circuit. The overloaded reference adjustment signal is used to lock the input level of the reference terminal of the sensing amplifier. This boundary limiting mechanism forces the theoretically calculated voltage compensation amount to converge within the physical hardware limit, preventing abnormal state switching of memory cells caused by excessive voltage compensation. This establishes the underlying hardware operating baseline of the non-volatile memory control system under interference accumulation conditions. During the process of the comparator obtaining the sensing margin, the main control logic applies a step test voltage to the redundant word line and uses the sensing amplifier to capture the bit line charging and discharging setup time during the system power-on initialization phase. The extracted analog delay level signal is quantized into a digital width margin reference value through the analog-to-digital conversion channel and pre-written into the limiting register on the comparator side. This overcomes the hardware isolation between physical analog quantities and digital arithmetic processing, providing the comparator with a physical basis for implementing digital-level limiting.

[0043] The above description is only a few preferred embodiments of the present invention and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present invention is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the above-mentioned inventive concept. For example, technical solutions formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in the embodiments of the present invention.

Claims

1. A non-volatile storage control system for dynamic threshold voltage adjustment, characterized in that, system include: The read interference monitoring unit is used to acquire the read operation history information of the target storage unit and its adjacent storage units, and to calculate the read interval duration data between two adjacent read operations based on the read operation history information. Temperature acquisition unit, used to acquire real-time temperature data of the current system environment; The threshold calibration control module is connected to the read interference monitoring unit and the temperature acquisition unit, respectively. It is used to determine the attenuation coefficient in the corresponding time domain based on the read interval duration data and the preset medium physical charge de-trapping characteristic curve. It also uses the attenuation coefficient to perform a reduction calculation on the initial interference accumulation value extracted from the non-volatile register at the previous moment to obtain the dynamic interference accumulation value at the current moment. The threshold calibration control module is also used to map and convert the real-time temperature data and the dynamic interference accumulation value to generate the target voltage offset corresponding to the target storage unit and output the corresponding reference adjustment signal to the read circuit. The readout circuit is connected to the threshold calibration control module. The readout circuit includes a sensing amplifier and a digital-to-analog converter module. The digital-to-analog converter module is used to adjust the input level of the reference terminal of the sensing amplifier according to the reference adjustment signal so that the input level of the reference terminal is locked at the target reference voltage that matches the target voltage offset.

2. The non-volatile storage control system for dynamic threshold voltage adjustment according to claim 1, characterized in that, When determining the cumulative value of dynamic interference, the threshold calibration control module retrieves the target attenuation factor corresponding to the reading interval duration data by searching the preset attenuation mapping table. The threshold calibration control module determines the product of the initial cumulative value of interference and the target attenuation factor as the existing interference correction component, and sums the existing interference correction component with the transient interference increment generated by this reading operation to complete the numerical update of the cumulative value of dynamic interference.

3. The non-volatile storage control system for dynamic threshold voltage adjustment according to claim 2, characterized in that, The read interference monitoring unit includes a timestamp memory, which is used to record the current count value of the system clock to generate the current timestamp each time a read command for the target memory unit is received. The interference monitoring unit calculates the difference between the current timestamp and the last read timestamp in the historical record, thereby generating read interval duration data.

4. The non-volatile storage control system for dynamic threshold voltage adjustment according to claim 1, characterized in that, When generating the target voltage offset, the threshold calibration control module determines the voltage regulation gain for the corresponding temperature range based on real-time temperature data. If the real-time temperature data exceeds the preset temperature alarm threshold, the threshold calibration control module linearly increases the conversion ratio between the cumulative dynamic interference value and the target voltage offset to compensate for the shrinkage of the read margin caused by the increased charge movement activity under high temperature conditions.

5. The non-volatile storage control system for dynamic threshold voltage adjustment according to claim 1, characterized in that, The read interference monitoring unit also includes an adjacent state sensor to identify the logical state distribution of stored charges in adjacent memory cells; the threshold calibration control module determines the spatial coupling capacitance strength factor based on the logical state distribution and uses the spatial coupling capacitance strength factor to adjust the gain of the dynamic interference accumulation value.

6. The non-volatile storage control system for dynamic threshold voltage adjustment according to claim 1, characterized in that, The reading circuit also includes an error rate statistics module, which is used to obtain the bit error rate during the data reading process after the target reference voltage is adjusted. If the bit error rate is higher than the preset safety limit, the error rate statistics module feeds back the adjustment step correction command to the threshold calibration control module so that the threshold calibration control module reduces the single adjustment span of the target voltage offset.

7. The non-volatile storage control system for dynamic threshold voltage adjustment according to claim 1, characterized in that, When the threshold calibration control module receives a system shutdown signal, it synchronously stores the current dynamic disturbance accumulation value into a non-volatile register. During the first read cycle after the system is powered on again, the threshold calibration control module extracts the interference record before the shutdown from the non-volatile register and determines the amount of charge loss based on the power outage duration, thus completing the initial alignment of the dynamic interference accumulation value.

8. The non-volatile storage control system for dynamic threshold voltage adjustment according to claim 1, characterized in that, The digital-to-analog converter module consists of a voltage divider resistor chain and a switching matrix. The switching matrix switches the physical nodes of the voltage divider resistor chain connected to the sensing amplifier according to the decoding level of the reference adjustment signal, thereby changing the absolute potential of the reference input level.

9. A non-volatile storage control system for dynamic threshold voltage adjustment according to claim 1, characterized in that, The threshold calibration control module is also connected to a cycle lifetime statistician to obtain the cumulative erase / write count data of the storage array. The threshold calibration control module performs a linear slope correction on the mapping function of the target voltage offset based on the cumulative erase / write count data to offset the degradation of charge retention performance of the target storage cell caused by the aging of the tunnel oxide layer.

Images