A memory circuit and a memory

Abstract

The application discloses a storage circuit and a memory, relates to the technical field of storage, and comprises a latch circuit added between a storage node and a driving circuit. The latch circuit utilizes the non-volatile characteristic of the latch circuit, acquires and latches data in the storage node in real time when a main power supply normally supplies power, can keep the latched data after the main power supply is powered off, and actively outputs the data to the driving circuit after re-powering, so that the driving circuit writes the data back to a storage capacitor according to the original refresh process. The technical problems of data loss of DRAM power failure and speed reduction caused by replacing the DRAM with non-volatile media are solved, the technical effects of non-volatile storage of power failure data and automatic recovery after power-on are achieved, and the application can be used in high-speed application scenarios such as servers and high-performance calculations.

Description

Technical Field

[0001] This application relates to the field of storage technology, and more particularly to a storage circuit and a memory. Background Technology

[0002] Currently, DDR (Double Data Rate) 5 memory uses the traditional 1T1C (One Transistor One Capacitor) DRAM (Dynamic Random-Access Memory) structure, meaning one access transistor and one storage capacitor. Data is represented by the charge of the storage capacitor. Therefore, DDR5 memory must be continuously refreshed to prevent data loss due to leakage of the access transistor. However, if the entire system loses power, the refresh stops because the external power supply ceases. The charge in the storage capacitor will dissipate within milliseconds, resulting in complete and unrecoverable data loss. To solve this problem, related technologies use non-volatile storage media to directly replace DRAM. However, the read and write speeds of these non-volatile storage media are far lower than the requirements of DDR5 memory, and are not on the same order of magnitude as the access latency required for high-speed applications. Therefore, they cannot be used in high-speed scenarios such as servers and high-performance computing. Summary of the Invention

[0003] This application provides a storage circuit and a memory to at least solve the problems of data loss due to power failure of DRAM and the decrease in access speed caused by directly replacing DRAM with non-volatile media in the related art.

[0004] This application provides a storage circuit, including: a storage node, including a storage capacitor, wherein the charge state of the storage capacitor represents the data stored in the storage node; a driving circuit, connected to the storage node and configured to perform access operations on the storage node; and a latching circuit, connected to both the storage node and the driving circuit, wherein the latching circuit is configured to acquire and latch the data stored in the storage node when the main power supply is in a normal power-on state, retain the latched data using its non-volatile characteristics when the main power supply is in a power-off state, and output the latched data to the driving circuit when the main power supply is powered on again, so that the driving circuit can recover the data of the storage node based on the data output by the latching circuit.

[0005] This application also provides a memory including a plurality of the memory circuits described above.

[0006] This application addresses the issue of adding a latch circuit between the storage node and the driver circuit. This latch circuit, utilizing its non-volatile characteristics, acquires and latches data in the storage node in real time when the main power supply is normal. After a power outage, it retains the latched data and actively outputs it to the driver circuit upon power restoration. The driver circuit then writes the data back to the storage capacitor according to the original refresh process. Thus, this application retains the original DRAM structure based on storage capacitors for high-speed read / write access, while simultaneously using a latch circuit with non-volatile characteristics to temporarily store data during power outages and restore it to the storage node upon power restoration. This eliminates the need for continuous refresh to maintain power-loss data, solving the technical problems of DRAM data loss during power outages and the reduced access speed caused by directly replacing DRAM with non-volatile media. It achieves the technical effect of non-volatile data retention during power outages and automatic recovery upon power restoration, enabling its use in high-speed applications such as servers and high-performance computing. Attached Figure Description

[0007] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of the structure of the first type of storage circuit provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of a second type of storage circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of a non-volatile latch circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a third type of storage circuit provided in an embodiment of this application. Detailed Implementation

[0009] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0010] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0011] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0012] Please refer to Figure 1 The storage circuit provided in this application includes: Storage node SN includes storage capacitors, and the charge state of the storage capacitors represents the data stored in storage node SN; Drive circuit 1 is connected to storage node SN and configured to perform access operations on storage node SN; The latch circuit 2 is connected to the storage node SN and the drive circuit 1 respectively. The latch circuit 2 is configured to acquire and latch the data stored in the storage node SN when the main power supply is in normal power supply state, retain the latched data by utilizing its non-volatile characteristics when the main power supply is in power failure state, and output the latched data to the drive circuit 1 when the main power supply is powered on again, so that the drive circuit 1 can recover the data of the storage node SN according to the data output by the latch circuit 2.

[0013] In this embodiment, the storage circuit includes at least three parts: a storage node SN, a driving circuit 1, and a latching circuit 2. The storage node SN contains a storage capacitor. Charge accumulates between the two electrodes of the storage capacitor, and the level of this charge determines whether the data stored in the storage node SN is logic 1 or logic 0. Specifically, a large amount of charge stored in the storage capacitor and a voltage close to the power supply voltage represent logic 1, while a small amount of charge and a voltage close to ground potential represent logic 0.

[0014] The driving circuit 1 is connected to the memory node SN. The driving circuit 1 is used to perform access operations on the memory node SN, including reading data from the storage capacitor and writing new data to the storage capacitor. During normal operation of the DRAM, the driving circuit 1 controls the voltage changes of the word line and bit line according to the read / write commands issued by the external controller, thereby completing the read / write operations on the memory node SN.

[0015] The latch circuit 2 is connected to both the storage node SN and the drive circuit 1. The latch circuit 2 uses a non-volatile storage medium, such as ferroelectric material. When the main power supply is in normal operation, the latch circuit 2 retrieves the currently stored data from the storage node SN in real time and latches this data internally. When the main power supply goes into a power-down state, the voltage gradually drops to zero. At this time, the storage capacitor in the storage node SN gradually loses data due to leakage, but the latch circuit 2, relying on the non-volatile characteristics of its internal storage medium, retains the data latched before the power failure. When the main power supply is restored from the power-down state, the latch circuit 2 actively outputs the previously held data to the drive circuit 1. After receiving this data, the drive circuit 1 rewrites it into the storage capacitor of the storage node SN, thus completing the data recovery process of the storage circuit. This embodiment solves the problem of DRAM data loss during power failure and avoids the access speed reduction problem caused by directly replacing the entire storage array with a slower non-volatile storage medium.

[0016] In one exemplary embodiment, reference is made to Figure 2 As shown, latch circuit 2 includes: The non-volatile latch sub-circuit 21 is configured to latch data through the polarization state of the internal storage medium, and the polarization state remains unchanged when the main power supply is in a power-off state. The input control sub-circuit 22 is configured to receive the internal clock signal and transmit the data stored in the storage node SN to the non-volatile latch sub-circuit 21 when the rising edge of the internal clock signal arrives, so as to set the polarization state. The output control sub-circuit 23 is configured to receive an enable signal that characterizes the state of the main power supply, and control the connection or disconnection between the non-volatile latch sub-circuit 21 and the drive circuit 1 according to the enable signal. The status is either normal power supply, power failure, or power-on.

[0017] In this embodiment, the latch circuit 2 is further divided into a non-volatile latch sub-circuit 21, an input control sub-circuit 22, and an output control sub-circuit 23. The non-volatile latch sub-circuit 21 latches data based on the polarization state of its internal storage medium. Taking ferroelectric materials as an example, the polarization state refers to the orientation of the domains in the ferroelectric material. This orientation can change when an external electric field is applied and can be maintained for a long time after the external electric field is removed. Therefore, when the main power supply is off, the polarization state inside the non-volatile latch sub-circuit 21 will not change due to the power loss, thus ensuring the persistence of the latched data.

[0018] The input control subcircuit 22 receives an internal clock signal, which is obtained by buffering an externally input clock. The input control subcircuit 22 is configured to transfer the currently stored data in the storage node SN to the non-volatile latch subcircuit 21 at the rising edge of the internal clock signal, thereby setting the internal polarization state of the non-volatile latch subcircuit 21. This edge-triggered sampling method ensures the timing accuracy of data writing and avoids erroneous latching due to signal contention.

[0019] The output control subcircuit 23 receives an enable signal, which indicates the state of the main power supply, including normal power supply, power-down, and power-on states. Based on the level of the enable signal, the output control subcircuit 23 controls the connection or disconnection between the non-volatile latch subcircuit 21 and the drive circuit 1. When the enable signal indicates that the latch circuit 2 should be in a non-output state, the output control subcircuit 23 sets the output terminal of the latch circuit 2 to a high-impedance state. At this time, the latch circuit 2 does not transmit any signal to the drive circuit 1. When the enable signal indicates that the latch circuit 2 should output data, the output control subcircuit 23 is turned on, connecting the non-volatile latch subcircuit 21 and the drive circuit 1. At this time, the data stored inside the non-volatile latch subcircuit 21 is transmitted to the drive circuit 1 via the output terminal. In this embodiment, the latch circuit 2 can automatically switch its operating mode at different power supply stages, ensuring real-time tracking of the storage node SN data during normal power supply, ensuring non-volatile data retention after power failure, and ensuring reliable data output after power-on.

[0020] In one exemplary embodiment, please refer to Figure 3 The non-volatile latch circuit 21 includes a first ferroelectric field-effect transistor FeFET1 and a second ferroelectric field-effect transistor FeFET2, which are cross-coupled.

[0021] In this embodiment, the non-volatile latch circuit 21 includes a first ferroelectric field-effect transistor (FeFET1) and a second ferroelectric field-effect transistor (FeFET2). A ferroelectric field-effect transistor is a metal-oxide-semiconductor field-effect transistor in which ferroelectric material is introduced into the gate insulating layer. When a sufficiently strong positive voltage pulse is applied between the gate and source, the domains within the ferroelectric layer flip and remain in a polarized state; even if the voltage pulse is removed, the polarization state persists. This polarization state changes the threshold voltage of the ferroelectric field-effect transistor, resulting in a permanent change in the magnitude of the ferroelectric field-effect transistor's on-state current. Therefore, the ferroelectric field-effect transistor can store data in the form of a polarized state, and this storage behavior is non-volatile.

[0022] The first ferroelectric field-effect transistor (FeFET1) and the second ferroelectric field-effect transistor (FeFET2) are connected by cross-coupling. Specifically, cross-coupling means that the drain of each transistor is connected to the gate of the other, forming a mutually locked structure. This structure ensures that the two ferroelectric field-effect transistors are always in complementary states; when one is in the on state, the other is in the off state, and this state combination is maintained unless there is an external write operation.

[0023] When data is written to the non-volatile latch circuit 21, the two ferroelectric field-effect transistors are set to opposite polarization states depending on the data being written. Even if the main power supply fails, the ferroelectric layer polarization states of the two ferroelectric field-effect transistors remain unchanged, and therefore their respective conduction characteristics also remain unchanged. After power is restored, the positive feedback of the cross-coupling quickly restores the internal node voltage to the logic level before the power failure, thereby outputting the correct data.

[0024] In an exemplary embodiment, the drain of the first ferroelectric field-effect transistor FeFET1 is connected to the gate of the second ferroelectric field-effect transistor FeFET2, and the drain of the second ferroelectric field-effect transistor FeFET2 is connected to the gate of the first ferroelectric field-effect transistor FeFET1.

[0025] In this embodiment, the cross-coupling method between the first ferroelectric field-effect transistor FeFET1 and the second ferroelectric field-effect transistor FeFET2 is as follows: the drain of the first ferroelectric field-effect transistor FeFET1 is connected to the gate of the second ferroelectric field-effect transistor FeFET2, and at the same time, the drain of the second ferroelectric field-effect transistor FeFET2 is connected to the gate of the first ferroelectric field-effect transistor FeFET1.

[0026] The working principle of the two ferroelectric field-effect transistors (FETs) is explained as follows: Assume that at a certain moment, the drain of the first FET, FeFET1, is at a high level. This high level is directly applied to the gate of the second FET, FeFET2, causing FeFET2 to tend to conduct, thereby pulling its drain down to a low level. The low-level drain of FeFET2 then feeds back to the gate of the first FET, FeFET1, causing FeFET1 to tend to turn off, thus maintaining its drain at a high level. This keeps the non-volatile latch circuit 21 locked in a stable state. If the drain of the first FET, FeFET1, is at a low level, the gate of the second FET, FeFET2, is at a low level, turning it off. The drain of FeFET2 is then pulled up to a high level by an external pull-up element. This high level then increases the gate voltage of the first FET, FeFET1, causing it to conduct, further pulling its drain down.

[0027] When the main power supply fails, although the power supply voltage gradually drops to zero, the polarization state of the two ferroelectric field-effect transistors does not change. After the main power supply is restored, the two ferroelectric field-effect transistors can quickly establish the correct logic state, which enhances the anti-interference capability of latch circuit 2.

[0028] In one exemplary embodiment, the non-volatile latch circuit 21 further includes: The first pull-up resistor R1 has its first end connected to the main power supply and its second end connected to the drain of the first ferroelectric field-effect transistor FeFET1. The source of the first ferroelectric field-effect transistor FeFET1 is grounded. The second pull-up resistor R2 has its first end connected to the main power supply and its second end connected to the drain of the second ferroelectric field-effect transistor FeFET2. The source of the second ferroelectric field-effect transistor FeFET2 is grounded.

[0029] In this embodiment, the non-volatile latch circuit 21 is further provided with a first pull-up resistor R1 and a second pull-up resistor R2. The function of the pull-up resistor is to pull up the drain voltage of the ferroelectric field-effect transistor (FeFET) to the power supply voltage when the ferroelectric field-effect transistor is turned off, thereby generating a high-level output. Specifically, assuming the first ferroelectric field-effect transistor FeFET1 is turned on, its drain is pulled low to near ground potential. This low level causes the second ferroelectric field-effect transistor FeFET2 to turn off through cross-coupling. The drain of the second ferroelectric field-effect transistor FeFET2 is then pulled up to the main power supply voltage through the second pull-up resistor R2, outputting a high level. Conversely, if the second ferroelectric field-effect transistor FeFET2 is turned on, its drain is at a low level, the first ferroelectric field-effect transistor FeFET1 is turned off, and the first pull-up resistor R1 pulls its drain up to a high level.

[0030] It is understandable that the choice of pull-up resistor value needs to consider the balance between power consumption and speed. A smaller resistance value results in a stronger pull-up capability and faster signal switching speed, but also higher static power consumption. A larger resistance value results in lower power consumption, but slower switching speed. During power-down, the non-volatile latch circuit 21 experiences no voltage difference across the pull-up resistor due to the main power supply voltage dropping to zero, thus consuming no energy. After the main power supply is restored, the pull-up resistor quickly resumes its pull-up function, working in conjunction with the polarization state of the ferroelectric field-effect transistor to ensure that the non-volatile latch circuit 21 outputs the correct logic level.

[0031] In one exemplary embodiment, the storage circuit further includes a holding capacitor, the gate of a first ferroelectric field-effect transistor FeFET1 is connected to the voltage holding terminal corresponding to the holding capacitor, and the gate of a second ferroelectric field-effect transistor FeFET2 is connected to the voltage holding terminal corresponding to the holding capacitor.

[0032] In this embodiment, the storage circuit also includes a holding capacitor. The gate of the first ferroelectric field-effect transistor FeFET1 is connected to the voltage holding terminal corresponding to the holding capacitor, and the gate of the second ferroelectric field-effect transistor FeFET2 is also connected to the voltage holding terminal. That is, the gates of the two ferroelectric field-effect transistors are connected to a node where a stable voltage is provided by the holding capacitor.

[0033] The purpose of the holding capacitor is to maintain the stability of the gate voltages of the two ferroelectric field-effect transistors (FETs) during mains power failure. Since it takes time for the mains power to drop from its normal voltage to zero volts, voltage fluctuations or slow slopes may occur on the power lines during this period. If the gates of the FETs are directly connected to the mains power or other unstable nodes, voltage fluctuations during power failure may generate spurious gate-source voltage pulses, altering the polarization state of the ferroelectric layer and leading to data errors.

[0034] When the main power supply fails, the charge stored in the holding capacitor can maintain the gate voltage for a short period of time, preventing a voltage difference sufficient to reverse polarization between the gate and source. This improves the resistance of the non-volatile latch circuit 21 to power drop events, enhancing the reliability of data retention. It is particularly suitable for applications with unstable power quality or rapid transient fluctuations. In this embodiment, the voltage holding terminal corresponds to... Figure 3 The VDD_RET node in the middle.

[0035] In one exemplary embodiment, the input control sub-circuit 22 includes: The input control transistor NM1 has an internal clock signal connected to its gate, its source connected to the memory node SN, and its drain connected to the gate of the first ferroelectric field-effect transistor FeFET1. The output control sub-circuit 23 includes: The output control transistor NM2 receives an enable signal at its gate, and its source is connected to the drain of the second ferroelectric field-effect transistor FeFET2. The drain of the output control transistor NM2 is connected to the drive circuit 1.

[0036] In this embodiment, the input control sub-circuit 22 includes an input control transistor NM1. The gate of the input control transistor NM1 is connected to the clock terminal of the latch circuit 2 to receive the internal clock signal CLK, the source is connected to the data terminal D of the latch circuit 2 to receive the data in the storage node SN, and the drain is connected to the gate of the first ferroelectric field-effect transistor FeFET1. When the internal clock signal is high (i.e., the rising edge arrives), the input control transistor NM1 is turned on, and the data stored in the storage node SN is directly transferred to the gate of the first ferroelectric field-effect transistor FeFET1, thereby setting the polarization state of the first ferroelectric field-effect transistor FeFET1 according to the voltage.

[0037] The output control sub-circuit 23 includes an output control transistor NM2. The gate of the output control transistor NM2 is connected to the enable terminal CE of the latch circuit 2 to receive an enable signal. Its source is connected to the drain of the second ferroelectric field-effect transistor FeFET2, and the drain is connected to the output terminal Q of the latch circuit 2 to transmit data to the drive circuit 1. The enable signal is generated by detecting the status of the main power supply. When the enable signal is high, the output control transistor NM2 is turned on, and the drain voltage of the second ferroelectric field-effect transistor FeFET2 is transmitted to the drive circuit 1. When the enable signal is low, the output control transistor NM2 is turned off, and the output terminal of the latch circuit 2 exhibits a high-impedance state, which does not interfere with other operations of the drive circuit 1.

[0038] The input control transistor NM1 and the output control transistor NM2 can be N-type metal-oxide-semiconductor field-effect transistors. Using a single transistor as the control switch results in a small circuit area and low parasitic capacitance, which is beneficial for improving operating speed. At the same time, this separate control method makes the data write path and data output path independent of each other; the write operation is controlled only by the clock, and the output operation is controlled only by the enable signal, facilitating flexible adjustment of the control logic under different power supply conditions.

[0039] In one exemplary embodiment, the enable signal includes a first enable signal or a second enable signal; Reference Figure 4 The storage circuit also includes a power failure detection circuit 3, configured to output a first enable signal when the main power supply is in a normal power supply state, and output a second enable signal when the main power supply is in a power-on state. The first enable signal is used to control the output terminal of the latch circuit 2 to be in a high impedance state, and the second enable signal is used to control the output terminal of the latch circuit 2 to be in an output state.

[0040] In this embodiment, the enable signal includes a first enable signal and a second enable signal. The storage circuit also includes a power-down detection circuit 3, which monitors the state of the main power supply and outputs corresponding enable signals according to the different states of the main power supply.

[0041] When the main power supply is in normal operating condition, the power-down detection circuit 3 outputs a first enable signal. This first enable signal controls the output of the latch circuit 2 to be in a high-impedance state. Under normal power supply conditions, although the latch circuit 2 internally latches data, it does not need to output to the drive circuit 1 because the data at the storage node SN is valid, and the drive circuit 1 can directly access the storage node SN. Setting the output to high impedance avoids signal conflicts between the latch circuit 2 and the drive circuit 1. Under power-down conditions, the main power supply voltage has dropped to a level where normal operation is impossible, and maintaining high impedance at the output of the latch circuit 2 is safe. Therefore, a low level can be considered a form of the first enable signal.

[0042] When the main power supply recovers from a power-down state to a power-on state, the power-down detection circuit 3 outputs a second enable signal. This second enable signal controls the output of the latch circuit 2 to switch to the output state, meaning the internally latched data is transmitted to the drive circuit 1 via the output. Upon receiving this data, the drive circuit 1 can then perform a data recovery operation. A high level is one form of the second enable signal.

[0043] In one exemplary embodiment, the power-down detection circuit 3 is further configured to output a first enable signal after a preset time following the output of the second enable signal.

[0044] In this embodiment, the power-down detection circuit 3 is also equipped with a delay function. Specifically, after outputting the second enable signal and waiting for a preset time, the power-down detection circuit 3 will automatically switch the output back from the second enable signal to the first enable signal.

[0045] The preset time duration needs to be determined based on the time required for the drive circuit 1 to complete writing data to the storage node SN. At the initial moment of power-on, the power-down detection circuit 3 outputs a second enable signal, enabling the output of the latch circuit 2. The drive circuit 1 then reads the data and begins writing it to the storage node SN. After the preset time, the data recovery operation is complete. At this point, the power-down detection circuit 3 outputs a first enable signal, resetting the output of the latch circuit 2 to a high-impedance state to avoid mutual interference between the latch circuit 2 and the drive circuit 1 during subsequent normal read / write operations.

[0046] This embodiment ensures the integrity of the data recovery operation and avoids bus conflicts that may be caused by the output of latch circuit 2 being in an enabled state for a long time, thus improving the reliability of the storage circuit.

[0047] In an exemplary embodiment, the power-down detection circuit 3 includes a detection transistor and a delay sub-circuit. The delay sub-circuit is connected to the main power supply and the detection transistor, respectively. The detection transistor is connected to the main power supply and the latch circuit 2, respectively. The delay sub-circuit is configured to generate a second enable signal at the connection between the detection transistor and the latch circuit 2 when the main power supply is in a re-energized state, and generate a first enable signal at the connection after a preset time.

[0048] In this embodiment, the power-down detection circuit 3 includes a detection transistor and a delay sub-circuit. The delay sub-circuit is connected to the main power supply and the detection transistor, respectively, and the detection transistor is connected to the main power supply and the latch circuit 2, respectively. When the main power supply is restored from a power-down state, the delay sub-circuit controls the connection between the detection transistor and the latch circuit 2 to generate a second enable signal and maintain it for a preset time, and then causes the connection to generate a first enable signal. As an optional embodiment, the delay sub-circuit may specifically include a first transistor, a second transistor, a delay capacitor, and a comparator unit. The first transistor may be a PMOS, and the second transistor may be an NMOS.

[0049] In this configuration, the source of the first transistor is connected to the main power supply, the gate receives the voltage from the main power supply after voltage division or inversion, and the drain is connected to the control terminal of the detection transistor. The drain of the second transistor is connected to the drain of the first transistor, the source is grounded, and the gate receives the bias voltage or control signal. One end of the delay capacitor is connected to the connection node between the first transistor and the second transistor, and the other end is grounded. The input terminal of the comparator unit is connected to the main power supply, and the output terminal is connected to the gate of the detection transistor.

[0050] Under normal power supply conditions, the main power supply voltage is stable, the first transistor is in the off state, and the control terminal of the detection transistor is pulled low, or pulled low by the second transistor, causing the connection between the detection transistor and latch circuit 2 to output a low level. When a power outage occurs and power is restored, the main power supply begins to rise from 0V. At this time, since the voltage across the delay capacitor cannot change abruptly, the initial voltage of the delay capacitor is 0V, making the gate-source voltage difference of the first transistor negative, and the PMOS instantaneously turns on. At this time, the control terminal of the detection transistor receives a high level, causing the connection to output a high level to latch circuit 2. As the power-on process continues, the main power supply charges the delay capacitor through the first transistor and the series resistor. When the voltage on the delay capacitor rises to the flip threshold of the comparator unit, or when the first transistor is turned off, after a preset time (determined by the RC time constant), the first transistor turns off, the control terminal of the detection transistor is pulled low again, the connection recovers, and continuously outputs a low level.

[0051] In this embodiment, the delay sub-circuit utilizes the characteristic that the voltage across the delay capacitor cannot change abruptly during the power-on of the main power supply. The PMOS transistor automatically turns on during the initial power-on phase, providing a high-level signal to the detection transistor within a preset time. This generates a high-level power-on pulse at the enable pin of the latch circuit, causing the latch circuit to output the non-volatile latched data to the drive circuit for memory node recovery. After the power-on duration exceeds the preset time corresponding to the RC time constant formed by the PMOS on-resistance and the delay capacitor, the PMOS turns off, the control pin of the detection transistor is pulled low, and the enable pin returns to a low level. This structure requires no additional clock or timer, the delay width can be flexibly adjusted by the MOS transistor size and capacitor value, there is virtually no static power consumption during normal power supply and power-off, and it is fully compatible with CMOS technology. It can achieve automatic and reliable non-volatile data recovery upon power-on while ensuring high-speed access at DDR5 levels.

[0052] In an exemplary embodiment, the storage circuit further includes a clock buffer circuit 4, the input of which is connected to an external clock source, the first output of which is connected to a driving circuit 1, and the second output of which is connected to a latch circuit 2. The clock buffer circuit 4 is configured to divide the external clock signal output from the external clock source into two internal clock signals.

[0053] In this embodiment, the storage circuit also includes a clock buffer circuit 4. The input terminal of the clock buffer circuit 4 is connected to an external clock source. The external clock source is typically provided by a clock generator on the system motherboard, such as a differential clock signal from a DDR5 interface. The clock buffer circuit 4 has a first output terminal and a second output terminal. The first output terminal is connected to the driver circuit 1, and the second output terminal is connected to the latch circuit 2.

[0054] The function of clock buffer circuit 4 is to divide the single external clock signal input from the external clock source into two internal clock signals. The frequency and phase of these two internal clock signals are basically the same as the original external clock signal, but due to the buffer drive, their driving capability is stronger and they can be provided to different load circuits without affecting each other.

[0055] In an exemplary embodiment, the storage node SN further includes an access transistor, the drain of which is connected to the driving circuit 1 via a bit line, the gate of which is connected to the driving circuit 1 via a word line, the source of which is connected to the first terminal of the storage capacitor and the latch circuit 2, respectively, and the second terminal of the storage capacitor is grounded.

[0056] In this embodiment, the storage node SN includes a storage capacitor and an access transistor. The access transistor has three electrodes: a drain, a gate, and a source. The drain of the access transistor is connected to the driving circuit 1 via a bit line. The bit line is a shared vertical signal line in the storage array, used to transmit read and write data. The gate of the access transistor is connected to the driving circuit 1 via a word line. The word line is a shared horizontal control line in the storage array, used to select a specific storage cell.

[0057] The source of the access transistor is connected to the first terminal of the storage capacitor and the latch circuit 2, respectively. The second terminal of the storage capacitor is grounded. The non-ground pin of the storage capacitor, i.e., the source of the access transistor, is led out to the data terminal of the latch circuit 2 to achieve data latching. Under normal operation, the driver circuit 1 applies a high level through the word line to turn on the access transistor, and reads or writes data through the bit line. When a write operation is performed, the driver circuit 1 applies the voltage of the data to be written to the bit line. The conducting access transistor charges or discharges the storage capacitor, and the voltage at the first terminal of the storage capacitor changes accordingly to the data voltage, thereby realizing data storage. When a read operation is performed, the driver circuit 1 precharges the bit line to the intermediate potential, and then turns on the access transistor. The charge in the storage capacitor shares charge with the parasitic capacitance of the bit line, causing a small change in the bit line voltage. The sensitive amplifier in the driver circuit 1 detects this change and outputs the amplified data.

[0058] Since the source of the access transistor is also connected to latch circuit 2, latch circuit 2 can monitor the voltage at the first terminal of the storage capacitor at any time without going through the access transistor and bit line. This direct connection method allows latch circuit 2 to obtain the real voltage value on storage node SN in real time, avoiding sampling errors caused by bit line parasitic capacitance and drive circuit 1 delay. Grounding the second terminal of the storage capacitor provides a stable reference potential, so that the amount of charge on the storage capacitor depends only on the voltage at the first terminal.

[0059] In an exemplary embodiment, the driving circuit 1 is specifically configured to receive data output by the latch circuit 2 when the main power supply is in a power-on state, and write the data output by the latch circuit 2 into the storage capacitor in the storage node SN according to a preset refresh operation.

[0060] In this embodiment, when the main power supply recovers from a power failure to normal operation, the latch circuit 2 outputs its stored data to the drive circuit 1. Upon receiving this data, the drive circuit 1 writes it into the storage capacitor in the storage node SN according to a preset refresh operation. This preset refresh operation is similar to the conventional refresh operation of a dynamic random access memory (DRAM). First, the word line is turned on to activate the access transistor. Then, the drive circuit 1 applies a data voltage to the word line, charging or discharging the storage capacitor through the access transistor, restoring the charge state of the storage capacitor to the level corresponding to the data output by the latch circuit 2. Following the normal refresh process, the drive circuit 1 refreshes the storage capacitor to the corresponding value under the instruction of this signal, completing the data recovery of the 1T1C storage cell. The same operation is then performed on the next 1T1C structure, and this process is repeated to complete the data refresh of the entire memory module.

[0061] In this embodiment, a refresh operation for the current storage cell can be automatically initiated upon receiving a system power-on reset signal. Unlike a normal refresh, which reads data from other storage areas or external sources and then writes it back, the refresh data in this embodiment originates from the latch circuit 2 associated with the same storage cell. The driver circuit 1 can reuse the write driver and word line decoder used in normal read / write operations, requiring no additional hardware. This design allows the storage circuit to automatically recover data using the original refresh operation after power-on, without modifying the operating procedures of the main control chip or memory controller. When the driver circuit 1 performs the refresh operation, it applies word line pulses and bit line voltages according to normal timing requirements to ensure that the storage capacitor is accurately written. After writing is completed, the data of storage node SN is completely consistent with that before power failure, and the storage circuit is restored to its state before power failure.

[0062] In one exemplary embodiment, the drive circuit 1 is specifically configured to perform a read-after-refresh operation in response to a read operation to maintain the charge of the storage capacitor when the main power supply is in a normal power supply state.

[0063] In this embodiment, when the main power supply is in normal operating condition, the drive circuit 1 responds to an external read operation command, reads data from the storage node SN, and outputs it. Because the storage capacitor of the dynamic random access memory (DRAM) has leakage current, a single read operation consumes some of the charge on the storage capacitor, resulting in a decrease in the charge level after the read operation. If this charge is not replenished in time, subsequent reads will result in errors. Immediately after performing a read operation, the drive circuit 1 automatically performs a read-after-refresh operation. The essence of this read-after-refresh operation is to rewrite the data just read onto the storage capacitor, thereby restoring the charge of the storage capacitor to its full level. Immediately after the read, the write drive circuit 1 rewrites and replenishes the capacitor charge. Specifically, the sensitive amplifier in the drive circuit 1 amplifies the weak read signal into a full-swing digital voltage, which is then fed back to the write drive circuit 1. The write drive circuit 1 then writes this voltage back to the storage capacitor through the bit line and access transistor. The read-after-refresh operation does not change the original data content of the storage node SN; it is only used to maintain the charge level of the storage capacitor and prevent data loss due to charge leakage.

[0064] Combination Figure 2 and Figure 3 The working principle of the storage circuit of this application will be explained in detail.

[0065] During the power-on phase, each 1T1C storage node SN on the memory module operates normally. The additional latch circuit 2 synchronizes the data of each 1T1C storage node SN in real time via the data terminal D. Since the additional latch circuit 2 is a static structure (without its own capacitor charging and discharging), its speed is much higher than that of the 1T1C storage cell, so it has no adverse impact on the speed of the original circuit structure. At this time, the main power supply (1.1V) supplies power to all components, the power-down detection circuit 3 outputs a low level (CE=0), and the non-volatile latch sub-circuit 21 is in the ready-to-output mode, that is, a hot standby state with internally stored data. During the write operation, the word line is set high, the access transistor is turned on, and after the bit line is pre-charged to 0.55V, the write drive circuit 1 loads the data voltage through strong drive capability. When writing logic 1, BL=1.1V, and when writing logic 0, BL=0V. The charge is charged into the storage capacitor through the access transistor or released from the storage capacitor. The voltage of the storage node SN is stable at 1.1V, that is, logic 1, or stable at 0V, that is, logic 0. During a read operation, the word line is set high, the access transistor is turned on, and the charge of the storage capacitor and the parasitic capacitance of the bit line are shared. Because the storage capacitor is much smaller than the parasitic capacitance of the bit line, it can only cause a change of 10-50mV in the bit line voltage. After the drive circuit 1 detects this slight change, it amplifies it to 1.1V or 0V. After reading, the write drive circuit 1 immediately rewrites to replenish the capacitor charge, and refreshes the circuit after reading. The additional latch circuit 2 introduces the current data, i.e., 1.1V / 0V of the storage node SN, into the FeFET of the internal circuit through the D terminal at the rising edge of the DDR5 clock. The ferroelectric layer MOS is polarized, with forward polarization = 1 and reverse polarization = 0, realizing real-time data backup.

[0066] During the power-down phase, the main power supply VDD gradually drops, while an on-chip holding capacitor connected to VDD_RET maintains a stable voltage, free from glitches and interference, preventing accidental modification of the FeFET polarization. At this time, the FeFET cross-coupled latch circuit 2 no longer responds to clock signals and input data, entering a non-volatile holding state. Since the polarization state of the FeFET ferroelectric gate was written and locked before the power-down, and VDD_RET provides a smooth, jitter-free holding potential for the gate, noise interference during the power-down process prevents polarization state reversal. Therefore, the single-bit data originally stored in the FeFET latch circuit 2 is preserved and will not be lost due to the main power failure. At the same time, the original 1T1C memory cell gradually loses charge due to capacitor leakage, and the data disappears. The additional FeFET latch circuit 2, as a non-volatile backup unit, completely retains the logic state before the power-down.

[0067] During the power-on recovery phase, when the system is powered on again and the main power supply VDD is restored, the power detection circuit outputs a valid enable signal, CE=1. Since the internal polarization state of the non-volatile latch sub-circuit 21 remains unchanged, its output is consistent with that before the power failure. That is, after power is restored, the same logic level as before the power failure can be output through the Q terminal immediately. This level outputs the stored data to the driver circuit 1, and then the driver circuit 1 writes the corresponding data into the 1T1C memory cell, enabling the 1T1C cell to quickly restore to its logic state before the power failure. This completes the data recovery of a single bit of data in this memory node SN. Therefore, the entire recovery process in this embodiment is automatically completed by hardware, without the need for external control signals or modifications to the pin definitions of the DDR interface. It is an internal addition and is fully compatible with ordinary DDR. Furthermore, this added latch circuit 2 is implemented using a static FET, which does not involve capacitor charging and discharging, resulting in extremely high speed—one dimension faster than dynamic capacitor charging and discharging. Therefore, it does not slow down the normal operation of the memory when there is no power failure, and the recovery time is short, achieving a non-volatile function that is ready to use upon power-on.

[0068] This application achieves single-bit-level non-volatility in DDR5 memory. After power failure, data is retained by the FeFET latch circuit 2. The loss of charge in the original 1T1C cell does not affect data security, thus solving the data loss problem associated with DDR5 power failures in related technologies. The latch circuit 2 adopts a static logic structure with no dynamic charging / discharging delay. Its operating speed perfectly matches the high-frequency timing of DDR5, without slowing down the read / write speed of the original memory cells. Furthermore, the additional latch circuit 2 requires no additional external power supply pins and does not alter the standard DDR5 package or peripheral circuitry, resulting in strong system compatibility and low modification costs. Upon power-up, the hardware automatically and quickly restores data to the 1T1C memory cells without software intervention or complex initialization processes, achieving power-on readiness and improving system startup and power-down recovery efficiency.

[0069] This application also provides a memory including a plurality of memory circuits as described in any of the embodiments above.

[0070] Specifically, this memory can be DDR5.

[0071] For a description of the memory provided in this application, please refer to the above embodiments; further details will not be repeated here.

[0072] The memory provided in this application has the same beneficial effects as the memory circuit described above.

[0073] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be performed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, systems-on-chips, or combinations thereof. The device may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, protocol stack, database management system, operating system, cross-platform runtime environment, virtual machine, or a combination thereof. The aforementioned computer program (also referred to as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0074] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0075] The foregoing has provided a detailed description of a storage circuit and memory provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A storage circuit, characterized in that, include: A storage node includes a storage capacitor, the charge state of which characterizes the data stored in the storage node; A driving circuit, connected to the storage node, is configured to perform access operations on the storage node; A latching circuit is connected to both the storage node and the driving circuit. The latching circuit is configured to acquire and latch the data stored in the storage node when the main power supply is in a normal power-on state, retain the latched data using its non-volatile characteristics when the main power supply is in a power-off state, and output the latched data to the driving circuit when the main power supply is powered on again, so that the driving circuit can recover the data of the storage node based on the data output by the latching circuit.

2. The storage circuit according to claim 1, characterized in that, The latching circuit includes: A non-volatile latch sub-circuit is configured to latch data through the polarization state of an internal storage medium, the polarization state remaining unchanged when the main power supply is in a power-off state; The input control sub-circuit is configured to receive an internal clock signal and transmit the data stored in the storage node to the non-volatile latch sub-circuit when the rising edge of the internal clock signal arrives, so as to set the polarization state. The output control sub-circuit is configured to receive an enable signal characterizing the state of the main power supply, and control the connection or disconnection between the non-volatile latch sub-circuit and the drive circuit according to the enable signal. The state can be the normal power supply state, the power outage state, or the power-on state.

3. The storage circuit according to claim 2, characterized in that, The non-volatile latch circuit includes a first ferroelectric field-effect transistor and a second ferroelectric field-effect transistor, which are cross-coupled.

4. The storage circuit according to claim 3, characterized in that, The drain of the first ferroelectric field-effect transistor is connected to the gate of the second ferroelectric field-effect transistor, and the drain of the second ferroelectric field-effect transistor is connected to the gate of the first ferroelectric field-effect transistor.

5. The storage circuit according to claim 4, characterized in that, The non-volatile latch circuit also includes: The first pull-up resistor has its first end connected to the main power supply and its second end connected to the drain of the first ferroelectric field-effect transistor. The source of the first ferroelectric field-effect transistor is grounded. The second pull-up resistor has its first end connected to the main power supply and its second end connected to the drain of the second ferroelectric field-effect transistor, with the source of the second ferroelectric field-effect transistor grounded.

6. The storage circuit according to claim 3, characterized in that, The storage circuit further includes a holding capacitor, wherein the gate of the first ferroelectric field-effect transistor is connected to the voltage holding terminal corresponding to the holding capacitor, and the gate of the second ferroelectric field-effect transistor is connected to the voltage holding terminal corresponding to the holding capacitor.

7. The storage circuit according to claim 3, characterized in that, The input control sub-circuit includes: An input control transistor is provided, the gate of which is connected to an internal clock signal, the source of which is connected to the memory node, and the drain of which is connected to the gate of the first ferroelectric field-effect transistor. The output control sub-circuit includes: An output control transistor is provided, the gate of which receives an enable signal, the source of which is connected to the drain of the second ferroelectric field-effect transistor, and the drain of which is connected to the driving circuit.

8. The storage circuit according to claim 2, characterized in that, The enable signal includes a first enable signal or a second enable signal; The storage circuit further includes a power failure detection circuit, configured to output a first enable signal when the main power supply is in the normal power supply state, and output a second enable signal when the main power supply is in the power-on state. The first enable signal is used to control the output terminal of the latch circuit to be in a high-impedance state, and the second enable signal is used to control the output terminal of the latch circuit to be in an output state.

9. The storage circuit according to claim 8, characterized in that, The power failure detection circuit is further configured to output the first enable signal after a preset time following the output of the second enable signal.

10. The storage circuit according to claim 9, characterized in that, The power failure detection circuit includes a detection transistor and a delay sub-circuit. The delay sub-circuit is connected to the main power supply and the detection transistor, respectively. The detection transistor is connected to the main power supply and the latch circuit, respectively. The delay sub-circuit is configured to generate a second enable signal at the connection between the detection transistor and the latch circuit when the main power supply is in a re-energized state, and to generate a first enable signal at the connection after the preset time.

11. The storage circuit according to claim 2, characterized in that, The storage circuit also includes a clock buffer circuit. The input of the clock buffer circuit is connected to an external clock source, the first output of the clock buffer circuit is connected to the driving circuit, and the second output of the clock buffer circuit is connected to the latch circuit. The clock buffer circuit is configured to divide the external clock signal output by the external clock source into two internal clock signals.

12. The storage circuit according to claim 1, characterized in that, The storage node further includes an access transistor, the drain of which is connected to the driving circuit via a bit line, the gate of which is connected to the driving circuit via a word line, the source of which is connected to the first terminal of the storage capacitor and the latch circuit, respectively, and the second terminal of the storage capacitor is grounded.

13. The storage circuit according to any one of claims 1-12, characterized in that, The drive circuit is specifically configured to receive the data output by the latch circuit when the main power supply is in a re-energized state, and write the data output by the latch circuit into the storage capacitor in the storage node according to a preset refresh operation.

14. The storage circuit according to claim 13, characterized in that, The drive circuit is specifically configured to perform a read-after-refresh operation in response to a read operation when the main power supply is in a normal power supply state, so as to maintain the charge of the storage capacitor.

15. A memory, characterized in that, It includes the storage circuits described in any one of claims 1-14.

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