Memory cell, memory and write, erase and read methods

Abstract

A memory cell, a memory and an operating method thereof, the memory cell comprising a first tube and a second tube, the first tube and the second tube comprising: a first gate structure and a second gate structure, located above a substrate, spaced and arranged adjacently; a first doped region and a second doped region, respectively located in the substrate on both sides of the whole structure composed of the first gate structure and the second gate structure; a third doped region located in the substrate spaced between the adjacent first gate structure and the second gate structure. The memory comprises a plurality of arrayed memory cells, and the operating method comprises write, erase and read operations of the memory. When performing the write operation, the other tube of the same memory cell as the to-be-written tube is turned on to assist the to-be-written tube to write data into the gate structure through the hot carrier effect, thereby effectively reducing the write voltage and the write time.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more specifically to a storage unit, a memory, and methods for writing, erasing, and reading. Background Technology

[0002] Existing technologies typically employ the Fowler-Nordheim (FN) tunneling effect to inject and extract charge carriers in dual-transistor SONOS memories, achieving low-power erasure and write operations. However, driving the FN tunneling effect requires applying a high bias voltage of 8V to 9V to create a strong electric field, which limits the application of these memories in low-bias scenarios. Furthermore, memories relying on FN tunneling are also limited by slow quantum processes, resulting in millisecond-level erase and write times, making them unable to meet the demands of high-speed writing.

[0003] Therefore, there is an urgent need for a storage unit, memory, and its operation method to meet the requirements of low bias voltage and high-speed writing. Summary of the Invention

[0004] The problem solved by this invention is to provide a storage unit, a memory, and an operation method thereof, which reduces the operating bias voltage and shortens the write time.

[0005] To address the aforementioned problems, the present invention provides a memory cell comprising: a first transistor and a second transistor, wherein the first transistor and the second transistor include: a first gate structure and a second gate structure, which are disposed on a substrate, spaced apart and adjacent to each other; a first doped region and a second doped region, which are respectively located in the substrate on both sides of an integral structure composed of the first gate structure and the second gate structure, wherein the first doped region is located on one side of the first gate structure and the second doped region is located on one side of the second gate structure; and a third doped region, which is located in the substrate spaced between adjacent first gate structures and second gate structures; wherein the first gate structure and the second gate structure each include a gate tunneling layer, a gate trap layer and a gate blocking layer stacked sequentially on the substrate, and the doping concentration of the third doped region is lower than that of the first doped region and the second doped region.

[0006] The first gate structure and the second gate structure also include sidewalls located on both sides of the stacked structure of the gate tunneling layer, the gate trap layer and the gate blocking layer.

[0007] The gate sidewalls between the first and second transistors are in contact with each other and cover the third doped region.

[0008] The present invention also provides a memory comprising memory cells as described above, wherein the plurality of memory cells are arranged in an array, and the memory cells further comprising: a first word line for electrically connecting the first gate structure of a first transistor located in the same row; a second word line for electrically connecting the second gate structure of a second transistor located in the same row; a first bit line for electrically connecting the first doped regions of memory cells located in the same column; a second bit line for electrically connecting the second doped regions of memory cells located in the same column; and a substrate connection line for electrically connecting the substrate of the memory cells.

[0009] The memory also includes a charge pump for applying bias voltage to the substrate contact line, the first word line, the second word line, the first bit line, and the second bit line.

[0010] The charge pump includes a single charge pump used to apply a positive bias voltage.

[0011] The charge pump includes a dual charge pump, which is used to apply a forward bias and a reverse bias.

[0012] The present invention also provides a method for writing to a memory as described above, comprising: selecting a transistor to be written to, and another transistor located in the same memory cell as the transistor to be written to be used as a non-transistor to be written to; applying a first bias voltage to the word line where the non-transistor to be written is located to turn on the non-transistor to be written to; applying a second bias voltage to the word line where the transistor to be written is located to allow carriers to enter the gate trap layer of the transistor to be written to be written by means of hot carrier injection, while forming a bias voltage difference between the first bit line and the second bit line selected on the row, and not forming a bias voltage difference between the first bit line and the second bit line not selected on the row.

[0013] The first bias voltage is greater than the threshold bias voltage of the non-write tube, but less than the second bias voltage.

[0014] The first and second transistors located in the same memory cell cannot be used as write transistors at the same time.

[0015] Each write operation involves one or more rows of data to be written to the specified write tube.

[0016] The rows to be written are multiple rows, and any two tubes to be written on these multiple rows do not belong to the same storage unit.

[0017] The present invention also provides a method for erasing a memory as described above, comprising: selecting a transistor to be erased; forming a bias voltage difference between the gate and the substrate of the transistor to be erased, and not forming a bias voltage difference between the gate and the substrate of a non-transistor corresponding to the transistor to be erased.

[0018] The tubes to be erased include multiple tubes, which can be arranged in one or more rows.

[0019] The tube to be erased comprises multiple rows of tubes, and the multiple rows include multiple adjacent rows.

[0020] The transistors located in the same memory cell as the transistor to be erased are considered as non-erasable transistors, and no bias voltage difference is formed between the gate and the substrate of the non-erasable transistor corresponding to the transistor to be erased.

[0021] The present invention also provides a method for reading a memory as described above, comprising: selecting a transistor to be read, wherein another transistor in the same memory cell of the transistor to be read is a non-transistor to be read; grounding the word line of the transistor to be read, applying a fourth bias voltage to the word line of the non-transistor to be read corresponding to the transistor to be read to turn on the non-transistor to be read, forming a bias voltage between the bit line of the non-transistor to be read and the bit line of the corresponding transistor to be read; and reading the current of the transistor to be read to determine the memory state of the transistor to be read.

[0022] Each read operation involves either a single read tube or multiple read tubes in the same row.

[0023] Compared with the prior art, the technical solution of the present invention has the following advantages: The memory cell provided by the present invention includes an adjacent first transistor and a second transistor. The first transistor and the second transistor include a third doped region shared by bits. When the first transistor or the second transistor in the memory cell is used as the transistor to be written, the other transistor is turned on to provide a carrier lateral channel including the third doped region. This allows the carriers in the memory cell to be stored in the gate trap layer of the transistor to be written by hot carrier injection, which effectively reduces the write bias voltage and shortens the write time. Attached Figure Description

[0024] Figure 1 A cross-sectional view of the intermediate structure of a memory cell according to an embodiment of the present disclosure is shown; Figure 2 A schematic diagram of the circuit structure of a memory according to an embodiment of the present disclosure is shown; Figure 3 A cross-sectional schematic diagram of the intermediate structure of the memory in a writing method according to an embodiment of the present disclosure is shown; Figure 4 A schematic diagram of the circuit structure of the memory in a writing method according to an embodiment of the present disclosure is shown; Figure 5 A cross-sectional schematic diagram of the intermediate structure of the memory in an erasure method according to an embodiment of the present disclosure is shown; Figure 6 A schematic diagram of the circuit structure of the memory in an erasure method according to an embodiment of the present disclosure is shown; Figure 7 A cross-sectional schematic diagram of the intermediate structure of the memory in a reading method according to an embodiment of the present disclosure is shown; Figure 8 A schematic diagram of the circuit structure of the memory in a reading method according to an embodiment of the present disclosure is shown. Detailed Implementation

[0025] As can be seen from the background technology, the write operation bias voltage of the existing dual-transistor SONOS memory used to store 2 bits of data is relatively high, which greatly limits its application in low-bias scenarios.

[0026] To solve the aforementioned technical problem, the present invention provides a memory cell, including a first transistor and a second transistor. The first transistor and the second transistor include: a first gate structure and a second gate structure, located on a substrate, spaced apart and adjacent to each other; a first doped region and a second doped region, respectively located in the substrate on both sides of the integral structure formed by the first gate structure and the second doped region, the first doped region being located on one side of the first gate structure and the second doped region being located on one side of the second gate structure; and a third doped region, located in the substrate spaced between adjacent first gate structures and second gate structures. The first gate structure and the second gate structure each include a gate tunneling layer, a gate trap layer, and a gate blocking layer stacked sequentially on the substrate, and the doping concentration of the third doped region is lower than that of the first doped region and the second doped region.

[0027] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0028] Figure 1 A cross-sectional view of the intermediate structure of a memory cell according to an embodiment of the present disclosure is shown; Figure 2 A schematic diagram of the circuit structure of a memory according to an embodiment of the present disclosure is shown.

[0029] like Figure 1 As shown, the memory cell 100 includes a substrate 1, which includes a first doped region 4 and a second doped region 5 located on both sides of the memory cell, as well as a lightly doped region located in a portion of the upper surface of the substrate.

[0030] In some embodiments, the substrate 1 is formed based on a CMOS process, and the constituent material of the substrate 1 may be single-crystal silicon, or other materials such as silicon on insulating material, silicon nitride, and silicon carbide.

[0031] Continue to refer to Figure 1 The storage structure 100 further includes a first gate structure 20 and a second gate structure 30, which are located on the substrate 1 and are arranged adjacent to each other in a direction parallel to the surface of the substrate 1.

[0032] In some embodiments, the first gate structure 20 and the second gate structure 30 are disposed apart.

[0033] The first gate structure 20 and the second gate structure 30 include a gate tunneling layer 7, a gate trapping layer 8 and a gate blocking layer 9 stacked sequentially on the substrate 1.

[0034] In some embodiments, the gate tunneling layer 7 is located between the substrate 1 and the gate trapping layer 8, and is used to provide a tunneling transport channel for charge carriers, such as allowing electrons to enter the gate trapping layer 8 through the FN tunneling effect or the hot charge carrier injection effect. The gate tunneling layer 7 may be composed of silicon dioxide or other materials. The gate trapping layer 8 is used to capture and store charge carriers. The gate trapping layer 8 may be composed of silicon nitride or other materials. The gate blocking layer 9 serves as a charge blocking layer to prevent charge carriers in the gate trapping layer 8 from flowing to the gate electrode. The gate blocking layer 9 may be composed of silicon oxide or other materials.

[0035] The first gate structure 20 and the second gate structure 30 further include sidewalls 10 on both sides of the stacked structure of the gate tunneling layer 7, the gate trap layer 8, and the gate barrier layer 9. The first gate structure 20 also includes a first gate electrode layer 2 located above the gate barrier layer 9, and the second gate structure 30 also includes a second gate electrode layer 3 located above the gate barrier layer 9. The first gate electrode layer 2 and the second gate electrode layer 3 serve as voltage application terminals to provide a vertical electric field and regulate the tunneling direction and velocity of charge carriers. The constituent materials of the first gate electrode layer 2 and the second gate electrode layer 3 may be polysilicon or other materials.

[0036] Continue to refer to Figure 1 The storage unit 100 includes a first tube 200 and a second tube 300.

[0037] The first transistor 200 includes a first gate structure 20 and a first doped region 4 located on one side of the first gate structure 20. The second transistor 300 includes a second gate structure 30 and a second doped region 5 located on one side of the second gate structure 30. The first gate electrode layer 2 and the second gate electrode layer 3 are respectively connected to word lines, and the first doped region 3 and the second doped region 4 are respectively connected to bit lines. Furthermore, the overall structure formed by the first gate structure 20 and the second gate structure 30 also includes a third doped region 6. The third doped region 6 is located within the substrate 1 between the first gate structure 20 and the third gate structure 3, and the doping concentration of the third doped region 6 is lower than that of the first doped region 4 and the second doped region 5. The first transistor 200 and the second transistor 300 have a structure similar to a MOS transistor.

[0038] In some embodiments, when one of the storage tubes 100 is performing a write operation, the other tube is turned on. For example, when the first tube 200 of the storage tube 100 is performing a write operation, the second tube 300 is turned on to assist charge carriers in entering the gate trap layer 8 of the first tube 200 through the channel including the third doped region 6.

[0039] Accordingly, this disclosure also provides a memory.

[0040] The memory includes a plurality of memory cells arranged in a cell-like manner. The memory cells are described in detail above. The memory also includes: a first word line for electrically connecting the first gate structure of a first transistor located in the same row; a second word line for electrically connecting the second gate structure of a second transistor located in the same row; a first bit line for electrically connecting the first doped regions of memory cells located in the same column; a second bit line for electrically connecting the second doped regions of memory cells located in the same column; and a substrate connection line for electrically connecting the substrate of the memory cells.

[0041] refer to Figure 2 This diagram illustrates a circuit structure of a memory according to an embodiment of the present disclosure. The first word line and the second word line are respectively connected to the first transistor and the second transistor of the same memory cell, and the first bit line and the second bit line are respectively connected to the first doped region and the second doped region. Adjacent first word lines and second word lines, as well as adjacent first bit lines and second bit lines, are of equal status; for clarity, they are distinguished using "". "The second word line and the second bit line are marked. The memory includes the first word line WLn and the second word line WLn." First line BLn, second line BLn And the base connection line PW, where n is a positive integer.

[0042] Specifically, in the memory cell 100, the first gate electrode layer 2 is connected to the first word line WLn, and the second gate electrode layer 3 is connected to the second word line WLn. The first doped region 3 is connected to the first bit line BLn, and the second doped region 4 is connected to the second bit line BLn. Furthermore, in several memory cells in the same row, the first gate electrode layer 2 of the first transistor 200 is connected to the same first word line, and the second gate electrode layer 3 of several second transistors 300 is connected to the same second word line; in several memory cells 100 in the same column, the first doped region 3 of several first transistors 200 is connected to the same first bit line, and the second doped region 4 of several second transistors 300 is connected to the same second bit line.

[0043] The memory also includes a charge pump for supplying charge to the substrate contact line PW, the first word line WLn, and the second word line WLn. First line BLn and second line BLn Apply a bias voltage.

[0044] In some embodiments, the charge pump includes a single charge pump for applying a positive bias.

[0045] Specifically, a forward bias voltage is generated by a single charge pump and a bias voltage reference value is set. Then, the transistor to be operated is determined by the external circuit. The bias voltage is applied to several first word lines, several second word lines, several first bit lines, several second bit lines, and the substrate contact line in the memory by voltage division or direct drive to form a relative bias voltage difference, so as to perform any operation of erasing, writing, and reading on several transistors to be operated in the memory.

[0046] For example, the charge pump includes a single charge pump, which sets a bias reference value and generates a positive high bias voltage. Combined with the selected transistors in the peripheral circuit, the positive high voltage, the positive low voltage formed by voltage division, and the grounded zero bias voltage are applied to a number of first word lines, a number of second word lines, a number of first bit lines, a number of second bit lines, and the substrate contact line to form a relative bias voltage difference, so as to perform a write operation on a number of transistors in the memory.

[0047] In other embodiments, the charge pump includes a dual charge pump for applying a forward bias and a reverse bias.

[0048] Specifically, the charge pump includes a dual charge pump consisting of two independent charge pumps to generate forward and reverse bias voltages respectively. The dual charge pump sets a reference bias voltage, and then, in conjunction with the peripheral circuitry, selects the transistor to be operated on. It first applies a positive bias voltage with a relative bias value to several first word lines, several second word lines, several first bit lines, several second bit lines, and the substrate contact line in the memory to perform any of the erase, write, and read operations on the transistors to be operated on. Furthermore, during erase and write operations on the transistors to be operated on, the dual charge pump further increases the applied bias voltage with a negative bias value to offset the reference bias voltage and reduce the absolute bias voltage value. The dual charge pump scheme in this disclosure eliminates the need to redesign the control logic and timing, directly reusing the operation flow of the relative bias value in the single charge pump, thus reducing the complexity of the circuit design.

[0049] For example, the charge pump of the memory is a dual charge pump. The dual charge pump uses zero bias as the reference bias. It starts a single charge pump for applying a positive bias to apply a positive bias with a relative bias value to a plurality of first word lines, a plurality of second word lines, a plurality of first bit lines, a plurality of second bit lines, and the substrate contact line in the memory to perform a write operation on the transistor to be operated. At the same time, it starts a single charge pump for applying a reverse bias to add a negative bias to all the applied positive bias, thereby shifting the reference bias of the dual charge pump downward and maintaining the relative bias value between the word line terminals and the bit line terminals in the memory. This reduces the absolute bias value of the electrodes and realizes the low-cost conversion of the single charge pump into a dual charge pump.

[0050] Accordingly, this disclosure also provides a method for writing to the memory as described above.

[0051] The writing method includes: selecting the transistor to be written and turning on the non-transistor to be written that is in the same memory cell as the transistor to be written, so that the charge carriers enter the gate trap layer of the transistor to be written through hot carrier injection.

[0052] Specifically, the transistor to be written to is selected, and a second bias voltage is applied to the word line where the transistor to be written is located; another transistor in the same memory cell as the transistor to be written to is selected as the non-written transistor, and the non-written transistor is turned on, including applying a first bias voltage to the word line where the non-written transistor is located, and forming a bias voltage difference between the first bit line and the second bit line selected on the row, so that the charge carriers flow to the side of the transistor to be written.

[0053] In some embodiments, the substrate connection line is first grounded, then the transistor to be written is selected based on the peripheral circuit, and another transistor in the same memory cell as the transistor to be written is designated as a non-written transistor. Next, a bias voltage is applied to the word line and bit line connected to the memory cell to be written, including the transistor to be written, so that charge carriers enter the gate trap layer of the transistor to be written through hot carrier injection.

[0054] The process of applying a bias voltage to the cell to be written includes: applying a first bias voltage to the word line where the non-to-be-written transistor is located to turn on the non-to-be-written transistor and provide a carrier channel; applying a second bias voltage to the transistor to be written to turn on the transistor to be written; applying a third bias voltage to the bit line connected to the cell to be written and grounding the bit line connected to the non-to-be-written transistor, so that a bias voltage difference is formed between the bit lines in the cell to be written, thereby accelerating the flow of carriers to the side of the transistor to be written.

[0055] With 4 The writing process will be explained using a memory as an example. Figure 3 A cross-sectional schematic diagram of the intermediate structure of the memory in a writing method according to an embodiment of the present disclosure is shown. The memory includes a storage cell composed of first transistors A1, B1, A2, and B2, and is described in detail with writing data to the first transistor A1 as an example.

[0056] like Figure 3 In the illustrated embodiment, electrons are injected into the gate trap layer 8 of the first transistor A1 via hot carrier input to write one byte, with the data being "1". First, the substrate connection line PW is grounded. Then, the transistor A1 to be written to is selected based on the peripheral circuitry, and another transistor A1 located in the same memory cell as the transistor to be written is also selected. As the non-write transistor, bias voltage is then applied to the word lines and bit lines connected to the memory cell to be written, including: biasing the non-write transistor A1. The word line WL1 Apply a first bias voltage V1 to turn on the non-write tube A1 So that the first tube A1 and the second tube A1 The third doped region 6 between them remains in a conducting state to provide an electron channel; a second bias voltage V2 is applied to the word line WL1 where the transistor A1 to be written is located to make it in a conducting state; a third bias voltage V3 is applied to the first bit line BL1 selected on the row to be written, and the second bit line BL1 is turned on. Grounding, so that the first bit line BL1 and the second bit line BL1 are grounded. A bias voltage difference is formed between them to create an accelerating electric field and generate a hot carrier injection effect. This allows a channel to be formed using the third doped region 6, enabling the non-write transistor A1 to... The generated electrons undergo channel hot carrier injection at the transistor A1 to be written. That is, the electrons enter the gate trap layer 8 of the first gate structure 20 from the second doped region 5 through the accelerating electric field and the third doped region 6 to complete the writing operation of the first transistor A1.

[0057] In some embodiments, the first bias voltage V1 is greater than the threshold bias voltage of the non-write transistor, and the first bias voltage V1 is less than the second bias voltage V2, so that the non-write transistor is in an on state but does not perform carrier tunneling.

[0058] In this embodiment of the disclosure, the threshold bias voltage of the non-write tube is 1.5V to 3V, the first bias voltage V1 is 3V, the second bias voltage V2 is 7V, and the third bias voltage V3 is 4V.

[0059] The writing method further includes: not performing a write operation on storage cells that are not selected on the line to be written.

[0060] Specifically, the first and second word lines of other memory cells in the same row as the cell to be written are grounded or set to float to avoid bias voltage difference and thus avoid hot carrier effect.

[0061] Continue to refer to Figure 3In the illustrated embodiment, the row containing the memory cell to be written is designated as the row to be written, and the first bit line BL2 and the second bit line BL2 of the unselected memory cell on the row to be written are defined. Grounding prevents the formation of a bias voltage difference, thus preventing the formation of a hot carrier injection effect between the first doped region 4 and the second doped region 5 of the unselected memory cell, thereby preventing write operations.

[0062] The writing method further includes: turning off the first or second tube of the storage cell that does not contain other rows of the tube to be written.

[0063] Specifically, in memory cells that do not contain the tube to be written to, a fourth bias voltage is applied to the word line connected to the first or second tube to turn off the tube, while a fifth bias voltage is applied to another word line to prevent carrier tunneling in the non-written tube.

[0064] Continue to refer to Figure 3 In the illustrated embodiment, the second tube A2 in the memory cell that does not contain other rows to be written to is turned off. and B2 That is, to add to the storage unit with the same letter and number identifier The word line WL2 connected to the pipe A fourth bias voltage V4 is applied to shut off the second tube, while a fifth bias voltage V5 is applied to the word line WL2, which is identified by the same letter and number, to prevent tunneling.

[0065] In some embodiments, the fifth bias voltage V5 is much lower than the second bias voltage V2.

[0066] In this embodiment of the disclosure, the fifth bias voltage V5 is 1.1V, and the fourth bias voltage V4 is -2V.

[0067] In some embodiments, the first and second tubes located in the same memory cell cannot be used as write tubes simultaneously.

[0068] Specifically, in the same cell to be written, the first transistor, through the electric field formed by the first doped region 4 and the second doped region 5, and the channel formed by the conductive third doped region 6, allows charge carriers to enter the gate trap layer of the transistor to be written through the hot carrier injection effect, thus completing the writing operation. The first and second transistors share the electric field formed by the first doped region 4 and the second doped region 5, as well as the channel formed by the conductive third doped region 6, allowing the non-to-be-written transistor to assist the transistor to be written in the writing operation.

[0069] In some embodiments, each write operation on the tube to be written is performed on a single line, meaning that write operations can be performed on several tubes in a single line simultaneously.

[0070] For example, in each write operation, a row is selected as the row to be written, and several transistors to be written to are selected. The transistors to be written to include first transistors and second transistors. Then, write operations are performed on the transistors to be written in the row to be written, including writing data "1" to several first transistors and writing data "0" to several second transistors. The gate structure of each transistor to be written is connected to the same word line.

[0071] In some embodiments, each write operation consists of multiple rows of write-to-write tubes, and any two write-to-write tubes on these multiple rows do not belong to the same storage unit.

[0072] In some embodiments, when the write tubes for each write operation include a plurality of write tubes in multiple rows, the write process for the plurality of write tubes includes injecting electrons into the gate trap layer of each write tube to write the data "1".

[0073] Specifically, a third bias voltage is applied to the word line connected to the transistor to be written, a first bias voltage is applied to the word line connected to the non-transistor to be written in the memory cell where the transistor to be written is located to turn on the transistor, and bias voltages are applied to the two bit line terminals of the memory cell where the transistor to be written is located to form a bias voltage difference.

[0074] In some embodiments, each write operation to a plurality of write tubes across multiple rows includes writing data "0" to each write tube.

[0075] Specifically, a third bias voltage is applied to the word line connected to the transistor to be written, a first bias voltage is applied to the word line connected to the non-transistor to be written in the memory cell where the transistor to be written is located to turn on the transistor, and the same bias voltage is applied to the two bit line terminals of the memory cell where the transistor to be written is located to prevent the formation of a bias voltage difference.

[0076] In some embodiments, when each write operation involves multiple rows of write tubes, the rows to be written have the same write data, that is, the same data is written to multiple write tubes with the same letter identifier.

[0077] Specifically, refer to Figure 4 This diagram illustrates a circuit structure of a memory in a writing method according to an embodiment of the present disclosure. First, the substrate connection line PW is grounded. Then, transistors to be written to are selected, including A1, B1, A2, and B2. Next, data "1" and data "0" are written to transistors A1 and B1, respectively. Word line WL1 and word line WL2 are also specified. Apply a second bias voltage V2 and a first bias voltage V1 respectively to select the write row of the transistor to be written to, located on the connected word line WL1; bit line BL1 and bit line BL2 A third bias voltage V3 is applied and grounded to create a sufficient bias voltage difference, allowing electrons to enter the gate trap layer (including A1) of the transistor to be written via the hot carrier effect, thus completing the writing of data "1"; bit line BL1 Together with bit line BL2, a ninth bias voltage V9 is applied to complete the process of writing data "0" to the write transistor B1 without forming a bias voltage difference. Simultaneously, the bit line bias voltages of the memory cells containing the write transistors A2 and B2 are consistent with the bit line bias voltages of the memory cells containing the write transistors A1 and B1, and word line WL2 and word line WL2... When the second bias voltage V2 and the first bias voltage V1 are applied respectively, data “1” and data “0” will be written into the transistors A2 and B2 respectively.

[0078] Accordingly, this disclosure also provides a method for erasing the memory as described above.

[0079] The erasure method includes: selecting the transistor to be erased and forming an electric field between the gate and the substrate of the transistor to be erased.

[0080] Specifically, select the transistor to be erased; establish a bias voltage difference between the gate and the substrate of the transistor to be erased.

[0081] In some embodiments, a sixth bias voltage is first applied to the substrate connection line, and then the transistor to be erased is selected based on the peripheral circuit. Next, bias voltages are set on the word lines and bit lines connected to the erased cell, including the transistor to be erased, including: setting both the first bit line and the second bit line of the erased cell to be floating or applying a sixth bias voltage to both to avoid the formation of a lateral electric field; grounding the word lines connected to the erased transistor to create a bias voltage difference between the gate structure of the erased transistor and the substrate, so that charge carriers can enter the gate trap layer of the erased transistor through the FN tunneling effect.

[0082] With 1 The erasure process will be explained using a memory chip of size 2 as an example. Figure 5 A cross-sectional schematic diagram of the intermediate structure of a memory in a writing method according to an embodiment of the present disclosure is shown. The memory includes first transistors A1 and A2 and a second transistor A1. A2 The storage unit is composed of the following detailed description, taking the erasure of the first tube A1 as an example.

[0083] like Figure 5 As shown, firstly, a sixth bias voltage V6 is applied to the base connection line PW. Then, the transistor to be erased, including A1, is selected based on the peripheral circuitry. Next, bias voltages are set for several word lines and bit lines of the memory, including: bias voltages on the first bit line BL1, BL2, and the second bit line BL1. BL2 A sixth bias voltage V6 is applied to all of them; the first word line WL2 and the second word line WL2 connected to the non-erasable cell are also subjected to this bias. Apply the sixth bias voltage V6; the non-erasable tube A1 of the cell to be erased. The second word line WL1 connected Apply the sixth bias voltage V6; ground the first word line WL1 connected to the transistor to be erased. Create a bias voltage difference between the gate structure of the transistor to be erased and the substrate, so that holes can enter the gate trap layer 8 of the transistor to be erased A1 through the FN tunneling effect to complete the erasure operation, and the data is "0".

[0084] In some embodiments, the memory includes a plurality of transistors to be erased, which are located in the same row. The method for erasing multiple transistors in the same row is similar to the method for erasing a single transistor as described above, and will not be repeated here.

[0085] In some embodiments, the erasure method further includes: a transistor located in the same memory cell as the transistor to be erased is designated as a non-erasable transistor, and no bias voltage difference is formed between the gate and the substrate of the non-erasable transistor corresponding to the transistor to be erased.

[0086] Specifically, a sixth bias voltage is applied to the word line connected to the unselected non-erasable transistor in the erase cell, so that no electric field is generated between the gate structure of the non-erasable transistor and the substrate, thereby avoiding the FN tunneling effect.

[0087] In some embodiments, reference Figure 6 The diagram shows a schematic of the memory circuit structure in a write method according to an embodiment of the present disclosure. The erase operation is performed in page mode on transistors A1, B1 to Bn in the same row, including setting the base connection line PW, the word lines and bit lines of the non-erasable transistors, and applying a sixth bias voltage V6 to the bit lines of the transistors to be erased, and grounding the word line WL1 of the transistors to be erased.

[0088] In this embodiment of the disclosure, the sixth bias voltage V6 is 7.8V.

[0089] In some embodiments, the memory has a plurality of eraseable tubes located in multiple rows.

[0090] Specifically, the page mode is used to erase multiple rows of transistors simultaneously, including grounding the word lines connected to the rows to be erased.

[0091] In some embodiments, the tube to be erased comprises multiple rows of tubes, the multiple rows comprising adjacent rows.

[0092] Continue to refer to Figure 5 The embodiment shown uses page mode to erase multiple rows of transistors A1 and A2 to be erased. Holes are injected into the gate trap layer 8 of the transistors to be erased to erase the entire row of data, which is "0". The erasure method includes: setting a base connection line PW, and word lines WL1 of the non-to-be-erased transistors. WL2 Bit line BL1 BL2 A sixth bias voltage V6 is applied to the bit lines BL1 and BL2 of the transistor to be erased, and the word lines WL1 and WL2 of the transistor to be erased are grounded.

[0093] The erasure method further includes applying the same bias voltage as the substrate to word lines connected to other rows, excluding the tube to be erased.

[0094] Specifically, a sixth bias voltage is applied to the word lines connected to the non-erasable transistors in other rows, excluding the transistor to be erased, to prevent carriers from entering the gate trap layer of the non-erasable transistors through the FN tunneling effect.

[0095] Continue to refer to Figure 6 The illustrated embodiment connects word lines WLn and WLn to other rows excluding the erase tube. Apply the sixth bias voltage V6.

[0096] Accordingly, this disclosure also provides a method for reading the memory as described above.

[0097] The reading method includes: reading the tube to be read and opening another tube in the same memory cell of the tube to be read.

[0098] Specifically, select the transistor to be read and ground the word line where the transistor to be read is located; take the other transistor in the same memory cell as the transistor to be read as the non-transistor to be read, apply a seventh bias voltage to the word line where the non-transistor to be read is located to turn on the non-transistor to be read, and form a bias voltage between the bit line of the non-transistor to be read and the bit line where the corresponding transistor to be read is located.

[0099] In some embodiments, the base connection line is first grounded, then the transistor to be read is selected based on the peripheral circuit, and another transistor in the same memory cell of the transistor to be read is designated as the non-read transistor. Next, bias voltages are applied to the word lines and bit lines connected to the memory cell to be read, including: grounding the word lines connected to the transistor to be read, so that the conduction characteristics of the transistor to be read are determined by a threshold bias voltage; applying a seventh bias voltage V7 to the non-read transistor to turn it on while preventing carrier tunneling; grounding the bit line of the non-read transistor as the ground terminal of the memory cell; and applying an eighth bias voltage V8 to the bit line of the transistor to be read, forming a bias voltage difference with the bit line bias of the non-read transistor to provide a drive bias voltage.

[0100] The reading method further includes: reading the current of the transistor to be read in order to determine the storage state of the transistor.

[0101] Specifically, when the read current is large, the storage state of the transistor to be read is determined to be "0", meaning there are no trapped electrons in the gate trap layer of the transistor to be read; when the read current is small, the storage state of the transistor to be read is determined to be "1", meaning there are trapped electrons in the gate trap layer of the transistor to be read. It should be noted that the seventh bias voltage V7 applied to the gate of the non-to-be-read transistor to turn it on is sufficiently small, and the source-drain resistance of the non-to-be-read transistor is much smaller than that of the transistor to be read, so much so that it can be ignored, making the magnitude of the read current mainly determined by the current of the transistor to be read.

[0102] It should be noted that the value of the reading current is affected by the size of the tube to be read.

[0103] In some embodiments, when electrons are trapped in the gate trap layer 8 of the read-to-cell transistor, the threshold bias voltage of the read-to-cell transistor rises to a positive value. Grounding the gate structure of the read-to-cell transistor prevents the formation of a conductive channel within the memory cell, resulting in a small read current.

[0104] In this embodiment of the disclosure, when the tube to be read has stored data "1", the reading current is small, ranging from 10nA to 1μA.

[0105] In other embodiments, no electrons are trapped in the gate trap layer 8 with the read transistor, and the threshold bias voltage of the read transistor is negative. The gate structure of the transistor to be read is grounded, forming a conductive channel within the memory cell, such that the read current is a large current.

[0106] In this embodiment of the disclosure, when the data "0" is already stored in the tube to be read, the reading current is relatively large, ranging from 1μA to 100μA.

[0107] In some embodiments, the tube to be read is one tube each time.

[0108] refer to Figure 7 The diagram shows a cross-sectional schematic of the intermediate structure of a memory in a reading method according to an embodiment of the present disclosure. The memory includes first transistors A1, B1, A2, B2, and a second transistor A1. B1 A2 B2 The storage unit composed of these components will be described in detail, taking the reading of the storage state of the first tube A1 as an example.

[0109] like Figure 7 In the embodiment shown, the base connection line PW is first grounded, then the transistor A1 to be read is selected based on the peripheral circuit, and another transistor A1 located in the same memory cell as the transistor to be read is also selected. As the non-read transistor A1, a bias voltage is then applied to the word line and bit line connected to the cell to be read, including: grounding the word line WL1 of the transistor to be read A1; and applying a bias voltage to the non-read transistor A1. The word line WL1 Apply a seventh bias voltage V7 to turn on the non-read transistor; apply an eighth bias voltage V8 to the bit line BL1 of the transistor A1 to be read and turn on the non-read transistor A1. bit line BL1 Grounding is used to create a bias voltage. Then, the current of the non-read transistor is read as 50nA, which indicates that there are trapped electrons in the gate trap layer 8 of the first transistor A1.

[0110] In some embodiments, the tubes to be read are located in the same row each time they are read.

[0111] In some embodiments, each read operation involves reading 8 or 16 bits of the same row together.

[0112] Example, reference Figure 8 The diagram illustrates a circuit structure of a memory in a reading method according to an embodiment of this disclosure. First, the base connection line PW is grounded. Then, based on the peripheral circuit, the first transistors of eight memory cells to be read (A1, B1 to G1, not shown in the figure) in alphabetical order are selected, and the second transistors of these memory cells (A1, B1 to G1, not shown in the figure) are... B1 To G1 (Not shown in the diagram) As the non-read transistor, the word line WL1 connected to the first transistor is grounded, and the word line WL1 connected to the second transistor is... Apply the eighth bias voltage V8, apply the seventh bias voltage V7 to the bit line connected to the first transistor, and ground the bit line connected to the second transistor.

[0113] The reading method further includes: in other memory cells located in the same row as the tube to be read, setting the bit line of the non-tube to be read to ground.

[0114] Continue to refer to Figure 7 In the embodiment shown, the memory includes first transistors A1, B1, A2, B2 and a second transistor A1. B1 A2 B2 The storage cell consists of two transistors, with the first transistor A1 being the transistor to be read. In the non-reading cells located in the same row as the cell containing the transistor A1, the first transistor B1 and the second transistor B1... For the non-read unit, the first bit line BL2 and the second bit line BL2 are... Grounding ensures there is no bias voltage difference between the source and drain of the first and second transistors and the substrate, thus avoiding any impact on the read current.

[0115] The reading method further includes: turning off the first and second tubes of the storage cells in other rows that do not contain the tube to be read.

[0116] Continue to refer to Figure 8 The illustrated embodiment performs a read operation on the first transistor connected to word line WL1, and shuts off the first and second transistors of other lines, including word lines WLn and WLn of other lines. Apply the ninth bias voltage V9.

[0117] By employing the writing method of this disclosure, a writing operation can be performed on the transistor to be written to in the memory cell of this disclosure. The writing voltage can be reduced to below 7V, the writing time can be shortened to the microsecond level, and the writing current can be controlled to below 0.1μA. This further verifies that in the memory cell of this disclosure, the transistor to be stored can undergo hot carrier injection using the writing method of this disclosure to reduce the writing voltage and increase the writing speed.

[0118] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A storage unit, characterized in that, include: A first tube and a second tube, the first tube and the second tube comprising: The first gate structure and the second gate structure are located on the substrate, spaced apart and adjacent to each other; The first doped region and the second doped region are located in the substrate on both sides of the integral structure composed of the first gate structure and the second gate structure, respectively. The first doped region is located on one side of the first gate structure, and the second doped region is located on one side of the second gate structure. The third doped region is located within the substrate spaced between adjacent first and second gate structures; The first gate structure and the second gate structure each include a gate tunneling layer, a gate trapping layer and a gate blocking layer stacked sequentially on the substrate, and the doping concentration of the third doped region is lower than that of the first doped region and the second doped region.

2. The storage unit according to claim 1, characterized in that, The first gate structure and the second gate structure also include sidewalls located on both sides of the stacked structure of the gate tunneling layer, the gate trap layer and the gate blocking layer.

3. The storage unit according to claim 2, characterized in that, The gate sidewalls between the first and second transistors are in contact with each other and cover the third doped region.

4. A memory comprising a plurality of memory cells as described in any one of claims 1 to 3, wherein the plurality of memory cells are arranged in an array, characterized in that, Also includes: The first word line is used to electrically connect the first gate structure of the first transistor located in the same row; The second word line is used to electrically connect the second gate structure of the second transistor located in the same row; The first line is used to electrically connect the first doped regions of memory cells located in the same column; The second bit line is used to electrically connect the second doped regions of memory cells located in the same column; Base connection wires are used to electrically connect the base of the memory cells.

5. The memory according to claim 4, characterized in that, The memory also includes a charge pump for applying bias voltage to the substrate contact line, the first word line, the second word line, the first bit line, and the second bit line.

6. The memory according to claim 5, characterized in that, The charge pump includes a single charge pump used to apply a positive bias voltage.

7. The memory according to claim 5, characterized in that, The charge pump includes a dual charge pump, which is used to apply a forward bias and a reverse bias.

8. A method for writing to a memory as described in any one of claims 4 to 7, comprising: Select the tube to be written to, and designate another tube in the same memory unit as the tube to be written to as the non-written tube; A first bias voltage is applied to the word line where the non-write transistor is located to turn on the non-write transistor. A second bias voltage is applied to the word line where the write transistor is located so that the carriers enter the gate trap layer of the write transistor by hot carrier injection. At the same time, a bias voltage difference is formed between the selected first bit line and the second bit line on the row, and no bias voltage difference is formed between the unselected first bit line and the second bit line on the row.

9. The writing method according to claim 8, characterized in that, The first bias voltage is greater than the threshold bias voltage of the non-write tube, but less than the second bias voltage.

10. The writing method according to claim 8, characterized in that, The first and second transistors located in the same memory cell cannot be used as write transistors at the same time.

11. The writing method according to claim 8, characterized in that, Each write operation involves one or more rows of data to be written to the specified write tube.

12. The writing method according to claim 11, characterized in that, The rows to be written are multiple rows, and any two tubes to be written on these multiple rows do not belong to the same storage unit.

13. A method for erasing a memory as described in any one of claims 4 to 7, comprising: Select the tube to be erased; A bias voltage difference is formed between the gate and the substrate of the transistor to be erased, while no bias voltage difference is formed between the gate and the substrate of the non-transistor corresponding to the transistor to be erased.

14. The erasure method according to claim 13, characterized in that, The tubes to be erased include multiple tubes, which can be arranged in one or more rows.

15. The erasure method according to claim 13, characterized in that, The tube to be erased comprises multiple rows of tubes, and the multiple rows include multiple adjacent rows.

16. The erasure method according to claim 13, characterized in that, The transistors located in the same memory cell as the transistor to be erased are considered as non-erasable transistors, and no bias voltage difference is formed between the gate and the substrate of the non-erasable transistor corresponding to the transistor to be erased.

17. A method for reading from a memory as described in any one of claims 4 to 7, comprising: Select the tube to be read, and the other tube in the same storage unit of the tube to be read is not the tube to be read; Ground the word line where the transistor to be read is located, apply a fourth bias voltage to the word line where the non-transistor to be read is located corresponding to the transistor to be read in order to turn on the non-transistor to be read, and form a bias voltage between the bit line of the non-transistor to be read and the bit line where the corresponding transistor to be read is located. The current of the transistor to be read is read to determine its storage status.

18. The reading method according to claim 17, characterized in that, Each read operation involves either a single read tube or multiple read tubes in the same row.

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