Storage circuit and electronic device
By designing a 2T0C-structured storage circuit and utilizing level control of the write and read units, the crosstalk problem of the DRAM storage module is solved, improving the accuracy and integration of data reading and reducing the use of capacitors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TSINGHUA UNIVERSITY
- Filing Date
- 2026-06-05
- Publication Date
- 2026-07-14
AI Technical Summary
Existing DRAM memory modules suffer from crosstalk issues, leading to data read errors. Furthermore, the large capacitor area and leakage problems affect data retention time.
The storage circuit adopts a 2T0C structure. Through the design of the write unit and the read unit, the write unit responds to the write word line level to store data to the read unit during the data writing stage, and reads data through the read bit line during the read stage. At the same time, it prevents the read bit line from charging the read word line at an appropriate level to avoid crosstalk.
This effectively avoids crosstalk between storage modules, improves the accuracy of data reading, reduces the use of capacitors, and enhances integration and read speed.
Smart Images
Figure CN122392592A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit technology, and more particularly to a memory circuit and electronic device. Background Technology
[0002] Dynamic random access memory (DRAM) is the most common type of system memory, comprising multiple DRAM modules. Traditional 1T1C (one-transistor one-capacitor) DRAM modules use capacitors to store data, controlling data writing to and reading from the capacitors via switches. Capacitors are prone to leakage, resulting in a relatively short data retention time for 1T1C DRAM modules. The capacitors must be recharged periodically to prevent data loss. Furthermore, the relatively large size of the capacitors imposes significant limitations on circuit dimensions.
[0003] Because the presence of capacitors introduces many drawbacks to DRAM memory modules, existing technologies have proposed 2T0C (two-transistor zero-capacitor) DRAM memory modules that require only two transistors and no capacitors, using the transistor gate as the storage node to store data. However, DRAM memory modules are typically distributed in an array. When reading data stored in a target 2T0C DRAM memory module, crosstalk from other 2T0C DRAM memory modules may cause errors in the data read from the target 2T0C DRAM memory module. Summary of the Invention
[0004] In view of this, the present disclosure proposes a storage circuit and electronic device. This storage circuit can avoid crosstalk between storage modules and improve the accuracy of data read from each storage module.
[0005] According to one aspect of this disclosure, a storage circuit is provided, comprising a plurality of storage modules distributed in an array, wherein the storage module in the i-th row and j-th column includes a write unit and a read unit, where i and j are positive integers; a first end of the write unit is connected to the i-th write word line, a second end is connected to the j-th write bit line, and a third end is connected to the first end of the read unit; a second end of the read unit is connected to the i-th read word line, and a third end is connected to the j-th read bit line; the write unit is configured to, during the data writing phase, in response to the active level of the i-th write word line, store the data written by the j-th write bit line to the read unit; the read unit is configured to, during the data reading phase, in response to the active level of the i-th read word line, read the stored data through the j-th read bit line; the read unit is further configured to, when the read word line connected to the storage circuit is active high, prevent the j-th read bit line from charging the i-th read word line; and when the read word line connected to the storage circuit is active low, prevent the i-th read word line from charging the j-th read bit line.
[0006] In one possible implementation, the write unit includes a write transistor, and the read unit includes a read transistor and a diode. The first terminal of the write transistor serves as the first terminal of the write unit and is connected to the i-th write word line, the second terminal serves as the second terminal of the write unit and is connected to the j-th write bit line, and the third terminal serves as the third terminal of the write unit and is connected to the first terminal of the read unit. Similarly, the first terminal of the read transistor serves as the first terminal of the read unit and is connected to the third terminal of the write unit, the second terminal serves as the second terminal of the read unit and is connected to the i-th read word line, the third terminal is connected to the first terminal of the diode, and the second terminal of the diode serves as the third terminal of the read unit and is connected to the j-th read bit line.
[0007] In one possible implementation, the write unit includes a write transistor, and the read unit includes a read transistor and a diode. The first terminal of the write transistor serves as the first terminal of the write unit and is connected to the i-th write word line, the second terminal serves as the second terminal of the write unit and is connected to the j-th write bit line, and the third terminal serves as the third terminal of the write unit and is connected to the first terminal of the read unit. The first terminal of the read transistor serves as the first terminal of the read unit and is connected to the third terminal of the write unit, the second terminal is connected to the second terminal of the diode, the third terminal serves as the third terminal of the read unit and is connected to the j-th read bit line, and the first terminal of the diode serves as the second terminal of the read unit and is connected to the i-th read word line.
[0008] In one possible implementation, the first end of the diode is the anode, the second end of the diode is the cathode, the i-th write word line is active high, the i-th read word line is active high, and during the data readout phase, before the level of the i-th read word line changes to high, the j-th read bit line is low and in a high-impedance state.
[0009] In one possible implementation, the write transistor is an N-type transistor, the read transistor is an N-type transistor, and during the data readout phase, when the level of the i-th read word line is active and the stored data is high, the second and third terminals of the read transistor are turned on, the anode of the diode is high and the cathode is low, causing the diode to conduct, and the j-th read bit line reads a high level; when the stored data is low, the second and third terminals of the read transistor are disconnected, and the j-th read bit line reads a low level.
[0010] In one possible implementation, the write transistor is an N-type transistor and the read transistor is a P-type transistor. During the data readout phase, when the level of the i-th read word line is active and the stored data is low, the second and third terminals of the read transistor are turned on, the anode of the diode is high and the cathode is low, causing the diode to conduct, and the j-th read bit line reads a high level. When the stored data is high, the second and third terminals of the read transistor are disconnected, and the j-th read bit line reads a low level.
[0011] In one possible implementation, the first end of the diode is the cathode, the second end of the diode is the anode, the i-th write word line is active high, the i-th read word line is active low, and during the data readout phase, before the level of the i-th read word line changes to high, the j-th read bit line is high and in a high-impedance state.
[0012] In one possible implementation, the write transistor is an N-type transistor, the read transistor is an N-type transistor, and during the data readout phase, when the level of the i-th read word line is active and the stored data is high, the second and third terminals of the read transistor are turned on, the anode of the diode is high and the cathode is low, causing the diode to conduct, and the j-th read bit line reads a low level; when the stored data is low, the second and third terminals of the read transistor are disconnected, and the j-th read bit line reads a high level.
[0013] In one possible implementation, the write transistor is an N-type transistor and the read transistor is a P-type transistor. During the data readout phase, when the level of the i-th read word line is active and the stored data is low, the second and third terminals of the read transistor are turned on, the anode of the diode is high and the cathode is low, causing the diode to conduct, and the j-th read bit line reads a low level. When the stored data is high, the second and third terminals of the read transistor are disconnected, and the j-th read bit line reads a high level.
[0014] According to another aspect of this disclosure, an electronic device is provided, including the storage circuit described above.
[0015] According to the storage circuit of this disclosure embodiment, the storage module in the i-th row and j-th column includes a write unit and a read unit. The first end of the write unit is connected to the i-th write word line, the second end is connected to the j-th write bit line, and the third end is connected to the first end of the read unit. The second end of the read unit is connected to the i-th read word line, and the third end is connected to the j-th read bit line. Therefore, the storage modules are distributed in an array in the storage circuit. The write unit is used to, during the data writing phase, in response to the active level of the i-th write word line, store the data written by the j-th write bit line to the read unit. The read unit is used to... During the data readout phase, in response to the active level of the i-th read word line, the stored data is read out through the j-th read bit line, enabling the storage module to have data read / write functions. The readout unit is also used to prevent the j-th read bit line from charging the i-th read word line when the read word line connected to the storage circuit is active high, and to prevent the i-th read word line from charging the j-th read bit line when the read word line connected to the storage circuit is active low. This ensures that each storage module will not cause crosstalk to other modules during the data readout phase of other modules, thereby improving the accuracy of the data read out by each storage module.
[0016] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0017] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.
[0018] Figure 1a A schematic diagram showing the structure of a prior art 1T1C DRAM memory module is provided.
[0019] Figure 1b A schematic diagram showing the structure of a prior art 2T0C DRAM memory module.
[0020] Figure 2aThis diagram illustrates crosstalk occurring between existing 2T0C-DRAM memory modules.
[0021] Figure 2b This diagram illustrates crosstalk occurring between existing 2T0C-DRAM memory modules.
[0022] Figure 3 An exemplary application scenario of a storage circuit according to an embodiment of this disclosure is shown.
[0023] Figure 4 A schematic diagram showing the structure of a storage circuit according to an embodiment of the present disclosure is provided.
[0024] Figure 5 A schematic diagram showing the structure of the write unit and the read unit according to an embodiment of the present disclosure is provided.
[0025] Figure 6 A schematic diagram showing the structure of the write unit and the read unit according to an embodiment of the present disclosure is provided.
[0026] Figure 7 A schematic diagram showing the structure of a storage circuit according to an embodiment of the present disclosure is provided.
[0027] Figure 8 A schematic diagram showing the structure of a storage circuit according to an embodiment of the present disclosure is provided.
[0028] Figure 9 A schematic diagram showing the structure of a storage circuit according to an embodiment of the present disclosure is provided.
[0029] Figure 10 A schematic diagram showing the structure of a storage circuit according to an embodiment of the present disclosure is provided. Detailed Implementation
[0030] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.
[0031] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.
[0032] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.
[0033] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.
[0034] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.
[0035] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.
[0036] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.
[0037] Figure 1a A schematic diagram showing the structure of a prior art 1T1C DRAM memory module is provided.
[0038] like Figure 1a As shown, the 1T1C DRAM memory module consists of a write transistor and a storage capacitor. The drain of the write transistor is connected to one plate of the storage capacitor, and the other plate of the storage capacitor is grounded. The gate level of the write transistor is adjusted by the word line WL to control the conduction of the source and drain of the write transistor, writing the data connected to the bit line BL at the source into the storage capacitor.
[0039] However, existing processes make it difficult to further reduce the area of the storage capacitor while maintaining stability, which limits the area of the 1T1C DRAM memory module. Furthermore, due to the high off-state current characteristic of silicon-based transistors, the 1T1C DRAM memory module must be periodically refreshed to ensure the accuracy of the stored data, which restricts improvements in speed, power consumption, and other performance aspects.
[0040] Figure 1b A schematic diagram showing the structure of a prior art 2T0C DRAM memory module.
[0041] like Figure 1b As shown, the existing 2T0C DRAM memory module includes a write transistor T. w and read transistor T r Write transistor T w The gate is connected to the write word line WWL, the source is connected to the write bit line WBL, and the drain is connected to the read transistor T. r The gate connection is established, and the connection point SN serves as the storage node of the memory module; the read transistor T... r The source is connected to the read word line RWL, and the drain is connected to the read bit line RBL.
[0042] like Figure 1b As shown, with the write transistor T w and read transistor T r Taking N-type transistors as an example, the storage principle of a 2T0C DRAM memory module is as follows: During the data writing phase, the level of the write bit line WBL is controlled according to the data to be stored, and then the level of the write word line WWL is controlled to make the source and drain of the write transistor conduct, writing the data to be stored into the memory node SN. During the data reading phase, the read bit line RBL is controlled to be high and in a high-impedance state, and the read word line RWL is controlled to be low. If the data stored in the memory node is 1, the source and drain of the read transistor conduct, and the read bit line RBL discharges through the read word line RWL, causing the read bit line RBL to read low-level data. If the data stored in the memory node is 0, the source and drain of the read transistor are disconnected, and the read bit line RBL reads high-level data. The data read by the read bit line, after being inverted, is the same as the data stored in the memory node SN.
[0043] Write transistor T w For N-type transistors, read transistor T r Taking a P-type transistor as an example, the storage principle of a 2T0C DRAM memory module is as follows: During the data writing phase, the level of the write bit line WBL is controlled according to the data to be stored, and then the level of the write word line WWL is controlled to turn on the source and drain of the write transistor, writing the data to be stored into the memory node SN. During the data reading phase, the read bit line RBL is controlled to be low and in a high-impedance state, and then the read word line RWL is controlled to be high. If the data stored in the memory node is 0, the source and drain of the read transistor are turned on, the read word line RWL charges the read bit line RBL, causing the read bit line RBL to read high-level data. If the data stored in the memory node is 1, the source and drain of the read transistor are disconnected, and the read bit line RBL reads low-level data. The data read by the read bit line, after being inverted, is the same as the data stored in the memory node SN.
[0044] Figure 2a and Figure 2b This diagram illustrates crosstalk occurring between existing 2T0C-DRAM memory modules.
[0045] like Figure 2a and Figure 2b As shown, write word line WWL1 connects to the gates of the write transistors in memory modules 1 and 2, and write word line WWL2 connects to the gates of the write transistors in memory modules 3 and 4. Write bit line WBL1 connects to the sources of the write transistors in memory modules 1 and 3, and write bit line WBL2 connects to the sources of the write transistors in memory modules 2 and 4. Read word line RWL1 connects to the sources of the read transistors in memory modules 1 and 2, and read word line RWL2 connects to the sources of the read transistors in memory modules 3 and 4. Read bit line RBL1 connects to the drains of the read transistors in memory modules 1 and 3, and read bit line RBL2 connects to the drains of the read transistors in memory modules 2 and 4.
[0046] like Figure 2a As shown, both the write transistor and the read transistor are N-type transistors, and the read word line is active low. Storage node SN1 of storage module 1 stores data 1, storage node SN2 of storage module 2 stores data 0, storage node SN3 of storage module 3 stores data 1, and storage node SN4 of storage module 4 stores data 1.
[0047] To read the data stored in memory module 2, the read bit line RBL2 needs to be controlled to a high level and in a high-impedance state, while the read word line RWL1 needs to be controlled to a low level. Since memory node SN2 stores 0 data, the source and drain of the read transistor in memory module 2 are disconnected, preventing read bit line RBL2 from charging read word line RWL1 through memory module 2. If crosstalk from other memory modules is not considered, read bit line RBL1 will read a high level.
[0048] However, since the data stored in storage nodes SN1, SN3, and SN4 is all 1, the drain and source of the read transistors in storage modules 1, 3, and 4 are all turned on. Read bit line RBL2 can be charged sequentially through the read transistors of storage module 4, read word line RWL2, storage module 3, read bit line RBL1, and storage module 1. Because read bit line RBL2 is in a high-impedance state, the charging operation causes the level of read bit line RBL2 to gradually decrease, eventually resulting in a low level read from read bit line RBL2. In other words, crosstalk between storage modules 1, 3, and 4 causes read bit line RBL2 to read incorrectly.
[0049] like Figure 2bAs shown, the write transistor is an N-type transistor, the read transistor is a P-type transistor, and the read word line is active high. Storage node SN1 of storage module 1 stores 0 data, storage node SN2 of storage module 2 stores 1 data, storage node SN3 of storage module 3 stores 0 data, and storage node SN4 of storage module 4 stores 0 data.
[0050] To read the data stored in memory module 2, the read bit line RBL2 needs to be controlled to a low level and in a high-impedance state, while the read word line RWL1 needs to be controlled to a high level. Since memory node SN2 stores a value of 1, the source and drain of the read transistor in memory module 2 are disconnected, preventing the read word line RWL1 from charging the read bit line RBL2 through memory module 2. If crosstalk from other memory modules is not considered, the read bit line RBL1 will read a low level.
[0051] However, since the data stored in storage nodes SN1, SN3, and SN4 is all 0, the drain and source of the read transistors in storage modules 1, 3, and 4 are all turned on. Read word line RWL1 can sequentially charge read bit line RBL2 through the read transistors of storage modules 1, 3, and 4. Because read bit line RBL2 is in a high-impedance state, the charging operation causes the level of read bit line RBL2 to gradually increase, eventually resulting in a high-level read. In other words, crosstalk between storage modules 1, 3, and 4 causes read bit line RBL2 to read incorrectly.
[0052] In summary, regardless of whether the read word line is active high or low, crosstalk exists between storage modules, causing errors in the data read by the storage modules.
[0053] In view of this, the present disclosure proposes a storage circuit and electronic device. This storage circuit can avoid crosstalk between storage modules and improve the accuracy of data read from each storage module.
[0054] Figure 3 An exemplary application scenario of a storage circuit according to an embodiment of this disclosure is shown.
[0055] like Figure 3 As shown, the storage circuit of this embodiment can be disposed in an electronic device. The storage circuit may include storage module 1-storage module 4.
[0056] Electronic devices may also include a processor, bit line driver circuits, and word line driver circuits. The bit line driver circuits are used to control the levels of write bit lines WBL1, WBL2 and read bit lines RBL1, RBL2, and the word line driver circuits are used to control the levels of write word lines WWL1, WWL2 and read word lines RWL1, RWL2.
[0057] When the processor selects a specific memory module in the memory circuit as the object to write or read data, it can output the address code corresponding to that memory module to the bit line driver circuit and word line driver circuit.
[0058] If the storage module is the object to be written, the processor can output the data to be stored to the bit line drive circuit. The processor controls the word line drive circuit to adjust the level of the write word line connected to the storage module corresponding to the address code, and controls the bit line drive circuit to adjust the level of the write bit line connected to the storage module corresponding to the address code, so as to write the data to the storage module through the write bit line.
[0059] If the storage module is the object to be read, the processor can control the word line drive circuit to adjust the level of the write word line and read word line connected to the storage module corresponding to the address code, and read the data stored in the storage module through the read bit line connected to the storage module.
[0060] Those skilled in the art will understand that the storage circuit may also include more storage modules, and the number of rows and columns of the storage modules can be set according to the application scenario requirements. The bit line driver circuit and the word line driver circuit can be selected as static logic or dynamic logic, and the number of bit lines that the bit line driver circuit can control and the number of word lines that the word line driver circuit can control can be adaptively adjusted according to the number of columns and rows of the storage module.
[0061] Those skilled in the art will understand that electronic devices may also include more circuits, such as control circuits. When an electronic device includes control circuits, the processor can control the bit line drive circuits and word line drive circuits through the control circuits. This disclosure does not limit the specific structure of the electronic device.
[0062] The exemplary structure of the storage circuit according to embodiments of the present disclosure, as well as the function of the storage circuit according to embodiments of the present disclosure, are described below.
[0063] In one possible implementation, the storage circuit includes multiple storage modules distributed in an array, wherein the storage module in the i-th row and j-th column includes a write unit and a read unit, where i and j are positive integers;
[0064] The first end of the write unit is connected to the i-th write word line, the second end is connected to the j-th write bit line, and the third end is connected to the first end of the read unit; the second end of the read unit is connected to the i-th read word line, and the third end is connected to the j-th read bit line.
[0065] The write unit is used to, during the data write phase, in response to the active level of the i-th write word line, store the data written by the j-th write bit line to the read unit;
[0066] The readout unit is used to read the stored data through the j-th read bit line in response to the active level of the i-th read word line during the data readout phase.
[0067] The readout unit is also used to prevent the j-th read bit line from charging the i-th read bit line when the read word line connected to the storage circuit is active high; and to prevent the i-th read word line from charging the j-th read bit line when the read word line connected to the storage circuit is active low.
[0068] Figure 4 A schematic diagram showing the structure of a storage circuit according to an embodiment of the present disclosure is provided.
[0069] like Figure 4 As shown, the storage circuit may include four storage modules arranged in a 2x2 array. Storage module 1 is in the 1st row and 1st column, storage module 2 is in the 1st row and 2nd column, storage module 3 is in the 2nd row and 1st column, and storage module 4 is in the 2nd row and 2nd column. WWL1 is the first write word line, WWL2 is the second write word line, RWL1 is the first read word line, and RWL2 is the second read word line. WBL1 is the first write bit line, WBL2 is the second write bit line, RBL1 is the first read bit line, and RBL2 is the second read bit line.
[0070] like Figure 4 As shown, storage module 1 may include a write unit 10 and a read unit 11. Storage module 1 is the storage module in the first row and first column (i=1, j=1). Therefore, the first end w11 of the write unit 10 is connected to the first (i=1) write word line WWL1, the second end w12 is connected to the first (j=1) write bit line WBL1, and the third end w13 is connected to the first end r11 of the read unit 11. The second end r12 of the read unit 11 is connected to the first (i=1) read word line RWL1, and the third end r13 is connected to the first (j=1) read bit line RBL1. The first end r11 of the read unit 11 is also the storage node SN1 of storage module 1.
[0071] Storage module 2 may include a write unit 20 and a read unit 21. Storage module 2 is the storage module in the first row and second column (i=1, j=2). Therefore, the first end w21 of the write unit 20 is connected to the first (i=1) write word line WWL1, the second end w22 is connected to the second (j=2) write bit line WBL2, and the third end w23 is connected to the first end r21 of the read unit 21. The second end r22 of the read unit 21 is connected to the first (i=1) read word line RWL1, and the third end r23 is connected to the second (j=2) read bit line RBL2. The first end r21 of the read unit 21 is also the storage node SN2 of storage module 2.
[0072] Storage module 3 may include a write unit 30 and a read unit 31. Storage module 3 is the storage module in the 2nd row and 1st column (i=2, j=1). Therefore, the first end w31 of the write unit 30 is connected to the second (i=2) write word line WWL2, the second end w32 is connected to the first (j=1) write bit line WBL1, and the third end w33 is connected to the first end r31 of the read unit 31. The second end r32 of the read unit 31 is connected to the second (i=2) read word line RWL2, and the third end r33 is connected to the first (j=1) read bit line RBL1. The first end r31 of the read unit 31 is also the storage node SN3 of storage module 3.
[0073] Storage module 4 may include a write unit 40 and a read unit 41. Storage module 4 is the storage module in the 2nd row and 2nd column (i=2, j=2). Therefore, the first end w41 of the write unit 40 is connected to the 2nd (i=2) write word line WWL2, the second end w42 is connected to the 2nd (j=2) write bit line WBL2, and the third end w43 is connected to the first end r41 of the read unit 41. The second end r42 of the read unit 41 is connected to the 2nd (i=2) read word line RWL2, and the third end r43 is connected to the 2nd (j=2) read bit line RBL2. The first end r41 of the read unit 41 is also the storage node SN4 of storage module 4.
[0074] The write and read units in each storage module have the same function. Taking storage module 2 as an example, when the write word line WWL1 is active, the second terminal w22 and the third terminal w23 of the write unit 20 are turned on. Therefore, during the data writing phase, the write unit 20 can, in response to the active level of the write word line WWL1, store the data written by the write bit line WBL2 to the read unit 21. Exemplarily, it can be stored at the first terminal r21 of the read unit 21. Details of the level changes of each word line and bit line during the data writing phase are given later. The bit lines remain on during data writing.
[0075] Taking storage module 2 as an example, during the data readout stage, the readout unit 21 can determine whether the second terminal r22 and the third terminal r23 of the readout unit 21 are conducting based on the levels of the first terminal r21, the second terminal r22, and the third terminal r23. After the level of the read word line RWL1 is valid, the data read through the read bit line RBL2 can represent the stored data. The details of the level changes of each word line and bit line during the data readout stage are given later.
[0076] Taking storage module 3 as an example, the read unit 31 can also be used to prevent the read bit line RBL1 from charging the read word line RWL2 through the read unit 31 when the read word line (including RWL1-RWL2) connected to the storage circuit is active at a high level.
[0077] See Figure 2bAssuming that the storage module 3 of this embodiment is used instead of... Figure 2b The storage module 3 shown is the storage module from which data needs to be read. Figure 2b The storage module 2 is shown. The read unit of the storage module 3 can prevent the read bit line RBL1 from charging the read word line RWL2 through the read unit 31. In this case, the charging path from the read word line RWL1 to the read bit line RBL2 is broken, and the read bit line RBL2 can accurately output a low level.
[0078] Taking storage module 3 as an example, the read unit 31 can also be used to prevent the read word line RWL2 from charging the read bit line RBL1 through the read unit 31 when the read word line (including RWL1-RWL2) connected to the storage circuit is active at a low level.
[0079] See Figure 2a Assuming that the storage module 3 of this embodiment is used instead of... Figure 2a The storage module 3 shown is the storage module from which data needs to be read. Figure 2a The storage module 2 is shown. The read unit of the storage module 3 can prevent the read word line RWL2 from charging the read bit line RBL1 through the read unit 31. In this case, the charging path from the read bit line RBL2 to the read word line RWL1 is broken, and the read bit line RBL2 can accurately output a high level.
[0080] Those skilled in the art will understand that, in practical applications, the read unit's structural design and the level control of the read word lines and read bit lines connected to the read unit can be used to ensure that when the stored data is low, the read unit also reads a low level, and when the stored data is high, the read unit also reads a high level. Alternatively, the read unit can be configured to read a high level when the stored data is low, and read a low level when the stored data is high. Details of the read unit's structural design and the level control of the read word lines and read bit lines connected to the read unit will be provided later.
[0081] According to the storage circuit of this disclosure embodiment, the storage module in the i-th row and j-th column includes a write unit and a read unit. The first end of the write unit is connected to the i-th write word line, the second end is connected to the j-th write bit line, and the third end is connected to the first end of the read unit. The second end of the read unit is connected to the i-th read word line, and the third end is connected to the j-th read bit line. Therefore, the storage modules are distributed in an array in the storage circuit. The write unit is used to, during the data writing phase, in response to the active level of the i-th write word line, store the data written by the j-th write bit line to the read unit. The read unit is used to... During the data readout phase, in response to the active level of the i-th read word line, the stored data is read out through the j-th read bit line, enabling the storage module to have data read / write functions. The readout unit is also used to prevent the j-th read bit line from charging the i-th read word line when the read word line connected to the storage circuit is active high, and to prevent the i-th read word line from charging the j-th read bit line when the read word line connected to the storage circuit is active low. This ensures that each storage module will not cause crosstalk to other modules during the data readout phase of other modules, thereby improving the accuracy of the data read out by each storage module.
[0082] The exemplary structures of the writing unit and reading unit according to embodiments of this disclosure are described below.
[0083] In one possible implementation, the write unit includes a write transistor, and the read unit includes a read transistor and a diode.
[0084] The first terminal of the write transistor is connected to the i-th write word line as the first terminal of the write unit, the second terminal is connected to the j-th write bit line as the second terminal of the write unit, and the third terminal is connected to the first terminal of the read unit as the third terminal of the write unit.
[0085] The first terminal of the read transistor is connected to the third terminal of the write unit as the first terminal of the read unit, the second terminal is connected to the i-th read word line as the second terminal of the read unit, the third terminal is connected to the first terminal of the diode, and the second terminal of the diode is connected to the j-th read bit line as the third terminal of the read unit.
[0086] Figure 5 A schematic diagram showing the structure of the write unit and the read unit according to an embodiment of the present disclosure is provided.
[0087] like Figure 5 As shown, taking storage module 3 as an example, the write unit 30 may include a write transistor T. W3 Write transistor T W3The first terminal of the write unit 30, w31, is connected to the write word line WWL2. The second terminal of the write unit 30, w32, is connected to the write bit line WBL1. The third terminal of the write unit 30, w33, is connected to the first terminal r31 of the read unit 31. Therefore, when the level of the write word line WWL2 is active, the second terminal (w32) and the third terminal (w33) of the write transistor can be turned on, thereby storing the data written by the write bit line WBL1 connected to the second terminal (w32) to the first terminal r31 of the read unit 31 connected to the third terminal (w33).
[0088] The readout unit 31 may include a read transistor T r3 And diode D3. Read transistor T. r3 The first terminal r31 of the read unit 31 is connected to the third terminal w33 of the write unit 30. The second terminal r32 of the read unit 31 is connected to the read word line RWL2. The third terminal is connected to the first terminal d31 of the diode D3. Therefore, the level of the stored data will determine the level of the read transistor T. r3 Whether the second and third terminals are conducting determines the voltage level of the first terminal d31 of diode D3.
[0089] The first terminal of the write transistor and the read transistor can be the gate, the second terminal can be the source (or drain), and the third terminal can be the drain (or source). This disclosure does not limit the specific types of the second and third terminals of the transistors.
[0090] The second terminal d32 of diode D3 is connected to the read bit line RBL1 as the third terminal r33 of read unit 31. Therefore, as long as the first terminal d31 and the second terminal d32 of diode D3 are disconnected, even if the second and third terminals of the read transistor are conducting, the diode can prevent read bit line RBL1 from charging read word line RWL2, or prevent read word line RWL2 from charging read bit line RBL1.
[0091] In one possible implementation, the write unit includes a write transistor, and the read unit includes a read transistor and a diode.
[0092] The first terminal of the write transistor is connected to the i-th write word line as the first terminal of the write unit, the second terminal is connected to the j-th write bit line as the second terminal of the write unit, and the third terminal is connected to the first terminal of the read unit as the third terminal of the write unit.
[0093] The first terminal of the read transistor is connected to the third terminal of the write unit as the first terminal of the read unit, the second terminal is connected to the second terminal of the diode, the third terminal is connected to the j-th read bit line as the third terminal of the read unit, and the first terminal of the diode is connected to the i-th read word line as the second terminal of the read unit.
[0094] Figure 6A schematic diagram showing the structure of the write unit and the read unit according to an embodiment of the present disclosure is provided.
[0095] like Figure 6 As shown, taking storage module 3 as an example, the structure of read unit 31 can also be designed with read transistor T. r3 The first terminal of the read unit 31 (r31) is connected to the third terminal (w33) of the write unit 30. The second terminal is connected to the second terminal (d32) of the diode D3. The third terminal of the read unit 31 (r33) is connected to the read bit line RBL1. The first terminal (d31) of the diode D3 is connected to the second terminal (r32) of the read unit 31, which is connected to the read word line RWL2. When the first terminal (d31) and the second terminal (d32) of the diode D3 are disconnected, even with the second and third terminals of the read transistor conducting, it can prevent the read bit line RBL1 from charging the read word line RWL2, or prevent the read word line RWL2 from charging the read bit line RBL1.
[0096] In this configuration, the memory module retains the advantages of the 2T0C structure, avoiding additional capacitor manufacturing processes and improving integration. No write transistors are needed during read operations, preventing data corruption and resulting in high read speeds.
[0097] In this embodiment of the disclosure, the write transistor can be an N-type transistor, and the read transistor can be either an N-type transistor or a P-type transistor. This embodiment of the disclosure does not limit the specific type of the read transistor.
[0098] The polarity of the first and second terminals of the diode can be set according to the effective level of the read line connected to the storage circuit. An exemplary method for setting the diode polarity and the effective level of the read line connected to the storage circuit is described below.
[0099] In one possible implementation, the first terminal of the diode is the anode, and the second terminal is the cathode.
[0100] The i-th write word line is active high, the i-th read word line is active high, and during the data readout phase, before the level of the i-th read word line changes to high, the j-th read bit line is low and in a high-impedance state.
[0101] For example, with Figure 5 For example, writing transistor T w3 It is an N-type transistor, therefore the write word line WWL2 is active high. If the read word line RWL2 is active high, then during the data readout phase, before the level of the read word line RWL2 changes to high, the read bit line RBL1 can be low and in a high-impedance state.
[0102] See Figure 2bAccording to the relevant description, when the read word line is active high, the read word line RWL1 can charge the read bit line RBL2 in sequence through the read transistor of storage module 1, the read bit line RBL1, the read transistor of storage module 3, the read word line RWL2, and the read transistor of storage module 4. Therefore, preventing the read bit line RBL1 from charging the read word line RWL2 through the read transistor of storage module 3 can avoid crosstalk problems.
[0103] The charging of read bit line RBL1 to read word line RWL2 indicates that read bit line RBL1 is at a high level and read word line RWL2 is at a low level. Therefore, the first terminal d31 of the diode can be the anode and the second terminal d32 of the diode can be the cathode. In this case, when read bit line RBL1 is at a high level and read word line RWL2 is at a low level, the cathode of the diode is at a high level. Regardless of whether the anode of the diode is at a high or low level, the anode and cathode of the diode are disconnected, preventing read bit line RBL1 from charging read word line RWL2 through the read transistor of storage module 3.
[0104] The following describes an exemplary data readout process for the readout unit when the read word line is active high and the read transistor is an N-type transistor.
[0105] In one possible implementation, both the write transistor and the read transistor are N-type transistors. During the data readout phase, when the level of the i-th read word line is active...
[0106] When the stored data is at a high level, the second and third terminals of the read transistor are turned on, the anode of the diode is at a high level and the cathode is at a low level, causing the diode to conduct, and the j-th read bit line reads a high level;
[0107] When the stored data is low, the second and third terminals of the read transistor are disconnected, and the j-th read bit line reads a low level.
[0108] Figure 7 A schematic diagram showing the structure of a storage circuit according to an embodiment of the present disclosure is provided.
[0109] like Figure 7 As shown, the read word line is active high, and both the write and read transistors are N-type transistors. Storage node SN1 of storage module 1 stores data 1, storage node SN2 of storage module 2 stores data 0, storage node SN3 of storage module 3 stores data 1, and storage node SN4 of storage module 4 stores data 1.
[0110] During the data readout phase of storage modules 1 / 3 / 4, since the stored data is at a high level (1), the second and third terminals of the read transistor are turned on. Because the read word line is active high, the anode of the diode is at a high level. The cathode of the diode is at a low level, therefore the diode is turned on, and the read bit line reads a high level.
[0111] During the data readout phase of storage module 2, since the stored data is at a low level (0), the second and third terminals of the read transistor are disconnected, and the read word line RWL1 cannot charge the read bit line RBL2 through the read transistor and diode of storage module 2. Because the diode in storage module 3 prevents the read bit line RBL1 from charging the read word line RWL2, the read word line RWL1 also cannot charge the read bit line RBL2 through other storage modules or word lines and bit lines connected to other storage modules. Under these circumstances, the read bit line RBL2 can be read as a low level.
[0112] The following describes an exemplary data readout process for the readout unit when the read word line is active high and the read transistor is a P-type transistor.
[0113] In one possible implementation, the write transistor is an N-type transistor, and the read transistor is a P-type transistor. During the data readout phase, when the level of the i-th read word line is active...
[0114] When the stored data is at a low level, the second and third terminals of the read transistor are turned on, the anode of the diode is at a high level and the cathode is at a low level, causing the diode to conduct, and the j-th read bit line reads a high level;
[0115] When the stored data is at a high level, the second and third terminals of the read transistor are disconnected, and the j-th read bit line reads a low level.
[0116] Figure 8 A schematic diagram showing the structure of a storage circuit according to an embodiment of the present disclosure is provided.
[0117] like Figure 8 As shown, the read word line is active high, the write transistor is an N-type transistor, and the read transistor is a P-type transistor. Storage node SN1 of storage module 1 stores 0 data, storage node SN2 of storage module 2 stores 1 data, storage node SN3 of storage module 3 stores 0 data, and storage node SN4 of storage module 4 stores 0 data.
[0118] During the data readout phase of storage modules 1 / 3 / 4, since the stored data is at a low level (0), the second and third terminals of the read transistor are turned on. Because the read word line is active high, the anode of the diode is at a high level. The cathode of the diode is at a low level, therefore the diode is turned on, and the read bit line reads a high level.
[0119] During the data readout phase of storage module 2, since the stored data is at a high level (1), the second and third terminals of the read transistor are disconnected, and the read word line RWL1 cannot charge the read bit line RBL2 through the read transistor and diode of storage module 2. Because the diode in storage module 3 prevents the read bit line RBL1 from charging the read word line RWL2, the read word line RWL1 also cannot charge the read bit line RBL2 through other storage modules and word lines or bit lines connected to other storage modules. Under these circumstances, the read bit line RBL2 can be read as a low level.
[0120] In one possible implementation, the first terminal of the diode is the cathode, and the second terminal is the anode.
[0121] The i-th write word line is active high, and the i-th read word line is active low. During the data readout phase, before the level of the i-th read word line changes to high, the j-th read bit line is high and in a high-impedance state.
[0122] For example, with Figure 5 For example, writing transistor T w3 It is an N-type transistor, therefore the write word line WWL2 is active high. If the read word line RWL2 is active low, then during the data readout phase, before the level of the read word line RWL2 changes to low, the read bit line RBL1 can be high and in a high-impedance state.
[0123] See Figure 2a According to the relevant description, when the read word line is active low, the read bit line RBL1 can be charged sequentially through the read transistor of storage module 4, the read word line RWL2, the read transistor of storage module 3, the read bit line RBL1, and the read transistor of storage module 1. Therefore, preventing the read word line RWL2 from charging the read bit line RBL1 through the read transistor of storage module 3 can avoid crosstalk problems.
[0124] When the read word line RWL2 charges the read bit line RBL1, it indicates that read word line RWL2 is at a high level and read bit line RBL1 is at a low level. Therefore, the first terminal d31 of the diode can be the cathode, and the second terminal d32 of the diode can be the anode. In this case, when read word line RWL2 is at a high level and read bit line RBL1 is at a low level, the anode of the diode is at a low level. Regardless of whether the cathode of the diode is at a high or low level, the anode and cathode of the diode are disconnected, preventing read word line RWL2 from charging read bit line RBL1.
[0125] The following describes an exemplary data readout process for the readout unit when the read word line is active low and the read transistor is an N-type transistor.
[0126] In one possible implementation, both the write transistor and the read transistor are N-type transistors. During the data readout phase, when the level of the i-th read word line is active...
[0127] When the stored data is at a high level, the second and third terminals of the read transistor are turned on, the anode of the diode is at a high level and the cathode is at a low level, causing the diode to conduct, and the j-th read bit line reads a low level;
[0128] When the stored data is at a low level, the second and third terminals of the read transistor are disconnected, and the j-th read bit line reads a high level.
[0129] Figure 9 A schematic diagram showing the structure of a storage circuit according to an embodiment of the present disclosure is provided.
[0130] like Figure 9 As shown, the read word line is active low, the write transistor is an N-type transistor, and the read transistor is an N-type transistor. Storage node SN1 of storage module 1 stores data 1, storage node SN2 of storage module 2 stores data 0, storage node SN3 of storage module 3 stores data 1, and storage node SN4 of storage module 4 stores data 1.
[0131] During the data readout phase of storage modules 1 / 3 / 4, since the stored data is at a high level (1), the second and third terminals of the read transistor are turned on. Because the read word line is active low, the anode of the diode is at a low level. The cathode of the diode is at a high level, therefore the diode is turned on, and the read bit line reads a low level.
[0132] During the data readout phase of storage module 2, since the stored data is at a low level (0), the second and third terminals of the read transistor are disconnected, and the read bit line RBL2 cannot charge the read word line RWL1 through the read transistor and diode of storage module 2. Because the diode in storage module 3 prevents the read word line RWL2 from charging the read bit line RBL1, the read bit line RBL2 also cannot charge the read word line RWL1 through other storage modules or word lines and bit lines connected to other storage modules. Under these circumstances, the read bit line RBL2 can read a high level.
[0133] The following describes an exemplary data readout process for the readout unit when the read word line is active low and the read transistor is a P-type transistor.
[0134] In one possible implementation, the write transistor is an N-type transistor and the read transistor is a P-type transistor. During the data readout phase, when the level of the i-th read word line is active...
[0135] When the stored data is at a low level, the second and third terminals of the read transistor are turned on, the anode of the diode is at a high level and the cathode is at a low level, causing the diode to conduct, and the j-th read bit line reads a low level;
[0136] When the stored data is at a high level, the second and third terminals of the read transistor are disconnected, and the j-th read bit line reads a high level.
[0137] Figure 10 A schematic diagram showing the structure of a storage circuit according to an embodiment of the present disclosure is provided.
[0138] like Figure 10 As shown, the read word line is active low, the write transistor is an N-type transistor, and the read transistor is a P-type transistor. Storage node SN1 of storage module 1 stores 0 data, storage node SN2 of storage module 2 stores 1 data, storage node SN3 of storage module 3 stores 0 data, and storage node SN4 of storage module 4 stores 0 data.
[0139] During the data readout phase of storage modules 1 / 3 / 4, since the stored data is at a low level (0), the second and third terminals of the read transistor are turned on. Because the read word line is active low, the anode of the diode is at a low level. The cathode of the diode is at a high level, therefore the diode is turned on, and the read bit line reads a low level.
[0140] During the data readout phase of storage module 2, since the stored data is at a high level (1), the second and third terminals of the read transistor are disconnected, and the read bit line RBL2 cannot charge the read word line RWL1 through the read transistor and diode of storage module 2. Because the diode in storage module 3 prevents the read word line RWL2 from charging the read bit line RBL1, the read bit line RBL2 also cannot charge the read word line RWL1 through other storage modules and word lines or bit lines connected to other storage modules. Under these circumstances, the read bit line RBL2 can read a high level.
[0141] Furthermore, the channel material of the read transistor can be various materials such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, and oxide semiconductor. The diode needs to have unidirectional conductivity and can be of the PN junction diode, metal-semiconductor junction diode, or other types. This disclosure does not limit the selection of materials or processes for the read transistor and diode.
[0142] This disclosure also proposes an electronic device including the storage circuit described above. The electronic device may further include a processor, a bit line driving circuit, a word line driving circuit, etc. A schematic diagram of the electronic device can be found [link to schematic diagram]. Figure 3 .
[0143] The electronic device may be a terminal device or a server, and the specific type of electronic device is not limited in the embodiments of this disclosure.
[0144] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0145] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A storage circuit, characterized in that, It includes multiple storage modules distributed in an array. The storage module in the i-th row and j-th column includes a write unit and a read unit, where i and j are positive integers. The first end of the writing unit is connected to the i-th write word line, the second end is connected to the j-th write bit line, and the third end is connected to the first end of the reading unit; the second end of the reading unit is connected to the i-th read word line, and the third end is connected to the j-th read bit line. The writing unit is used to, during the data writing phase, in response to the active level of the i-th write word line, store the data written by the j-th write bit line to the reading unit; The readout unit is used to read out the stored data through the j-th read bit line in response to the active level of the i-th read word line during the data readout phase. The readout unit is further configured to, when the read word line connected to the storage circuit is active high, prevent the j-th read bit line from charging the i-th read word line; and when the read word line connected to the storage circuit is active low, prevent the i-th read word line from charging the j-th read bit line.
2. The storage circuit according to claim 1, characterized in that, The write unit includes a write transistor, and the read unit includes a read transistor and a diode. The first terminal of the write transistor is connected to the i-th write word line as the first end of the write unit, the second terminal is connected to the j-th write bit line as the second end of the write unit, and the third terminal is connected to the first end of the read unit as the third end of the write unit. The first terminal of the read transistor serves as the first terminal of the read unit and is connected to the third terminal of the write unit. The second terminal serves as the second terminal of the read unit and is connected to the i-th read word line. The third terminal is connected to the first terminal of the diode. The second terminal of the diode serves as the third terminal of the read unit and is connected to the j-th read bit line.
3. The storage circuit according to claim 1, characterized in that, The write unit includes a write transistor, and the read unit includes a read transistor and a diode. The first terminal of the write transistor is connected to the i-th write word line as the first end of the write unit, the second terminal is connected to the j-th write bit line as the second end of the write unit, and the third terminal is connected to the first end of the read unit as the third end of the write unit. The first terminal of the read transistor is connected to the third terminal of the write unit as the first terminal of the read unit, the second terminal is connected to the second terminal of the diode, the third terminal is connected to the j-th read bit line as the third terminal of the read unit, and the first terminal of the diode is connected to the i-th read word line as the second terminal of the read unit.
4. The storage circuit according to claim 2 or 3, characterized in that, The first terminal of the diode is the anode, and the second terminal of the diode is the cathode. The i-th write line is active high, the i-th read line is active high, and during the data reading phase, before the level of the i-th read line changes to high, the j-th read line is low and in a high-impedance state.
5. The storage circuit according to claim 4, characterized in that, The write transistor is an N-type transistor, the read transistor is an N-type transistor, and during the data readout phase, when the level of the i-th read word line is active... When the stored data is at a high level, the second and third terminals of the read transistor are turned on, the anode of the diode is at a high level and the cathode is at a low level, causing the diode to turn on, and the j-th read bit line reads a high level; When the stored data is at a low level, the second and third terminals of the read transistor are disconnected, and the j-th read bit line reads a low level.
6. The storage circuit according to claim 4, characterized in that, The write transistor is an N-type transistor, and the read transistor is a P-type transistor. During the data readout phase, when the level of the i-th read word line is active... When the stored data is at a low level, the second and third terminals of the read transistor are turned on, the anode of the diode is at a high level and the cathode is at a low level, causing the diode to conduct, and the j-th read bit line reads a high level; When the stored data is at a high level, the second and third terminals of the read transistor are disconnected, and the j-th read bit line reads a low level.
7. The storage circuit according to claim 2 or 3, characterized in that, The first terminal of the diode is the cathode, and the second terminal of the diode is the anode. The i-th write line is active high, the i-th read line is active low, and during the data reading phase, before the level of the i-th read line changes to high, the j-th read line is high and in a high-impedance state.
8. The storage circuit according to claim 7, characterized in that, The write transistor is an N-type transistor, the read transistor is an N-type transistor, and during the data readout phase, when the level of the i-th read word line is active... When the stored data is at a high level, the second and third terminals of the read transistor are turned on, the anode of the diode is at a high level and the cathode is at a low level, causing the diode to conduct, and the j-th read bit line reads a low level; When the stored data is at a low level, the second and third terminals of the read transistor are disconnected, and the j-th read bit line reads a high level.
9. The storage circuit according to claim 7, characterized in that, The write transistor is an N-type transistor, and the read transistor is a P-type transistor. During the data readout phase, when the level of the i-th read word line is active... When the stored data is at a low level, the second and third terminals of the read transistor are turned on, the anode of the diode is at a high level and the cathode is at a low level, causing the diode to turn on, and the j-th read bit line reads a low level; When the stored data is at a high level, the second and third terminals of the read transistor are disconnected, and the j-th read bit line reads a high level.
10. An electronic device, characterized in that, The storage circuit includes any one of claims 1-9.