Phase change memory and electronic device

Abstract

The embodiment of the present disclosure provides a phase change memory and an electronic device, the phase change memory comprises a plurality of memory chips, each memory chip comprises a first sub-array and a second sub-array; a memory chip control module configured to generate a write driving control signal in the process of a data write operation; a first array driver connected with the memory chip control module and the first sub-array, configured to receive and respond to the write driving control signal, and write first to-be-written data into the selected phase change memory unit in the first sub-array; a second array driver connected with the memory chip control module and the second sub-array, configured to receive and respond to the write driving control signal, and write second to-be-written data into the selected phase change memory unit in the second sub-array. In this way, the write bandwidth is increased, and the additional consumption of the chip area is greatly reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a phase-change memory and an electronic device. Background Technology

[0002] Phase-change memory (PCM) is a novel non-volatile memory technology. Its core principle is based on the reversible transition of phase-change materials between crystalline and amorphous states. PCM materials (such as chalcogenide alloys) exhibit significantly different electrical properties in different physical states: crystalline PCM materials exhibit low resistance, while amorphous PCM materials exhibit high resistance. Through this resistance difference, PCM cells can store binary data (0s and 1s).

[0003] It should be understood that the working mechanism of phase-change memory relies on electric current heating the material to different temperatures, thereby triggering the phase change process. With the continuous advancement of nanofabrication processes and materials science, PCM technology is gradually maturing and is expected to become a bridge connecting high-speed memory (such as dynamic random access memory DRAM) and large-capacity non-volatile memory (such as NAND flash memory), with wide applications in data centers, embedded systems, and artificial intelligence accelerators.

[0004] Although PCM exhibits significant advantages in non-volatility, read speed, and 3D stacking, it still has a clear bottleneck in write performance, which limits its widespread application in high-performance storage scenarios. Summary of the Invention

[0005] This disclosure provides a phase-change memory and an electronic device that enables parallel data writing to a memory tile, increasing write bandwidth while minimizing area overhead.

[0006] The technical solution of this disclosure embodiment is implemented as follows: In a first aspect, embodiments of this disclosure provide a phase-change memory, the phase-change memory including a plurality of memory chips, each memory chip including a first subarray and a second subarray, the first subarray and the second subarray each including a plurality of phase-change memory cells arranged in an array; Each of the memory chips further includes a memory chip control module, a first array driver, and a second array driver; the memory chip control module is configured to generate a write drive control signal during a data write operation; the first array driver, connected to the memory chip control module and the first subarray, is configured to receive and respond to the write drive control signal to write first data to be written to a selected phase-change memory cell in the first subarray; the second array driver, connected to the memory chip control module and the second subarray, is configured to receive and respond to the write drive control signal to write second data to be written to a selected phase-change memory cell in the second subarray; wherein the values ​​of the first data to be written and the second data to be written are the same or different.

[0007] In some embodiments, for the first subarray or the second subarray, the phase-change memory cells arranged along a first direction are connected to the same word line, and the phase-change memory cells arranged along a second direction are connected to the same bit line; the first subarray and the second subarray are arranged sequentially along the first direction; the projections of the plurality of word lines in the first subarray and the plurality of word lines in the second subarray along the first direction overlap.

[0008] In some embodiments, the data write operation includes a first stage and a second stage that occur sequentially; the write drive control signal corresponding to the first stage instructs the writing of a first value into a selected phase-change memory cell, and the write drive control signal corresponding to the second stage instructs the writing of a second value into the selected phase-change memory cell; wherein the first value indicates one of data 1 and data 0, and the second value indicates the other of data 1 and data 0.

[0009] In some embodiments, the first array driver is specifically configured to, in the first stage, receive and operate based on the drive control signal to write the first value to the first subarray if the first data to be written is a first value; and in the second stage, receive and operate based on the drive control signal to write the second value to the first subarray if the first data to be written is a second value. The second array driver is specifically configured to, in the first stage, receive and operate based on the drive control signal to write the first value to the second subarray if the second data to be written is a first value; and in the second stage, receive and operate based on the drive control signal to write the second value to the second subarray if the second data to be written is a second value.

[0010] In some embodiments, the memory chip further includes a first drive switch; the first drive switch is connected to the first array driver and configured to, if the first data to be written is a first value, enable the first array driver in the first stage to write the first value; and disable the first array driver in the second stage; or, if the first data to be written is a second value, disable the first array driver in the first stage; and enable the first array driver in the second stage to write the second value. The storage chip further includes a second drive switch: the second drive switch is connected to the second array driver and is configured to, if the second data to be written is a first value, enable the second array driver in the first stage to write the first value; and disable the second array driver in the second stage; or, if the second data to be written is a second value, disable the second array driver in the first stage; and enable the second array driver in the second stage to write the second value.

[0011] In some embodiments, the first array driver includes a first word line driver and a first gating unit, and the second array driver includes a second word line driver and a second gating unit; The first word line driver is configured to operate in response to the received write drive control signal and generate a first word line drive voltage; The first gating unit is connected to the first word line driver and a plurality of word lines in the first subarray, and is configured to send the first word line driving voltage to the selected word line in the first subarray in response to the first word line selection signal. The second word line driver is configured to operate in response to the received write drive control signal to generate a second word line drive voltage; The second gating unit is connected to the second word line driver and a plurality of word lines in the second subarray, and is configured to send the second word line driving voltage to the selected word line in the second subarray in response to the second word line selection signal; The first gating unit and the second gating unit have the same device structure.

[0012] In some embodiments, the first array driver includes a first sub-bit line driver and a third gating unit, and the second array driver includes a second sub-bit line driver and a fourth gating unit; The first sub-bit line driver is configured to operate in response to the received write drive control signal to generate a first sub-bit line drive voltage; The third gating unit is connected to the first sub-bit line driver and a plurality of bit lines in the first sub-array, and is configured to send the first sub-bit line driving voltage to the selected bit line in the first sub-array in response to the first bit line selection signal. The second sub-bit line driver is configured to operate in response to the received write drive control signal to generate a second sub-bit line drive voltage; The fourth gating unit is connected to the second sub-bit line driver and a plurality of bit lines in the second sub-array, and is configured to send the second sub-bit line driving voltage to the selected bit line in the second sub-array in response to the second bit line selection signal; The third gating unit and the fourth gating unit may have different or the same device structures.

[0013] In some embodiments, the chip control module is further configured to generate a read drive control signal during a data read operation; the first array driver, connected to the chip control module, is configured to receive and respond to the read drive control signal to read data from the phase change memory cell selected in the first subarray; the second array driver, connected to the chip control module, is configured to receive and respond to the read drive control signal to read data from the phase change memory cell selected in the second subarray.

[0014] In some embodiments, the phase-change memory includes a plurality of memory banks, each memory bank including two half-memory banks and a memory bank control module; each half-memory bank includes a plurality of memory chips; the memory bank control module is configured to generate an intermediate control signal in response to an externally sent command signal; the memory chip control module is connected to the memory bank control module of its respective memory bank and is configured to generate a write drive control signal in response to the intermediate control signal when the command signal indicates a write operation.

[0015] Secondly, embodiments of this disclosure provide an electronic device, which includes the phase-change memory described in the first aspect.

[0016] This disclosure provides a phase-change memory and an electronic device that can significantly reduce the additional consumption of chip area while increasing write bandwidth. At the same time, due to the large number of circuit multiplexing, it can also effectively save the write power consumption per unit bandwidth. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a phase-change memory provided by related technologies; Figure 2 This is a schematic diagram of a phase-change memory array provided by related technologies; Figure 3 This is a timing operation diagram of a memory chip control module provided by related technologies; Figure 4 This is a schematic diagram of a phase-change memory provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of a phase-change memory array provided in an embodiment of this disclosure; Figure 6 This is a timing operation diagram of a memory chip control module provided in an embodiment of this disclosure; Figure 7 This is a detailed structural schematic diagram of the memory chip provided in the embodiments of this disclosure; Figure 8 This is a schematic diagram of the framework structure of the phase-change memory provided in this embodiment of the disclosure. Detailed Implementation

[0018] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0020] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0021] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0022] First, the nouns and terms used in the embodiments of this disclosure will be explained: Word line (WL); Bit line (BL).

[0023] It should be understood that the write operation of phase-change memory (PDM) relies on the phase transition process between the crystalline and amorphous states of the phase change material, and this process has a certain physical time consumption. Specifically, writing data "0" (also known as the reset operation) typically takes about one hundred nanoseconds, while writing data "1" (also known as the set operation) takes several hundred nanoseconds, thus limiting the overall write bandwidth of PDM. Since write operations are a critical part of many storage applications (such as databases, caching, and artificial intelligence training), the slow write performance of PDM weakens its competitiveness in high-performance computing environments to some extent. Therefore, how to effectively improve the write bandwidth of PDM and shorten the operation time of set and reset operations has become a core technical problem that urgently needs to be solved in the research and industrialization of PDM.

[0024] Please see Figure 1 It shows a schematic diagram of the structure of a phase-change memory 10 provided by related technologies. For example... Figure 1 As shown, the phase-change memory 10 includes multiple memory banks. Figure 1 Only one is shown. Each memory bank includes a Bank Control Unit (BCU) and two half-banks. The two half-banks are located in... Figure 1 They are referred to as the first half of the memory and the second half of the memory, respectively.

[0025] like Figure 1 As shown, each half-cell includes multiple teslet chips. Each teslet chip includes a chip control module, word line drivers, bit line drivers, and a phase-change memory array (PCA). Figure 1 Omitted, please see below. Figure 2 ).like Figure 2 As shown, the phase change memory array includes multiple phase change memory cells arranged in an array. Figure 2 Each intersection point can be considered as a phase-change memory cell. Multiple phase-change memory cells arranged along the first direction X are connected to the same word line WL0, WL1, WL2, WL3... and multiple phase-change memory cells arranged along the second direction Y are connected to the same bit line BL0, BL1, BL2, BL3... The word line driver is used to provide the word line driving voltage, and the bit line driver is used to provide the bit line driving voltage, thereby realizing data writing.

[0026] It should be understood that a storage system is typically formed by connecting an external controller and a phase-change memory (PCM). The external controller (e.g., a system-on-a-chip, SoC) controls the operation of the PCM 10. Regarding... Figure 1 and Figure 2The phase-change memory 10 shown operates as follows when writing data: Upon receiving a write command from an external controller, the memory bank control module generates an intermediate control signal and sends it to the memory chip control module of each memory chip. The memory chip control module operates based on the intermediate control signal and the data signal (DQ, i.e., the data to be written) sent by the external controller, generating a reset drive control signal (corresponding to the Reset operation) or a set drive control signal (corresponding to the Set operation). The reset drive control signal instructs the word line driver and bit line driver to provide the corresponding drive voltage to write data 0; the set drive control signal instructs the word line driver and bit line driver to provide the corresponding drive voltage to write data 1.

[0027] In other words, the bank control module only responds to write commands and does not distinguish between reset and set operations; however, the chip control module does distinguish between reset and set operations. Please see [link to relevant documentation]. Figure 3 For a set operation, the set drive control signal output by the memory chip control module will follow the timing sequence above, taking approximately several hundred nanoseconds. For a reset operation, the reset drive control signal output by the memory chip control module will follow the timing sequence below. Although the effective operation time for a reset operation is shorter (approximately tens to one hundred nanoseconds), because the same write operation simultaneously writes data to multiple memory chips (and each memory chip only writes one bit of data), some memory chips may need to write 0s while others may need to write 1s. Therefore, the overall duration of the write operation must be fixed. Figure 3 The reset operation also includes an idle phase, so the actual time taken for the set and reset operations is the same, both being several hundred nanoseconds.

[0028] Overall, for the phase-change memory 10, since the memory chip control module needs to output different drive control signals for reset and set operations, it is impossible to complete the parallel execution of reset and set operations simultaneously through the same memory chip control module. Therefore, in order to increase the amount of data written in parallel, the entire memory bank is often copied, but this will significantly increase the chip area and the effect is limited.

[0029] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0030] In one embodiment of this disclosure, please refer to Figure 4 This illustrates a schematic diagram of the structure of a phase-change memory 20 provided in an embodiment of this disclosure. For example... Figure 4 As shown, the phase-change memory 20 includes multiple memory chips 30_0, 30_1, etc. These memory chips are also called tiles. It should be understood that the structure and working principle of different memory chips are the same; therefore, memory chip 30 will be used below to refer to any one memory chip.

[0031] like Figure 5 As shown, each memory chip 30 includes a first subarray 31 and a second subarray 32. The first subarray 31 and the second subarray 32 each include a plurality of phase-change memory cells arranged in an array. Figure 5 The intersection of the word line and the bit line can be regarded as a phase change memory cell. Multiple phase change memory cells arranged along the first direction X are connected to the same word line WL0_0, WL1_0..., and multiple phase change memory cells arranged along the second direction Y are connected to the same bit line BL0, BL1, BL2, BL3.

[0032] It should be understood that, for Figure 5 The first subarray 31 shows four word lines WL0_0, WL1_0, WL2_0, and WL3_0, and two bit lines BL0 and BL1; the second subarray 32 shows four word lines WL0_1, WL1_1, WL2_1, and WL3_1, and two bit lines BL2 and BL3. However, the number of word lines and bit lines in the first subarray 31 is unlimited, and the number of word lines and bit lines in the second subarray 32 is unlimited.

[0033] In one specific embodiment, the number of word lines, bit lines, and phase-change memory cells in the first subarray 31 and the second subarray 32 are all the same, which facilitates parallel writing or reading.

[0034] In another specific embodiment, the number of word lines, bit lines, and phase-change memory cells of the first subarray 31 and the second subarray 32 can also be designed to be different to provide more flexible data storage space.

[0035] like Figure 4 As shown, each memory chip 30 also includes a memory chip control module 33, a first array driver 34, and a second array driver 35. The memory chip control module 33 is configured to generate a write drive control signal during a data write operation. The first array driver 34 is connected to the memory chip control module 33 and the first subarray 31, and is configured to receive and respond to the write drive control signal to write the first data to be written to the selected phase change memory cell in the first subarray 31. The second array driver 35 is connected to the memory chip control module 33 and the second subarray 32, and is configured to receive and respond to a write drive control signal to write a second data to be written to a selected phase change memory cell in the second subarray 32; wherein the values ​​of the first data to be written and the second data to be written are the same or different.

[0036] It should also be noted that, for Figure 1 The phase-change memory 10 shown requires the memory chip control module to distinguish between reset and set operations, thus making it impossible to achieve parallel writing of 2 bits of data using the same memory chip control module. However, the phase-change memory 20 provided in this embodiment does not distinguish between reset and set operations, or in other words, the write drive control signal uses the same timing sequence whether writing data 1 or data 0 (see the following for a more detailed explanation), thus enabling parallel writing of 2 bits of data or even more bits of data.

[0037] In this embodiment of the present disclosure, the phase-change memory cells in each Tile are divided into relatively independent first subarray 31 and second subarray 32. Each subarray corresponds to its own array driver. The two array drivers can operate based on the same write drive control signal, thereby writing 1 bit of data to each of the first subarray 31 and the second subarray 32, realizing parallel writing of the Tile and increasing the write bandwidth. At the same time, the first subarray 31 and the second subarray 32 share the same Tile control module 33, eliminating the need to copy the entire bank, and the change in chip area is minimal.

[0038] In some embodiments, such as Figure 5 As shown, the first subarray 31 and the second subarray 32 are arranged sequentially along the first direction X. At this time, the projections of multiple word lines WL0_0, WL1_0, WL2_0, and WL3_0 in the first subarray 31 and multiple word lines WL0_1, WL1_1, WL2_1, and WL3_1 in the second subarray 32 overlap along the first direction X. That is, the projections of WL0_0 and WL0_1 overlap along the first direction X, the projections of WL1_0 and WL1_1 overlap along the first direction X, and so on… For example, for Figure 2 The provided phase-change memory 10, assuming the phase-change memory array in the memory tile includes 1024×1024 phase-change memory cells, has a total of 1024 bit lines and 1024 word lines; then in one feasible embodiment, each word line is divided into two parts along a first direction, that is... Figure 2 The character line WL0 in the middle is divided into Figure 5In the array, WL0_0 and WL0_1 have the same number of bit lines. 512 bit lines belong to the first subarray 31, and the other 52 bit lines belong to the second subarray 32. Thus, the number of phase-change memory cells included in each tile remains unchanged at 1024×1024, while the number of word lines becomes 2048 and the number of bit lines remains 1024. The structural changes are minor, and the overall storage capacity of the phase-change memory 20 remains unchanged, but the write bandwidth can be doubled.

[0039] In some embodiments, see Figure 6 The aforementioned data write operation includes a first stage and a second stage that occur sequentially; the write drive control signal corresponding to the first stage indicates that a first value is written to the selected phase change memory cell, and the write drive control signal corresponding to the second stage indicates that a second value is written to the selected phase change memory cell. The first value indicates one of data 1 and data 0, and the second value indicates the other of data 1 and data 0. In this way, the write drive control signal can realize the writing of the first value (e.g., data 0) and / or the second value (e.g., data 1).

[0040] It should be understood that Figure 6 The example shown uses a first value of 0 (i.e., the first stage corresponds to the Reset operation) and a second value of 1 (i.e., the second stage corresponds to the Set operation). However, this does not constitute a limitation. It can also be designed so that the first stage is used to write data 1 and the second stage is used to write data 0.

[0041] In this way, each data write operation includes a writing phase for data 1 and a writing phase for data 0. That is, each data write operation provides the possibility of writing 1 and the possibility of writing 0, thereby ensuring that the timing of the write drive control signal remains consistent in each data write operation.

[0042] In comparison, for Figure 1 In the phase-change memory 10 shown, the memory chip control module generates different drive control signals depending on the specific operation type, such as a Set operation or a Reset operation. Therefore, Set and Reset operations cannot be performed simultaneously. However, in the phase-change memory 20 provided in this embodiment, the Reset and Set operations are combined into a single operation, thus ensuring that the behavior of the memory chip control module 33 remains consistent regardless of whether a Set or Reset operation is performed.

[0043] In some embodiments, the first array driver 34 is specifically configured to, in a first stage, receive and operate based on a drive control signal to write the first value to the first subarray 31 if the first data to be written is a first value; and in a second stage, receive and operate based on a drive control signal to write the second value to the first subarray 31 if the first data to be written is a second value. The second array driver 35 is specifically configured such that if the second data to be written is a first value, it receives and operates based on the drive control signal in the first stage to write the first value to the second subarray 32; if the second data to be written is a second value, it receives and operates based on the drive control signal in the second stage to write the second value to the second subarray 32.

[0044] In one specific embodiment, please refer to Figure 7 The memory chip 30 also includes a first drive switch 36 and a second drive switch 37; the first drive switch 36 is connected to the first array driver 34 (specifically the first word line driver 341 and the first sub-bit line driver 343) and is used to control the first array driver 34 to work at an appropriate time; the second drive switch 37 is connected to the second array driver 35 (specifically the second word line driver 341 and the second sub-bit line driver 343) and is used to control the second array driver 35 to work at an appropriate time.

[0045] Please refer to Tables 1 and 2 below. Assuming the first stage is used to perform a reset operation and the second stage is used to perform a set operation, and the two bits of data written in parallel to the same memory chip are denoted as A and B, then Table 1 shows the working process of the first array driver 34 and the second array driver 35, as detailed below: The first drive switch 36 is connected to the first array driver 34 and is configured to enable the first array driver 34 in the first stage to write the first value if the first data to be written is a first value; and to turn off the first array driver 34 in the second stage if the first data to be written is a second value; or, if the first data to be written is a second value, to turn off the first array driver 34 in the first stage; and to enable the first array driver 34 in the second stage to write the second value.

[0046] The second drive switch 37 is configured to, in the first stage, enable the second array driver 35 to write the first value if the second data to be written is the first value, and in the second stage, disable the second array driver 35; or, in the first stage, disable the second array driver 35 if the second data to be written is the second value, and in the second stage, enable the second array driver 35 to write the second value.

[0047] Table 1

[0048] Table 2

[0049] In another specific embodiment, the first drive switch 36 can be coupled between the output terminal of the memory chip control module 33 and the input terminal of the first array driver 34 to shield or transmit the write drive control signal; the second drive switch 37 can be coupled between the output terminal of the memory chip control module 33 and the input terminal of the second drive switch 37 to shield or transmit the write drive control signal.

[0050] Overall, for the same memory tile, after enabling simultaneous operation of multiple memory cells, different memory cells may be writing different data. For example, one memory cell may be writing data 1 (Set operation), while the other is writing data 0 (Reset operation). This can lead to conflicts in the behavior of the memory tile control circuit. In the embodiments of this disclosure, this conflict is resolved by merging the Set and Reset operations.

[0051] Since the Set and Reset operations are combined in this embodiment, it is necessary to distinguish the actual operation type of a single operation. Therefore, this invention achieves the distinction between Set and Reset operations by introducing data into the control of the drive switch. As shown in Tables 1 and 2, when data A and B are written to the same memory chip simultaneously, if data A and data B are different, this embodiment will complete the operation in different time slots, corresponding to time-division multiplexing; if data A and data B are the same, this invention will write the two data in parallel and simultaneously in the same time slot.

[0052] Assuming the Set operation takes 450 nanoseconds (ns) and the Reset operation takes 50 ns, for Figure 1 The phase-change memory 10 shown requires two Set serial operations to write 2 bits of data to the same memory tile, taking 450 × 2 = 900 ns. However, in the example implementation, 2 bits of data can be written sequentially, with a maximum time of 450 + 50 = 500 ns, resulting in an approximately 80% increase in write bandwidth.

[0053] In some embodiments, see Figure 7 The first array driver 34 includes a first word line driver 341, a first gating unit 342, a first sub-bit line driver 343, and a third gating unit 344; The first word line driver 341 is configured to operate in response to a received write drive control signal and generate a first word line drive voltage; The first gating unit 342 is connected to the first word line driver 341 and a plurality of word lines in the first subarray 31, and is configured to send a first word line driving voltage to the selected word line in the first subarray 31 in response to a first word line selection signal.

[0054] The first sub-bit line driver 343 is configured to operate in response to a received write drive control signal to generate a first sub-bit line drive voltage; The third gating unit 344 is connected to the first sub-bit line driver 343 and a plurality of bit lines in the first sub-array 31, and is configured to send the first sub-bit line driving voltage to the selected bit line in the first sub-array 31 in response to the first bit line selection signal. In some embodiments, the write drive control signal includes a word line drive control signal and a bit line drive control signal. The word line drive control signal is used to transmit to the first word line driver 341 at an appropriate time, and the bit line drive control signal is used to transmit to the first sub-bit line driver 351 at an appropriate time, thereby writing the corresponding data.

[0055] It should be noted that the first word line selection signal and the first bit line selection signal are generated based on the address signal sent by the external controller. The address signal indicates the addressing information of the phase-change memory cell to be written. The first gating unit 342 selects the corresponding word line in the first subarray 31 based on the address signal, thereby sending the first word line drive voltage to the corresponding word line. The third gating unit 352 selects the corresponding bit line in the first subarray 31 based on the address signal, thereby sending the first bit line drive voltage to the corresponding bit line to write data to the selected phase-change memory cell in the first subarray 31.

[0056] Similarly, the structure of the second array driver 35 can be referenced to that of the first array driver 34. See also... Figure 7 The second array driver 35 includes a second word line driver 351, a second gating unit 352, a second sub-bit line driver 353, and a fourth gating unit 354; The second word line driver 351 is configured to operate in response to a received write drive control signal and generate a second word line drive voltage. The second gating unit 352 is connected to the second word line driver 351 and a plurality of word lines in the second subarray 32, and is configured to send a second word line driving voltage to the selected word line in the second subarray 32 in response to a second word line selection signal. The second sub-bit line driver 353 is configured to operate in response to a received write drive control signal to generate a second sub-bit line drive voltage; The fourth gating unit 354 is connected to the second sub-bit line driver and a plurality of bit lines in the second sub-array 32, and is configured to send the second sub-bit line driving voltage to the selected bit line in the second sub-array 32 in response to the second bit line selection signal. Similarly, the second word line select signal and the second bit line select signal are generated based on the address signal sent by the external controller.

[0057] In some implementations, the first gating unit 342 and the second gating unit 352 have the same device structure.

[0058] For example, Figure 1 The word line driver portion of the phase-change memory 10 shown is copied, that is, the structure of the second word line driver 341 can be copied to the first word line driver 331, and the structure of the second gating unit 352 can be copied to the first gating unit 351. The layout design can be reused, reducing the workload of design.

[0059] In some embodiments, the device structures of the third gating unit 344 and the fourth gating unit 354 are different.

[0060] For example, Figure 1 The phase-change memory 10 shown is divided into two independent parts, unlike the word line driving part which is copied. This ensures that the overall number of memory cells remains unchanged, and the area of ​​the bit line driving part does not increase. In this scenario, the area occupied by the third gating unit 344 and the fourth gating unit 354 is approximately equal to the area occupied by the first gating unit 342, and the area occupied by the second gating unit 352 is equal to that of the first gating unit 342.

[0061] In other words, taking 2-bit data parallel operation as an example, to achieve 2-bit parallel operation, this embodiment only copies the driver for the word line portion, while splitting the driver for the bit line portion to ensure that the chip capacity remains unchanged. Thus, for Figure 2 The memory slice shown in the figure suffers from interference between adjacent memory cells, leading to operation failures. This is because adjacent memory cells always share the same word line (WL) or bit line (BL), causing simultaneous operation on multiple memory cells to interfere with each other. However, memory slice 30, as shown in the figure, divides the memory cells into two completely independent blocks by copying the word line drive portion and splitting the bit line drive portion. Simultaneous operation on these two blocks no longer interferes with each other, thus allowing parallel operation on 2 bits of data.

[0062] Thus, assuming Figure 1The phase-change memory 20 shown has 256 tiles. Since each tile can only support writing 1 bit of data simultaneously, it can support a maximum of 256 bits of data written in parallel. However, for the phase-change memory 20 provided in this embodiment of the present disclosure, since each tile supports writing 2 bits of data simultaneously, it can support a maximum of 512 bits of data written in parallel.

[0063] In other embodiments, the first gating unit 342 and the second gating unit 352 may be designed differently, and the devices of the third gating unit 344 and the fourth gating unit 354 may be configured to be the same.

[0064] In some embodiments, the memory chip control module 33 is further configured to generate a read drive control signal during a data read operation; The first array driver 34 is connected to the memory chip control module 33 and is configured to receive and respond to a read drive control signal to read data from the selected phase change memory cell in the first subarray 31. The second array driver 35, connected to the memory chip control module 33, is configured to receive and respond to a read drive control signal to read data from the selected phase change memory cell in the second subarray 32.

[0065] For the phase-change memory 20 provided in this embodiment, the read operation can also read 2 bits of data in the same memory tile in parallel, which also expands the read bandwidth.

[0066] It should also be noted that the phase-change memory 20 and the embodiments provided in this disclosure... Figure 1 The phase-change memory 10 shown is roughly similar at the bank level. For example... Figure 8 As shown, the phase-change memory 20 also includes multiple memory banks 21 ( Figure 8 (Only one is shown), each memory bank 21 includes a memory bank control module 210, a first half-memory bank 220_0, and a second half-memory bank 220_1. Each half-memory bank includes multiple of the aforementioned memory chips 30. Figure 8 Only one is shown.

[0067] For the same memory bank, all memory chip control modules 311 respond to the same memory bank control module 210 and operate accordingly.

[0068] The storage control module 210 is configured to generate intermediate control signals in response to command signals sent from the outside. The memory chip control module 33 is configured to generate a write drive control signal in response to an intermediate control signal when a write operation is indicated by a command signal.

[0069] It should be noted that the command signal indicates the type of operation, such as a read operation or a write operation. The command signal is sent by the external controller to the phase-change memory 20.

[0070] Thus, for Figure 1 The phase-change memory 10 shown requires the chip control module 33 to respond to the data signal (DQ) to distinguish between Set and Reset operations; however, for the phase-change memory 20 provided in this embodiment, each write operation of the chip control module 33 includes both Set and Reset operations, therefore it does not need to respond to the data signal (DQ). Figure 7 The first drive switch 36 and the second drive switch 37 need to determine the timing of operation of the first array drive circuit 34 and the second array drive circuit 35 based on the data signal (DQ).

[0071] As can be seen from the above, neither the storage bank control module nor the storage chip control module 33 introduces information related to the data to be written for write operations. Therefore, the actions of both for set and reset operations are the same, providing a structural basis for parallel data writing.

[0072] In summary, this application's embodiments optimize the architecture of the memory bank, achieving parallel writing and increasing write bandwidth while reducing the additional chip area. Specifically, on the one hand, to achieve parallel operation, this invention only copies the drivers of the word lines (WL) or bit lines (BL) within the memory tile; on the other hand, to still reuse the memory tile control module 33 and solve the problem that the memory tile control module 33 cannot simultaneously perform set and reset operations, this disclosure embodiment concatenates the set and reset operations, so that a single write operation simultaneously includes one set and one reset operation; finally, to select the correct operation type from set and reset, this disclosure embodiment introduces write data into the first drive switch 36 and the second drive switch 37, controlling the start and stop of the drive through the write data, thereby enabling the first array driver and the second array control driver to operate during the required working phase, simultaneously achieving time-division multiplexing and parallel writing.

[0073] Thus, referring to Table 3, for technical solution one, which increases the amount of data written in parallel by directly increasing the number of banks, the number of bank control modules 210, chip control modules 33, word line drive circuits, and bit line drive circuits increases synchronously, while the power consumption per unit bandwidth remains unchanged. However, for the phase-change memory unit 20 provided in this embodiment, the bank control modules 210 and chip control modules 33 remain unchanged, the number of word line drive circuits doubles, and the bit line drive circuits remain almost unchanged (only split into two parts), resulting in a reduction in power consumption per unit bandwidth. Therefore, this embodiment can significantly reduce the additional consumption of chip area while increasing write bandwidth, and due to the large amount of circuit multiplexing, it can also effectively save on write power consumption per unit bandwidth.

[0074] Table 3

[0075] In another embodiment of this disclosure, the first subarray 31 and the second subarray 32 may be arranged along the second direction Y. Further details can be found in the accompanying description.

[0076] In another embodiment of this disclosure, for the phase-change memory 20, each memory tile further includes a third subarray and a third array driver; The third array driver, connected to the memory chip control module 33 and the third subarray, is configured to receive and respond to the write drive control signal to write third data to be written to the phase-change memory cells in the third subarray; or... Receive and respond to the read drive control signal to read data from the selected phase change memory cell in the third subarray.

[0077] In this way, by dividing the phase-change memory cells inside the memory chip into three relatively independent subarrays, parallel writing or reading of three bits of data can be achieved. The structure of the third subarray can be the same as that of the first subarray 31, and the structure and operation of the third array driver can be the same as those of the third array driver.

[0078] Based on this, the same storage tile can support a larger number of parallel data writes or reads (e.g., 4-bit, 5-bit, 6-bit, etc.).

[0079] In one embodiment of this disclosure, an electronic device is provided, which includes the aforementioned phase-change memory 20. This electronic device may be a user equipment (UE), mobile device, user terminal, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc.

[0080] The above description is merely an example embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0081] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0082] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0083] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0084] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0085] The features disclosed in the several method or circuit embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or circuit embodiments.

[0086] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A phase-change memory, characterized in that, The phase change memory includes multiple memory chips, each memory chip including a first subarray and a second subarray, the first subarray and the second subarray each including multiple phase change memory cells arranged in an array; Each of the aforementioned memory chips also includes a memory chip control module, a first array driver, and a second array driver; The memory chip control module is configured to generate a write drive control signal during a data write operation. The first array driver, connected to the memory chip control module and the first subarray, is configured to receive and respond to the write drive control signal to write first data to be written to the selected phase change memory cell in the first subarray. The second array driver, connected to the memory chip control module and the second subarray, is configured to receive and respond to the write drive control signal to write second data to be written to the selected phase change memory cell in the second subarray; The values ​​of the first data to be written and the second data to be written may be the same or different.

2. The phase-change memory according to claim 1, characterized in that, For the first subarray or the second subarray, the phase-change memory cells arranged along the first direction are connected to the same word line, and the phase-change memory cells arranged along the second direction are connected to the same bit line. The first subarray and the second subarray are arranged sequentially along the first direction; The plurality of word lines in the first subarray are located on the extensions of the plurality of word lines in the second subarray.

3. The phase-change memory according to claim 1 or 2, characterized in that, The data write operation includes a first phase and a second phase that occur sequentially. The write drive control signal corresponding to the first stage indicates that a first value is written to the selected phase change memory cell, and the write drive control signal corresponding to the second stage indicates that a second value is written to the selected phase change memory cell. The first value indicates one of data 1 and data 0, and the second value indicates the other of data 1 and data 0.

4. The phase-change memory according to claim 3, characterized in that, The first array driver is specifically configured such that if the first data to be written is a first value, then in the first stage, it receives and operates based on the drive control signal to write the first value to the first sub-array; if the first data to be written is a second value, then in the second stage, it receives and operates based on the drive control signal to write the second value to the first sub-array. The second array driver is specifically configured such that, if the second data to be written is a first value, it receives and operates based on the drive control signal in the first stage to write the first value to the second sub-array; and if the second data to be written is a second value, it receives and operates based on the drive control signal in the second stage to write the second value to the second sub-array.

5. The phase-change memory according to claim 4, characterized in that, The storage chip also includes a first drive switch; The first drive switch, connected to the first array driver, is configured to enable the first array driver in the first stage to write the first value if the first data to be written is a first value; and to turn off the first array driver in the second stage. Alternatively, if the first data to be written is the second value, then in the first stage, the first array driver is turned off; In the second phase, the first array driver is enabled to write the second value; The memory chip also includes a second drive switch: The second drive switch, connected to the second array driver, is configured to enable the second array driver in the first stage to write the first value if the second data to be written is a first value; and to disable the second array driver in the second stage. Alternatively, if the second data to be written is the second value, then in the first stage, the second array driver is turned off; In the second phase, the second array driver is enabled to write the second value.

6. The phase-change memory according to claim 5, characterized in that, The first array driver includes a first word line driver and a first gating unit, and the second array driver includes a second word line driver and a second gating unit; The first word line driver is configured to operate in response to the received write drive control signal and generate a first word line drive voltage; The first gating unit is connected to the first word line driver and a plurality of word lines in the first subarray, and is configured to send the first word line driving voltage to the selected word line in the first subarray in response to the first word line selection signal. The second word line driver is configured to operate in response to the received write drive control signal to generate a second word line drive voltage; The second gating unit is connected to the second word line driver and a plurality of word lines in the second subarray, and is configured to send the second word line driving voltage to the selected word line in the second subarray in response to the second word line selection signal; The first gating unit and the second gating unit have the same device structure.

7. The phase-change memory according to claim 5, characterized in that, The first array driver includes a first sub-bit line driver and a third gating unit, and the second array driver includes a second sub-bit line driver and a fourth gating unit; The first sub-bit line driver is configured to operate in response to the received write drive control signal to generate a first sub-bit line drive voltage; The third gating unit is connected to the first sub-bit line driver and a plurality of bit lines in the first sub-array, and is configured to send the first sub-bit line driving voltage to the selected bit line in the first sub-array in response to the first bit line selection signal. The second sub-bit line driver is configured to operate in response to the received write drive control signal to generate a second sub-bit line drive voltage; The fourth gating unit is connected to the second sub-bit line driver and a plurality of bit lines in the second sub-array, and is configured to send the second sub-bit line driving voltage to the selected bit line in the second sub-array in response to the second bit line selection signal; The third gating unit and the fourth gating unit may have different or the same device structures.

8. The phase-change memory according to claim 1 or 2, characterized in that, The memory chip control module is also configured to generate a read drive control signal during a data read operation. The first array driver, connected to the memory chip control module, is configured to receive and respond to the read drive control signal to read data from the phase change memory cell selected in the first sub-array; The second array driver, connected to the memory chip control module, is configured to receive and respond to the read drive control signal to read data from the selected phase-change memory cell in the second sub-array.

9. The phase-change memory according to claim 8, characterized in that, The phase-change memory includes multiple memory cells, each memory cell including two half-memory cells and a memory cell control module; each half-memory cell includes multiple memory chips; The storage control module is configured to generate an intermediate control signal in response to an externally sent command signal; The memory chip control module is connected to the memory bank control module of its respective memory bank and is configured to generate a write drive control signal in response to the intermediate control signal when the command signal indicates a write operation.

10. An electronic device, characterized in that, The electronic device includes a phase-change memory as described in any one of claims 1-9.

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