Configurable ratio logic unit based on memristor and method of using the same

By designing a configurable ratio logic unit based on memristors and utilizing pre-configured resistive states to perform voltage division, the problems of insufficient operation speed, durability and robustness of existing logic units are solved, and efficient and reliable logic calculation is achieved.

CN122392595APending Publication Date: 2026-07-14SHANGHAI JIAOTONG UNIV
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SHANGHAI JIAOTONG UNIV
Filing Date
2026-04-02
Publication Date
2026-07-14

AI Technical Summary

Technical Problem

Existing memristor-based logic units have shortcomings in terms of operation speed and durability, output signal transmission overhead and system robustness. In particular, in state logic, the calculation results need to be read and level converted by external circuits, and they are sensitive to process deviations.

Method used

Design a configurable ratio logic unit based on memristors. Selectively conduct a resistive voltage divider network through input branches A and B, perform resistive voltage division using pre-configured resistive states, and quantize the analog level into a standard CMOS digital signal through the output decision branch, avoiding the SET/RESET process and enhancing robustness.

Benefits of technology

It achieves high-efficiency computing, reduces computational latency, enhances logic completeness and CMOS compatibility, improves system reliability and robustness, and is suitable for digital circuits such as FPGAs.

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Abstract

The application provides a configurable ratio logic unit based on a memristor, comprising: an input A branch that receives an input signal A and selectively conducts a supply voltage to a specific memristor path of a resistive voltage dividing network to build an upper pull network of the logic unit; an input B branch that receives an input signal B and selectively conducts a reference ground potential to a specific memristor path of the resistive voltage dividing network to build a lower pull network of the logic unit; a resistive voltage dividing network that performs resistive voltage division by using a combination of pre-configured resistance states of the memristor in a calculation stage to generate an internal analog level at a common intermediate node that represents a calculation result; a programming control branch that provides a high voltage bias path for the generation and resistance state rewriting of conductive filaments in a medium layer of the memristor array in an initialization and configuration stage that is not calculated; and an output decision branch that real-time samples an analog level of the intermediate node, quantizes, amplifies and shapes the analog level into a standard CMOS digital logic signal based on an asymmetric decision threshold.
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