Non-volatile memory device, method of operating the same, and storage apparatus

Abstract

A nonvolatile memory device and an operating method thereof and a storage device are provided. The nonvolatile memory device includes a memory cell array including a plurality of cell strings having a plurality of memory cells classified as pages, a row decoder connected to the memory cell array through a string selection line, a ground selection line, and a word line, and a page buffer connected to the memory cell array through a bit line. In response to a read command for a first page being received from an external device, the row decoder applies a first voltage to the word line to correspond to a first capacitance of memory cells of the first page. In response to a read command for a first partial page of the first page being received from the external device, the row decoder applies a second voltage to the word line to correspond to a second capacitance of memory cells of the first partial page.

Description

Technical Field

[0001] The embodiments of this disclosure described herein relate to electronic devices, and more specifically, to non-volatile memory devices with reduced power consumption, methods of operating the non-volatile memory devices, and storage devices including the non-volatile memory devices. Background Technology

[0002] Semiconductor memory devices can refer to memory devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Semiconductor memory devices can be primarily classified as volatile memory devices or non-volatile memory devices.

[0003] Volatile memory devices are those that lose the data stored within them when the power is turned off. Examples of volatile memory devices include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Synchronous DRAM. Non-volatile memory devices are those that retain the data stored within them even when the power is turned off. Examples of non-volatile memory devices include Read-Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM), Flash Memory, Phase-Change RAM (PRAM), Magnetic RAM (MRAM), and Resistive RAM (RRAM).

[0004] As semiconductor memory devices become increasingly integrated, various research efforts are underway to reduce power consumption. Therefore, methods for reducing power consumption remain a subject of research and development in highly integrated memory devices. Summary of the Invention

[0005] Embodiments of this disclosure provide a non-volatile memory device with reduced power consumption, a method of operating the non-volatile memory device, and a storage device including the non-volatile memory device.

[0006] According to an embodiment, a non-volatile storage device includes: a memory cell array comprising a plurality of cell strings having a plurality of memory cells classified as pages; a row decoder connected to the memory cell array via a string select line, a ground select line, and a word line, and configured to apply a voltage to the string select line and the ground select line; and a page buffer connected to the memory cell array via a bit line and configured to apply a voltage to the bit line. In response to a read command for a first page being received from an external device, the row decoder applies a first voltage to the word line corresponding to a first capacitance of a memory cell in the first page. In response to a read command for a first portion of the first page being received from the external device, the row decoder applies a second voltage to the word line corresponding to a second capacitance of a memory cell in the first portion of the page. The channel of each cell string is formed to have a channel voltage in response to the voltage being applied to the string select line, the ground select line, the word line, and the bit line. The first capacitor is formed between the channel of the cell string connected to the bit line associated with the first page and the word line to which the first voltage is applied. The second capacitor is formed between the channel of the cell string connected to the bit line associated with the first partial page and the word line to which the second voltage is applied. The amount of the second capacitor is less than the amount of the first capacitor.

[0007] According to an embodiment, a method of operating a non-volatile memory device includes a memory cell array comprising a plurality of cell strings having a plurality of memory cells classified as pages. The method includes: in response to receiving a read command for a first page from an external device, applying a first voltage to a word line corresponding to a first capacitance of a memory cell in the first page; in response to receiving a read command for a first portion of the first page from the external device, applying a second voltage to the word line corresponding to a second capacitance of a memory cell in the first portion of the first page; and forming a channel having a channel voltage for each cell string by applying voltages to the string select line, the ground select line, the word line, and the bit line. The first capacitance is formed between the channel of the cell string connected to the bit line associated with the first page and the word line to which the first voltage is applied. The second capacitance, different from the first capacitance, is formed between the channel of the cell string connected to the bit line associated with the first portion of the page and the word line to which the second voltage is applied.

[0008] According to an embodiment, a storage device includes: a non-volatile storage device; and a controller configured to access the non-volatile storage device. The non-volatile storage device includes: a memory cell array comprising a plurality of cell strings having a plurality of memory cells classified as pages; a row decoder connected to the memory cell array via a string select line, a ground select line, and a word line, and configured to apply a voltage to the string select line and the ground select line; and a page buffer connected to the memory cell array via a bit line and configured to apply a voltage to the bit line. In response to a read command for a first page being received from the controller, the row decoder applies a first voltage to the word line corresponding to a first capacitance of a memory cell in the first page. In response to a read command for a first portion of the first page being received from the controller, the row decoder applies a second voltage to the word line corresponding to a second capacitance of a memory cell in the first portion of the page. The first capacitor is formed between the channel of the cell string connected to the bit line associated with the first page and the word line to which the first voltage is applied. The second capacitor, unlike the first capacitor, is formed between the channel of the cell string connected to the bit line associated with the first portion of the page and the word line to which the second voltage is applied. Attached Figure Description

[0009] The above and other objects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating a non-volatile storage device according to an embodiment of the present disclosure.

[0011] Figure 2 An example is shown of a portion of a storage block included in the first or second sheet.

[0012] Figure 3 A first example of an operation method for a non-volatile storage device is shown.

[0013] Figure 4 It shows in Figure 2 An example of the process of performing partial access operations within a storage block.

[0014] Figure 5 An embodiment of the present disclosure illustrates a non-volatile memory device performing a partial access operation in a state in which at least some of the cell strings in the partial cell string that are structurally associated with the partial cell string that is the target of the partial access are prohibited from acting as the load of the word line.

[0015] Figure 6 An example embodiment is shown in Figure 2 An example of programming the first to eighth special storage units in a storage block.

[0016] Figure 7 An example is shown where a non-volatile storage device according to an example embodiment only bears the load of a third portion of the cell string as the target of a partial access operation.

[0017] Figure 8 An example of a group of multiple bit lines according to an example embodiment is shown.

[0018] Figure 9 Another example of a group of multiple bit lines according to an example embodiment is shown.

[0019] Figure 10 An example of a non-volatile storage device according to an example embodiment is shown, which is used to perform partial access operations in a state where at least some of the cell strings in a partial cell string do not act as loads for word lines.

[0020] Figure 11 An example embodiment is shown. Figure 10 Examples of operating methods for non-volatile storage devices.

[0021] Figure 12 The unit string is shown according to an example embodiment. Figure 10 Non-volatile memory devices and Figure 11 An example of the floating operation method.

[0022] Figure 13 The unit string is shown according to an example embodiment. Figure 10 Non-volatile memory devices and Figure 11 An example of a floating operation method.

[0023] Figure 14 An example embodiment is shown. Figure 1 or Figure 10 Examples of operating methods for non-volatile storage devices.

[0024] Figure 15 An example embodiment is shown in Figure 2 Execute in the unit string Figure 14 Examples of operation methods.

[0025] Figure 16 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0026] Figure 17 This is a diagram illustrating a system according to an embodiment of the present disclosure. Detailed Implementation

[0027] The embodiments of this disclosure will now be described in detail and clearly to the extent that those skilled in the art can readily implement this disclosure.

[0028] Figure 1 This is a block diagram illustrating a non-volatile storage device 100 according to an embodiment of the present disclosure. Reference Figure 1 The non-volatile memory device 100 includes a first plane PL1, a second plane PL2, a first line decoder RDC1, a second line decoder RDC2, a first page buffer PB1, a second page buffer PB2, a pass / fail check block (or pass / fail check circuit) PFC, a first data input and output circuit DIO1, a second data input and output circuit DIO2, and a control logic circuit CL.

[0029] Each of the first PL1 and the second PL2 comprises multiple memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz comprises multiple memory cells. Each of the memory blocks BLK1 to BLKz can be connected to the first row decoder RDC1 and the second row decoder RDC2 via at least one ground select line GSL, a word line WL, and at least one string select line SSL. Some of the word lines WL can be used as dummy word lines. Each of the memory blocks BLK1 to BLKz can be connected to the first page buffer PB1 or the second page buffer PB2 via multiple bit lines BL. For example, the memory blocks BLK1 to BLKz of the first PL1 can be connected to the first page buffer PB1 via multiple bit lines BL, and the memory blocks BLK1 to BLKz of the second PL2 can be connected to the second page buffer PB2 via multiple bit lines BL. The memory blocks BLK1 to BLKz of the first PL1 and the second PL2 can be connected together to multiple bit lines BL.

[0030] In this embodiment, each of the plurality of storage blocks BLK1 to BLKz can correspond to a unit of erase operation. Storage cells belonging to each storage block can be erased simultaneously. As another example, each storage block can be divided into multiple sub-blocks. Each of the multiple sub-blocks can correspond to a unit of erase operation.

[0031] The first line decoder RDC1 and the second line decoder RDC2 are connected to the first PL1 and the second PL2 via the ground select line GSL, the word line WL, and the serial select line SSL. The first line decoder RDC1 and the second line decoder RDC2 operate under the control of the control logic circuit CL.

[0032] The first line decoder RDC1 and the second line decoder RDC2 can decode the line address RA received from the control logic circuit CL, and can control the voltage to be applied to the serial select line SSL, the word line WL and the ground select line GSL depending on the decoded line address.

[0033] The first page buffer PB1 and the second page buffer PB2 are connected to the first PL1 and the second PL2 respectively via multiple bit lines BL. The first page buffer PB1 and the second page buffer PB2 are connected to the first data input and output circuit DIO1 and the second data input and output circuit DIO2 respectively via multiple data lines DL. The first page buffer PB1 and the second page buffer PB2 operate under the control of the control logic circuit CL.

[0034] During programming operations, either the first page buffer PB1 or the second page buffer PB2 can store data to be written to the memory cell. Based on the stored data, either the first page buffer PB1 or the second page buffer PB2 can apply voltages to multiple bit lines BL. During read operations or during verification read operations (which are performed during programming or erasing operations), either the first page buffer PB1 or the second page buffer PB2 can sense the voltage of the bit lines BL and can store the sensed result.

[0035] In a verification read operation associated with a programming or erasing operation, a pass / fail check block (PFC) can verify the sensing results of the first page buffer PB1 or the second page buffer PB2. For example, in a verification read operation performed during a programming operation, the pass / fail check block (PFC) can count the number of values ​​(e.g., the number of 0s) corresponding to on-cells that have not been programmed to a target threshold voltage or higher.

[0036] During the verification read operation performed in the erase operation, the pass / fail check block (PFC) can count the number of values ​​(e.g., the number of 1s) corresponding to off-cells that have not been erased to a target threshold voltage or lower. When the count result is greater than or equal to the threshold, the pass / fail check block (PFC) can output a failure signal to the control logic circuit (CL). When the count result is less than the threshold, the pass / fail check block (PFC) can output a pass signal to the control logic circuit (CL). Depending on the verification result of the pass / fail check block (PFC), a programming loop for programming operations can be further executed, or an erase loop for erasing operations can be further executed.

[0037] The first data input / output circuit DIO1 and the second data input / output circuit DIO2 are connected to the first page buffer PB1 and the second page buffer PB2 via multiple data lines DL, respectively. The first data input / output circuit DIO1 and the second data input / output circuit DIO2 can receive the column address (or the decoded column address) CLA from the control logic circuit CL. Depending on the column address CLA, the first data input / output circuit DIO1 and the second data input / output circuit DIO2 can output the data "DATA" read from the first page buffer PB1 and the second page buffer PB2 to external devices, respectively. Depending on the column address CLA, the first data input / output circuit DIO1 and the second data input / output circuit DIO2 can transmit the data "DATA" received from external devices to the first page buffer PB1 and the second page buffer PB2, respectively.

[0038] The control logic circuit CL can receive commands and addresses CA from external devices. The control logic circuit CL can decode the commands and addresses CA received from the external devices and can control the non-volatile memory device 100 based on the decoded commands and addresses CA. For example, the control logic circuit CL can provide the row address RA to the first row decoder RDC1 and the second row decoder RDC2. The control logic circuit CL can provide the column address CLA to the first data input / output circuit DIO1 and the second data input / output circuit DIO2.

[0039] The control logic circuit CL may include a capacitor control circuit CC. The capacitor control circuit CC can prevent an increase in the power used to bias (or apply) the word line WL due to unintended capacitance when the non-volatile memory device 100 accesses the memory cell of the first PL1 or the second PL2 (e.g., performs a write or read operation on the memory cell).

[0040] Figure 2 An example is shown of a portion of one of the memory blocks BLK1 to BLKz included in either the first PL1 or the second PL2. (Reference) Figure 1 and Figure 2 One of the memory blocks BLK1 through BLKz may include multiple cell strings. Each cell string may be a stack of cell transistors connected to one of the first bit line BL1 and the second bit line BL2 and connected to one of the first string select lines SSL1 through the fourth string select line SSL4.

[0041] Each of the multiple cell strings may include a first ground select transistor GST1 and a second ground select transistor GST2 stacked sequentially, a first memory cell MC1 to a sixteenth memory cell MC16 stacked sequentially on the second ground select transistor GST2, and a first string select transistor SST1 and a second string select transistor SST2 stacked sequentially on the sixteenth memory cell MC16.

[0042] exist Figure 2 In this diagram, the directions in which the first selection line SSL1, the second selection line SSL2, the third selection line SSL3, and the fourth selection line SSL4 extend can be referred to as the "row direction". The first selection line SSL1 is said to "correspond to the first row of cells", the second selection line SSL2 is said to "correspond to the second row of cells", the third selection line SSL3 is said to "correspond to the third row of cells", and the fourth selection line SSL4 is said to "correspond to the fourth row of cells".

[0043] The direction in which the first bit line BL1 and the second bit line BL2 extend can be referred to as the "column direction". The first bit line BL1 is referred to as "corresponding to the first column cell string", and the second bit line BL2 is referred to as "corresponding to the second column cell string".

[0044] The first ground selection transistor GST1 of multiple unit strings can be connected together to the common source line CSL.

[0045] like Figure 2 The shaded areas indicate that the first ground selection transistor GST1 in the first row and the first ground selection transistor GST1 in the second row can be connected together to the first ground selection line GSL1. The first ground selection transistor GST1 in the third row and the first ground selection transistor GST1 in the fourth row can be connected together to the second ground selection line GSL2.

[0046] As described with reference to the first ground selection transistor GST1, the second ground selection transistors GST2 in the first row and GST2 in the second row can be connected together to the third ground selection line (e.g., GSL3). The second ground selection transistors GST2 in the third row and GST2 in the fourth row can be connected together to the fourth ground selection line (e.g., GSL4).

[0047] like Figure 2 The shaded areas, the fourth storage unit MC4 of the cell string in the first row, the fourth storage unit MC4 of the cell string in the second row, the fourth storage unit MC4 of the cell string in the third row, and the fourth storage unit MC4 of the cell string in the fourth row can all be connected to the fourth word line WL4.

[0048] As described with reference to the fourth storage cell MC4, the first storage cell MC1, the second storage cell MC2, and the third storage cell MC3 in the first row, the first storage cell MC1, the second storage cell MC2, and the third storage cell MC3 in the second row, the first storage cell MC1, the second storage cell MC2, and the third storage cell MC3 in the third row, and the first storage cell MC1, the second storage cell MC2, and the third storage cell MC3 in the fourth row can be connected to the first word line (e.g., WL1), the second word line (e.g., WL2), and the third word line (e.g., WL3), respectively.

[0049] Referring to the description of the fourth storage unit MC4, the fifth storage unit MC5, the sixth storage unit MC6, the seventh storage unit MC7, the eighth storage unit MC8, the ninth storage unit MC9, the tenth storage unit MC10, the eleventh storage unit MC11, the twelfth storage unit MC12, the thirteenth storage unit MC13, the fourteenth storage unit MC14, the fifteenth storage unit MC15, and the sixteenth storage unit MC16 of the first row of the cell string; the fifth storage unit MC5, the sixth storage unit MC6, the seventh storage unit MC7, the eighth storage unit MC8, the ninth storage unit MC9, the tenth storage unit MC10, the eleventh storage unit MC11, the twelfth storage unit MC12, the thirteenth storage unit MC13, the fourteenth storage unit MC14, the fifteenth storage unit MC15, and the sixteenth storage unit MC16 of the third row of the cell string; and the fifth storage unit MC5, the sixth storage unit MC6, the seventh storage unit MC7, the eighth storage unit MC8, the ninth storage unit MC9, the tenth storage unit MC10, and the eleventh storage unit MC11 of the third row of the cell string. The twelfth storage unit MC12, the thirteenth storage unit MC13, the fourteenth storage unit MC14, the fifteenth storage unit MC15, and the sixteenth storage unit MC16 of the fourth row of the cell string, and the fifth storage unit MC5, the sixth storage unit MC6, the seventh storage unit MC7, the eighth storage unit MC8, the ninth storage unit MC9, the tenth storage unit MC10, the eleventh storage unit MC11, the twelfth storage unit MC12, the thirteenth storage unit MC13, the fourteenth storage unit MC14, and the fifteenth storage unit MC15. The sixteenth memory cell MC16 can be connected to the fifth word line (e.g., WL5), the sixth word line (e.g., WL6), the seventh word line (e.g., WL7), the eighth word line (e.g., WL8), the ninth word line (e.g., WL9), the cross line (e.g., WL10), the eleventh word line (e.g., WL11), the twelfth word line (e.g., WL12), the thirteenth word line (e.g., WL13), the fourteenth word line (e.g., WL14), the fifteenth word line (e.g., WL15), and the sixteenth word line (e.g., WL16), respectively.

[0050] In an embodiment, storage cells placed at the same height within a row of cells can form a page. In an embodiment, a page from one of the first storage blocks BLK1 to BLKz (e.g., BLK1) of the first PL1 that is connected to a word line (e.g., the fourteenth word line WL14) can be used together with a page from one of the first storage blocks BLK1 to BLKz (e.g., BLK1) of the second PL2 that is connected to a word line (e.g., the fourteenth word line WL14) of the first storage block BLK1 to BLKz (e.g., BLK1) of the second PL2 as a super page.

[0051] like Figure 2 In the shaded area, the first string select transistor SST1 of the first row of cells can be connected to the first string select line SSL1, the first string select transistor SST1 of the second row of cells can be connected to the second string select line SSL2, the first string select transistor SST1 of the third row of cells can be connected to the third string select line SSL3, and the first string select transistor SST1 of the fourth row of cells can be connected to the fourth string select line SSL4.

[0052] The second string select transistor SST2 in the first row, the second string select transistor SST2 in the second row, the second string select transistor SST2 in the third row, and the second string select transistor SST2 in the fourth row can be connected to the fifth string select line (e.g., SSL5), the sixth string select line (e.g., SSL6), the seventh string select line (e.g., SSL7), and the eighth string select line (e.g., SSL8), respectively.

[0053] To prevent unnecessary complexity in drawing, Figure 2 Some lines and some line labels have been omitted.

[0054] Figure 3 A first example of the operation method of the non-volatile storage device 100 is shown. (Reference) Figure 1 and Figure 3 In operation S110, the non-volatile storage device 100 can receive access commands. For example, the non-volatile storage device 100 can receive access commands from an external storage controller or a memory controller. Access commands may include write commands, read commands, or erase commands.

[0055] In operation S120, the non-volatile storage device 100 can determine whether the received access command is a partial access command. For example, when an access command requests access to a superpage of the first PL1 and the second PL2 of the non-volatile storage device 100, that is, when the access command is received together with an address (e.g., a physical address) indicating the entire superpage, the access command can be identified as a full access command. When an access command requests access to a portion of a superpage of the first PL1 and the second PL2 of the non-volatile storage device 100, that is, when the access command is received together with an address (e.g., a physical address) indicating a portion of a superpage, the access command can be identified as a partial access command.

[0056] When the received access command is a partial access command, in operation S130, the non-volatile memory device 100 can access the word line with partial capacitance. In operation S140, the non-volatile memory device 100 can access a portion of the bit line to continue the partial access operation.

[0057] For example, in a partial access operation, the unit string may include a first part of the unit string and a second part of the unit string. The first part of the unit string includes the unit string that serves as the access target, while the second part of the unit string does not include the unit string that serves as the access target. Due to the structural characteristics of the first PL1 and the second PL2, the first part of the unit string may include a third part of the unit string and a fourth part of the unit string. The third part of the unit string includes the unit string that serves as the access target (or is the unit string that serves as the access target), and the fourth part of the unit string operates in association with the third part of the unit string.

[0058] When both the third and fourth part of the cell string are biased, the first row decoder RDC1 and the second row decoder RDC2 can withstand the capacitive load of the third and fourth part of the cell string connected to the first word line WL1 to the sixteenth word line WL16 of the first PL1 and the second PL2; in contrast, when only the third part of the cell string is biased, the first row decoder RDC1 and the second row decoder RDC2 can withstand only the capacitive load of the third part of the cell string.

[0059] In an embodiment, the biased cell string may include forming a channel of the cell string having a channel voltage by applying a specific voltage via a first bit line BL1, a second bit line BL2, or a common source line CSL and applying a bias voltage to the cell string via first word lines WL1 to sixteenth word lines WL16. For example, the biased cell string may also include applying a specific voltage via a first string select transistor SST1 and a second string select transistor SST2, and a first ground select transistor GST1 and a second ground select transistor GST2. Based on coupling effects, the channel voltage of the cell string can act as a load for the first word lines WL1 to sixteenth word lines WL16. That is, the biased cell string may include applying a voltage to the first word lines WL1 to sixteenth word lines WL16, in which the cell string acts as a load.

[0060] When the received access command is a full access command instead of a partial access command, in operation S150, the non-volatile memory device 100 can access the word line with full capacitance. For example, the non-volatile memory device 100 can withstand the capacitive load of both the third and fourth part of the cell string by biasing both the third and fourth part of the cell string. In operation S160, the non-volatile memory device 100 can access the entire bit line to continue the full access operation.

[0061] The number of bit lines accessed in a partial access operation is less than the number of bit lines accessed in a full access operation. Typically, biasing the word line can be performed without capacitive load difference in both partial and full access operations. Conversely, the non-volatile memory device according to embodiments of this disclosure can apply a different capacitance to partial access operations than to full access operations, and therefore, the amount of power required to bias the word line in partial access operations can be reduced. For example, the capacitance of the word line in a partial access operation can be less than the capacitance of the word line in a full access operation.

[0062] Figure 4 It shows in Figure 2 An example of the process of performing partial access operations within a storage block. (See reference) Figure 1 , Figure 2 and Figure 4 In an embodiment, the target of a partial access operation may be a string of cells connected to the first bit line BL1 (e.g., the selected bit line) and the first string of select lines SSL1, while the string of cells connected to the second bit line BL2 (e.g., the unselected bit line) and the first string of select lines SSL1 may not be the target of the partial access operation.

[0063] For the cell string to be biased as the target of a partial access operation, the first string select transistor SST1 of the cell string in the first row can be turned on through the first string select line SSL1, and the second string select transistor SST2 of the cell string in the first row can be turned on through the corresponding string select line (e.g., the fifth string select line SSL5).

[0064] The first ground selection transistor GST1 in the first row of cells can be turned on via the first ground selection line GSL1, and the second ground selection transistor GST2 in the first row of cells can be turned on via the corresponding ground selection line (e.g., the third ground selection line GSL3).

[0065] The first memory cell MC1 to the sixteenth memory cell MC16 connected to the first string select line SSL1 may include a channel that each has a channel voltage through the following voltages: the voltage supplied to the channel from the first bit line BL1 through the first string select transistor SST1 and the second string select transistor SST2, or the voltage supplied from the common source line CSL through the first ground select transistor GST1 and the second ground select transistor GST2.

[0066] Reference Figure 2In the described configuration, the unit string (e.g., the third part unit string) that serves as a partial access target and is connected to the first bit line BL1 and the first string select line SSL1, and the unit string (e.g., the fourth part unit string) that is connected to the second bit line BL2 and the first string select line SSL1, can act as the load for the first word line WL1 to the sixteenth word line WL16, and therefore, the power consumption may increase when driving the word lines.

[0067] The first string select transistor SST1 in the second row of cells can be turned off via the second string select line SSL2, and the second string select transistor SST2 in the second row of cells can be turned off via the corresponding string select line (e.g., the sixth string select line SSL6).

[0068] The first ground selection transistor GST1 in the second row of the cell string can be turned on through the first ground selection line GSL1, and the second ground selection transistor GST2 in the second row of the cell string can be turned on through the corresponding ground selection line (e.g., the third ground selection line GSL3).

[0069] The first memory cell MC1 to the sixteenth memory cell MC16 connected to the second string select line SSL2 may include channels each having a channel voltage supplied from the common source line CSL through the first ground select transistor GST1 and the second ground select transistor GST2.

[0070] Reference Figure 2 In the described configuration, the unit string (e.g., the third part unit string) that serves as a partial access target and is connected to the first bit line BL1 and the first string select line SSL1, as well as the unit string (e.g., the fourth part unit string) that is connected to the second bit line BL2 and the first string select line SSL1 and the second string select line SSL2 (e.g., the fourth part unit string) can act as the load for the first word line WL1 to the sixteenth word line WL16, and therefore, the power consumption may increase when driving the word lines.

[0071] Because the cell strings connected to the third string select line SSL3, the fourth string select line SSL4, and the second ground select line GSL2 do not include the third portion of the cell strings, these cell strings can be included in the second portion of the cell strings, which does not include the cell strings that are the access targets. Because all the first string select transistors SST1, the second string select transistor SST2, the first ground select transistor GST1, and the second ground select transistor GST2 in the second portion of the cell strings are turned off, the second portion of the cell strings can not act as the load for the first word lines WL1 to the sixteenth word lines WL16.

[0072] like Figure 4 The shadow in the reference Figure 2 In the described structure, both the third and fourth part unit strings can serve as loads for the first word line WL1 to the sixteenth word line WL16. To prevent the aforementioned problems, this disclosure intends to provide embodiments in which at least some of the third and fourth part unit strings do not serve as word line loads.

[0073] Figure 5 An example of a method for performing a partial access operation by a non-volatile memory device 100 according to an embodiment of the present disclosure is shown in a state in which the non-volatile memory device prohibits at least some of the partial cell strings that are structurally associated with the partial cell string that is the target of the partial access from acting as the load of the word line.

[0074] refer to Figure 1 , Figure 2 and Figure 5 The non-volatile storage device 100 can be programmed with special memory cells. These special memory cells may include references. Figure 2 Some of the storage cells described are the first storage cell MC1 to the sixteenth storage cell MC16. Special storage cells may not be used for storing data (e.g., user data) and may be used to control the channels of the remaining storage cells (i.e., the storage cells used to store user data). The pattern of special data programmed in the special storage cells may be determined by the structure or operating characteristics of the non-volatile storage device 100.

[0075] A special memory cell can support the non-volatile memory device 100 to perform partial access operations in the following state: in this state, the non-volatile memory device 100 prohibits at least some of the partial cell strings (e.g., the fourth partial cell string) that are structurally associated with the cell string that is the target of the partial access (e.g., the third partial cell string) from being used as word line loads.

[0076] In operation S220, the non-volatile memory device 100 can access word lines and can access special word lines. For example, the non-volatile memory device 100 can apply a voltage to a special word line to bias or float the channel of a third portion of the cell string that is the target of a partial access operation. The non-volatile memory device 100 can apply a voltage to the word line to perform a partial access operation.

[0077] In operation S230, the non-volatile memory device 100 can access a portion of the bit lines. For example, the non-volatile memory device 100 can continue the partial access operation by accessing the portion of the bit lines corresponding to the third portion of the cell string that is the target of the partial access operation.

[0078] Figure 6 It shows in Figure 2An example of programming the first special memory cell SMC1 to the eighth special memory cell SMC8 in a memory block. (See reference) Figure 2 and Figure 6 In each cell string, the four memory cells adjacent to the first ground selection transistor GST1 and the second ground selection transistor GST2 (e.g., Figure 2 The first storage unit MC1 to the fourth storage unit MC4 can be programmed as the first special storage unit SMC1 to the fourth special storage unit SMC4.

[0079] In each cell string, the four memory cells adjacent to the first string select transistor SST1 and the second string select transistor SST2 (e.g., Figure 2 The thirteenth storage unit (MC13) to the sixteenth storage unit (MC16) can be programmed into the fifth special storage unit (SMC5) to the eighth special storage unit (SMC8).

[0080] In this embodiment, the first special storage units SMC1 to the fourth special storage units SMC4 and the fifth special storage units SMC5 to the eighth special storage units SMC8 can be programmed to have predetermined states containing non-user data. Here, user data can refer to information collected from users through various touchpoints such as websites, applications, and interactions, used to understand user behavior, preferences, and demographic data, thereby enabling strategic decision-making and personalized user experiences.

[0081] In each cell string, the storage cells located between the first special storage cells SMC1 to the fourth special storage cells SMC4 and the fifth special storage cells SMC5 to the eighth special storage cells SMC8 (e.g., Figure 2 The fifth storage unit MC5 to the twelfth storage unit MC12 can be used as the first storage unit MC1 to the eighth storage unit MC8 (e.g., a regular storage unit configured to store user data).

[0082] Each special memory cell can be programmed to have one of a plurality of different states. Different states can correspond to different threshold voltage ranges. For example, each special memory cell can be programmed to belong to a threshold voltage range corresponding to one of a first state S1 and a second state S2. In an embodiment, it is assumed that each voltage within the threshold voltage range of the second state S2 is higher than each voltage within the threshold voltage range of the first state S1. In an embodiment, at least some special memory cells commonly connected to a special word line can be programmed to have different threshold voltages depending on the direction of the bit line parallel to the bit line. In an embodiment, at least some special memory cells commonly connected to a special word line can be programmed to have different threshold voltages depending on the direction of the string select line parallel to the string.

[0083] In each cell string, the pattern of the state programmed in the first special memory cell SMC1 to the fourth special memory cell SMC4 can be the same as the pattern of the state programmed in the fifth special memory cell SMC5 to the eighth special memory cell SMC8.

[0084] In this embodiment, multiple bit lines BL, including the first bit line BL1 and the second bit line BL2, can be classified into multiple groups. These multiple groups can correspond to units of partial access operations. For example, when the non-volatile memory device 100 supports partial access operations in 8-bit units, the multiple bit lines BL can be classified into multiple groups, each comprising eight bit lines. When the non-volatile memory device 100 supports partial access operations in 8KB units, the multiple bit lines BL can be classified into multiple groups, each comprising 8KB bit lines.

[0085] In each of the multiple groups, the first special memory cells SMC1 to SMC4 or the fifth special memory cells SMC5 to SMC8, which share a ground selection line GSL1 or GSL2, can have different state modes. Based on the different modes, the first special memory cells SMC1 to SMC4 and the fifth special memory cells SMC5 to SMC8 can enable the application of a channel load of a portion of the cell string as the target of a partial access operation to only the first word lines WL1 to WL8 connected to the first memory cells MC1 to MC8.

[0086] Figure 7 An example is shown where a non-volatile memory device 100 only bears the load of a third portion of the cell string as the target of a partial access operation. (Reference) Figure 1 and Figure 7 The non-volatile storage device 100 can apply one of a first voltage V1 and a second voltage V2 to each of the first special word lines SWL1 to the eighth special word lines SWL8, which are connected to the first special memory cells SMC1 to the eighth special memory cells SMC8.

[0087] The first voltage V1 can have a voltage level between the threshold voltage range of the first state S1 and the threshold voltage range of the second state S2. That is, the first voltage V1 can turn on the special memory cell of the first state S1 and turn off the special memory cell of the second state S2.

[0088] The second voltage V2 can have a voltage level higher than the threshold voltage range of the second state S2. That is, the second voltage V2 can turn on the special memory cell of the first state S1 and can also turn on the special memory cell of the second state S2.

[0089] When a first voltage V1, a second voltage V2 is applied to the first special word line SWL1 to the fourth special word line SWL4 respectively, the first special memory cell SMC1 to the fourth special memory cell SMC4, which are connected to the first bit line BL1 and the first string select line SSL1 and are located in the first row and the first column of the third part of the cell string, can be turned on.

[0090] When a first voltage V1, a second voltage V2 is applied to the fifth special word line SWL5 to the eighth special word line SWL8 respectively, the fifth special memory cell SMC5 to the eighth special memory cell SMC8, which are connected to the first bit line BL1 and the first string select line SSL1 and are located in the first row and the first column of the third part of the cell string, can be turned on.

[0091] Because the first ground selection transistor GST1 and the second ground selection transistor GST2, as well as the first string selection transistor SST1 and the second string selection transistor SST2, located in the first row and the first column of the third part of the cell string are also turned on, the third part of the cell string, which is the target of the partial access operation, can act as the load of the first word line WL1 to the eighth word line WL8.

[0092] When a first voltage V1, a second voltage V2, a third voltage V1, a fourth voltage V2 are applied to the first special word line SWL1 to the fourth special word line SWL4 respectively, the first special memory cell SMC1, the second special memory cell SMC2, and the fourth special memory cell SMC4 of the fourth part of the cell string located in the second row and the first column, which are connected to the first bit line BL1 and the second string select line SSL2, can be turned on, and the third special memory cell SMC3 of the fourth part of the cell string can be turned off.

[0093] When a first voltage V1, a second voltage V2, and a third voltage V2 are applied to the fifth special word line SWL5 to the eighth special word line SWL8 respectively, the fifth special memory cell SMC5, the sixth special memory cell SMC6, and the eighth special memory cell SMC8 of the fourth part of the cell string located in the second row and the first column, which are connected to the first bit line BL1 and the second string select line SSL2, can be turned on, and the seventh special memory cell SMC7 of the fourth part of the cell string can be turned off.

[0094] The fourth segment of the cell string located in the second row and first column can be disconnected from the common source line CSL through the turned-off third special memory cell SMC3, and can be disconnected from the first word line BL1 through the turned-off first string select transistor SST1, second string select transistor SST2, and the turned-off seventh special memory cell SMC7. Therefore, the fourth segment of the cell string located in the second row and first column can be in a floating state and can not act as a load for the first word lines WL1 to the eighth word lines WL8.

[0095] When a first voltage V1, a second voltage V2, and a third voltage V1, a fourth voltage V2 are applied to the first special word line SWL1 to the fourth special word line SWL4 respectively, the first special memory cell SMC1, the third special memory cell SMC3, and the fourth special memory cell SMC4 of the fourth part of the cell string located in the first row and the second column, which are connected to the second bit line BL2 and the first string select line SSL1, can be turned on, and the second special memory cell SMC2 of the fourth part of the cell string can be turned off.

[0096] When a first voltage V1, a second voltage V2, and a third voltage V1 are applied to the fifth special word line SWL5 to the eighth special word line SWL8 respectively, the fifth special memory cell SMC5, the seventh special memory cell SMC7, and the eighth special memory cell SMC8 of the fourth part of the cell string located in the first row and the second column, which are connected to the second bit line BL2 and the first string select line SSL1, can be turned on, and the sixth special memory cell SMC6 of the fourth part of the cell string can be turned off.

[0097] The fourth part of the cell string located in the first row and second column can be disconnected from the common source line CSL through the second special memory cell SMC2, which is turned off, and can be disconnected from the second bit line BL2 through the sixth special memory cell SMC6, which is turned off. Therefore, the fourth part of the cell string located in the first row and second column can be in a floating state and can not act as a load for the first word line WL1 to the eighth word line WL8.

[0098] For reference Figure 7 As described, the non-volatile storage device 100 according to embodiments of this disclosure can reduce the load on the word lines during partial access operations by using some of the memory cells as special memory cells. Therefore, the amount of power required to drive the word lines can be reduced.

[0099] In an embodiment, during a full access operation, the non-volatile memory device 100 according to an embodiment of the present disclosure can apply a second voltage V2 to all first special word lines SWL1 to eighth special word lines SWL8. Because the first special memory cells SMC1 to eighth special memory cells SMC8 of the cell string are turned on, the cell string can be accessed by controlling the first ground select transistor GST1 and the second ground select transistor GST2, as well as the first string select transistor SST1 and the second string select transistor SST2.

[0100] As another example, in a full access operation, the non-volatile storage device 100 according to an embodiment of the present disclosure can use the state mode of the first special memory cell SMC1 to the eighth special memory cell SMC8 by applying a first voltage V1 to a second voltage V2 to the first special word line SWL1 to the eighth special word line SWL8.

[0101] For example, in Figure 7 In the first row of special word lines, when a second voltage V2 is applied to the second special word line SWL2 and the sixth special word line SWL6, the second special memory cell SMC2 and the sixth special memory cell SMC6 of the first row of cell strings can be turned on. That is, the first row of cell strings can be selected for full access operations. Therefore, the load on the cell strings from the first word line WL1 to the eighth word line WL8 during full access operations can be reduced. Similarly, when the non-volatile memory device 100 applies a first voltage V1 and a second voltage V2 to the first special word lines SWL1 to the eighth special word lines SWL8, the non-volatile memory device 100 can select the second row of cell strings for full access operations and can prevent the load on the first row of cell strings from being applied to the first word lines WL1 to the eighth word lines WL8.

[0102] In this embodiment, the number of special storage units used in a unit string is not limited. Furthermore, the number of programmable states in each special storage unit is not limited.

[0103] In the embodiment, the operation of programming the first special memory cell SMC1 to the eighth special memory cell SMC8 can be controlled by the capacitor control circuit CC, and the operation of appropriately applying the first voltage V1 and the second voltage V2 for partial access operation to the first special word line SWL1 to the eighth special word line SWL8 can be controlled.

[0104] Figure 8 An example of a group of multiple bit lines (BL) is shown. (Reference) Figure 8 The diagram shows the cell strings connected to the first bit line BL1 through the sixteenth bit line BL16. Special memory cells (SMCs) can be set at opposite ends of each cell string.

[0105] In an embodiment, each of the plurality of groups may include four bit lines, and therefore, the non-volatile memory device 100 may support partial access operations corresponding to 4-bit units or multiples of 4-bit units.

[0106] In embodiments, the group of bit lines can be implemented depending on the input and output structure of the non-volatile memory device 100. For example, the input and output structure of the non-volatile memory device 100 can be based on a finger structure. In a finger-structured input and output structure, the non-volatile memory device 100 can select non-adjacent bit lines (e.g., BL1, BL5, BL9, and BL13) as targets for input and output to external devices (e.g., a memory controller or storage controller). Therefore, the non-volatile memory device 100 can select non-adjacent bit lines BL1, BL5, BL9, and BL13 as a group.

[0107] and Figure 8 As shown in the example, you can select a group that includes bit lines that are not adjacent to it, such as a group that includes bit lines BL2, BL6, BL10 and BL14, a group that includes bit lines BL3, BL7, BL11 and BL15, and a group that includes bit lines BL4, BL8, BL12 and BL16.

[0108] The number of bit lines included in each group of multiple bit lines is not limited. The number of bit lines included in each group may vary depending on the structural characteristics or required specifications of the non-volatile memory device 100.

[0109] Figure 9 Another example of a group of multiple bit lines (BL) is shown. (Reference) Figure 9 The diagram shows the cell strings connected to the first bit line BL1 through the sixteenth bit line BL16. Special memory cells (SMCs) can be set at opposite ends of each cell string.

[0110] In an embodiment, each of the plurality of groups may include four bit lines, and therefore, the non-volatile memory device 100 may support partial access operations corresponding to 4-bit units or multiples of 4-bit units.

[0111] In embodiments, the grouping of bit lines can be implemented depending on the input and output structure of the non-volatile memory device 100. For example, the input and output structure of the non-volatile memory device 100 can be based on a chunk structure. In the chunk structure of the input and output structure, the non-volatile memory device 100 can select adjacent bit lines (e.g., BL1, BL2, BL3, and BL4) as targets for input and output to external devices (e.g., a memory controller or storage controller). Therefore, the non-volatile memory device 100 can select adjacent bit lines (e.g., BL1, BL2, BL3, and BL4) as a group.

[0112] and Figure 9 As shown in the example, you can select a group that includes the bit lines adjacent to it, such as a group that includes bit lines BL5, BL6, BL7 and BL8, a group that includes bit lines BL9, BL10, BL11 and BL12, and a group that includes bit lines BL13, BL14, BL15 and BL16.

[0113] The number of bit lines included in each group of multiple bit lines is not limited. The number of bit lines included in each group may vary depending on the structural characteristics or required specifications of the non-volatile memory device 100.

[0114] Figure 10 An example of a non-volatile storage device 100' is shown, which is used to perform partial access operations when at least some of the partial cell strings in a partial cell string do not act as word line loads.

[0115] refer to Figure 10 The non-volatile storage device 100' includes a first PL1, a second PL2, a first row decoder RDC1, a second row decoder RDC2, a first page buffer PB1, a second page buffer PB2, a pass / fail check block PFC, a first data input and output circuit DIO1, a second data input and output circuit DIO2, and a control logic circuit CL.

[0116] and Figure 1 Compared to the non-volatile storage device 100, the serial select line SSL and the ground select line GSL can be separated between the first PL1 and the second PL2, and are not connected to each other. For example, the first line decoder RDC1 can select the first PL1 by using the serial select line SSL and the ground select line GSL. Similarly, the second line decoder RDC2 can select the second PL2 by using the serial select line SSL and the ground select line GSL.

[0117] In this embodiment, the word line WL can be connected together between the first PL1 and the second PL2. The first row decoder RDC1 and the second row decoder RDC2 can be biased by the common word line WL.

[0118] Apart from the connection between the first PL1 and the second PL2, components of the non-volatile storage device 100' can be configured to connect with a reference. Figure 1 The components described in the non-volatile storage device 100 are the same. Therefore, additional descriptions will be omitted to avoid redundancy.

[0119] In an embodiment, each of the first storage blocks BLK1 to the z-th storage block BLKz of the first PL1 and the second PL2 may include a reference. Figure 2 and Figure 4 or Figure 6 and Figure 7 The described unit string.

[0120] Figure 11 It shows Figure 10 An example of the operation method of the non-volatile storage device 100'. (See reference...) Figure 10 and Figure 11 In operation S310, the non-volatile memory device 100' can bias the serial select line SSL and ground select line GSL of the selected and unselected chips.

[0121] For example, one of the first row decoders RDC1 and the second row decoder RDC2 can bias the voltage used for partial access operations onto the chip in the first PL1 and the second PL2 corresponding to one row decoder via the serial select line SSL and the ground select line GSL. The other of the first row decoders RDC1 and the second row decoder RDC2 can bias the voltage used for floating cell strings onto the chip in the first PL1 and the second PL2 corresponding to the other row decoder via the serial select line SSL and the ground select line GSL.

[0122] In operation S320, non-volatile memory device 100' can access word lines. When non-volatile memory device 100' accesses word lines, the first PL1 and the second PL2 can bias the cell strings of the first PL1 and the first PL2 through a common word line WL.

[0123] In operation S330, the non-volatile memory device 100' can access bit lines selected for partial access operations.

[0124] Figure 12 The unit string is shown to pass through Figure 10 Non-volatile memory device 100' and Figure 11 An example of an operation method that is floated. Figure 12 In this configuration, bit lines BL1 to BL8 can be included in the first PL1, and bit lines BL9 to BL16 can be included in the second PL2. In this embodiment, it is assumed that bit lines BL1 to BL8 share a common source line, and bit lines BL9 to BL16 share a common source line.

[0125] refer to Figure 2 , Figure 10 and Figure 12 When a partial access operation is performed on bit lines BL1 to BL8, the first row decoder RDC1 can turn on the string select transistor and ground select transistor of the cell string corresponding to bit lines BL1 to BL8. Therefore, the load of the cell string connected to bit lines BL1 to BL8, which is the target of the partial access operation, can apply the load of the cell string to word line WL as follows.

[0126] The second-line decoder RDC2 can turn off the string select transistor and ground select transistor for the cell strings corresponding to the ninth bit line BL9 through the sixteenth bit line BL16. Therefore, during partial access operations, the load connected to the cell strings of the ninth bit line BL9 through the sixteenth bit line BL16 can be omitted from the word line WL.

[0127] As another example, partial access operations can be performed on some bit lines from the first bit line BL1 to the eighth bit line BL8 (e.g., the first bit line BL1 to the fourth bit line BL4). The first row decoder RDC1 can turn on the string select transistors for the cell strings corresponding to the first bit lines BL1 to the fourth bit lines BL4. The first row decoder RDC1 can turn off the string select transistors for the cell strings corresponding to the fifth bit line BL5 to the eighth bit line BL8. The first row decoder RDC1 can turn on the ground select transistors for the cell strings corresponding to the first bit lines BL1 to the eighth bit lines BL8.

[0128] The second-line decoder RDC2 can turn off the string select transistor and ground select transistor corresponding to the ninth bit line BL9 through the sixteenth bit line BL16. Therefore, the load of the cell string connected to the ninth bit line BL9 through the sixteenth bit line BL16, which is not a target of part of the access operation, can be omitted from the word line WL.

[0129] For example, when a partial access operation is performed on the first bit line BL1 to the fourth bit line BL4, the word line WL can only bear the capacitance of the cell string corresponding to the first bit line BL1 to the eighth bit line BL8, and not the capacitance of the cell string corresponding to the first bit line BL1 to the sixteenth bit line BL16.

[0130] Figure 13 The unit string is shown to pass through Figure 10 Non-volatile memory device 100' and Figure 11 This section provides an example of a floating application using the specified operation method. Figure 13 In this configuration, bit lines BL1 to BL8 may be included in the first PL1, and bit lines BL9 to BL16 may be included in the second PL2. In this embodiment, it is assumed that bit lines BL1 to BL8 share a common source line, and bit lines BL9 to BL16 share a common source line. (See reference...) Figures 1 to 9 The special storage unit can be set in Figure 13 The opposite ends of the unit string.

[0131] refer to Figure 7 , Figure 10 and Figure 13 When a partial access operation is performed on the first bit line BL1 and the fifth bit line BL5, the first row decoder RDC1 can turn on the string select transistor and the ground select transistor corresponding to the cell string from the first bit line BL1 to the eighth bit line BL8. Furthermore, the first row decoder RDC1 can turn on the special memory cell SMC of the cell string corresponding to the first bit line BL1 and the fifth bit line BL5, and can control the special memory cell SMC of the cell string corresponding to the second bit line BL2 to the fourth bit line BL4 and the sixth bit line BL6 to the eighth bit line BL8, so that the current corresponding to the second bit line BL2 to the fourth bit line BL4 and the sixth bit line BL6 to the eighth bit line BL8 is blocked. Therefore, the load of the cell string connected to the first bit line BL1 and the fifth bit line BL5, which is the target of partial access, can be applied to the word line WL.

[0132] The second-line decoder RDC2 can turn off the string select transistor and ground select transistor for the cell strings corresponding to the ninth bit line BL9 through the sixteenth bit line BL16. Therefore, the load of the cell strings connected to the ninth bit line BL9 through the sixteenth bit line BL16, which are not targeted as part of the access operation, can be omitted from the word line WL.

[0133] As described above, since the SSL and GSL of the first PL1 and the second PL2 are separated, and the special memory cell SMC is set in the cell string, the minimum unit of partial access operation can be further reduced.

[0134] In this embodiment, the capacitor control circuit CC can control the following operations: floating the cell string of one of the first PL1 and the second PL2 by using the first row decoder RDC1 and the second row decoder RDC2. Furthermore, the capacitor control circuit CC can control the following operations: programming the special memory cell SMC and appropriately applying the first voltage V1 and the second voltage V2 for partial access operations to the special word line.

[0135] Figure 14 It shows Figure 1 Non-volatile storage device 100 or Figure 10 An example of the operation method of the non-volatile storage device 100'. (See reference) Figure 1 , Figure 10 and Figure 14 In operation S410, non-volatile memory devices 100 or 100' can bias selected bit lines and unselected bit lines.

[0136] For example, the first page buffer PB1 and the second page buffer PB2 can apply a third voltage V3 to the selected bit lines among the multiple bit lines used for partial access operations. For example, the third voltage V3 can be a voltage biased to the cell string through a string select transistor used for partial access operations (or access operations), and can have a level where the string select transistor is not turned off.

[0137] The first page buffer PB1 and the second page buffer PB2 can apply a fourth voltage V4 to the bit lines that are not selected for partial access operations. For example, the fourth voltage V4 can have a level such that when it is supplied to the string select transistor, the string select transistor is turned off.

[0138] In operation S420, non-volatile memory device 100' can access word lines. When non-volatile memory device 100' accesses word lines, the first PL1 and the second PL2 can bias the cell strings of the first PL1 and the first PL2 through a common word line WL.

[0139] In operation S430, the non-volatile memory device 100' can access some bit lines selected for partial access operations. In an embodiment, the string selection transistors of the cell strings corresponding to bit lines not selected for partial access operations can be turned off. Therefore, the bit lines not selected for partial access can be avoided.

[0140] Figure 15 It shows in Figure 2 Execute in the unit string Figure 14 Examples of operation methods. (See reference) Figure 1 or Figure 10 as well as Figure 14 and Figure 15You can select the cell string located in the first row and first column that is connected to the first selection line SSL1 and the first bit line BL1 for partial read operations.

[0141] A third voltage V3 can be applied to the first bit line BL1, and the first string selection transistor SST1 and the second string selection transistor SST2 located in the first row and first column of the third part of the cell string can be turned on. The first ground selection transistor GST1 and the second ground selection transistor GST2 of the third part of the cell string can also be turned on. Therefore, the third part of the cell string located in the first row and first column can act as the load for the first word line WL1 to the sixteenth word line WL16.

[0142] The first string select transistor SST1 and the second string gate transistor SST2, located in the second row and first column of the fourth part of the cell string connected to the second string select line SSL2 and the first bit line BL1, can be turned off, while the first ground select transistor GST1 and the second ground select transistor GST2 of the fourth part of the cell string can be turned on. Therefore, the fourth part of the cell string located in the second row and first column can act as the load for the first word line WL1 to the sixteenth word line WL16.

[0143] In this embodiment, the second bit line BL2 may not be selected for partial access operations. Therefore, the string select transistor connected to the second bit line BL2 can be turned off by the fourth voltage V4.

[0144] The first ground selection transistor GST1 and the second ground selection transistor GST2, located in the first row and second column, and connected to the first string selection line SSL1 and the second bit line BL2, can be turned on. Therefore, the fourth string of cells located in the first row and second column can act as the load for the first word line WL1 to the sixteenth word line WL16.

[0145] The first ground selection transistor GST1 and the second ground selection transistor GST2, located in the second row and second column, and connected to the second string selection line SSL2 and the second bit line BL2, can be turned on. Therefore, the fourth part of the cell string located in the second row and second column can act as the load for the first word line WL1 to the sixteenth word line WL16.

[0146] As described above, the non-volatile memory device 100 according to embodiments of the present disclosure can suppress voltage supply from the first bit line BL1 through the first string select transistor SST1 and the second string select transistor SST2 to the cell string located in the second row and first column, and thus can reduce the load on the cell string located in the second row and first column.

[0147] In an embodiment, turning off the first string select transistor SST1 or the second string select transistor SST2 by using the fourth voltage V4 of the second bit line BL2 may include: removing the on-condition of the first string select transistor SST1 or the second string select transistor SST2 by setting the fourth voltage V4 to be higher than or equal to the gate voltage of the first string select transistor SST1 or the second string select transistor SST2.

[0148] In embodiments, partial access commands (or full access commands) may include: partial write commands (or full write commands), partial read commands (or full read commands), partial program verification read commands (or full program verification read commands), or partial erase verification read commands (or full erase verification read commands). Without departing from the technical spirit of this disclosure, the references may be modified and applied depending on the type of partial access command. Figures 1 to 15 The method described.

[0149] In an embodiment, the operation of applying a third voltage V3 and a fourth voltage V4 for partial access operations to multiple bit lines BL can be controlled by a capacitor control circuit CC.

[0150] Figure 16 A storage device 200 according to an embodiment of the present disclosure is shown. Reference Figure 16 The storage device 200 may include a non-volatile storage device 210, a memory controller 220, and an external buffer 230. The non-volatile storage device 210 may include multiple storage cells. Each of the multiple storage cells may store two bits or more.

[0151] For example, the non-volatile memory device 210 may include at least one of a variety of non-volatile memory devices such as flash memory devices, phase-change memory devices, ferroelectric memory devices, magnetic memory devices, and resistive memory devices.

[0152] The memory controller 220 can receive various requests from an external host device for writing or reading data from the non-volatile storage device 210. The memory controller 220 can store (or buffer) user data communicating with the external host device in an external buffer 230, and can also store metadata for managing the storage device 200 in the external buffer 230.

[0153] The memory controller 220 can access the non-volatile memory device 210 via the first signal line SIGL1 and the second signal line SIGL2. For example, the memory controller 220 can send commands and addresses to the non-volatile memory device 210 via the first signal line SIGL1. The memory controller 220 can also exchange data with the non-volatile memory device 210 via the first signal line SIGL1. In embodiments, the signal lines for communicating commands and addresses and for exchanging data can be the same signal line or separate signal lines.

[0154] The memory controller 220 can send a first control signal to the non-volatile memory device 210 via the second signal line SIGL2. The memory controller 220 can receive a second control signal from the non-volatile memory device 210 via the second signal line SIGL2.

[0155] In an embodiment, the memory controller 220 may be configured to control two or more non-volatile memory devices. The memory controller 220 may independently provide a first signal line and a second signal line for each of the two or more non-volatile memory devices.

[0156] As another example, the memory controller 220 may share a first signal line with two or more non-volatile memory devices. The memory controller 220 may share some of the second signal lines with two or more non-volatile memory devices, and may provide other signal lines of the second signal line independently.

[0157] External buffer 230 may include random access memory. For example, external buffer 230 may include at least one of dynamic random access memory, phase change random access memory, ferroelectric random access memory, magnetic random access memory, and resistive random access memory.

[0158] The memory controller 220 may include a bus 221, a host interface 222, an internal buffer 223, a processor 224, a buffer controller 225, a memory manager 226, and an error correction code (ECC) block 227.

[0159] Bus 221 provides a communication channel between components of memory controller 220. Host interface 222 can receive various requests from external host devices and can parse the received requests. Host interface 222 can store the parsed requests in internal buffer 223.

[0160] Host interface 222 can send various responses to external host devices. Host interface 222 can exchange signals with external host devices according to a given communication protocol. Internal buffer 223 may include random access memory. For example, internal buffer 223 may include static random access memory or dynamic random access memory.

[0161] Processor 224 can execute an operating system or firmware to drive memory controller 220. Processor 224 can read parsed requests stored in internal buffer 223 and can generate commands and addresses for controlling non-volatile memory device 210. Processor 224 can provide the generated commands and addresses to memory manager 226.

[0162] Processor 224 can store various metadata used for managing storage device 200 in internal buffer 223. Processor 224 can access external buffer 230 through buffer controller 225. Processor 224 can control buffer controller 225 and memory manager 226 so that user data stored in external buffer 230 is provided to non-volatile storage device 210.

[0163] Processor 224 can control host interface 222 and buffer controller 225 to provide data stored in external buffer 230 to external host devices. Processor 224 can control buffer controller 225 and memory manager 226 to store data received from non-volatile storage device 210 in external buffer 230. Processor 224 can control host interface 222 and buffer controller 225 to store data received from external host devices in external buffer 230.

[0164] Under the control of processor 224, buffer controller 225 can write data to or read data from external buffer 230. Memory manager 226 can communicate with non-volatile memory device 210 via first signal line SIGL1 and second signal line SIGL2 under the control of processor 224.

[0165] The memory manager 226 can access the non-volatile memory device 210 under the control of the processor 224. For example, the memory manager 226 can access the non-volatile memory device 210 via the first signal line SIGL1 and the second signal line SIGL2. The memory manager 226 can communicate with the non-volatile memory device 210 based on a standard-defined protocol or a manufacturer-defined protocol.

[0166] Error correction code block 227 can perform error correction encoding on the data to be provided to non-volatile storage device 210 by using error correction code ECC. Error correction code block 227 can perform error correction decoding on the data received from non-volatile storage device 210 by using error correction code ECC.

[0167] In this embodiment, the external buffer 230 and buffer controller 225 may be omitted from the storage device 200. When the external buffer 230 and buffer controller 225 are omitted, the functions described as being performed by the external buffer 230 or buffer controller 225 may be performed by the internal buffer 223.

[0168] In an embodiment, the non-volatile storage device 210 may include a reference. Figures 1 to 15 The non-volatile memory device 100 or non-volatile memory device 100' is described. The non-volatile memory device 210 can access word lines based on a partial capacitance in response to a partial access command, and can access word lines based on the full capacitance in response to a full access command. Therefore, the power required to drive word lines by the non-volatile memory device 210 can be reduced.

[0169] Figure 17 This is a diagram of a system that utilizes a storage device according to an embodiment. Figure 17 The system 1000 can essentially be a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Figure 17 System 1000 is not necessarily limited to mobile systems and can be a PC, laptop, server, media player, or automotive device (e.g., navigation device).

[0170] refer to Figure 17 System 1000 may include a main processor 1100, memory (e.g., 1200a and 1200b), and storage devices (e.g., 1300a and 1300b). Furthermore, system 1000 may include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0171] The main processor 1100 can control all operations of the system 1000, and more specifically, can control the operations of other components included in the system 1000. The main processor 1100 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor.

[0172] The main processor 1100 may include at least one CPU core 1110 and a controller 1120 configured to control memory 1200a and memory 1200b and / or storage devices 1300a and 1300b. In some embodiments, the main processor 1100 may also include an accelerator 1130, which is dedicated circuitry for high-speed data operations such as artificial intelligence (AI) data operations. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU) and is implemented as a chip physically separated from other components of the main processor 1100.

[0173] Memory 1200a and memory 1200b can be used as the main storage devices of system 1000. While each of memory 1200a and memory 1200b may include volatile memory such as static random access memory (SRAM) and / or dynamic RAM (DRAM), each of memory 1200a and memory 1200b may include non-volatile memory such as flash memory, phase-change RAM (PRAM), and / or resistive RAM (RRAM). Memory 1200a and memory 1200b can be implemented in the same package as the main processor 1100.

[0174] Storage devices 1300a and 1300b can be used as non-volatile storage devices configured to store data regardless of whether they are powered on, and have a larger storage capacity than memory 1200a and 1200b. Storage devices 1300a and 1300b may respectively include storage controllers (STRG CTRL) 1310a and 1310b, and NVMs (non-volatile memory) 1320a and 1320b, which are configured to store data via the control of storage controllers 1310a and 1310b. While NVMs 1320a and 1320b may include flash memory with a two-dimensional (2D) or three-dimensional (3D) V-NAND structure, they may also include other types of NVMs, such as PRAM and / or RRAM.

[0175] Storage devices 1300a and 1300b may be physically separated from the main processor 1100 and included in the system 1000, or implemented in the same package as the main processor 1110. Furthermore, storage devices 1300a and 1300b may be of the type of solid-state drive (SSD) or memory card, and may be detachably combined with other components of the system 1000 via an interface (e.g., connection interface 1480 described below). Storage devices 1300a and 1300b may be devices applying standard protocols, such as Universal Flash Memory (UFS), embedded multimedia card (eMMC), or Non-Volatile Memory Fast (NVMe), but are not limited to these.

[0176] Image capture device 1410 can capture still images or moving images. Image capture device 1410 may include a camera, a portable video camera, and / or a webcam.

[0177] User input device 1420 can receive various types of data input by the user of system 1000, and includes a touchpad, keypad, keyboard, mouse and / or microphone.

[0178] Sensor 1430 can detect various types of physical quantities that can be obtained from outside the system 1000 and convert the detected physical quantities into electrical signals. Sensor 1430 may include temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors, and / or gyroscope sensors.

[0179] Communication device 1440 can send and receive signals between other devices outside system 1000 according to various communication protocols. Communication device 1440 may include an antenna, transceiver, and / or modem.

[0180] The display 1450 and the speaker 1460 can be used as output devices, which are configured to output visual and auditory information to the user of the system 1000, respectively.

[0181] The power supply device 1470 can appropriately convert the power supplied from the battery (not shown) embedded in the system 1000 and / or an external power source, and supply the converted power to each component of the system 1000.

[0182] The connection interface 1480 provides a connection between the system 1000 and an external device that connects to the system 1000 and can send and receive data from the system 1000. The connection interface 1480 can be implemented using various interface schemes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, eMMC interface, UFS interface, Embedded UFS (eUFS) interface, and Compact Flash (CF) card interface.

[0183] In the embodiment, reference Figure 16 The described storage device 200 can be implemented using each of storage devices 1300a and 1300b. Each of NVM 1320a and NVM 1320b may include Figure 16 The non-volatile memory device 210. Each of NVM 1320a and NVM 1320b can access the word line based on partial capacitance in response to a partial access command, and can access the word line based on full capacitance in response to a full access command. Therefore, the power required to drive the word line in each of NVM 1320a and NVM 1320b can be reduced.

[0184] In the above embodiments, the components according to this disclosure are described using the terms "first," "second," "third," etc. However, the terms "first," "second," "third," etc., can be used to distinguish components from each other and do not limit this disclosure. For example, the terms "first," "second," "third," etc., do not imply any form of order or numerical meaning.

[0185] In the above embodiments, boxes are used to indicate components according to embodiments of this disclosure. Boxes can be implemented as various hardware devices such as integrated circuits (ICs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs); firmware driving the hardware device; software such as an application program; or a combination of hardware devices and software. Furthermore, boxes may include circuits implemented using semiconductor elements in integrated circuits, or circuits registered as intellectual property (IP).

[0186] According to embodiments of this disclosure, when a portion of a page is accessed, the word line is biased to correspond to the capacitance of that portion of the page, rather than the capacitance of the entire page. Therefore, a non-volatile memory device with reduced power consumption, a method of operating the non-volatile memory device, and a memory device including the non-volatile memory device are provided.

[0187] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made to this disclosure without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A non-volatile storage device, the non-volatile storage device comprising: A storage cell array comprising multiple cell strings having multiple storage cells classified as pages; A row decoder, which is connected to the memory cell array via a serial select line, a ground select line, and a word line, and is configured to apply a voltage to the serial select line and the ground select line; and Page buffers, which are connected to the memory cell array via bit lines and configured to apply voltage to the bit lines, The row decoder is configured to apply a first voltage to the word line in response to a read command for the first page being received from an external device, corresponding to a first capacitance of a memory cell in the first page. The row decoder is configured to: in response to a read command for a first portion of the first page being received from the external device, apply a second voltage to the word line corresponding to a second capacitor of a memory cell in the first portion of the page. Each cell string's channel is configured to have a channel voltage in response to the voltage being applied to the string select line, the ground select line, the word line, and the bit line. The first capacitor is formed between the channel of the cell string connected to the bit line associated with the first page and the word line to which the first voltage is applied. The second capacitor is formed between the channel of the cell string connected to the bit line associated with the first portion of the page and the word line to which the second voltage is applied, and The amount of the second capacitor is less than the amount of the first capacitor.

2. The non-volatile storage device according to claim 1, wherein, The page buffer is configured to access memory cells connected to bit lines corresponding to the first portion of the page.

3. The non-volatile storage device according to claim 1, wherein: Each of the plurality of cell strings includes: a ground selection transistor, the ground selection transistors being stacked sequentially; a memory cell, the memory cell being located on the ground selection transistor; and a string selection transistor, the string selection transistor being located on the memory cell. The ground selection transistor is connected to the ground selection line. The string select transistor is connected to the string select line. The storage unit is connected to the word line. The storage unit includes special storage units and normal storage units. The special storage units are configured to be programmed to have a predetermined state, and the normal storage units are configured to store user data. The word lines include special word lines and normal word lines. The special word lines are connected to the special memory cells, and the normal word lines are connected to the normal memory cells.

4. The non-volatile storage device according to claim 3, wherein, The row decoder is configured to: in response to the read command for the first page, activate the special storage unit, and The row decoder is configured to selectively turn the special storage unit on and off in response to the read command for the first portion of the page.

5. The non-volatile storage device according to claim 3, wherein, The special memory cell includes a first special memory cell adjacent to the ground selection transistor and a second special memory cell adjacent to the string selection transistor, and The normal storage unit is located between the first special storage unit and the second special storage unit.

6. The non-volatile storage device according to claim 5, wherein, The row decoder is configured to: in response to the read command for the first portion of the page, turn on the first special storage unit and the second special storage unit corresponding to the first portion of the page, and turn off the first special storage unit and the second special storage unit not corresponding to the first portion of the page.

7. The non-volatile storage device according to claim 3, wherein, The special storage cell is programmed to have one of a plurality of threshold voltages.

8. The non-volatile storage device according to claim 7, wherein, Special memory cells that are connected together to a special word line are programmed to have different threshold voltages depending on the orientation of the bit line.

9. The non-volatile storage device according to claim 7, wherein, Special memory cells connected together to a special word line are programmed to have different threshold voltages depending on the direction of the string select line.

10. The non-volatile storage device according to claim 7, wherein, The plurality of storage cells are classified into multiple groups depending on the orientation of the bit lines, and In this context, special memory cells connected to a special word line are programmed to have the same threshold voltage in the same group and to have different threshold voltages in different groups.

11. The non-volatile storage device according to claim 1, wherein, The storage cell array includes a first slab and a second slab, the first slab including a first storage cell, and the second slab including a second storage cell. The row decoder includes a first row decoder connected to the first chip and a second row decoder connected to the second chip.

12. The non-volatile storage device according to claim 11, wherein, The first line decoder and the second line decoder are configured to: apply voltage to the string select line and the ground select line in response to the read command for the first page, and One of the first row decoder and the second row decoder is configured to apply voltage to some of the string select lines and some of the ground select lines in response to the read command for the first portion of the page.

13. The non-volatile storage device according to claim 11, wherein, The first and second pieces are connected together to the word line. The first chip is connected to the first row decoder via a first select line and a first ground select line, and The second chip is connected to the second row decoder via a second select line and a second ground select line.

14. The non-volatile storage device according to claim 1, wherein, The page buffer is configured to apply a voltage to the bit line in response to a read command for the first page to access the memory cell of the first page, and The page buffer is configured to: in response to a read command for the first portion of the page, apply a voltage to the bit line corresponding to the memory cell of the first portion of the page to access the memory cell of the first portion of the page.

15. The non-volatile storage device according to claim 14, wherein, The page buffer is configured to: in response to the read command for the first portion of the page, apply a voltage to a bit line among the bit lines that does not correspond to the memory cell of the first portion of the page, so as to turn off the string select transistor that does not correspond to the memory cell of the first portion of the page.

16. A method of operating a non-volatile storage device, the non-volatile storage device comprising a memory cell array, the memory cell array comprising a plurality of cell strings, the plurality of cell strings having a plurality of memory cells classified as pages, the method comprising: Voltage is applied to the memory cell array via the serial select line, the ground select line, and the bit line; In response to receiving a read command for the first page from an external device, a first voltage is applied to the word line to correspond to the first capacitance of the memory cell of the first page; In response to receiving a read command for a first portion of the first page from the external device, a second voltage is applied to the word line to correspond to the second capacitance of the memory cell of the first portion of the page; and By applying voltages to the string select line, the ground select line, the word line, and the bit line, a channel with a channel voltage is formed for each cell string. The first capacitor is formed between the channel of the cell string connected to the bit line associated with the first page and the word line to which the first voltage is applied, and The second capacitor, unlike the first capacitor, is formed between the channel of the cell string connected to the bit line associated with the first partial page and the word line to which the second voltage is applied.

17. The method of claim 16, wherein, The second capacitor, which applies the second voltage to the word line to correspond to the memory cell of the first portion of the page, includes: The first special memory cell connected to the first special word line in the word lines is connected; and Selectively turn on and off the second special memory cell connected to the second special word line among the word lines.

18. The method of claim 16, wherein, The second capacitor, which applies the second voltage to the word line to correspond to the memory cell of the first portion of the page, includes: The first string selection transistor associated with the first portion of the page is turned on via the first row decoder associated with the first portion of the page; and The second string selection transistor, which is not associated with the first portion of the page, is turned off by the second row decoder.

19. The method of claim 16, wherein, Applying the voltage to the memory cell array via the string select line, the ground select line, and the bit line includes: Apply a voltage to the bit line associated with the first portion of the page for access; and A voltage is applied to a bit line not associated with the first portion of the page for floating.

20. A storage device, the storage device comprising: Non-volatile storage devices; and A controller configured to access the non-volatile storage device. The non-volatile storage device includes: A storage cell array comprising multiple cell strings having multiple storage cells classified as pages; A row decoder, connected to the memory cell array via a serial select line, a ground select line, and a word line, and configured to apply a voltage to the serial select line and the ground select line; and Page buffers, which are connected to the memory cell array via bit lines and configured to apply voltage to the bit lines, The row decoder is configured to apply a first voltage to the word line in response to a read command for the first page being received from the controller, corresponding to a first capacitance of the memory cell of the first page. The row decoder is configured to apply a second voltage to the word line in response to a read command for a first portion of the first page being received from the controller, corresponding to a second capacitance of a memory cell in the first portion of the page. Each cell string's channel is configured to have a channel voltage in response to the voltage being applied to the string select line, the ground select line, the word line, and the bit line. The first capacitor is formed between the channel of the cell string connected to the bit line associated with the first page and the word line to which the first voltage is applied, and The second capacitor, unlike the first capacitor, is formed between the channel of the cell string connected to the bit line associated with the first partial page and the word line to which the second voltage is applied.

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