Method of programming a pmos otp memory array, memory, array and electronic system

Abstract

The application discloses a programming method of a PMOS OTP memory array, a memory, an array and an electronic system. The method comprises the following steps: during a programming operation, a target bias voltage is applied to a source line which is commonly connected to all memory cells; wherein the value of the target bias voltage is greater than the threshold voltage of a PMOS selection tube and less than the programming high voltage of the PMOS OTP memory. The problem that, after the size of the PMOS selection tube is scaled down in the prior art, the off-leakage current of the PMOS selection tube of the unselected programming memory cell is increased, a large amount of leakage current can lower the programming high voltage on the bit line of the to-be-programmed target memory cell, and finally the programming of the to-be-programmed target memory cell is failed is solved.

Description

Technical Field

[0001] This application belongs to the field of memory programming technology, and in particular relates to a programming method, memory, array and electronic system for a PMOS OTP memory array. Background Technology

[0002] For non-volatile memory, the goal of a write operation is to place externally stored data into the memory cell; programming is the core execution step of the write operation. PMOS OTP (PMOS One-Time Programmable Memory), as an important non-volatile memory solution, has all its memory cells shipped in a default unprogrammed state. It only has one programming opportunity during the entire chip's lifespan; after programming, the state is permanently fixed and can only be read, not erased or modified. A complete write operation on a PMOS OTP involves first locating the target memory cell to be programmed using row and column addressing, establishing a suitable operating voltage, and then injecting charge into the gate of the PMOS floating gate transistor in the target memory cell to change the cell's conductivity state, i.e., changing the PMOS floating gate transistor from an on state to an off state. Since all memory cells in a PMOS OTP are shipped with their unprogrammed floating gates in a low-threshold on-state by default, the threshold voltage of the floating gate increases after programming and charge is injected, causing it to turn off. This distinguishes different logic values ​​and completes the writing of externally stored data. Because the floating gate is completely encased in an insulating oxide layer, the injected charge does not dissipate naturally, and the data is permanently preserved after power loss. For a one-time programmable OTP, the core essence of the write operation is programming; therefore, the industry typically refers to the write operation of an OTP as programming. Without programming, it is impossible to write externally stored data, and the memory cannot perform its storage function. When programming memory cells in a PMOS OTP memory array, existing technologies typically use the following voltage configuration: applying a high voltage to the N-type well containing the target memory cell; applying a 0V voltage to the select gate of the target memory cell to turn on the PMOS select transistor; applying a high programming voltage to the bit line containing the target memory cell; and simultaneously applying a high voltage to the select gate of the unselected memory cell to attempt to completely turn it off. Under this configuration, the common source line is typically maintained at a 0V potential.

[0003] However, with the continuous advancement of semiconductor process nodes, memory device miniaturization has become an inevitable requirement for improving integration and reducing costs. However, in traditional programming schemes, to achieve reliable shutdown, the select gate of the unselected memory cell needs to withstand the same voltage as the programming high voltage. The design of the PMOS select transistor must be able to withstand a relatively high programming high voltage, thus limiting its critical dimensions such as minimum channel length, making it difficult to scale synchronously with the core logic devices. If the size of the PMOS select transistor is forcibly reduced in pursuit of high density, its shutdown characteristics under programming high voltage will deteriorate, generating a significant leakage current. This leakage current forms an additional current path on the shared bit line, thereby lowering the effective programming high voltage that should be applied to the floating gate of the target memory cell, ultimately leading to programming operation failure or an unreliable programming state. Summary of the Invention

[0004] The purpose of this application is to provide a programming method, memory, array, and electronic system for a PMOS OTP memory array, which solves the problem in the prior art where, after the size of the PMOS select transistor is miniaturized, the leakage current of the PMOS select transistor of the unselected memory cell increases when it is turned off. The large leakage current will lower the high programming voltage on the bit line of the target memory cell to be programmed, ultimately causing the programming of the target memory cell to fail.

[0005] In a first aspect, this application provides a programming method for a PMOS OTP memory array, the method comprising:

[0006] During programming, a target bias voltage is applied to the source line common to all memory cells; wherein the value of the target bias voltage is greater than the threshold voltage of the PMOS select transistor and less than the programming high voltage of the PMOS OTP memory.

[0007] In one embodiment, the target bias voltage is in the range of 0 to 1.8V.

[0008] In one embodiment, the target bias voltage is a DC voltage or a pulse voltage.

[0009] In one implementation, the effective duration of the target bias voltage completely covers the effective duration of the programming high voltage on the bit line where the target memory cell to be programmed is located.

[0010] In one implementation, the target bias voltage is established 10ns to 200ns before the programming high voltage on the bit line where the target memory cell to be programmed is located, and the target bias voltage is removed 10ns to 200ns after the programming high voltage on the bit line where the target memory cell to be programmed is located.

[0011] In one embodiment, the programming high voltage of the PMOS OTP memory is 7.8~8.5V.

[0012] Secondly, this application provides a PMOS OTP memory, the memory comprising: a PMOS OTP memory array and a control circuit; the control circuit is configured to employ the programming method of the PMOS OTP memory array as described above when performing a programming operation.

[0013] Thirdly, this application provides a PMOS OTP memory array, comprising: a plurality of memory cells, all of which are connected to a common source line; and a programming control circuit configured to apply the aforementioned target bias voltage to the source line during programming operations.

[0014] Fourthly, this application provides an electronic system, including, for example, a PMOS OTP memory or a PMOS OTP memory array.

[0015] As described above, the programming method, memory, array, and electronic system of the PMOS OTP memory array described in this application have the following beneficial effects:

[0016] This application uniformly raises the source potential of the PMOS select transistors of all memory cells by applying a target bias voltage to the common source line of all memory cells. Specifically, the gate potential of the PMOS select transistor for memory cells not selected for programming remains fixed. As the source potential increases, the potential difference between the source and gate potential decreases accordingly. Even if the PMOS select transistor experiences a short-channel effect due to size reduction, resulting in a lower threshold voltage, the turn-off condition of the PMOS select transistor can still be met. Therefore, the PMOS select transistors of memory cells not selected for programming can still be reliably turned off, ultimately effectively suppressing leakage current and preventing the high programming voltage on the bit line of the target memory cell from being pulled down by leakage current, thus ensuring successful programming of the target memory cell. Attached Figure Description

[0017] Figure 1 The diagram shows a schematic of a PMOS OTP memory array structure.

[0018] Figure 2 The diagram shows a schematic of a PMOS OTP memory structure.

[0019] Figure 3 The diagram shows the equivalent circuit of a PMOS OTP memory structure.

[0020] Explanation of reference numerals in the accompanying drawings: 100, storage unit. Detailed Implementation

[0021] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0022] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0023] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0024] To address the aforementioned technical issues, this application proposes a programming method, memory, array, and electronic system for a PMOS OTP memory array. This method enables the PMOS select transistor to be reliably turned off even after the PMOS select transistor size is miniaturized, effectively suppressing leakage current and preventing the high programming voltage on the bit line of the target memory cell from being pulled down by leakage current, thus ensuring successful programming of the target memory cell.

[0025] Please see Figures 1 to 3 ,by Figure 1 Taking the 2x4 PMOS OTP memory array shown as an example, the four memory cells 100 in the first row share the select gate SG1 signal line, the four memory cells 100 in the second row share the select gate SG2 signal line, the two memory cells 100 in the first column share bit line BL1, the two memory cells 100 in the second column share bit line BL2, the two memory cells 100 in the third column share bit line BL3, and the two memory cells 100 in the fourth column share bit line BL4. In the PMOS OTP memory array, memory cells 100 in adjacent rows share a source line SL. Figure 2The PMOS OTP memory shown is an example. This PMOS OTP memory fabricates two series-connected PMOS field-effect transistors in the same N-type well. The left side is a PMOS floating-gate transistor, whose gate is a floating gate used to store charge; the gate of this PMOS floating-gate transistor is not connected to any potential. The right side is a PMOS select transistor, whose gate serves as the gate voltage input terminal; the gate of this PMOS select transistor is a polysilicon gate. The drain of the PMOS select transistor and the source of the PMOS floating-gate transistor share an active region. When a fixed bias voltage is applied to the drain and body of the PMOS floating-gate transistor, and a scan voltage is applied to the source of the PMOS select transistor, the gate of the PMOS floating-gate transistor is not connected to any potential during operation. The overlap capacitance between the gate and source of the PMOS floating-gate transistor couples a portion of the voltage difference between the source and drain to the gate of the PMOS floating-gate transistor, thereby controlling the floating-gate PMOS channel current. Figure 3 This is the equivalent circuit structure diagram of the PMOS OTP memory, namely the circuit structure diagram of memory cell 100.

[0026] The technical solutions in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0027] This embodiment provides a programming method for a PMOS OTP memory array, the method comprising: applying a target bias voltage to the source line common to all memory cells during programming operations. For example, using... Figure 1 For example, during programming operations, a target bias voltage VBB is applied to the source line SL that is common to all memory cells 100.

[0028] The target bias voltage VBB is greater than the threshold voltage Vth of the PMOS select transistor and less than the programming high voltage VPP of the PMOSOTP memory.

[0029] In this embodiment, the programming high voltage VPP is 7.8 to 8.5V.

[0030] In some embodiments, the value of the programming high voltage VPP can be determined according to the process characteristics of the PMOS OTP memory, and is not limited to 7.8 to 8.5V, which will not be elaborated on here.

[0031] This embodiment sets a programming high voltage of 7.8 to 8.5V, which can cover most existing power supply circuits. There is no need to integrate a dedicated charge pump or voltage regulation circuit with a higher voltage. That is, it will not increase the chip area and manufacturing cost, thus achieving the effect of cost reduction and efficiency improvement.

[0032] In some embodiments, a power rail including the target bias voltage VBB is integrated inside the chip with integrated PMOS OTP. A MOS switch controlled by a programmable controller is added between the source line SL and the power rail. In standby mode, the switch is open and the source line SL maintains a 0V standby potential. During programming operation, the switch is closed and the source line SL is directly connected to the power rail including the target bias voltage VBB to obtain the target bias voltage VBB. There is no need to add an additional voltage generation circuit, and the chip area and cost are hardly increased.

[0033] In some embodiments, a miniature low-dropout linear regulator or low-load charge pump is integrated inside the chip that integrates the PMOS OTP. The output voltage is set by programmable control logic, and the output terminal is directly connected to the common source line SL. It can flexibly output any target value within the bias range, i.e., the target bias voltage VBB.

[0034] Specifically, the threshold voltage Vth of this PMOS select transistor is an important parameter of semiconductor devices, representing the minimum voltage required for the PMOS OTP device to transition from the off state to the on state. In a PMOS transistor, the threshold voltage Vth is defined as the minimum gate bias voltage required to form a conductive channel between the source and drain. That is, when the gate-source voltage reaches the threshold voltage, the channel begins to form, and the device enters the on state.

[0035] In some embodiments, the target bias voltage VBB ranges from 0 to 1.8V. In this embodiment, the target bias voltage VBB ranges from 0.8 to 1.8V.

[0036] This embodiment limits the target bias voltage VBB range to 0.8~1.8V, which can cover the power supply voltage of the PMOSOTP memory array to the greatest extent. This can avoid the risk of misprogramming of PMOS floating gate transistors and abnormal charge leakage caused by excessively high source bias, and also prevent the problem of insufficient rise of the 100 threshold voltage of the memory cell and programming failure.

[0037] In some embodiments, in order to achieve better leakage current suppression and lower programming power consumption, the target bias voltage VBB can also be set to a range of 1.2V to 1.8V, etc., which will not be elaborated on here.

[0038] For example, with Figure 1For example, assuming the memory cell 100 in the first row and second column is the target memory cell to be programmed, and the memory cell 100 in the second row and second column is the memory cell not selected for programming, the gate of the selection transistor of the memory cell in the first row is connected to the SG1 signal line and the gate of the selection transistor of the memory cell in the second row is connected to the SG2 signal line for row addressing; the drain of the selection transistor of all memory cells in each column is connected to the corresponding BL line, i.e., bit lines BL1~BL4, for column addressing, transmitting programming high voltage VPP and read voltage; that is, in this embodiment, the drain of the selection transistor of the target memory cell to be programmed is connected to the bit line BL2 and the gate is connected to the SG1 signal line, the drain of the selection transistor of the memory cell not selected for programming is connected to the bit line BL2 and the gate is connected to the SG2 signal line, the drain of the selection transistor of the target memory cell to be programmed is connected to the bit line BL2 to apply programming high voltage VPP, and the gate of the selection transistor of the target memory cell to be programmed is connected to the SG1 signal line to apply low level, the applied low level is 0, the remaining bit lines BL1, BL3 and BL4 are kept floating, and the gate of the selection transistor of the memory cell not selected for programming is connected to the SG2 signal line to apply programming high voltage VPP.

[0039] Because the miniaturization of PMOS select transistors leads to a shorter channel length, which in turn causes a short-channel effect, the threshold voltage Vth of the PMOS transistor shifts positively, meaning the absolute value of the threshold voltage of the PMOS transistor decreases. According to the turn-off logic of the PMOS OTP programming scheme, the bit lines and N-wells of all memory cells in the same column of the PMOS OTP memory array need to be connected to the programming high voltage VPP. The gate voltage Vg of the PMOS select transistor of the target memory cell to be programmed and the unselected memory cell to be programmed are applied differently, while the source line SL is applied with a positive target bias voltage VBB. In this embodiment, when the body effect is generated by applying the programming high voltage VPP to the N-well, the drain-source voltage difference of the PMOS select transistor in the unselected memory cell is reduced by raising the source potential, thereby suppressing the subthreshold leakage current of the unselected memory cell caused by the short-channel effect, without affecting the programming operation of the target memory cell to be programmed, thus adapting to the requirements of PMOS select transistor miniaturization.

[0040] Specifically, in the same column of unprogrammed memory cells, the gate voltage Vg of the PMOS select transistor is the programming high voltage VPP applied by the SG2 signal line, and the source voltage Vs is the positive target bias voltage VBB applied on the source line SL. Since the threshold voltage Vth of the PMOS transistor is negative, its conduction condition is gate-source voltage Vgs < Vth, and its turn-off condition is Vgs ≥ Vth. At this time, the gate-source voltage difference Vgs of the unprogrammed memory cells is VPP - Vs = (7.8~8.5) - (0.8~1.8) = 6~7.7V, which is much greater than the threshold voltage Vth of the PMOS transistor, and fully satisfies the turn-off condition of Vgs ≥ Vth. The PMOS select transistor in the unprogrammed memory cells can be reliably turned off. Even though the PMOS threshold voltage shifts forward due to the short-channel effect, in this embodiment, the threshold voltage Vth of the PMOS transistor before the forward shift is -0.8V, and the threshold voltage Vth of the PMOS transistor after the forward shift becomes -0.7V. Vgs is still much larger than the threshold voltage after the shift, which can effectively suppress subthreshold leakage current and prevent the VPP on the bit line of the target cell to be programmed from being pulled down by leakage current, thus ensuring programming reliability. Compared with the traditional solution, the source line SL is not forward biased in the traditional solution, i.e., Vs=0V. Therefore, the gate-source voltage difference Vgs=VPP-0=7.8~8.5V of the unselected memory cell, although it seems to meet the turn-off condition, the leakage-induced barrier reduction effect caused by the short-channel effect is significant. The subthreshold leakage current cannot be effectively suppressed. A large leakage current will pull down the high programming voltage VPP on the bit line of the target memory cell to be programmed, ultimately causing the programming of the target memory cell to fail. This embodiment reduces the drain-source voltage Vds of unselected memory cells by applying a positive target bias voltage of 0.8V to 1.8V to the source line SL, which can significantly suppress subthreshold leakage current without affecting the programming operation of selected cells, thus meeting the requirements for miniaturization of PMOS select transistors.

[0041] Programming Operation: Apply a low level (0) to the SG1 signal line containing the target memory cell to be programmed. At this time, the gate voltage Vg of the PMOS select transistor of the target memory cell to be programmed is 0V, the source voltage Vs is 0.8V to 1.8V, and the gate-source voltage difference Vgs is 0 - (0.8V to 1.8V) = -0.8V to -1.8V. This satisfies the PMOS turn-on condition of Vgs < Vth, and the PMOS select transistor of the target memory cell to be programmed is fully turned on, providing power to the target memory cell to be programmed. A high programming voltage VPP (7.8~8.5V) is applied to the bit line BL2. Because the selector is turned on, VPP is directly applied to the drain of the P-channel floating gate transistor. The source of the P-channel floating gate transistor is connected to the source line SL and receives the positive target bias voltage VBB, where VBB=Vs. At this time, the drain-source voltage difference of the P-channel floating gate transistor is large, that is, the value of VPP-Vs is large, which can accelerate the generation of hot holes in the channel. The hot holes cross the oxide layer and inject into the floating gate of the floating gate transistor, completing the charge injection, thus realizing the programming operation of the target cell to be programmed.

[0042] Read operation: A low-level read signal is applied to the SG1 signal line (set to 0V in this embodiment). The PMOS select transistor of the target memory cell to be programmed is turned on, and the corresponding bit line BL2 is connected to the read determination circuit. During reading, the source line SL is grounded, i.e., Vs=0. The memory state is distinguished by detecting the current of the bit line BL2: If the target memory cell to be programmed has been programmed, the threshold voltage of the P-channel floating gate transistor of the target memory cell shifts to a positive value due to the charge injected into the floating gate. At this time, under the action of the pre-charge level, the floating gate transistor of the bit line BL2 is turned on, forming a current from the source to the drain. A significant current appears in the bit line BL2, which is determined to be logic 1. If the target memory cell to be programmed has not been programmed, the P-channel floating gate transistor has not been injected with charge and still maintains the original threshold voltage, remaining in the off state. There is almost no current in the bit line BL2, which is determined to be logic 0, and the read operation is completed.

[0043] In this embodiment, by applying a target bias voltage VBB to the source line SL, the select transistor of the unselected memory cell always meets the turn-off condition and is completely turned off. The bit line BL2 has almost no current, so there will be no leakage current interfering with the current determination of the target memory cell to be programmed, thus ensuring the accuracy of reading.

[0044] In some embodiments, the target bias voltage VBB is a DC voltage or a pulse voltage.

[0045] This embodiment sets the target bias voltage VBB as a DC voltage, eliminating the need for additional modulation logic. This simplifies control, minimizes chip area and cost, and is suitable for most PMOS OTP devices requiring single-cycle continuous programming. Setting the target bias voltage VBB as a pulse voltage allows the target bias voltage VBB applied to the source line SL to be output synchronously with the programming pulse. The target bias voltage is maintained only when the programming pulse is active. The target bias voltage VBB can be removed when the PMOS OTP device is in standby mode, effectively reducing overall programming power consumption.

[0046] In some embodiments, the effective duration of the target bias voltage VBB completely covers the effective duration of the programming high voltage VPP on the bit line where the target memory cell to be programmed is located.

[0047] For example, after entering the programming flow, the target bias voltage VBB on the source line SL is first established. After an interval of 10ns to 200ns (in this embodiment, it is set to 80ns), a programming high voltage Vpp of 7.8 to 8.5V is applied to the bit line BL where the target memory cell to be programmed is located. When the preset programming cycle ends, the programming high voltage Vpp on the bit line BL where the target memory cell to be programmed is located is first removed. After an interval of 10ns to 200ns (in this embodiment, it is set to 80ns), the target bias voltage VBB on the source line SL is removed. In this embodiment, the effective duration of the target bias voltage VBB on the source line SL from its establishment to its removal completely covers the entire effective duration of the programming high voltage Vpp on the bit line BL where the target memory cell to be programmed is located. This ensures that the drain-induced barrier reduction effect of the unselected memory cell can be continuously and stably suppressed throughout the entire preset programming cycle.

[0048] The preset programming cycle can be determined according to the process specifications of the PMOS OTP memory, which ensures the programming success rate without adding extra programming time. This solves the problem in traditional solutions where leakage current lowers the effective programming high voltage VPP of the bit line BL where the target memory cell is located, requiring an additional extension of the programming cycle to compensate for insufficient charge injection.

[0049] In this embodiment, the channel length of the PMOS selector is reduced by 25% compared to the traditional scheme. The total leakage current of the unselected memory cell is reduced by 91% compared to the traditional source line SL zero bias scheme, and the programming success rate reaches 100%, meeting the reliability requirements of the memory device.

[0050] It should be noted that during the programming operation of this application, the memory cells that are not selected for programming are those memory cells in the PMOS OTP memory array that are not addressed and do not require this programming write operation.

[0051] In another exemplary embodiment, this application also provides a PMOS OTP memory, including: a PMOS OTP memory array and a control circuit; the control circuit is configured to use a programming method for the PMOS OTP memory array when performing a programming operation.

[0052] In another exemplary embodiment, this application also provides a PMOS OTP memory array, including: a plurality of memory cells 100, all memory cells 100 being connected to a common source line; and a programming control circuit configured to apply a target bias voltage as described in the above embodiment to the source line during programming operations.

[0053] In this embodiment, the target bias voltage VBB is set lower than the programming high voltage VPP of the PMOS OTP memory. In this embodiment, the programming high voltage VPP is 7.8 to 8.5V, which will not cause misprogramming of the PMOS floating gate transistor, and the area of ​​the entire PMOS OTP memory array is reduced by 2%.

[0054] In another exemplary embodiment, this application also provides an electronic system comprising a PMOS OTP memory device as described above or a PMOS OTP memory array as described above.

[0055] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A programming method for a PMOS OTP memory array, characterized in that, The method includes: During programming, a target bias voltage is applied to the source line common to all memory cells; wherein the value of the target bias voltage is greater than the threshold voltage of the PMOS select transistor and less than the programming high voltage of the PMOS OTP memory.

2. The method according to claim 1, characterized in that, The target bias voltage ranges from 0 to 1.8V.

3. The method according to claim 1 or 2, characterized in that, The target bias voltage is a DC voltage or a pulse voltage.

4. The method according to claim 3, characterized in that, The effective duration of the target bias voltage completely covers the effective duration of the programming high voltage on the bit line where the target memory cell to be programmed is located.

5. The method according to claim 4, characterized in that, The target bias voltage is established 10ns to 200ns earlier than the programming high voltage on the bit line where the target memory cell to be programmed is located, and the target bias voltage is canceled 10ns to 200ns later than the programming high voltage on the bit line where the target memory cell to be programmed is located.

6. The method according to claim 1, characterized in that, The programming high voltage of the PMOS OTP memory is 7.8~8.5V.

7. A PMOS OTP memory, characterized in that, The PMOS OTP memory includes: a PMOS OTP memory array and a control circuit; The control circuit is configured to employ the method as described in any one of claims 1 to 6 when performing programming operations.

8. A PMOS OTP memory array, characterized in that, include: Multiple memory cells, all of which are connected to a single source line; The programming control circuit is configured to apply a target bias voltage as described in any one of claims 1 to 6 to the source line during programming operations.

9. An electronic system, characterized in that, This includes the PMOS OTP memory as described in claim 7 or the PMOS OTP memory array as described in claim 8.

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