Multi-memory test architecture determination method and apparatus, computer device, and medium

Abstract

The application relates to the technical field of integrated circuits, and discloses a multi-memory test architecture determination method and device, computer equipment and a medium. The multi-memory test architecture determination method constructs a multi-target unified quantification model with a configurable weight as the core, performs weighted summation on three types of indexes, namely area overhead, timing penalty and test time, under a unified dimension, and realizes fine quantification comparison of two MBIST architectures, namely a conventional interface type and a shared bus type. Through a two-stage optimization process, a hybrid architecture division scheme close to a global optimal solution can be automatically output in units of memories, the optimal test architecture is determined for the memories, and an approximately optimal solution at the global level is realized.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method, apparatus, computer device and medium for determining a multi-memory test architecture. Background Technology

[0002] As integrated circuit design scales continue to increase, the number of integrated memories in chips is also growing, making memory testing a critical aspect of chip testing. Memory Built-In Self-Test (MBIST) is a widely adopted memory testing technology that integrates test circuitry within the chip to enable self-testing of the memory.

[0003] In the electronic design automation process, there are two main architectures for MBIST solutions for memory: conventional interface MBIST architecture and shared bus MBIST architecture.

[0004] Conventional interface-based MBIST architectures insert an independent MBIST interface for each memory, and insert multiplexers at the beginning of the register-to-memory path. Inserting multiplexers in the register-to-memory path introduces additional latency and increases the risk of timing violations. Simultaneously, adding diagnostic registers and other circuitry to each memory causes the test circuit area to increase linearly with the number of memories and the size of the ports. In the implementation of conventional interface-based MBIST architectures, the grouping strategy often affects the test circuit area, test time, and physical implementation difficulty. Current automatic MBIST grouping techniques are typically based on classical or heuristic algorithms, making it difficult to achieve a fine-grained trade-off among multiple objectives.

[0005] The shared-bus MBIST architecture aggregates multiple memories into a bus-level test object by multiplexing the functional bus data path and centrally inserting the MBIST interface outside the bus. This architecture avoids inserting extra logic into the timing-critical register-to-memory path, reducing timing risks, while also saving data switching and diagnostic logic, thus reducing area overhead. However, due to the time-sharing access to memory via the shared bus, test time often increases, and the adjustable strategies are limited by the inherent access logic between the functional bus and memory.

[0006] Therefore, determining the optimal test architecture for memory and achieving a near-optimal solution at the global level has become an urgent technical problem to be solved. Summary of the Invention

[0007] This application provides a method, apparatus, computer device, and medium for determining a multi-memory test architecture, which determines the optimal test architecture for the memory and achieves a near-optimal solution at the global level.

[0008] In a first aspect, this application provides a method for determining a multi-memory test architecture, the method comprising: Obtain attribute information of at least two memories and configure each target weight coefficient. The attribute information includes the bit width, depth, function bus identifier, bit width splicing group identifier and the corresponding timing margin of the path from the register to the memory for each memory. The target weight coefficient includes target area weight coefficient, target timing penalty weight coefficient and target test time weight coefficient. Based on the preset area model, timing penalty model, and test time model, the normalized area overhead, normalized timing penalty, and normalized test time of each memory under the built-in self-test MBIST architecture of a conventional interface memory are calculated. Based on the normalized area overhead, the normalized timing penalty, the normalized test time, and each of the target weight coefficients, calculate the shared adaptability score and global objective function value of each memory. Based on the ranking of the shared adaptability scores, each memory is changed to a shared bus MBIST architecture one by one, the total number of change steps is determined, and the target boundary point is determined based on the number of change steps and the global objective function value; A preset number of candidate memories are determined based on the target boundary point, and the architecture combination strategy of each candidate memory is traversed. A multi-memory test architecture is determined based on the architecture combination strategy and the global objective function value.

[0009] Secondly, this application also provides a multi-memory test architecture determination apparatus, the apparatus comprising: The target weight coefficient configuration module is used to obtain attribute information of at least two memories and configure each target weight coefficient. The attribute information includes the bit width, depth, function bus identifier, bit width splicing group identifier and the corresponding timing margin of the path from the register to the memory for each memory. The target weight coefficient includes target area weight coefficient, target timing penalty weight coefficient and target test time weight coefficient. The normalized information calculation module is used to calculate the normalized area overhead, normalized timing penalty, and normalized test time of each memory under the built-in self-test MBIST architecture of a conventional interface memory, based on a preset area model, timing penalty model, and test time model. The global objective function value calculation module is used to calculate the shared fitness score and global objective function value of each memory based on the normalized area overhead, the normalized timing penalty, the normalized test time, and each of the objective weight coefficients. The target boundary point determination module is used to change each of the memories to a shared bus MBIST architecture one by one according to the ranking of the shared adaptability scores, determine the total number of change steps, and determine the target boundary point according to the number of change steps and the global objective function value; The multi-memory test architecture determination module is used to determine a preset number of candidate memories based on the target boundary point, traverse the architecture combination strategy of each candidate memory, and determine the multi-memory test architecture based on the architecture combination strategy and the global objective function value.

[0010] Thirdly, this application also provides a computer device, the computer device including a memory and a processor; the memory is used to store a computer program; the processor is used to execute the computer program and, when executing the computer program, implement the multi-memory test architecture determination method as described above.

[0011] Fourthly, this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, causes the processor to implement the multi-memory test architecture determination method described above.

[0012] This application discloses a method, apparatus, computer device, and medium for determining a multi-memory test architecture. The method includes acquiring attribute information of at least two memories and configuring target weight coefficients for each. The attribute information includes the bit width, depth, function bus identifier, bit width splicing group identifier, and corresponding register-to-memory path timing margin for each memory. The target weight coefficients include a target area weight coefficient, a target timing penalty weight coefficient, and a target test time weight coefficient. Based on a preset area model, timing penalty model, and test time model, the method calculates the normalized area overhead, normalized area ratio, and normalized time ratio of each memory under the built-in self-testing MBIST architecture of a conventional interface-type memory. The process involves: standardizing timing penalties and normalizing test time; calculating the shared adaptability score and global objective function value for each memory based on the normalized area overhead, normalized timing penalties, normalized test time, and each target weight coefficient; sequentially converting each memory to a shared bus MBIST architecture according to the ranking of the shared adaptability scores, determining the total number of conversion steps, and determining the target boundary point based on the number of conversion steps and the global objective function value; determining a preset number of candidate memories based on the target boundary point, traversing the architecture combination strategy of each candidate memory, and determining the multi-memory test architecture based on the architecture combination strategy and the global objective function value. Through this method, this application constructs a multi-objective unified quantization model with configurable weights as its core, weighting and summing the three categories of indicators—area overhead, timing penalties, and test time—under a unified dimension, achieving a refined quantitative comparison of two MBIST architectures: conventional interface type and shared bus type. Through a two-stage optimization process, a near-globally optimal hybrid architecture partitioning scheme can be automatically output on a memory-by-memory basis, determining the optimal test architecture for the memory and achieving a near-optimal solution at the global level. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic flowchart of a method for determining a multi-memory test architecture provided in an embodiment of this application; Figure 2 A schematic block diagram of a multi-memory test architecture determination apparatus provided for embodiments of this application; Figure 3 A schematic block diagram of the structure of a computer device provided for an embodiment of this application. Detailed Implementation

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0016] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0017] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0018] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0019] This application provides a method, apparatus, computer device, and medium for determining a multi-memory test architecture. The method can be applied to servers. By constructing a multi-objective unified quantization model with configurable weights, it weights and sums three metrics—area overhead, timing penalty, and test time—under a unified scale, achieving a refined quantitative comparison of two MBIST architectures: conventional interface-type and shared bus-type. Through a two-stage optimization process, it can automatically output a near-globally optimal hybrid architecture partitioning scheme on a memory-by-memory basis, determining the optimal test architecture for the memory and achieving a near-optimal solution at the global level.

[0020] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0021] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating a method for determining a multi-memory test architecture according to an embodiment of this application. This method can be applied to servers to determine the optimal test architecture for memory, achieving a near-optimal solution at the global level.

[0022] like Figure 1As shown, the method for determining the multi-memory test architecture specifically includes steps S10 to S50.

[0023] Step S10: Obtain attribute information of at least two memories and configure each target weight coefficient. The attribute information includes the bit width, depth, function bus identifier, bit width splicing group identifier and the corresponding timing margin of the path from the register to the memory for each memory. The target weight coefficient includes the target area weight coefficient, the target timing penalty weight coefficient and the target test time weight coefficient. Specifically, attribute information of each memory is collected from the chip design database, and the attribute information includes: Bit width: includes data bit width and address bit width, used in subsequent area models to calculate the observed logic area, bypass logic area and differential logic area; Depth: This refers to the storage depth of the memory, used in the test time model to calculate the test time for a single memory segment; Function bus identifier: Used to identify the function bus to which each memory belongs. In a shared bus MBIST architecture, memories on the same function bus share the MBIST interface. Bit-width splicing group identifier: Used to identify memory groups that can be spliced ​​within the same functional bus. Memory groups within the bit-width splicing group are tested in parallel as a whole. Register-to-memory path timing margin: used in timing penalty models to evaluate the impact of conventional interface-type MBIST architecture on timing convergence.

[0024] Based on design requirements, configure the weight coefficients for three optimization objectives: area, timing penalty, and test time, including: Target area weighting coefficient (denoted as w) area ): Used to weigh the importance of the test circuit area increment in the overall objective function; Target time-series penalty weight coefficient (denoted as w) timing ): Used to weigh the importance of R2M path timing violation risk in the overall objective function; Target test time weighting coefficient (denoted as w) time ): Used to weigh the importance of test duration in the overall objective function; Among them, the three types of weight coefficients satisfy the normalization constraint conditions: w area +w timing +w time =1.

[0025] The relative magnitudes of each weight coefficient are dynamically adjusted according to the different requirements of the design scenario: When the design is sensitive to chip area, increase the configured value of the target area weighting coefficient (e.g., w).area >0.5); When the design is sensitive to timing convergence, increase the configured value of the target timing penalty weight coefficient (e.g., w). timing >0.5); When the design is sensitive to test efficiency, increase the configured value of the target test time weighting coefficient (e.g., w). time >0.5).

[0026] Step S20: Based on the preset area model, timing penalty model, and test time model, calculate the normalized area overhead, normalized timing penalty, and normalized test time of each memory under the built-in self-test MBIST architecture of the conventional interface type memory. Specifically, for the i-th memory, its original area overhead under the conventional interface-type MBIST architecture consists of common logic area and differentiated logic area.

[0027] (1) Calculate the common logic area: Common logic is the part that is independent of the selected MBIST architecture, including observation logic and bypass logic.

[0028] The formula for calculating the observed logical area is:

[0029] The formula for calculating the bypass logic area is: .

[0030] Among them, Given the address of the i-th memory and the number of control line signals, Let be the data bit width of the i-th memory. For configurable observation signal compression ratio, The areas of gates DFF, AND2, XOR2, and MUX21 are determined by process parameters.

[0031] The total logical area of ​​the i-th memory is:

[0032] (2) Calculating the differential logic area: Differentiated logic is a part closely related to the test architecture, including input switching logic, comparison logic, diagnostic logic, etc. Under a conventional interface-type MBIST architecture, the formula for calculating the differential logic area of ​​the i-th memory is:

[0033] in The area of ​​gates OAI22 and OAI31 is determined by process parameters.

[0034] In a typical interface-based MBIST architecture, the global differentiation logic is the sum of all memory differentiation logic.

[0035] In a shared bus MBIST architecture, the differentiation logic uses the maximum data and control signal bit width of the memory connected to each bus (denoted as ). and ) Calculation: Assuming there are Q buses, the differential logic of the i-th bus can be approximated as follows:

[0036] In the shared bus-based MBIST architecture, the global differentiation logic is the sum of the differentiation logic of all buses:

[0037] Furthermore, the MBIST test algorithm is hard-coded in the MBIST controller. For an MBIST controller with a specified test algorithm, the area overhead can be approximated as a constant, denoted as . The number of global MBIST controllers is denoted as The grouping strategy of a conventional interface-based MBIST architecture directly affects the number of MBIST controllers. Automatic grouping technology is usually implemented based on classic or heuristic algorithms. This system does not limit the grouping algorithm.

[0038] Given a conventional interface-type and shared bus-type MBIST converged architecture, the global area increment is calculated as follows: 。

[0039] Based on engineering experience, the global area range is preset [Area] min Area max The area overhead of the i-th memory is normalized using a min-max method: ,in, This is the normalized area overhead of the i-th memory in a conventional interface-type MBIST architecture.

[0040] Based on path timing margin r 2m_slackir Calculate the timing penalty value for each memory.

[0041] The timing penalty model is defined as generating a penalty only when the timing margin is negative; a positive or zero value indicates that the timing requirements are met, and the penalty value is zero. The specific calculation formula is as follows: ; like >0, then =0; if <0, then = That is, the absolute value of the timing violation is taken as the penalty amount.

[0042] When normalizing the timing penalty value, a global timing penalty range is preset [Timing]. min Timing max Timing min Usually set to 0, Timing max Based on the worst-case timing violation scenario in the design, the normalized calculation formula is as follows: Among them, TimingPenalty norm,i This is the normalized timing penalty for the i-th memory in the conventional interface-type MBIST architecture.

[0043] The performance evaluation module calculates the test time for each memory module in individual tests based on the memory depth information. The test time for a single memory module is directly proportional to its depth, and the calculation formula is as follows:

[0044] in, Let be the depth of the i-th memory. For the constant coefficients of the selected test algorithm (e.g., for the March C-algorithm, Typically, 10 or 12 is used to represent the number of memory accesses. The clock cycle for MBIST testing.

[0045] When normalizing the test time, the system presets a global test time range [Time]. min Time max ], where Time min Theoretically, the fastest single-memory test time, Time max The normalized calculation formula for the total time of all memory serial tests is as follows: .

[0046] Step S30: Calculate the shared fitness score and global objective function value of each memory based on the normalized area overhead, the normalized timing penalty, the normalized test time, and each of the target weight coefficients. Specifically, the shared adaptability score is used to measure the net benefit of each memory changing from a conventional interface-type MBIST architecture to a shared bus-type MBIST architecture. The higher the score, the more suitable the memory is for a shared bus architecture.

[0047] Define a shared adaptability score for each memory, using the following formula: , in, , , For the weighting coefficients, satisfying , , , These represent the dimensionless normalized values ​​of the area overhead, timing penalty, and test time for the i-th memory in a conventional interface-type MBIST architecture. This score measures the net benefit of changing each memory from a conventional interface-type architecture to a shared bus architecture; a higher score indicates a better fit for a shared bus architecture.

[0048] The calculation of the global objective function value requires a specific architecture partitioning scheme. In the first phase of optimization in subsequent step S40, the global metric needs to be recalculated after each change in the memory architecture. This example illustrates the calculation method for the global metric using the initial state (all memories are of conventional interface type architecture). In practical applications, it needs to be dynamically calculated based on the current architecture partitioning scheme.

[0049] (1) Calculate the global normalized total area cost For a given architecture partitioning scheme, based on the globally normalized area overhead... Global normalization timing penalty Global normalized test time And the corresponding target weight coefficients, calculate the global objective function value J: .

[0050] Step S40: According to the ranking of the shared adaptability scores, change each memory to a shared bus MBIST architecture one by one, determine the total number of change steps, and determine the target boundary point according to the number of change steps and the global objective function value; The shared fitness score and the global objective function value jointly support the two-stage optimization process: In the first phase of optimization, the memory is sorted from largest to smallest according to the shared adaptability score of each memory, and the memory is changed from the conventional interface type MBIST architecture to the shared bus type MBIST architecture one by one. For each change step, the global objective function value of the current architecture partitioning scheme is calculated, and the optimal number of change steps is determined by comparing the global objective function values ​​of each step. In the second phase of optimization, near the optimal number of change steps determined in the first phase, candidate memories with shared fitness scores close to the threshold are selected. Their architecture combination strategies are traversed, and the final multi-memory test architecture is determined by comparing the global objective function values ​​of each combination strategy.

[0051] All N memories are initially configured as a conventional interface-type MBIST architecture as the initial architecture partitioning scheme, and scored according to the sharing adaptability of each memory. The memory changes are sorted from largest to smallest to obtain the memory change sequence. The higher the shared adaptability score, the more suitable the memory is for a shared bus MBIST architecture, and therefore it is prioritized for change in the change sequence.

[0052] According to the memory change sequence, each memory is changed from a conventional interface-type MBIST architecture to a shared bus-type MBIST architecture one by one, specifically including: From step 1 to step N, each step changes a memory from a conventional interface-type MBIST architecture to a shared bus-type MBIST architecture, for a total of N change operations; After each change is completed, record the current change step number k (k=1,2,...,N). At this point, there are k memory devices using a shared bus MBIST architecture, and N... k memory units employ a conventional interface-type MBIST architecture; For the current architecture partitioning scheme corresponding to the number of change steps k, recalculate the global normalized area overhead. Global normalization timing penalty Global normalized test time And calculate the global objective function value J(k) under the current architecture partitioning scheme: .

[0053] Specifically, the calculation of global normalized area overhead requires adding the differentiated logic area of ​​the conventional interface-type MBIST architecture and the differentiated logic area of ​​the shared bus-type MBIST architecture according to the current architecture partitioning scheme, and adding the common logic area and MBIST controller area; the calculation of global normalized timing penalty is the sum of the memory timing penalties of all architectures using the conventional interface-type MBIST architecture; the calculation of global normalized test time is the maximum value of the total test time of the conventional interface-type MBIST architecture and the total test time of the shared bus-type MBIST architecture.

[0054] Compare the global objective function values ​​J(k) corresponding to each change step k (k=0,1,2,...,N, where k=0 represents the initial state of all memory using the conventional interface-type MBIST architecture), select the change step that minimizes the global objective function value as the optimal change step, and take the position corresponding to the optimal change step as the target boundary point. The target boundary point divides the memory into two regions: Shared bus MBIST architecture region: The first k memory units in the sequence are changed to adopt a shared bus MBIST architecture; Conventional interface-type MBIST architecture region: N after sorting in the sequence. k memory units, using a conventional interface-type MBIST architecture.

[0055] Step S50: Determine a preset number of candidate memories based on the target boundary point, and traverse the architecture combination strategy of each candidate memory. Determine the multi-memory test architecture based on the architecture combination strategy and the global objective function value.

[0056] Specifically, taking the target boundary point as the center, m memories are selected as candidate memories within a preset neighborhood range, where m is a positive integer less than N. Preferably, the value of m is between 5 and 15.

[0057] The candidate memory includes a boundary memory near the target boundary point, which is a memory with a shared fitness score close to the critical value at the target boundary point.

[0058] Traversing m candidate memories 2 m There are several architecture combination strategies, each corresponding to different configuration combinations of candidate memories between built-in self-test architecture in conventional interface-type memories and built-in self-test architecture in shared bus-type memories. For each architecture combination strategy, the architecture partitioning of non-candidate memories remains consistent with the target boundary point, and only the architecture configuration of candidate memories is changed to form a complete architecture partitioning scheme.

[0059] For each architecture combination strategy, calculate the corresponding global objective function value and evaluate the impact of each architecture combination strategy on the following combination effects: Bus controller test time balance: Certain candidate memory combinations can make the test time of each bus controller more balanced, reducing the overall test time; Number of built-in self-test controllers in conventional interface memory: Certain candidate memory combinations can reduce the number of built-in self-test controllers in conventional interface memory, thereby reducing overall area overhead; Timing penalty distribution: Certain candidate memory combinations can optimize the distribution of timing penalties across buses, reducing overall timing risk.

[0060] The architecture combination strategy that minimizes the global objective function value is selected as the neighborhood optimal configuration. The neighborhood optimal configuration is then merged with the architecture partitioning of non-candidate memories at the target boundary point to obtain the final multi-memory test architecture partitioning scheme.

[0061] This embodiment discloses a method for determining a multi-memory test architecture. The method includes acquiring attribute information of at least two memories and configuring target weight coefficients for each. The attribute information includes the bit width, depth, function bus identifier, bit width splicing group identifier, and corresponding register-to-memory path timing margin for each memory. The target weight coefficients include a target area weight coefficient, a target timing penalty weight coefficient, and a target test time weight coefficient. Based on a preset area model, timing penalty model, and test time model, the method calculates the normalized area overhead and normalized timing penalty of each memory under the built-in self-test MBIST architecture of a conventional interface-type memory. The process involves: calculating the shared adaptability score and global objective function value for each memory based on the normalized area overhead, normalized timing penalty, normalized test time, and the target weight coefficients; sequentially converting each memory to a shared bus MBIST architecture according to the ranking of the shared adaptability scores, determining the total number of conversion steps, and determining the target boundary point based on the number of conversion steps and the global objective function value; determining a preset number of candidate memories based on the target boundary point, traversing the architecture combination strategy of each candidate memory, and determining the multi-memory test architecture based on the architecture combination strategy and the global objective function value. Through this method, this application constructs a multi-objective unified quantization model with configurable weights as its core, weighting and summing the three indicators of area overhead, timing penalty, and test time under a unified dimension, achieving a refined quantitative comparison of two MBIST architectures: conventional interface type and shared bus type. Through a two-stage optimization process, it can automatically output a near-globally optimal hybrid architecture partitioning scheme on a memory-by-memory basis, determining the optimal test architecture for the memory, and achieving a near-optimal solution at the global level.

[0062] based on Figure 1 In the illustrated embodiment, step S10 includes: Extract the bit width and depth of each memory from the chip design database; Analyze the function bus connection relationships to determine the function bus identifier; Identify the bit-width splicing configuration and determine the bit-width splicing group identifier for each of the memories; Perform static timing analysis to obtain the path timing margin from the register to the memory corresponding to each memory.

[0063] Specifically, the chip design database is accessed to read the memory cell library file and memory instantiation information; the data bit width parameters of each memory are extracted, where the data bit width is the bit width of the memory data port; the address bit width parameters of each memory are extracted, where the address bit width is the bit width of the memory address port; and the depth parameters of each memory are extracted, where the depth is the storage capacity of the memory, which is calculated from the address bit width or obtained by directly reading the memory capacity parameters.

[0064] Read the netlist file or connection description file of the chip design to identify the data path between the memory and the functional modules; trace the physical connection between the memory data port and the functional bus to determine the functional bus to which each memory belongs; assign a unique bus identifier to each functional bus to generate a functional bus identifier; associate the functional bus identifier with the corresponding memory for storage, and the functional bus identifier is used for subsequent test time calculation and controller configuration under the self-test architecture built into the shared bus type memory.

[0065] Read the bit-width splicing configuration information of the chip design. The bit-width splicing configuration information describes the connection relationship of multiple memories accessed in parallel on the function bus in a splicing manner; identify the memory sets belonging to the same splicing group. The memories in the same splicing group share the same function bus, and the data port bit widths are spliced ​​to form a complete data path; assign a unique group identifier to each bit-width splicing group to generate a bit-width splicing group identifier; associate the bit-width splicing group identifier with the corresponding memory and store it. The bit-width splicing group identifier is used to identify parallel test groups in the built-in self-test architecture of shared bus type memory. The memories in the same splicing group are treated as a whole test object for parallel testing.

[0066] Read the timing constraint file of the chip design to determine the timing check requirements of the register-to-memory path; call the static timing analysis tool to calculate the delay of the data path from the register output to the memory input; obtain the setup time margin and hold time margin of each memory path, and take the worst value as the path timing margin; associate the path timing margin with the corresponding memory and store it. The path timing margin is used for subsequent timing penalty model calculation and shared fitness scoring. A negative path timing margin indicates that the memory has a timing violation risk under the built-in self-test architecture of the conventional interface type memory, and it is suitable to give priority to the built-in self-test architecture of the shared bus type memory.

[0067] In a specific embodiment, step S10 further includes: Obtain the original area weight coefficient, the original time penalty weight coefficient, and the original test time weight coefficient; Adjust the original area weight coefficient, the original time penalty weight coefficient, and / or the original test time weight coefficient according to the preset design requirements and preset weight configuration template to determine each of the target weight coefficients, wherein the sum of each of the target weight coefficients is 1.

[0068] Specifically, the system receives the user-inputted raw weight coefficients, including the raw area weight coefficient, the raw time penalty weight coefficient, and the raw test time weight coefficient; or, it reads the default weight configuration file to obtain the preset raw weight coefficients, in which the raw area weight coefficient, the raw time penalty weight coefficient, and the raw test time weight coefficient are initially set to 1 / 3; the obtained raw area weight coefficient, raw time penalty weight coefficient, and raw test time weight coefficient are stored in the weight coefficient cache area as the benchmark value for subsequent adjustments.

[0069] The system receives preset design requirements from the user, including area-priority requirements, timing-priority requirements, test-time-priority requirements, or balanced optimization requirements. When the preset design requirement is area-priority, the system increases the original area weight coefficient and decreases the original timing penalty weight coefficient and the original test-time weight coefficient, making area optimization dominant in the global objective function value. When the preset design requirement is timing-priority, the system increases the original timing penalty weight coefficient and decreases the original area weight coefficient and the original test-time weight coefficient, making timing convergence dominant in the global objective function value. When the preset design requirement is test-time-priority, the system increases the original test-time weight coefficient and decreases the original area weight coefficient and the original timing penalty weight coefficient, making test-time reduction dominant in the global objective function value. When the preset design requirement is balanced optimization, the system keeps the original area weight coefficient, the original timing penalty weight coefficient, and the original test-time weight coefficient approximately equal.

[0070] Preset weight configuration templates are provided, including an area-first template, a time-first template, a test-time-first template, and a balanced template. In the area-first template, the target area weight coefficient is greater than the target time-penalty weight coefficient and the target test-time weight coefficient. Preferably, the target area weight coefficient is 0.5, the target time-penalty weight coefficient is 0.3, and the target test-time weight coefficient is 0.2. In the time-first template, the target time-penalty weight coefficient is greater than the target area weight coefficient and the target test-time weight coefficient. Preferably, the target time-penalty weight coefficient is 0.5, the target area weight coefficient is 0.3, and the target test-time weight coefficient is 0.2. In the test-time-first template, the target test-time weight coefficient is greater than the target area weight coefficient and the target time-penalty weight coefficient. Preferably, the target test-time weight coefficient is 0.5, the target area weight coefficient is 0.3, and the target time-penalty weight coefficient is 0.2. In the balanced template, the target area weight coefficient, the target time-penalty weight coefficient, and the target test-time weight coefficient are equal, all being 1 / 3.

[0071] The system receives the user's selection instruction for the preset weight configuration template and adjusts the original area weight coefficient, original time penalty weight coefficient, and original test time weight coefficient to the template setting value according to the weight coefficient value corresponding to the selected template.

[0072] The adjusted original area weight coefficient, original time penalty weight coefficient, and original test time weight coefficient are determined as the target area weight coefficient, target time penalty weight coefficient, and target test time weight coefficient, respectively. The sum of the target weight coefficients is calculated and verified to be equal to 1. When the sum is equal to 1, each target weight coefficient is directly output.

[0073] based on Figure 1 In the illustrated embodiment, step S20 includes: Based on the area model, the observation logic area and bypass logic area are calculated according to the number of port signals of each memory, and the differential logic area is calculated according to the address bit width and data bit width of each memory. Combined with the controller area of ​​the MBIST architecture, the original area overhead of each memory is obtained, and the original area overhead is normalized based on the preset area engineering to obtain the normalized area overhead. Specifically, calculate the common logic area: common logic is the part that is independent of the selected MBIST architecture, including observation logic and bypass logic.

[0074] The formula for calculating the observed logical area is:

[0075] The formula for calculating the bypass logic area is: .

[0076] Among them, Given the address of the i-th memory and the number of control line signals, Let be the data bit width of the i-th memory. For configurable observation signal compression ratio, The areas of gates DFF, AND2, XOR2, and MUX21 are determined by process parameters.

[0077] The total logical area of ​​the i-th memory is: .

[0078] The number C of MBIST controllers is determined based on the grouping strategy of the conventional interface-type MBIST architecture. ctrl Area of ​​a single MBIST controller ctrl Calculate the total area of ​​the MBIST controller to specify the constant values ​​for the test algorithm: Area ctrl,total =C ctrl ×Area ctrl .

[0079] The original area overhead of the i-th memory is obtained by summing the observed logic area, bypass logic area, differential logic area, and MBIST controller area.

[0080] Based on the timing penalty model, the original timing penalty value is calculated according to the path timing margin corresponding to each memory, and the original timing penalty value is normalized based on the preset timing penalty engineering to obtain the normalized timing penalty. Specifically, the normalized area overhead (Area) of the i-th memory is calculated using the min-max normalization method. norm,i : Among them, Area min and Area max Based on engineering experience, these represent the minimum and maximum area overhead of a single memory module, respectively.

[0081] Based on the test time model, the original test time is calculated according to the depth of each memory, the constant coefficient of the test algorithm, and the clock cycle. The original test time is then normalized based on a preset test time engineering to obtain the normalized test time.

[0082] Specifically, based on the path timing margin r 2m_slackir Calculate the timing penalty value for each memory.

[0083] The timing penalty model is defined as generating a penalty only when the timing margin is negative; a positive or zero value indicates that the timing requirements are met, and the penalty value is zero. The specific calculation formula is as follows: ; like >0, then =0; if <0, then = That is, the absolute value of the timing violation is taken as the penalty amount.

[0084] When normalizing the timing penalty value, a global timing penalty range is preset [Timing]. min Timing max Timing min Usually set to 0, Timing max Based on the worst-case timing violation scenario in the design, the normalized calculation formula is as follows: Among them, TimingPenalty norm,i This is the normalized timing penalty for the i-th memory in the conventional interface-type MBIST architecture.

[0085] The performance evaluation module calculates the test time for each memory module in individual tests based on the memory depth information. The test time for a single memory module is directly proportional to its depth, and the calculation formula is as follows:

[0086] in, Let be the depth of the i-th memory. For the constant coefficients of the selected test algorithm (e.g., for the March C-algorithm, Typically, 10 or 12 is used to represent the number of memory accesses. The clock cycle for MBIST testing.

[0087] When normalizing the test time, the system presets a global test time range [Time]. min Time max ], where Time min Theoretically, the fastest single-memory test time, Time max The normalized calculation formula for the total time of all memory serial tests is as follows: .

[0088] based on Figure 1 In the illustrated embodiment, step S30 includes: The normalized area cost, the normalized timing penalty, and the normalized test time are multiplied by each of the target weight coefficients and then summed in a weighted manner to obtain the shared fitness score. Calculate the total global normalized area, the total global normalized timing penalty, and the total global normalized test time based on the normalized area cost, the normalized timing penalty, and the normalized test time, respectively. The global objective function value is obtained based on the total global normalized area, the total global normalized time penalty, the total global normalized test time, and the weight coefficients of each objective.

[0089] Specifically, the normalized area overhead, normalized timing penalty, and normalized test time of the i-th memory are multiplied by the target area weight coefficient, target timing penalty weight coefficient, and target test time weight coefficient, respectively, and then summed in a weighted manner to obtain the shared fitness score of the i-th memory.

[0090] For a given architecture partitioning scheme, the normalized area overhead of all memories using the conventional interface-type MBIST architecture and the normalized area overhead of all memories using the shared bus-type MBIST architecture are summed to obtain the total global normalized area.

[0091] The total normalized timing penalty is obtained by summing the normalized timing penalties of all memories using the conventional interface-type MBIST architecture. The timing impact of memories using the shared bus-type MBIST architecture on the R2M path is approximately zero and is not included in the total timing penalty.

[0092] Calculate the test time for the conventional interface-type MBIST architecture and the shared bus-type MBIST architecture separately, and take the maximum of the two as the total global normalized test time: The standard interface-type MBIST architecture: Based on the controller grouping strategy, the memory is divided into multiple parallel groups. The memory within a group is tested in parallel, and the memory between groups is tested serially. The test time of a single controller is the sum of the test times of each parallel group. When multiple controllers are in parallel, the maximum value of the test times of each controller is taken. In the shared bus MBIST architecture: based on the bit-width splicing group identifier, the memory within the same splicing group is tested in parallel as a whole, while non-spliced ​​memory is tested serially. The test time of a single bus is the sum of the test times of each test object. When multiple buses are tested in parallel, the maximum value of the test times of each bus is taken.

[0093] The total global normalized area, total global normalized timing penalty, and total global normalized test time are multiplied by the target area weight coefficient, target timing penalty weight coefficient, and target test time weight coefficient, respectively, and then summed in a weighted manner to obtain the global objective function value J. The global objective function value is used to evaluate the overall cost of the corresponding architecture partitioning scheme. The smaller J is, the better the overall performance of the architecture partitioning scheme in terms of area, timing, and test time.

[0094] based on Figure 1 In the illustrated embodiment, step S40 includes: Each of the aforementioned memories is initialized to the conventional interface-type MBIST architecture; According to the sorting of the shared adaptability scores, each memory is changed to the shared bus type MBIST architecture, and each change of a memory is recorded as a change step; The summation of each change step is taken as the total number of change steps. The memory corresponding to the number of change steps with the smallest global objective function value is selected as the objective boundary point.

[0095] Specifically, each memory is initialized to the built-in self-test architecture of the conventional interface type memory. At this time, all N memories adopt the built-in self-test architecture of the conventional interface type memory, and the number of memories sharing the built-in self-test architecture of the bus type memory is zero, which is recorded as the 0th change step.

[0096] Read the shared adaptability score of each memory and sort them from largest to smallest to form a change sequence. The larger the shared adaptability score, the more suitable the memory is for the built-in self-test architecture of the shared bus type memory, and the higher it ranks in the change sequence, and the priority is given to architecture change.

[0097] The memory is changed one by one from the built-in self-test architecture of the conventional interface type memory to the built-in self-test architecture of the shared bus type memory, and each time the architecture change of a single memory is completed, it is recorded as a change step.

[0098] At the k-th change step, the first k memories in the change sequence have been changed to a shared bus type memory with built-in self-test architecture, while the remaining Nk memories retain the conventional interface type memory with built-in self-test architecture, where the value of k ranges from 0 to N.

[0099] For each change step, the global objective function value is recalculated based on the current architecture partitioning scheme. The global objective function value corresponding to each change step is recorded to form a change curve containing N+1 data points.

[0100] The summation of each change step is taken as the total change step, which is N, equal to the total number of memory units. The total change step represents the search space size of the first stage of optimization. The traversal of all change steps and the calculation of the global objective function value are completed in O(N) linear complexity.

[0101] The number of change steps that minimizes the global objective function value is selected from the change curves. The memory location corresponding to this number of change steps is the target boundary point. The target boundary point divides the memory into two parts: the memory on one side of the target boundary point uses a shared bus type memory with an integrated self-test architecture, while the memory on the other side of the target boundary point uses a conventional interface type memory with an integrated self-test architecture. The target boundary point is the initial optimal solution obtained in the first stage of optimization. A near-global optimal architecture partitioning scheme is quickly determined with linear complexity, providing a basic boundary position for the second stage of optimization.

[0102] based on Figure 1 In the illustrated embodiment, step S50 includes: Using the target boundary point as the center, determine the preset number of candidate memories; Each of the aforementioned architecture combination strategies is generated based on all the aforementioned candidate memories, and the global objective function value corresponding to each of the aforementioned architecture combination strategies is calculated using the global objective function value; The architecture combination strategy with the smallest global objective function value is selected as the in-boundary combination strategy, and the multi-memory test architecture is determined based on the other memories outside the target boundary and the in-boundary combination strategy.

[0103] Specifically, taking the target boundary point as the center, m memory locations are selected as candidate memory locations within a preset neighborhood, where m is a positive integer less than N.

[0104] Candidate memories include boundary memories near the target boundary and with shared fitness scores close to the critical value. The architecture selection of boundary memories is highly sensitive to the global objective function value. Specifically, candidate memories contain m / 2 memories before and after the target boundary, or the number of memories before and after the boundary may be adjusted according to the actual boundary conditions. The identified candidate memory identifiers are stored in the candidate set cache for subsequent generation and traversal of architecture combination strategies.

[0105] Based on all candidate memories, various architecture combination strategies are generated. Each candidate memory has two architecture options: a conventional interface-type memory with an in-memory self-test architecture or a shared bus-type memory with an in-memory self-test architecture. A total of 2 architecture combinations are generated from all m candidate memories. m A strategy for combining different architectures.

[0106] For each architecture combination strategy, the architecture partitioning of non-candidate memories is kept consistent with the target boundary point, and only the architecture configuration of candidate memories is changed to form a complete architecture partitioning scheme. For each complete architecture partitioning scheme, the total global normalized area, the total global normalized timing penalty, and the total global normalized test time are recalculated based on the area model, the timing penalty model, and the test time model.

[0107] The global objective function value for each architecture combination strategy is calculated using the global objective function value. The calculation formula is as follows: ; in, , , These represent the normalized dimensionless values ​​of total area overhead, total timing penalty, and total test time under the current architecture partitioning scheme.

[0108] Compare all 2 m The global objective function value corresponding to each architecture combination strategy is calculated, and the architecture combination strategy with the smallest global objective function value is selected as the in-boundary combination strategy. The in-boundary combination strategy is the optimal architecture configuration for the candidate memory, with an O(2^3) time complexity. m The controllable exhaustive complexity captures the combined effects between memory locations, making up for the limitations of the first-stage greedy strategy and further improving the global optimal solution.

[0109] The multi-memory test architecture is determined based on other memories outside the target boundary and the combination strategy within the boundary.

[0110] Specifically, the architecture division of non-candidate memories at the target boundary point is combined with the combination strategy within the boundary point: for non-candidate memories, the architecture selection determined by the target boundary point is maintained, that is, the memory on one side of the target boundary point adopts a shared bus type memory built-in self-test architecture, and the memory on the other side adopts a conventional interface type memory built-in self-test architecture; for candidate memories, the architecture configuration determined by the combination strategy within the boundary point is adopted.

[0111] The merged complete architecture partitioning scheme is used as the final output of the multi-memory test architecture to guide each memory in selecting either the built-in self-test architecture of a conventional interface type memory or the built-in self-test architecture of a shared bus type memory for implementation.

[0112] Please see Figure 2 , Figure 2 This embodiment of the present application provides a schematic block diagram of a multi-memory test architecture determination apparatus, which is used to perform the aforementioned multi-memory test architecture determination method. The multi-memory test architecture determination apparatus can be configured on a server.

[0113] like Figure 2 As shown, the multi-memory test architecture determination apparatus 400 includes: The target weight coefficient configuration module 410 is used to obtain attribute information of at least two memories and configure each target weight coefficient. The attribute information includes the bit width, depth, function bus identifier, bit width splicing group identifier and corresponding register-to-memory path timing margin of each memory. The target weight coefficient includes target area weight coefficient, target timing penalty weight coefficient and target test time weight coefficient. The normalized information calculation module 420 is used to calculate the normalized area overhead, normalized timing penalty, and normalized test time of each memory under the built-in self-test MBIST architecture of a conventional interface type memory based on a preset area model, timing penalty model, and test time model. The global objective function value calculation module 430 is used to calculate the shared fitness score and global objective function value of each memory based on the normalized area overhead, the normalized timing penalty, the normalized test time, and each of the objective weight coefficients. The target boundary point determination module 440 is used to change each of the memories to a shared bus type MBIST architecture one by one according to the ranking of the shared adaptability scores, determine the total number of change steps, and determine the target boundary point according to the number of change steps and the global objective function value; The multi-memory test architecture determination module 450 is used to determine a preset number of candidate memories based on the target boundary point, traverse the architecture combination strategy of each candidate memory, and determine the multi-memory test architecture based on the architecture combination strategy and the global objective function value.

[0114] Furthermore, the target weight coefficient configuration module 410 includes: The bit width and depth extraction unit is used to extract the bit width and depth of each memory from the chip design database; A function bus identifier determination unit is used to parse the function bus connection relationship and determine the function bus identifier; The bit-width splicing group identifier determination unit is used to identify the bit-width splicing configuration and determine the bit-width splicing group identifier of each memory. The path timing margin acquisition unit is used to perform static timing analysis to acquire the path timing margin from the register to the memory corresponding to each memory.

[0115] Furthermore, the target weight coefficient configuration module 410 includes: The original coefficient acquisition unit is used to acquire the original area weight coefficient, the original time penalty weight coefficient, and the original test time weight coefficient. The target weight coefficient configuration unit is used to adjust the original area weight coefficient, the original timing penalty weight coefficient and / or the original test time weight coefficient according to the preset design requirements and the preset weight configuration template, and to determine each of the target weight coefficients, wherein the sum of each of the target weight coefficients is 1.

[0116] Furthermore, the normalized information calculation module 420 includes: The normalized area overhead acquisition unit is used to calculate the observation logic area and bypass logic area based on the area model and the number of port signals of each memory, calculate the differential logic area based on the address bit width and data bit width of each memory, combine the controller area of ​​the MBIST architecture to obtain the original area overhead of each memory, and normalize the original area overhead based on a preset area engineering to obtain the normalized area overhead. The normalized timing penalty acquisition unit is used to calculate the original timing penalty value based on the timing penalty model and the path timing margin corresponding to each memory, and to normalize the original timing penalty value based on a preset timing penalty process to obtain the normalized timing penalty. The normalized test time acquisition unit is used to calculate the original test time based on the test time model, according to the depth of each memory, the constant coefficient of the test algorithm and the clock cycle, and to normalize the original test time based on the preset test time engineering to obtain the normalized test time.

[0117] Furthermore, the global objective function value calculation module 430 includes: The shared fitness score acquisition unit is used to multiply the normalized area cost, the normalized time penalty, and the normalized test time by each of the target weight coefficients and then sum them up in a weighted manner to obtain the shared fitness score. The normalized total amount acquisition unit is used to calculate the total global normalized area, the total global normalized time penalty, and the total global normalized test time based on the normalized area cost, the normalized timing penalty, and the normalized test time, respectively. The global objective function value acquisition unit is used to obtain the global objective function value based on the total global normalized area, the total global normalized time penalty, the total global normalized test time, and each of the objective weight coefficients.

[0118] Furthermore, the target boundary point determination module 440 includes: A conventional interface-type MBIST architecture initialization unit is used to initialize each of the memories into the conventional interface-type MBIST architecture. The change step recording unit is used to change each of the memories to the shared bus type MBIST architecture according to the sorting of the shared adaptability scores, and record each change of a memory as a change step; The total number of change steps determination unit is used to sum up each of the change steps to obtain the total number of change steps; The target boundary point determination unit is used to select the memory corresponding to the number of change steps with the smallest global objective function value as the target boundary point.

[0119] Furthermore, the multi-memory test architecture determination module 450 includes: A candidate memory determination unit is used to determine the preset number of candidate memories centered on the target boundary point; A global objective function value calculation unit is used to generate each of the architecture combination strategies based on all the candidate memories, and to calculate the global objective function value corresponding to each of the architecture combination strategies through the global objective function value. A multi-memory test architecture determination unit is used to select the architecture combination strategy with the smallest global objective function value as the intra-boundary combination strategy, and to determine the multi-memory test architecture based on the other memories outside the objective boundary and the intra-boundary combination strategy.

[0120] It should be noted that those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the above-described apparatus and modules can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0121] The aforementioned device can be implemented as a computer program, which can be used in, for example... Figure 3 It runs on the computer device shown.

[0122] Please see Figure 3 , Figure 3 This is a schematic block diagram illustrating the structure of a computer device according to an embodiment of this application. The computer device may be a server.

[0123] See Figure 3 The computer device includes a processor, memory, and network interface connected via a system bus, wherein the memory may include non-volatile storage media and internal memory.

[0124] Non-volatile storage media can store operating systems and computer programs. These computer programs include program instructions that, when executed, cause the processor to perform any multi-memory test architecture determination method.

[0125] The processor provides computing and control capabilities, supporting the operation of the entire computer device.

[0126] Internal memory provides an environment for the execution of computer programs in non-volatile storage media, which, when executed by a processor, enable the processor to perform any multi-memory test architecture determination method.

[0127] This network interface is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0128] It should be understood that the processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, a general-purpose processor can be a microprocessor or any conventional processor.

[0129] In one embodiment, the processor is configured to run a computer program stored in memory to perform the following steps: Obtain attribute information of at least two memories and configure each target weight coefficient. The attribute information includes the bit width, depth, function bus identifier, bit width splicing group identifier and the corresponding timing margin of the path from the register to the memory for each memory. The target weight coefficient includes target area weight coefficient, target timing penalty weight coefficient and target test time weight coefficient. Based on the preset area model, timing penalty model, and test time model, the normalized area overhead, normalized timing penalty, and normalized test time of each memory under the built-in self-test MBIST architecture of a conventional interface memory are calculated. Based on the normalized area overhead, the normalized timing penalty, the normalized test time, and each of the target weight coefficients, calculate the shared adaptability score and global objective function value of each memory. Based on the ranking of the shared adaptability scores, each memory is changed to a shared bus MBIST architecture one by one, the total number of change steps is determined, and the target boundary point is determined based on the number of change steps and the global objective function value; A preset number of candidate memories are determined based on the target boundary point, and the architecture combination strategy of each candidate memory is traversed. A multi-memory test architecture is determined based on the architecture combination strategy and the global objective function value.

[0130] In one embodiment, attribute information of at least two memories is obtained to achieve: Extract the bit width and depth of each memory from the chip design database; Analyze the function bus connection relationships to determine the function bus identifier; Identify the bit-width splicing configuration and determine the bit-width splicing group identifier for each of the memories; Perform static timing analysis to obtain the path timing margin from the register to the memory corresponding to each memory.

[0131] In one embodiment, the weight coefficients for each objective are configured to achieve the following: Obtain the original area weight coefficient, the original time penalty weight coefficient, and the original test time weight coefficient; Adjust the original area weight coefficient, the original time penalty weight coefficient, and / or the original test time weight coefficient according to the preset design requirements and preset weight configuration template to determine each of the target weight coefficients, wherein the sum of each of the target weight coefficients is 1.

[0132] In one embodiment, based on a preset area model, timing penalty model, and test time model, the normalized area overhead, normalized timing penalty, and normalized test time of each memory under the built-in self-test MBIST architecture in a conventional interface-type memory are calculated to achieve: Based on the area model, the observation logic area and bypass logic area are calculated according to the number of port signals of each memory, and the differential logic area is calculated according to the address bit width and data bit width of each memory. Combined with the controller area of ​​the MBIST architecture, the original area overhead of each memory is obtained, and the original area overhead is normalized based on the preset area engineering to obtain the normalized area overhead. Based on the timing penalty model, the original timing penalty value is calculated according to the path timing margin corresponding to each memory, and the original timing penalty value is normalized based on the preset timing penalty engineering to obtain the normalized timing penalty. Based on the test time model, the original test time is calculated according to the depth of each memory, the constant coefficient of the test algorithm, and the clock cycle. The original test time is then normalized based on a preset test time engineering to obtain the normalized test time.

[0133] In one embodiment, the shared fitness score and global objective function value of each memory are calculated based on the normalized area overhead, the normalized timing penalty, the normalized test time, and each of the target weight coefficients, for the purpose of: The normalized area cost, the normalized timing penalty, and the normalized test time are multiplied by each of the target weight coefficients and then summed in a weighted manner to obtain the shared fitness score. Calculate the total global normalized area, the total global normalized timing penalty, and the total global normalized test time based on the normalized area cost, the normalized timing penalty, and the normalized test time, respectively. The global objective function value is obtained based on the total global normalized area, the total global normalized time penalty, the total global normalized test time, and the weight coefficients of each objective.

[0134] In one embodiment, each memory is converted to a shared bus MBIST architecture one by one according to the ranking of the shared adaptability scores, the total number of conversion steps is determined, and a target boundary point is determined based on the number of conversion steps and the global objective function value, for the purpose of: Each of the aforementioned memories is initialized to the conventional interface-type MBIST architecture; According to the sorting of the shared adaptability scores, each memory is changed to the shared bus type MBIST architecture, and each change of a memory is recorded as a change step; The summation of each change step is taken as the total number of change steps. The memory corresponding to the number of change steps with the smallest global objective function value is selected as the objective boundary point.

[0135] In one embodiment, a preset number of candidate memories are determined based on the target boundary point, and the architecture combination strategy of each candidate memory is traversed. A multi-memory test architecture is then determined based on the architecture combination strategy and the global objective function value, for the purpose of: Using the target boundary point as the center, determine the preset number of candidate memories; Each of the aforementioned architecture combination strategies is generated based on all the aforementioned candidate memories, and the global objective function value corresponding to each of the aforementioned architecture combination strategies is calculated using the global objective function value; The architecture combination strategy with the smallest global objective function value is selected as the in-boundary combination strategy, and the multi-memory test architecture is determined based on the other memories outside the target boundary and the in-boundary combination strategy.

[0136] The embodiments of this application also provide a computer-readable storage medium storing a computer program, the computer program including program instructions, and the processor executing the program instructions to implement any of the multi-memory test architecture determination methods provided in the embodiments of this application.

[0137] The computer-readable storage medium may be an internal storage unit of the computer device described in the foregoing embodiments, such as the hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, SmartMedia Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the computer device.

[0138] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for determining a multi-memory test architecture, characterized in that, include: Obtain attribute information of at least two memories and configure each target weight coefficient. The attribute information includes the bit width, depth, function bus identifier, bit width splicing group identifier and the corresponding timing margin of the path from the register to the memory for each memory. The target weight coefficient includes target area weight coefficient, target timing penalty weight coefficient and target test time weight coefficient. Based on the preset area model, timing penalty model, and test time model, the normalized area overhead, normalized timing penalty, and normalized test time of each memory under the built-in self-test MBIST architecture of a conventional interface memory are calculated. Based on the normalized area overhead, the normalized timing penalty, the normalized test time, and each of the target weight coefficients, calculate the shared adaptability score and global objective function value of each memory. Based on the ranking of the shared adaptability scores, each memory is changed to a shared bus MBIST architecture one by one, the total number of change steps is determined, and the target boundary point is determined based on the number of change steps and the global objective function value; A preset number of candidate memories are determined based on the target boundary point, and the architecture combination strategy of each candidate memory is traversed. A multi-memory test architecture is determined based on the architecture combination strategy and the global objective function value.

2. The method for determining a multi-memory test architecture according to claim 1, characterized in that, The acquisition of attribute information from at least two memories includes: Extract the bit width and depth of each memory from the chip design database; Analyze the function bus connection relationships to determine the function bus identifier; Identify the bit-width splicing configuration and determine the bit-width splicing group identifier for each of the memories; Perform static timing analysis to obtain the path timing margin from the register to the memory corresponding to each memory.

3. The method for determining a multi-memory test architecture according to claim 2, characterized in that, The configuration of each target weight coefficient includes: Obtain the original area weight coefficient, the original time penalty weight coefficient, and the original test time weight coefficient; Adjust the original area weight coefficient, the original time penalty weight coefficient, and / or the original test time weight coefficient according to the preset design requirements and preset weight configuration template to determine each of the target weight coefficients, wherein the sum of each of the target weight coefficients is 1.

4. The method for determining a multi-memory test architecture according to claim 1, characterized in that, The calculation of normalized area overhead, normalized timing penalty, and normalized test time for each memory under the built-in self-testing MBIST architecture in a conventional interface-type memory, based on a preset area model, timing penalty model, and test time model, includes: Based on the area model, the observation logic area and bypass logic area are calculated according to the number of port signals of each memory, and the differential logic area is calculated according to the address bit width and data bit width of each memory. Combined with the controller area of ​​the MBIST architecture, the original area overhead of each memory is obtained, and the original area overhead is normalized based on the preset area engineering to obtain the normalized area overhead. Based on the timing penalty model, the original timing penalty value is calculated according to the path timing margin corresponding to each memory, and the original timing penalty value is normalized based on the preset timing penalty engineering to obtain the normalized timing penalty. Based on the test time model, the original test time is calculated according to the depth of each memory, the constant coefficient of the test algorithm, and the clock cycle. The original test time is then normalized based on a preset test time engineering to obtain the normalized test time.

5. The method for determining a multi-memory test architecture according to claim 1, characterized in that, The step of calculating the shared fitness score and global objective function value of each memory based on the normalized area overhead, the normalized timing penalty, the normalized test time, and each of the target weight coefficients includes: The normalized area cost, the normalized timing penalty, and the normalized test time are multiplied by each of the target weight coefficients and then summed in a weighted manner to obtain the shared fitness score. Calculate the total global normalized area, the total global normalized timing penalty, and the total global normalized test time based on the normalized area cost, the normalized timing penalty, and the normalized test time, respectively. The global objective function value is obtained based on the total global normalized area, the total global normalized time penalty, the total global normalized test time, and the weight coefficients of each objective.

6. The method for determining a multi-memory test architecture according to claim 1, characterized in that, The step of changing each memory to a shared bus MBIST architecture one by one according to the ranking of the shared adaptability scores, determining the total number of change steps, and determining the target boundary point according to the number of change steps and the global objective function value includes: Each of the aforementioned memories is initialized to the conventional interface-type MBIST architecture; According to the sorting of the shared adaptability scores, each memory is changed to the shared bus type MBIST architecture, and each change of a memory is recorded as a change step; The summation of each change step is taken as the total number of change steps. The memory corresponding to the number of change steps with the smallest global objective function value is selected as the objective boundary point.

7. The method for determining a multi-memory test architecture according to claim 1, characterized in that, The step of determining a preset number of candidate memories based on the target boundary point, traversing the architecture combination strategy of each candidate memory, and determining the multi-memory test architecture based on the architecture combination strategy and the global objective function value includes: Using the target boundary point as the center, determine the preset number of candidate memories; Each of the aforementioned architecture combination strategies is generated based on all the aforementioned candidate memories, and the global objective function value corresponding to each of the aforementioned architecture combination strategies is calculated using the global objective function value; The architecture combination strategy with the smallest global objective function value is selected as the in-boundary combination strategy, and the multi-memory test architecture is determined based on the other memories outside the objective boundary and the in-boundary combination strategy.

8. A multi-memory test architecture determination apparatus, characterized in that, include: The target weight coefficient configuration module is used to obtain attribute information of at least two memories and configure each target weight coefficient. The attribute information includes the bit width, depth, function bus identifier, bit width splicing group identifier and the corresponding timing margin of the path from the register to the memory for each memory. The target weight coefficient includes target area weight coefficient, target timing penalty weight coefficient and target test time weight coefficient. The normalized information calculation module is used to calculate the normalized area overhead, normalized timing penalty, and normalized test time of each memory under the built-in self-test MBIST architecture of a conventional interface memory, based on a preset area model, timing penalty model, and test time model. The global objective function value calculation module is used to calculate the shared fitness score and global objective function value of each memory based on the normalized area overhead, the normalized timing penalty, the normalized test time, and each of the objective weight coefficients. The target boundary point determination module is used to change each of the memories to a shared bus MBIST architecture one by one according to the ranking of the shared adaptability scores, determine the total number of change steps, and determine the target boundary point according to the number of change steps and the global objective function value; The multi-memory test architecture determination module is used to determine a preset number of candidate memories based on the target boundary point, traverse the architecture combination strategy of each candidate memory, and determine the multi-memory test architecture based on the architecture combination strategy and the global objective function value.

9. A computer device, characterized in that, The computer device includes a memory and a processor; The memory is used to store computer programs; The processor is configured to execute the computer program and, in executing the computer program, implement the multi-memory test architecture determination method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to implement the multi-memory test architecture determination method as described in any one of claims 1 to 7.

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