Test data processing system, algorithmic pattern generator, memory chip automated test equipment, link protection code generation method, test data processing method and computer program product

Abstract

This application discloses a test data processing system, an algorithm graphics generator, an automated testing device for memory chips, a link protection code generation method, a test data processing method, and a computer program product, belonging to the field of memory chip testing technology. The system includes: a configuration register group for storing static preset parameters of the current test mode, the static preset parameters including at least the storage interface protocol rules used in the current test mode; a burst context extraction circuit for real-time detection of the start signal of burst transmission during the dynamic operation of the algorithm graphics generator, extracting dynamic burst information and raw test data of the current burst transmission; and a link protection code generation circuit for dynamically generating the link protection code of the current burst transmission by parsing the dynamic burst information and raw test data according to the storage interface protocol rules obtained from the configuration register group. This application can significantly reduce testing complexity and significantly improve testing efficiency.

Description

Technical Field

[0001] This application relates to the field of memory chip testing technology, and in particular to a test data processing system, an algorithm graphics generator, an automated testing device for memory chips, a link protection code generation method, a test data processing method, and a computer program product. Background Technology

[0002] Link Protection Code (LPC) is a type of integrity verification field embedded in the data transmitted by a high-speed storage interface protocol. It is used by the receiving end to detect whether errors have occurred during data transmission.

[0003] Existing link protection codes typically rely on offline preprocessing for generation. This involves pre-calculating the corresponding link protection codes using offline scripts and preloading the static test data containing these codes into the memory of the automated test equipment (ATE) for subsequent test pattern execution. This method results in high complexity and low testing efficiency because the link protection codes are statically coupled to the original test data, require separate maintenance of offline scripts for each storage interface protocol and test mode, and necessitates regenerating and reloading all data whenever test parameters change. Summary of the Invention

[0004] This application provides a test data processing system, an algorithm graphics generator, an automated testing device for memory chips, a link protection code generation method, a test data processing method, and a computer program product, which significantly reduce testing complexity, greatly improve testing efficiency, and support the reuse of test data for different protocols.

[0005] In a first aspect, embodiments of this application provide a test data processing system, applied to an algorithmic graphics generator of an automated testing equipment for memory chips, the test data processing system comprising: A configuration register group is used to store static preset parameters for the current test mode. The static preset parameters include at least the storage interface protocol rules used by the current test mode. A burst context extraction circuit, connected to the configuration register group, is used to detect the start signal of burst transmission in real time during the dynamic operation of the algorithm graphics generator, and extract the dynamic burst information and raw test data of the current burst transmission. The link protection code generation circuit, connected to the burst context extraction circuit and the configuration register group, is used to parse the dynamic burst information and original test data according to the storage interface protocol rules obtained from the configuration register group, and dynamically generate the link protection code for the current burst transmission.

[0006] In at least one possible implementation, the link protection code generation circuit specifically includes: The bit mapping unit is used to perform bit mapping on the original test data according to the bit mapping rules of the current storage interface protocol and the dynamic burst information to form mapped data; The encoding calculation unit, connected to the bit mapping unit, is used to perform encoding calculations on the mapped data according to the encoding rules of the current storage interface protocol, and generate redundant check bits as the link protection code.

[0007] In at least one possible implementation, the dynamic burst information includes at least the starting address and burst length of the current burst transmission, and the bit mapping unit includes: The sequential arrangement of sub-units is used to identify the start and end boundaries of the current burst transmission, and to arrange the data units in the original test data in address order, at least according to the start address and burst length. The rearrangement subunit, connected to the sequential arrangement subunit, is used to rearrange the data units arranged in address order according to the bit mapping rule, as the mapped data.

[0008] In at least one possible implementation, the encoding calculation includes cyclic redundancy check or link error correction code encoding calculation.

[0009] In at least one possible implementation, the dynamic burst information further includes the read / write direction of the current burst transmission, and the bit mapping unit or the encoding calculation unit is further configured to select the corresponding bit mapping rule or encoding rule according to the read / write direction.

[0010] In at least one possible implementation, the static preset parameter further includes the data bus width of the chip under test; The burst context extraction circuit is also used to determine the number of parallel data bits for each data cycle based on the data bus width, so as to extract the original test data of the corresponding bit width. The bit mapping unit is also used to divide the raw test data into data units that match the encoder input granularity according to the data bus width.

[0011] In at least one possible implementation, the static preset parameters further include the encoding enable state of the current test mode, and the link protection code generation circuit includes: Multiple protocol-specific processing branches are independently set up for each storage interface protocol. Each protocol-specific processing branch is used to generate the link protection code according to its corresponding storage interface protocol. A multiplexer is used to select the link protection code generated by the corresponding protocol-specific processing branch from each of the protocol-specific processing branches according to the currently configured storage interface protocol type.

[0012] In at least one possible implementation, the system further includes: An output routing circuit, connected to the multiplexer, is used to embed the generated link protection code into the original test data at a fixed output position specified by the storage interface protocol, thereby forming the target test data output.

[0013] In at least one possible implementation, each protocol-specific processing branch contains a bit mapping circuit and an encoding logic circuit corresponding to the storage interface protocol.

[0014] In at least one possible implementation, the link protection code generation circuit is configured as a general logic calculation matrix.

[0015] In at least one possible implementation, the static preset parameters further include mask information, and the general logical calculation matrix specifically includes: A bit-select array is connected to the configuration register group. Its input receives raw test data and is used to select the bits to participate in the operation from the raw test data according to the bit mapping mask in the mask information, and output the selected data. An XOR operation array, connected to the bit selection array, is used to perform an XOR operation on the selected data to generate a link protection code and embed it into the output data.

[0016] In at least one possible implementation, the static preset parameters further include an encoding enable state, and the link protection code generation circuit determines whether to perform the generation operation based on the encoding enable state.

[0017] Secondly, embodiments of this application provide an algorithmic graphics generator, which includes the test data processing system as described in the first aspect.

[0018] Thirdly, embodiments of this application provide an automated testing device for memory chips, which includes a test data processing system as described in the first aspect or an algorithm graphics generator as described in the second aspect.

[0019] Fourthly, embodiments of this application provide a link protection code generation method, applied to automated testing equipment for memory chips, the link protection code generation method comprising: During the dynamic operation of the algorithm graphics generator, the start signal of burst transmission is detected in real time, and the dynamic burst information and raw test data of the current burst transmission are extracted. Based on the current storage interface protocol rules, the dynamic burst information and the original test data are parsed to dynamically generate the link protection code for the current burst transmission; The current storage interface protocol rules are obtained from the static preset parameters of the current test mode.

[0020] In at least one possible implementation, the dynamic generation of the link protection code for the current burst transmission specifically includes: According to the bit mapping rules of the current storage interface protocol, the original test data is bit-mapped based on the dynamic burst information to form mapped data; The mapped data is encoded according to the encoding rules of the current storage interface protocol to generate a redundancy check bit, which serves as the link protection code.

[0021] In at least one possible implementation, the dynamic burst information includes at least the starting address and burst length of the current burst transmission, and the bit mapping of the original test data based on the dynamic burst information to form mapped data specifically includes: The data units in the original test data are arranged in address order at least according to their starting address and burst length; The data units arranged in address order are rearranged according to the bit mapping rules of the current storage interface protocol to form the mapping data.

[0022] In at least one possible implementation, the static preset parameter further includes an encoded enable state.

[0023] In at least one possible implementation, the encoding calculation is a cyclic redundancy check or link error correction code encoding calculation.

[0024] In at least one possible implementation, the dynamic burst information further includes the read / write direction of the current burst transmission, and before the bit mapping or encoding calculation, it further includes selecting the corresponding bit mapping rule or encoding rule according to the read / write direction.

[0025] In at least one possible implementation, the static preset parameter further includes the data bus width of the chip under test; Before the encoding calculation, the raw data is further divided into data units that match the encoder input granularity according to the data bus width; When extracting the raw test data, the number of parallel data bits for each data cycle is determined based on the data bus width.

[0026] Fifthly, embodiments of this application provide a test data processing method applied to an automated testing equipment for memory chips, the test data processing method comprising: Generate a link protection code according to the link protection code generation method described in the fourth aspect; The generated link protection code for the current burst transmission is embedded into the original test data to form a complete target test data output.

[0027] In at least one possible implementation, embedding the generated link protection code of the current burst transmission into the original test data specifically includes: According to the fixed output position rules of the current storage interface protocol and the dynamic control signals issued by the algorithm graphics generator, the generated link protection code is written into the original test data according to the predetermined output arrangement to form the target test data. The target test data is output from at least one pre-configured data path.

[0028] Sixthly, embodiments of this application provide a computer program product, the computer program product comprising: computer program code, which, when run on a computer, causes the computer to perform steps in the link protection code generation method as described in the fourth aspect or steps in the test data processing method as described in the fifth aspect.

[0029] The beneficial effects of this application are: This application embodiment configures static preset parameters in the configuration register group and pre-stores the storage interface protocol rules of the static test mode, enabling the system to flexibly adapt to multiple storage interface protocols. The burst context extraction circuit captures the dynamic information of each burst transmission in real time, achieving dynamic perception of the original test data. Furthermore, the link protection code generation circuit calculates the link protection code required for the current burst transmission in real time based on static rules and dynamic burst information during the dynamic operation of the algorithm graphics generator, ensuring a perfect match between the link protection code and the data transmission time. This significantly improves the anti-interference capability and transmission reliability of the test data, significantly enhances test efficiency and accuracy, and reduces test complexity. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of the test data processing system according to an embodiment of this application.

[0032] Figure 2This is a schematic diagram of the link protection code generation circuit in the test data processing system of this application embodiment.

[0033] Figure 3 This is a schematic diagram of the structure of the bit mapping unit in the test data processing system of this application embodiment.

[0034] Figure 4 This is a schematic diagram of the structure of the test data processing system according to the first embodiment of this application.

[0035] Figure 5 This is a schematic diagram of the structure of a second embodiment of the test data processing system of this application.

[0036] Figure 6 This is a schematic diagram of the structure of an automated testing device for memory chips according to an embodiment of this application.

[0037] Figure 7 This is a flowchart illustrating the link protection code generation method according to an embodiment of this application.

[0038] Figure 8 This is a schematic diagram of the link protection code calculation process in the link protection code generation method of this application embodiment.

[0039] Figure 9 This is a schematic diagram of the bit mapping process of the link protection code generation method according to an embodiment of this application.

[0040] Figure 10 This is a flowchart illustrating the test data processing method according to an embodiment of this application.

[0041] Explanation of reference numerals in the attached figures: 1. Configure the register set; 2. Burst context extraction circuit; 3. Link protection code generation circuit; 30. General logic calculation matrix; 31. Bit mapping unit; 32. Encoding calculation unit; 311. Sequential arrangement subunit; 312. Rearrangement subunit; 301. Protocol-specific processing branch; 302. Multiplexer; 303. Output layout circuit; 304. Bit selection array; 305. XOR operation array. 10. Test data processing system; 100. Algorithm graphics generator; 1000. Automated testing equipment for memory chips. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be described in detail below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0043] It should be noted that: throughout the accompanying drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions; in the description of this application, the terms "center," "longitudinal," "lateral," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; in the description of this application, "first," "second," etc., are only used to distinguish each other, and do not indicate their degree of importance or order, etc.

[0044] In the description of this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to fixed connections, movable connections, or detachable connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal communication between two components, etc. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0045] In the field of semiconductor testing technology, automated testing equipment for memory chips needs to support multiple memory interface protocols, multiple encoding methods, and chips under test with different bit widths. Testing memory chips typically requires writing a large number of test patterns. For Dynamic Random Access Memory (DRAM) that uses high-speed memory protocols, such as some generations of DDR, LPDDR, and GDDR memory chips, the test patterns not only need to reflect the protocol transaction sequence and raw data, but also usually need to meet the requirements of the target protocol for link integrity protection fields.

[0046] Existing link protection code generation methods typically rely on offline preprocessing. Based on the target protocol and transaction parameters, the corresponding link protection code needs to be pre-calculated using an offline script, and static test data containing the link protection code is pre-loaded into the ATE's internal memory for subsequent test execution. While this method is advantageous for local development and debugging targeting a single protocol or transaction mode, offering advantages such as direct implementation and low environment dependency, it still has the following drawbacks: In existing DRAM protocols of various generations, there are often significant differences in the rules regarding the input arrangement, calculation logic, and output mapping of the link protection field. This results in complex and difficult-to-reuse logic for generating related test vectors. To address the differences in input bit mapping, calculation logic, and output location rules among different DRAM protocols, it is necessary to maintain independent offline link protection code generation scripts for each protocol, making it difficult to reuse them in a unified test graph writing process. Even under the same protocol, changes in read / write direction, burst transmission order, data length, bit mapping relationships, and other state variations will alter the link protection code generation rules. Since the offline script generation results are static, any minor adjustments to the test conditions often require rerunning the script and reloading the test data. In the final test data, the statically generated link protection code is coupled with the original test data, making it difficult to directly trace back the original test algorithm intent, protocol state, or specific burst boundary from the final test data. This results in an opaque test graph development process, invisible debugging logic, and low efficiency in subsequent location and maintenance. When the same protocol rule needs to serve different test scenarios, it is still necessary to maintain the interrelated static results separately. Once the rule configuration is updated, transaction parameters are adjusted, or the original data is changed, if the relevant results are not recalculated and reloaded synchronously, it can easily lead to data inconsistency or comparison failure, affecting test development and debugging efficiency.

[0047] In view of this, embodiments of this application provide a test data processing system applied to the Algorithmic Pattern Generator (ALPG) of automated testing equipment for memory chips. This system can dynamically generate corresponding link protection codes based on configured mode parameters, runtime burst information, and raw data, while taking into account the differences between various DRAM protocols. This supports data reuse in different testing scenarios, thereby significantly improving testing efficiency and accuracy while reducing testing complexity. Please refer to... Figure 1 The test data processing system includes: Configure register group 1 to store static preset parameters for the current test mode. The static preset parameters include at least the storage interface protocol rules used by the current test mode. The burst context extraction circuit 2, connected to the configuration register group 1, is used to detect the start signal of burst transmission in real time during the dynamic operation of the algorithm graphics generator, and extract the dynamic burst information and raw test data of the current burst transmission. The link protection code generation circuit 3 is connected to the burst context extraction circuit 2 and the configuration register group 1. It is used to parse the dynamic burst information and the original test data according to the storage interface protocol rules obtained from the configuration register group 1, and dynamically generate the link protection code for the current burst transmission.

[0048] In automated testing of memory chips, the algorithm graphics generator needs to send a large amount of test data to the chip under test. However, different memory interface protocols (such as DDR4, DDR5, GDDR6, etc.) have different requirements for data link protection, and burst transmissions have dynamic characteristics (such as different burst lengths, starting addresses, read / write directions, etc.). Existing technologies use offline scripts to add protection codes, which cannot adapt to the real-time changing burst transmission context. This makes it very easy for the link protection codes to be mismatched with the actual situation, thus affecting the integrity and reliability of the test data.

[0049] In this embodiment, by configuring static preset parameters in configuration register group 1 and pre-storing the storage interface protocol rules of the static test mode, the system can flexibly adapt to multiple storage interface protocols; by capturing the dynamic information of each burst transmission in real time through burst context extraction circuit 2, dynamic perception of the original test data is realized; and by calculating the link protection code required for the current burst transmission in real time based on static rules and dynamic burst information through link protection code generation circuit 3, the protection code is ensured to be perfectly matched with the data transmission time, which greatly improves the anti-interference ability and transmission reliability of the test data.

[0050] Configuration register group 1 can consist of a set of readable and writable registers. For example, multiple registers can be instantiated inside the FPGA, and static parameters such as protocol type, bus width, and encoding enable can be written through the host computer configuration interface.

[0051] The burst context extraction circuit 2 can continuously parse the control command words output by the front-end module. When a valid burst start control word is detected, a burst transmission is determined to have started, thereby extracting dynamic burst information such as column address, burst sequence, and burst length at that moment.

[0052] The link protection code generation circuit 3 can be implemented using combinational logic or sequential logic, and performs Cyclic Redundancy Check (CRC) or Link Error Correction Code (Link ECC) encoding on the data according to the protocol rules.

[0053] The entire system can be integrated into the ALPG module of ATE and run in a hardware pipeline manner, without occupying software processing time, and the response speed is exponentially faster than software processing.

[0054] In at least one possible implementation, the storage interface protocol includes any one of the following: DDR4 protocol, DDR5 protocol, GDDR5 protocol, GDDR6 protocol, and LPDDR5 protocol. It can also be dynamically added or removed as needed during subsequent maintenance.

[0055] Please refer to Figure 2 In at least one possible implementation, the link protection code generation circuit 3 specifically includes: Bit mapping unit 31 is used to perform bit mapping on the original test data according to the bit mapping rules of the current storage interface protocol and the dynamic burst information to form mapped data; The encoding calculation unit 32, connected to the bit mapping unit 31, is used to perform encoding calculations on the mapped data according to the encoding rules of the current storage interface protocol to generate redundant check bits as the link protection code.

[0056] In different storage interface protocols, the input of encoding algorithms typically requires data to be arranged in a specific order. Directly encoding the raw test data will result in calculation results that do not conform to the protocol specifications, thus failing to be correctly verified by the receiving end. Therefore, it is necessary to rearrange the data units in the raw test data according to the bit mapping rules corresponding to the protocol, so as to meet the encoder input order specified by the current storage interface protocol.

[0057] In this embodiment, a bit mapping unit 31 is set up to convert the original test data into mapped data that conforms to the requirements of the current protocol. Then, the encoding calculation unit 32 performs the encoding, thereby ensuring that the generated link protection code fully complies with the protocol specifications and that the receiving end can correctly decode and verify it. In addition, this structure separates mapping and encoding, which facilitates the reuse of different mapping rules and encoding algorithms.

[0058] The bit mapping unit 31 in this embodiment can be implemented using a crossbar or a multiplexer array to dynamically select data bits based on the address and sequence signals in the dynamic burst information. According to the corresponding storage interface protocol, the encoding calculation automatically selects the corresponding encoding polynomial, segmented calculation order, and intermediate result combination relationship according to the rules of the storage interface protocol. The encoding rules under different protocol types differ in at least one aspect of the encoding polynomial, segmented calculation order, and intermediate result combination relationship. For example, the encoding calculation can be CRC (such as DDR4) or Link ECC encoding calculation (such as LPDDR5). Accordingly, the encoding calculation unit 32 can be implemented using an XOR circuit.

[0059] Please refer to Figure 3 In at least one possible implementation, the dynamic burst information includes at least information such as the starting address and burst length of the current burst transmission, and the bit mapping unit 31 specifically includes: Sequential arrangement subunit 311 is used to identify the start and end boundaries of the current burst transmission, and to arrange the data units in the original test data in address order at least according to the start address and burst length; The rearrangement subunit 312, connected to the sequential arrangement subunit 311, is used to rearrange the data units arranged in address order according to the bit mapping rule, as the mapping data.

[0060] In at least one possible implementation, the dynamic burst information also includes the read / write direction of the current burst transmission. The bit mapping unit 31 or the encoding calculation unit 32 is further configured to select the corresponding bit mapping rule or encoding rule according to the read / write direction. By selecting different mapping / encoding rules according to the read / write direction, the processing flow under different operations is optimized.

[0061] In at least one possible implementation, the static preset parameter further includes the data bus width of the chip under test; The burst context extraction circuit 2 is also used to determine the number of parallel data bits for each data cycle based on the data bus width, so as to extract the original test data of the corresponding bit width; The bit mapping unit 31 is also used to divide the original test data into data units that match the encoder input granularity according to the data bus width. By adaptively dividing the data units according to the bus width of the chip under test, the matching of the encoder input data granularity is ensured and the hardware utilization is improved.

[0062] In this embodiment of the application, a protocol selection field, an encoding enable field, an encoding type field, and a bus width field (such as x4, x8, x16, x32) can be added to the configuration register group 1.

[0063] The bit mapping unit 31 can switch the mapping mode of internal data bits according to dynamic burst information; the encoding calculation unit 32 can reuse different XOR polynomials according to different storage interface protocols.

[0064] Please refer to Figure 4 In at least one possible implementation, the static preset parameters further include the encoding enable state of the current test mode, and the link protection code generation circuit 3 includes: Multiple protocol-specific processing branches 301 are independently set up for each storage interface protocol. Each protocol-specific processing branch 301 is used to generate the link protection code according to its corresponding storage interface protocol. The multiplexer 302 is used to select the link protection code generated by the corresponding protocol-specific processing branch 301 from each of the protocol-specific processing branches 301 according to the currently configured storage interface protocol type.

[0065] The data processing flow, encoding algorithm, and timing requirements of different storage interface protocols vary greatly. Although it is possible to achieve this using a single reconfigurable circuit, it is easy to lead to complex circuit design, difficulty in timing convergence, and difficulty in achieving the optimal performance of each protocol at the same time.

[0066] In this embodiment, by setting up a dedicated processing branch 301 for each protocol independently, and performing in-depth optimization for each protocol-specific processing branch 301, the best area, power consumption and timing performance are obtained. At the same time, by switching between multiple dedicated processing branches 301 through a multiplexer 302, the user only needs to configure the protocol type to automatically select the correct processing path, which is simple and convenient to use.

[0067] The protocol-specific processing branch 301 in this embodiment can be configured with independent branches for DDR4, DDR5, GDDR6, etc. Each protocol-specific processing branch 301 internally contains the bit mapping circuit and encoding logic circuit corresponding to the memory interface protocol. The multiplexer 302 can be a combinational logic multiplexer, selecting one output according to the protocol type code in the configuration register group 1.

[0068] Please continue to refer to this. Figure 4 In at least one possible implementation, the system further includes: The output routing circuit 303 is connected to the multiplexer 302 and is used to embed the generated link protection code into the original test data according to the fixed output position specified by the storage interface protocol to form the target test data output.

[0069] Storage interface protocols (such as DDR5 and LPDDR5) strictly define the physical location of the link protection code during data transmission. For example: Some protocols require a CRC code to be appended to the last few cycles of a data burst.

[0070] Some protocols require Link ECC and data to appear on different data pins at the same time.

[0071] If the output position is incorrect, the chip under test (DUT) will read the protection code at the wrong position, resulting in verification failure and mistakenly believing that the link is faulty.

[0072] The link protection code generation circuit 3 calculates the value of the link protection code.

[0073] Therefore, after the link protection code is generated, it needs to be inserted into the original data stream at a fixed position specified by the protocol (such as the end of the data packet, a specific column address, etc.), and the insertion position varies depending on the protocol. If processed by a general-purpose circuit, additional address comparison and timing control are required.

[0074] In this embodiment of the application, by setting the embedding position of the link protection code in the output layout circuit 303, the output format of different protocols can be flexibly adapted, for example: Based on the fixed output location rules of the storage interface protocol, determine where to place the generated link protection code.

[0075] Based on the test graphic control information, we can determine whether the CRC should be output in the current cycle.

[0076] The link protection code is decomposed bit by bit and written to the corresponding position in the output data buffer.

[0077] The final target test data, containing the link protection code at the correct location, is sent to the subsequent data selector.

[0078] In at least one possible implementation, the link protection code generation circuit 3 is configured as a general logic calculation matrix 30.

[0079] When processing specific protocols, dedicated hardware branches offer advantages such as fewer logic layers, easier timing closure, and no parsing overhead, making them suitable for scenarios with extremely high test frequency requirements. However, dedicated hardware branches embed bit mapping, encoding order, and output arrangement rules internally within the circuit. When supporting new protocols or sub-modes, new processing branches must be added at the hardware logic circuit level. This results in protocol expansion requiring modifications to the hardware logic circuit, long update cycles, and limited flexibility. Therefore, please refer to... Figure 5 This application embodiment also provides a more flexible implementation method, namely, using a general logic calculation matrix 30, configuring different masks to simulate different calculation rules, and supporting new protocols or sub-modes through software updates without modifying the hardware circuit.

[0080] The general logic computation matrix 30 in this embodiment can be composed of a multi-layer XOR gate array, with each level corresponding to a coefficient term of the encoded polynomial. By configuring the mask information in register group 1, the connection method of the matrix can be changed, thereby realizing different generator polynomials.

[0081] Please continue to refer to this. Figure 5In at least one possible implementation, the static preset parameters further include mask information, and the general logic calculation matrix 30 specifically includes: The bit selection array 304 is connected to the configuration register group 1. Its input terminal receives the original test data and is used to select the bits to participate in the operation from the original test data according to the bit mapping mask in the mask information, and output the selected data. The XOR operation array 305 is connected to the bit selection array 304 and is used to perform XOR operation on the selected data to generate a link protection code and embed it into the output data.

[0082] In at least one possible implementation, the static preset parameters further include an encoding enable state, and the link protection code generation circuit 3 determines whether to perform the generation operation based on the encoding enable state.

[0083] In some test scenarios, link protection may not be necessary, and direct bypass coding can save power consumption and time.

[0084] In this embodiment of the application, the generation of protection codes can be dynamically enabled or disabled through the encoding enable state, which improves the flexibility of the system.

[0085] Based on the above embodiments, please refer to Figure 6 This application also provides an algorithmic graphics generator 100, which includes a test data processing system 10 as described in any at least one of the foregoing embodiments.

[0086] Traditional algorithmic graph generators are only responsible for generating test data and do not include the function of real-time insertion of link protection codes, which makes the output data susceptible to interference or bit errors during transmission.

[0087] In this embodiment of the application, by integrating the test data processing system 10 inside the ALPG100, the ALPG100 can directly output test data streams with link protection codes without the need for external post-processing modules, which simplifies the overall architecture of the automatic test equipment and improves the reliability and real-time performance of data output.

[0088] The test data processing system 10 of this application embodiment can be used as the final stage module of the output pipeline of ALPG100. The raw test data generated by the internal address generator and data generator of ALPG100 is processed by the system and then directly output to the chip under test through the physical layer interface.

[0089] Please continue to refer to this. Figure 6Based on the above embodiments, this application also provides an automated testing device 1000 for memory chips, which includes a test data processing system 10 as described in any at least one of the foregoing embodiments or an algorithm graphics generator 100 as described in any at least one of the foregoing embodiments.

[0090] The ATE1000 in this embodiment may include multiple test channels sharing a central ALPG100. The main control computer of the ATE1000 writes test mode parameters through the configuration memory group interface and saves them as static preset parameters. After the test is started, the ALPG100 can automatically generate a data stream with link protection code.

[0091] Please refer to Figure 7 This application also provides a link protection code generation method, applied to a memory chip automated testing equipment 1000, the link protection code generation method comprising: In step S100, the start signal of burst transmission is detected in real time during the dynamic operation of the algorithm graphics generator, and the dynamic burst information and raw test data of the current burst transmission are extracted. In step S200, the dynamic burst information and the original test data are parsed according to the current storage interface protocol rules, and the link protection code for the current burst transmission is dynamically generated. The current storage interface protocol rules are obtained from the static preset parameters of the current test mode.

[0092] Please refer to Figure 8 In at least one possible implementation, the dynamic generation of the link protection code for the current burst transmission specifically includes: In step S201, according to the bit mapping rules of the current storage interface protocol, the original test data is bit mapped based on the dynamic burst information to form mapped data; In step S202, the mapping data is encoded according to the encoding rules of the current storage interface protocol to generate a redundancy check bit, which serves as the link protection code.

[0093] Please refer to Figure 9 In at least one possible implementation, the dynamic burst information includes at least the starting address and burst length of the current burst transmission, and the bit mapping of the original test data based on the dynamic burst information to form mapped data specifically includes: In step S2011, the data units in the original test data are arranged in address order at least according to their starting address and burst length; In step S2012, the data units arranged in address order are rearranged according to the bit mapping rules of the current storage interface protocol to form the mapping data.

[0094] In at least one possible implementation, the static preset parameter further includes an encoded enable state; The encoding calculation is a CRC or Link ECC encoding calculation; The storage interface protocol includes at least one of the following: DDR4 protocol, DDR5 protocol, GDDR5 protocol, GDDR6 protocol, and LPDDR5 protocol. The dynamic burst information also includes the read / write direction of the current burst transmission. Before the bit mapping or encoding calculation, the corresponding bit mapping rule or encoding rule is selected according to the read / write direction. The static preset parameters also include the data bus width of the chip under test. Before the encoding calculation, the raw data is divided into data units that match the encoder input granularity according to the data bus width. When extracting the raw test data, the number of parallel data bits for each data cycle is determined according to the data bus width.

[0095] Please refer to Figure 10 This application also provides a test data processing method, applied to a memory chip automated testing equipment 1000, the test data processing method comprising: In steps S100-S200, a link protection code is generated according to the link protection code generation method described in any at least one of the foregoing embodiments. In step S300, the generated link protection code of the current burst transmission is embedded into the original test data to form a complete target test data output.

[0096] In at least one possible implementation, embedding the generated link protection code of the current burst transmission into the original test data specifically includes: According to the fixed output position rules of the current storage interface protocol and the dynamic control signals issued by the algorithm graphics generator 100, the generated link protection code is written into the original test data according to the predetermined output arrangement to form the target test data. The target test data is output from at least one pre-configured data path.

[0097] The embodiments of this application are described in detail below with reference to examples.

[0098] The purpose of this example is to provide a test data processing system 10 and method for memory chip interface testing, which is used to automatically generate link protection codes in real time during the dynamic operation of ALPG100. By establishing a unified mode configuration mechanism, burst transmission extraction mechanism, encoding generation mechanism and fixed position output mechanism for encoding results for different memory interface protocol modes, it solves the technical problems in existing memory chip test development such as difficulty in logic reuse, high maintenance costs and lack of transparency in the debugging process.

[0099] The core technical problem this example aims to solve is to provide a solution that can uniformly adapt to multiple storage interface protocols at the hardware level and generate link protection codes in real time based on dynamic burst information at runtime. This addresses the problem in existing technologies where test data generation heavily relies on offline preprocessing and is difficult to support data reuse in dynamic testing scenarios.

[0100] In response to the aforementioned core technical issues, this example further addresses the following technical problems: To address the issue that the differences in computational logic and output format between different DRAM protocols have led to the need for existing technologies to maintain offline scripts independently for each protocol, making it difficult to reuse them under a unified framework; This addresses the issue that changes in mode parameters (such as the width of the data bus of the chip under test, encoding enable status, and signal valid polarity) or runtime burst information (such as read / write direction and burst sequence) can cause existing static data to fail to adapt automatically, requiring frequent reloading.

[0101] This addresses the issues in existing solutions where test intent and protocol state are not traceable and development / debugging logic is invisible in offline generation mode.

[0102] This addresses the issue of data inconsistency or comparison failure caused by different sources of rule configuration or raw data updates in multi-scenario applications.

[0103] This example provides a test data processing system 10 and method for testing memory chip interfaces. Within the same test data processing link, corresponding link protection codes can be dynamically generated based on protocol rules, mode parameters, runtime burst information, and raw data. These codes are then written to the corresponding positions of the target test data according to a predetermined output arrangement and sent to the subsequent data selector as the data source. This allows the same ATE1000 to support test data generation for different protocol products through rule switching.

[0104] The test data processing system 10 in this example can be divided along the processing link into a protocol rule and mode parameter configuration section, a runtime burst context extraction section, and a link protection code generation section (including an encoding operation section and a result arrangement and output section), and can correspondingly include the following digital logic circuit units: Configuration register group 1 is used to receive and configure static preset parameters, including mode parameters such as the current storage interface protocol type, encoding enable status, signal valid polarity, default padding value, and data bus width of the chip under test. It also loads the corresponding bit mapping rules, encoding rules, fixed position output rules, and encoding application conditions according to the current storage interface protocol type.

[0105] The burst context extraction circuit 2 is used to identify dynamic burst information such as the start and end boundaries, burst length, burst order, read and write direction and related control status of the current burst transmission based on the timing information and control information of the test pattern during the dynamic operation of the algorithm pattern generator 100, and to extract the original test data participating in the calculation of the current link protection code.

[0106] The link protection code generation circuit 3 is used to perform bit mapping on the extracted raw test data in units of one burst transmission according to the rules corresponding to the target protocol (i.e., the current storage interface protocol), and then perform CRC or Link ECC encoding calculation according to the encoding rules corresponding to the current storage interface protocol to obtain the link protection code; wherein, the encoding rules under different protocols may differ in terms of encoding polynomial, segment calculation order, and intermediate result combination relationship.

[0107] The output layout circuit 303 is used to output the layout method according to the test pattern control information and the fixed position specified by the protocol, write the link protection code as a component of the target test data into the corresponding position of the original test data to form the target test data, and send the target test data to the subsequent data selector as the data source.

[0108] In terms of link connection, configuration register group 1 serves as a global configuration module, and its outputs act on the link protection code generation circuit 3 and the output layout circuit 303, respectively, providing information such as bit mapping rules, encoding rules, and fixed position output rules corresponding to the storage interface protocol. In the main data path, the burst context extraction circuit 2 is connected in series after the previous stage raw test data generation path. It is responsible for performing protocol-independent dynamic burst information identification and raw test data extraction, and transmitting the extracted raw data and runtime dynamic burst information to the link protection code generation circuit 3 for processing. The link protection code generation circuit 3 performs bit mapping and encoding calculations to obtain the link protection code based on the received raw data and the corresponding protocol configuration, and sends the calculation result to the output layout circuit 303. The output layout circuit 303 is connected to the subsequent data selector, and writes the link protection code into the corresponding position of the target test data according to the current storage interface protocol rules and test pattern control information, and outputs it. Through the above connection relationship, each circuit module sequentially completes rule constraints, burst identification, link protection code generation, and target test data arrangement in the same test data processing link, so that the same ATE1000 can support different protocol products by switching rules while keeping the processing link consistent.

[0109] Please refer to Figure 1 The test data processing system 10 provided in this example mainly includes a configuration register group 1, a burst context extraction circuit 2, and a link protection code generation circuit 3. The system can obtain the current storage interface protocol and test mode parameters from the static preset parameters configured in the configuration register group 1. Combined with the burst context extraction circuit 2 to detect real-time burst transmission, it extracts the original test data and dynamic burst information. After bit mapping, encoding calculation, and output arrangement by the link protection code generation circuit 3, the system finally forms the target test data that can be used by the subsequent data selector. Figure 4 and Figure 5 Two typical examples of the hardware implementation of the link protection code generation circuit 3 are shown respectively. The difference is that the former designs a protocol-specific processing branch 301 for different storage interface protocols. Each protocol-specific processing branch 301 has bit mapping, encoding order and output arrangement rules embedded in it. Protocol switching is achieved by selecting the corresponding protocol-specific processing branch 301. The latter uses a general logic calculation matrix 30 to integrate the protocol differences into the static preset parameters configured by the host computer and send them to the general logic calculation matrix 30 for dynamic hardware execution.

[0110] Example 1: Link protection code generation circuit 3 sets up a dedicated processing branch for each storage interface protocol. Please refer to Figure 4In this embodiment, the hardware internally sets up independent protocol-specific processing branches 301 for each target protocol (such as DDR4, DDR5, GDDR5, GDDR6, LPDDR5, etc.). Each protocol-specific processing branch 301 internally contains a bit mapping circuit, encoding logic circuit, and output layout control circuit corresponding to the storage interface protocol, which is used to directly complete the generation of link protection codes and result layout constraints required by the storage interface protocol within the protocol-specific processing branch 301.

[0111] During execution, configuration register group 1 outputs the currently selected protocol enable signal and corresponding mode parameters; burst context extraction circuit 2 sends the extracted raw test data in parallel to each protocol-specific processing branch 301; each protocol-specific processing branch 301 generates the corresponding link protection code in real time according to the storage interface protocol rules embedded in it; then, according to the current storage interface protocol type, the system selects the target link protection code from each protocol-specific processing branch 301 through multiplexer 302 (MUX), and output arrangement circuit 303 encapsulates it with the raw test data into target test data, and outputs it to the subsequent data selector.

[0112] The advantage of Example 1 lies in its deterministic dedicated hardware circuitry for processing paths, resulting in fewer logic layers, easier timing convergence, and simultaneous operation of all branches. Switching protocols only requires changing the selection signal of the multiplexer 302 (MUX), meeting the real-time requirements of high-speed storage testing. Each protocol-specific processing branch 301 is optimized at the circuit level for that specific protocol, eliminating the overhead of general logic parameter configuration, facilitating easier timing convergence, and allowing for higher operating frequencies. This makes it suitable for hardware platforms with relatively fixed protocol types and extremely high test frequency requirements.

[0113] Example 2: The link protection code generation circuit 3 is implemented using a general logic calculation matrix 30. Please refer to Figure 5 In Example 2, instead of setting up separate circuits for specific protocols, a general logic calculation matrix 30 driven by unified static preset parameters in configuration register group 1 is used. This general logic calculation matrix 30 integrates bit selection logic, XOR operation logic, and output bit arrangement rules, transforming protocol differences into loadable software configuration rules.

[0114] Before execution begins, the host computer configures the storage interface protocol type and test mode parameters, pre-configuring bit mapping, protocol encoding, and output arrangement as static preset parameters. A corresponding configuration mask is generated for each output bit and written to configuration register group 1. These static preset parameters define the mapping relationship between each output bit and the input signal bit, thus specifying which input bits participate in the XOR logic combination of the current output bit.

[0115] During execution, the general logic calculation matrix 30 combines the link protection code generation and output arrangement functions through configuration items; the general logic calculation matrix 30 directly selects the bits to participate in the operation from the original test data and performs an XOR operation based on the mask information in the static preset parameters, and the result of the operation is the predetermined bit output of the target test data.

[0116] Example 2's advantage lies in its high flexibility; it allows for software updates to support new protocols or sub-modes without modifying the hardware circuitry. Its limitations are that different protocols vary significantly, and some calculation rules are related to dynamic, bursty information, leading to potentially very complex software-generated configurations. This necessitates reserving substantial configuration storage space in the hardware, potentially increasing the complexity of internal storage resource management and rule generation algorithms.

[0117] This example also provides corresponding test data processing methods, which can be implemented by following these steps: Pre-configure static preset parameters: Write static preset parameters related to the current test mode, such as protocol type, encoding enable state, signal valid polarity, default fill value, and data bus width of the chip under test, into the corresponding configuration register group, so that the static preset parameters serve as the control basis for the generation and output arrangement of the current link protection code during the test data processing of this application embodiment.

[0118] Extracting the current burst transmission: During the dynamic operation of the ALPG100 test graph, the current burst transmission is identified and extracted from the test graph data stream to obtain dynamic burst information such as the current burst read / write direction, current burst length, current burst sequence, data boundary corresponding to the current burst, and related control status.

[0119] Extract the data to be encoded: the static preset parameters in configuration register group 1, the current burst transmission defined during the dynamic operation of the ALPG100 test pattern, and the original test data extracted from the test pattern data stream to participate in the calculation of the current link protection code.

[0120] Bit mapping: The extracted raw test data is used as input, and bit mapping is performed on the raw test data according to the bit mapping rules corresponding to the current storage interface protocol to form mapped data for encoding calculation.

[0121] Calculate the link protection code: Perform CRC or Link ECC encoding calculation on the mapped data according to the encoding rules corresponding to the current storage interface protocol to generate the link protection code corresponding to the current burst transmission; wherein, the encoding rules under different protocols may differ in terms of encoding polynomial, segment calculation order, and intermediate result combination relationship.

[0122] Organize and output target test data: According to the fixed output position rules of the current storage interface protocol and the test graphic control information, the link protection code obtained by the execution encoding calculation is written into the corresponding position in the original test data according to the output arrangement method specified by the fixed output position rules to form target test data, and the target test data is output to the subsequent data selector for subsequent test processes to select according to the set method.

[0123] The above steps are executed continuously in the same test data processing link to complete the entire processing process from mode parameter configuration, burst transmission identification, raw test data extraction, bit mapping, encoding calculation to target test data output.

[0124] The implementation of this example achieves at least the following effects: This example enhances the reusability of multi-protocol test development and reduces maintenance costs: It converges the scattered bit mapping rules, encoding rules and fixed position output rules under different protocols into a unified processing framework, thereby eliminating the need to maintain independent processes for each protocol, greatly reducing redundant development and the burden of rule maintenance.

[0125] This improves the transparency and traceability of the test data processing process: This example connects mode parameter configuration, burst transmission identification, raw test data extraction, bit mapping, encoding calculation, and output arrangement into a continuous processing link, so that there is a clear correspondence between the generation basis of the link protection code, the burst boundary, and the output result, which facilitates the location of problems and the debugging.

[0126] This reduces the risk of data inconsistency across multiple test scenarios: This example automatically generates link protection codes and arranges the output of target test data based on the same set of protocol configurations, mode parameters, and runtime burst information, avoiding logical deviations caused by manual intervention or multi-source maintenance, and ensuring data consistency across different test scenarios.

[0127] The test platform's protocol scalability and compatibility have been enhanced: While maintaining consistency in the processing links, this example only requires switching the bit mapping rules, encoding rules, and fixed position output rules corresponding to the protocol to support the generation of link protection codes for different products using different deposit interface protocols and the output arrangement of target test data. This greatly improves the flexibility and reusability of subsequent expansion to add new protocols or sub-modes.

[0128] The utilization of the ATE1000's internal data storage resources has been optimized: Compared with existing technologies that typically require preloading a large amount of static test data containing link protection codes, this example dynamically generates link protection codes and organizes target test data based on protocol rules and runtime burst information, thereby significantly reducing static data usage and achieving effective support for longer-cycle test sequences.

[0129] The logic for calling the subsequent data selector has been simplified: This example writes the link protection code into the target test data according to the predetermined output arrangement and sends it to the subsequent data selector as the data source. This enables the subsequent selection logic to remain relatively stable under different test scenarios and improves the reusability of the data interface.

[0130] This application also provides a computer program product, which includes computer program code that, when run on a computer, causes the computer to perform the steps of the method in any of the possible implementations of the foregoing embodiments.

[0131] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0132] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A test data processing system, applied to an algorithmic graphics generator in automated testing equipment for memory chips, characterized in that, The test data processing system includes: A configuration register group is used to store static preset parameters for the current test mode. The static preset parameters include at least the storage interface protocol rules used by the current test mode. A burst context extraction circuit, connected to the configuration register group, is used to detect the start signal of burst transmission in real time during the dynamic operation of the algorithm graphics generator, and extract the dynamic burst information and raw test data of the current burst transmission. The link protection code generation circuit, connected to the burst context extraction circuit and the configuration register group, is used to parse the dynamic burst information and original test data according to the storage interface protocol rules obtained from the configuration register group, and dynamically generate the link protection code for the current burst transmission.

2. The test data processing system according to claim 1, characterized in that, The link protection code generation circuit specifically includes: The bit mapping unit is used to perform bit mapping on the original test data according to the bit mapping rules of the current storage interface protocol and the dynamic burst information to form mapped data; The encoding calculation unit, connected to the bit mapping unit, is used to perform encoding calculations on the mapped data according to the encoding rules of the current storage interface protocol, and generate redundant check bits as the link protection code.

3. The test data processing system according to claim 2, characterized in that, The dynamic burst information includes at least the starting address and burst length of the current burst transmission, and the bit mapping unit includes: The sequential arrangement of sub-units is used to identify the start and end boundaries of the current burst transmission, and to arrange the data units in the original test data in address order, at least according to the start address and burst length. The rearrangement subunit, connected to the sequential arrangement subunit, is used to rearrange the data units arranged in address order according to the bit mapping rule, as the mapped data.

4. The test data processing system according to claim 3, characterized in that, The encoding calculation includes cyclic redundancy check or link error correction code encoding calculation; The dynamic burst information also includes the read / write direction of the current burst transmission, and the bit mapping unit or the encoding calculation unit is further used to select the corresponding bit mapping rule or encoding rule according to the read / write direction; The static preset parameters also include the data bus width of the chip under test; The burst context extraction circuit is also used to determine the number of parallel data bits for each data cycle based on the data bus width, so as to extract the original test data of the corresponding bit width. The bit mapping unit is also used to divide the raw test data into data units that match the encoder input granularity according to the data bus width.

5. The test data processing system according to any one of claims 1-4, characterized in that, The static preset parameters also include the encoding enable state of the current test mode, and the link protection code generation circuit includes: Multiple protocol-specific processing branches are independently set up for each storage interface protocol. Each protocol-specific processing branch is used to generate the link protection code according to its corresponding storage interface protocol. A multiplexer is used to select the link protection code generated by the corresponding protocol-specific processing branch from each of the protocol-specific processing branches according to the currently configured storage interface protocol type.

6. The test data processing system according to claim 5, characterized in that, The system also includes: An output routing circuit, connected to the multiplexer, is used to embed the generated link protection code into the original test data according to the fixed output position specified by the storage interface protocol, thereby forming the target test data output. Each protocol-specific processing branch contains a bit mapping circuit and encoding logic circuit corresponding to the storage interface protocol.

7. The test data processing system according to any one of claims 1-4, characterized in that, The link protection code generation circuit is configured as a general logic calculation matrix.

8. The test data processing system according to claim 7, characterized in that, The static preset parameters also include mask information, and the general logical calculation matrix specifically includes: A bit-select array is connected to the configuration register group. Its input receives raw test data and is used to select the bits to participate in the operation from the raw test data according to the bit mapping mask in the mask information, and output the selected data. An XOR operation array, connected to the bit selection array, is used to perform an XOR operation on the selected data to generate a link protection code and embed it into the output data.

9. The test data processing system according to claim 7, characterized in that, The static preset parameters also include an encoding enable state, and the link protection code generation circuit determines whether to perform the generation operation based on the encoding enable state.

10. An algorithmic graphics generator, characterized in that, It includes a test data processing system as described in any one of claims 1-9.

11. An automated testing device for memory chips, characterized in that, It includes a test data processing system as described in any one of claims 1-9 or an algorithm graphics generator as described in claim 10.

12. A link protection code generation method, applied to automated testing equipment for memory chips, characterized in that, The link protection code generation method includes: During the dynamic operation of the algorithm graphics generator, the start signal of burst transmission is detected in real time, and the dynamic burst information and raw test data of the current burst transmission are extracted. Based on the storage interface protocol rules obtained from the static preset parameters of the current test mode, the dynamic burst information and the original test data are parsed to dynamically generate the link protection code for the current burst transmission.

13. The link protection code generation method according to claim 12, characterized in that, The dynamic generation of the link protection code for the current burst transmission specifically includes: According to the bit mapping rules of the current storage interface protocol, the original test data is bit-mapped based on the dynamic burst information to form mapped data; The mapped data is encoded according to the encoding rules of the current storage interface protocol to generate a redundancy check bit, which serves as the link protection code.

14. The link protection code generation method according to claim 13, characterized in that, The dynamic burst information includes at least the starting address and burst length of the current burst transmission. The step of bit-mapping the original test data based on the dynamic burst information to form mapped data specifically includes: The data units in the original test data are arranged in address order at least according to their starting address and burst length; The data units arranged in address order are rearranged according to the bit mapping rules of the current storage interface protocol to form the mapping data.

15. The link protection code generation method according to any one of claims 13-14, characterized in that, The static preset parameters also include an encoded enable state; The encoding calculation is a cyclic redundancy check or link error correction code encoding calculation; The dynamic burst information also includes the read / write direction of the current burst transmission. Before the bit mapping or encoding calculation, the corresponding bit mapping rule or encoding rule is selected according to the read / write direction. The static preset parameters also include the data bus width of the chip under test; Before the encoding calculation, the raw data is further divided into data units that match the encoder input granularity according to the data bus width; When extracting the raw test data, the number of parallel data bits for each data cycle is determined based on the data bus width.

16. A test data processing method, applied to automated testing equipment for memory chips, characterized in that, The test data processing method includes: The link protection code is generated according to any one of claims 12-15; The generated link protection code for the current burst transmission is embedded into the original test data to form a complete target test data output.

17. The test data processing method according to claim 16, characterized in that, The step of embedding the generated link protection code of the current burst transmission into the original test data specifically includes: According to the fixed output position rules of the current storage interface protocol and the dynamic control signals issued by the algorithm graphics generator, the generated link protection code is written into the original test data according to the predetermined output arrangement to form the target test data. The target test data is output from at least one pre-configured data path.

18. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by the processor, they implement the link protection code generation method as described in any one of claims 12-15 or the test data processing method as described in any one of claims 16-17.

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