Ecc real-time decoding circuit supporting 2-bit error correction and memory chip

Abstract

The application discloses an ECC low-delay real-time decoding circuit supporting 2-bit error correction, comprising an ECC encoder, a nonvolatile memory and an ECC decoder, the ECC decoder comprising: a syndrome generator, an extension decoding module, an error locating module, a double error detection module and a data error correction module, the syndrome generator being used for calculating and outputting first and second syndrome state signals from inputted data to be decoded, the double error detection module being used for receiving and comparing the first and second syndrome state signals to identify error positions, the error locating module being connected with the double error detection module and used for determining error types according to the number of identified error positions, and the error correction module being used for outputting an error state signal when the error type is determined as 3-bit or more than 3-bit errors. The syndrome generator and the extension decoding module are processed in parallel to quickly locate errors and reduce decoding delay, the double error detection module can distinguish error types to avoid false correction, the ECC low-delay real-time decoding circuit is integrated in a memory chip, the chip area increases little, and the error correction capability is improved to 2-bit, and the error detection is improved to 3-bit or more than 3-bit.

Description

Technical Field

[0001] This invention relates to the field of memory chip technology, and specifically to an ECC real-time decoding circuit and memory chip that supports 2-bit error correction. Background Technology

[0002] In memory chips, data is susceptible to bit errors due to interference and device aging, which affect its reliability, data retention, and durability. ECC technology is the mainstream solution.

[0003] Existing ECC technologies include SECDED, BCH, and LDPC codes. Among them, BCH and LDPC codes have strong error correction capabilities, but they cannot achieve real-time decoding, making them unsuitable for products with high real-time requirements such as Spinor flash memory and DRAM. The SECDED scheme is based on Hamming codes, which are simple to encode and fast to decode, and are commonly used error correction schemes for such storage devices. It can achieve 1-bit error correction and 2-bit detection, but it has significant limitations. It cannot handle 3-bit or higher multi-bit errors, has low storage density, and low reliability in complex operating environments. Summary of the Invention

[0004] Based on this, it is necessary to address the issues that existing SECDED Hamming code decoding circuits can only achieve 1-bit error correction and 2-bit error detection, and that BCH and LDPC codes cannot achieve real-time error correction, thus failing to meet the high reliability requirements of storage devices and being unsuitable for storage devices such as Spinor flash memory and DRAM. Therefore, a real-time ECC decoding circuit and storage chip supporting 2-bit error correction should be proposed. This circuit uses a parallel processing architecture of adjoint comparison and multiple extended decoding to identify 3-bit and above uncorrectable errors, thereby improving data reliability.

[0005] A low-latency real-time ECC decoding circuit supporting 2-bit error correction includes an ECC encoder, a non-volatile memory, and an ECC decoder. The ECC encoder calculates an ECC check bit based on the original data, combines the original data and the ECC check bit to form encoded data, and writes this encoded data into the non-volatile memory. The non-volatile memory outputs the data to be decoded to the ECC decoder. The ECC decoder includes: The synergistic generator calculates and outputs the first synergistic state signal from the input data to be decoded; The extended decoding module inverts each bit of the data to be decoded and processes them in parallel. It uses the same ECC decoding algorithm as the syndrome generator to calculate and output the second syndrome state signal. The error location module is connected to the accompaniment generator and the extended decoding module, and receives and compares the first and second types of accompaniment state signals to identify the error location. A dual error detection module is connected to the error location module. It determines the error type based on the number of identified error locations. When the number of error locations exceeds 2 bits, it is determined to be a 3-bit or higher error and an error indication signal is output. The data error correction module is connected to the dual error detection module and outputs an error status signal when a 3-bit or higher error is detected.

[0006] In some embodiments, the ECC encoder calculates 8 ECC check bits based on 64-bit raw data, combines them to form 72-bit encoded data, and writes it into NOR flash memory; the NOR flash memory outputs the 72-bit data to be decoded to the ECC decoder; the ECC decoder includes: The synergistic generator calculates and outputs the first synergistic state signal from the input 72-bit data to be decoded. 72 extended decoding modules, each corresponding to one bit of the 72 bits of data to be decoded, invert the corresponding bits and process them in parallel, and use the same ECC decoding algorithm as the syndrome generator to calculate and output the second syndrome state signal. The error location module is connected to the accompaniment generator and 72 extended decoding modules, and receives and compares the first and second types of accompaniment state signals to identify the error location. A dual error detection module is connected to the error location module. It determines the error type based on the number of identified error locations. When the number of error locations exceeds 2 bits, it is determined to be a 3-bit or higher error and an error indication signal is output. The data error correction module is connected to the dual error detection module. When a 2-bit error is detected, the data is corrected and the original 64-bit data is restored according to the error location identified by the error location module. When a 3-bit or higher error is detected, an error status signal is output.

[0007] In some embodiments, the 72 extended decoding modules invert the corresponding bits of the 72-bit data to be decoded while keeping the remaining bits unchanged, and then output the generated second synergistic state signal to the dual error detection module.

[0008] In some embodiments, the 72 extended decoding modules operate in a parallel synchronous mode, and the processing clock of each extended decoding module is consistent with the processing clock of the synodal generator.

[0009] In some embodiments, the determination logic of the error location module is as follows: based on the comparison results of the first and second synergistic state signals, identify the 1-bit / 2-bit error location; when the first synergistic state signal output by the synergistic generator is a 1-bit error and can be corrected, it is determined to be a 1-bit error; when the first synergistic state signal output by the synergistic generator is a 2-bit error detection, and there are at least two extended decoding modules outputting a second synergistic state signal that is a 1-bit error and can be corrected or has no error, it is determined to be a 2-bit error and an error correction instruction is sent to the data error correction module.

[0010] In some embodiments, the determination logic of the error location module is as follows: When the first symptom corresponds to a 1-bit error, it is determined to be a 1-bit error; If the first symptom corresponds to a 2-bit error, and the second symptom of at least two extended decoding modules corresponds to no error or a 1-bit error, it is determined to be a 2-bit error.

[0011] In some embodiments, the data error correction module further includes a data verification feedback unit, which, after completing 2-bit error correction, feeds back the corrected 72-bit data to the synergistic generator for secondary verification. After confirming that the error correction result is correct, it outputs the restored original 64-bit data. If the secondary verification finds that there is still an error, it triggers the dual error detection module to output a 3-bit or higher error indication signal.

[0012] In some embodiments, the ECC encoder employs the DEDSEC encoding mechanism.

[0013] A memory chip, characterized in that it includes an ECC low-latency real-time decoding circuit supporting 2-bit error correction as described in any one of claims 1 to 8, the memory chip comprising a random-access memory device, the random-access memory device including at least one of Spinor flash memory and DRAM.

[0014] This invention, through a parallel processing architecture of adjoint comparison and multi-extension decoding, can accurately locate and correct 2-bit errors and identify 3-bit and above uncorrectable errors, thereby improving data reliability. The parallel synchronous working mode significantly reduces decoding latency, enabling real-time error correction. With high circuit reusability and clear logic, the secondary verification mechanism further ensures the effectiveness of error correction. It can be applied to the application requirements of high-reliability, high-speed read and write memory chips. The chip area is increased by 2%, and the error detection capability, data durability, and data retention time can all be improved several times. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] in: Figure 1 This is a schematic diagram of the process of writing ECC encoding into NOR flash memory for an ECC real-time decoding circuit that supports 2-bit error correction, as described in an embodiment of the present invention. Figure 2 This is a schematic diagram of the data reading and decoding process of an ECC real-time decoding circuit that supports 2-bit error correction, as described in an embodiment of the present invention. Figure 3 This is the core module architecture of the decoder of an ECC real-time decoding circuit that supports 2-bit error correction, as described in the embodiments of the present invention.

[0017] Figure 4 This is a block diagram of a 64-bit data multiplexed ECC decoder circuit that supports 2-bit error correction, as described in an embodiment of the present invention. Detailed Implementation

[0018] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0019] To address the issue that existing SECDED Hamming code decoding circuits can only achieve 1-bit error correction and 2-bit error detection, while BCH and LDPC codes cannot achieve real-time error correction and thus fail to meet the high reliability requirements of SPINOR flash memory, DRAM, and other storage devices, the following will combine the attached... Figure 1 To be continued Figure 4 The present invention provides a detailed description of an ECC real-time decoding circuit and memory chip that supports 2-bit error correction.

[0020] Please see Figure 1 , Figure 2 , Figure 3 and Figure 4 , Figure 1 This is a schematic diagram of the process of writing ECC encoding into NOR flash memory for an ECC real-time decoding circuit that supports 2-bit error correction, as described in an embodiment of the present invention. Figure 2 This is a schematic diagram of the data reading and decoding process of an ECC real-time decoding circuit that supports 2-bit error correction, as described in an embodiment of the present invention. Figure 3 This is the core module architecture of the decoder of an ECC real-time decoding circuit that supports 2-bit error correction, as described in the embodiments of the present invention. Figure 4 This is a block diagram of a 64-bit data multiplexed ECC decoder circuit that supports 2-bit error correction, as described in an embodiment of the present invention.

[0021] The encrypted startup architecture of the automotive ECU of the present invention will be further described in detail below with reference to specific embodiments.

[0022] A low-latency real-time ECC decoding circuit supporting 2-bit error correction includes an ECC encoder, a non-volatile memory, and an ECC decoder. The ECC encoder calculates an ECC check bit based on the original data, combines the original data and the ECC check bit to form encoded data, and writes this encoded data into the non-volatile memory. The non-volatile memory outputs the data to be decoded to the ECC decoder. The ECC decoder includes: The synergistic generator calculates and outputs the first synergistic state signal from the input data to be decoded; The extended decoding module inverts each bit of the data to be decoded and processes them in parallel. It uses the same ECC decoding algorithm as the syndrome generator to calculate and output the second syndrome state signal. The error location module is connected to the accompaniment generator and the extended decoding module, and receives and compares the first and second types of accompaniment state signals to identify the error location. A dual error detection module is connected to the error location module. It determines the error type based on the number of identified error locations. When the number of error locations exceeds 2 bits, it is determined to be a 3-bit or higher error and an error indication signal is output. The data error correction module is connected to the dual error detection module and outputs an error status signal when a 3-bit or higher error is detected.

[0023] Specifically, the ECC encoder is implemented using hardware logic circuits. The input terminal receives external raw data of arbitrary width from 8 to 128 bits. The internally integrated encoding algorithm unit calculates the corresponding number of ECC check bits based on improved Hamming code logic to ensure that the encoding speed meets real-time requirements. Its output terminal is connected to the non-volatile memory write terminal, which combines the raw data and check bits in the order of "raw data first, check bits last" to form encoded data, and synchronously writes it to the non-volatile memory for storage, which facilitates subsequent rapid decomposition and decoding.

[0024] The non-volatile memory uses NOR flash memory. The read end is connected to the input end of the ECC decoder. When reading data, the stored encoded data is output in real time as the data to be decoded. There is no additional buffering delay, ensuring the basic requirements of real-time decoding.

[0025] The ECC decoder is the core module, which includes a syntactic generator, an extended decoding module, an error location module, a dual error detection module, and a data error correction module. Each submodule is implemented using hardware parallel logic to avoid software decoding delays, as detailed below: Syndrome generator: Directly connected to the read end of non-volatile memory, after receiving the data to be decoded, it uses the decoding algorithm corresponding to the encoder to calculate the first syndrome state signal with the number of check bits within one clock cycle, which is used to initially determine the existence and type of error.

[0026] Extended decoding modules: The number of modules corresponds one-to-one with the number of bits in the data to be decoded. Each module's input terminal is connected to the data to be decoded. During operation, only its corresponding bit is inverted while the remaining bits remain unchanged. Then, the second syndrome state signal is output in parallel through the same algorithm as the syndrome generator, and the synchronous operation has no serial delay.

[0027] Error location module: It adopts a logic comparison circuit, connects the synergistic generator and all extended decoding modules, receives two types of synergistic signals in real time, and accurately locates the error position within one clock cycle by comparing the differences through preset logic.

[0028] Dual error detection module: Connects to the error location module, with a built-in counting unit to count the number of error locations and determine the error type: 1 bit is a 1-bit error, 2 bits is a 2-bit error, and more than 2 bits is a 3-bit or higher error and an error indication signal is output.

[0029] Data error correction module: Connects to the dual error detection module, receives the judgment result, corrects 1-bit and 2-bit errors by inverting the position and outputting the original data; outputs error status signals for 3-bit and above errors to avoid erroneous data from affecting system reliability.

[0030] Beneficial effects: This embodiment achieves rapid correction of 1-bit and 2-bit errors by having the encoder and extended decoding module work in parallel, which solves the limitation of the existing SECDED scheme that can only correct 1-bit errors. At the same time, it avoids the problem that BCH code and LDPC code cannot be decoded in real time. The dual error detection module identifies 3-bit and above errors, which improves the reliability of data storage. It can handle 3-bit and above multi-bit errors, and has high storage density and high reliability in complex working environments.

[0031] In one embodiment, the ECC encoder calculates 8 ECC check bits based on 64-bit raw data, combines them to form 72-bit encoded data, and writes it into NOR flash memory; the NOR flash memory outputs the 72-bit data to be decoded to the ECC decoder; the ECC decoder includes: The synergistic generator calculates and outputs the first synergistic state signal from the input 72-bit data to be decoded. 72 extended decoding modules, each corresponding to one bit of the 72 bits of data to be decoded, invert the corresponding bits and process them in parallel, and use the same ECC decoding algorithm as the syndrome generator to calculate and output the second syndrome state signal. The error location module is connected to the accompaniment generator and 72 extended decoding modules, and receives and compares the first and second types of accompaniment state signals to identify the error location. A dual error detection module is connected to the error location module. It determines the error type based on the number of identified error locations. When the number of error locations exceeds 2 bits, it is determined to be a 3-bit or higher error and an error indication signal is output. The data error correction module is connected to the dual error detection module. When a 2-bit error is detected, the data is corrected and the original 64-bit data is restored according to the error location identified by the error location module. When a 3-bit or higher error is detected, an error status signal is output.

[0032] Specifically, the ECC encoder uses a hardware integrated circuit specifically designed for encoding 64-bit raw data. It calculates 8 ECC check bits based on an improved Hamming code algorithm, completing the encoding in one clock cycle. The output is connected to the NOR flash memory (SPINOR flash memory chip) write end, combining the 64-bit raw data with the 8 check bits into 72-bit encoded data (arranged in the order of "64-bit raw data + 8-bit check bits"), and synchronously writes it to the flash memory storage, suitable for real-time reading without latency requirements.

[0033] The NOR flash memory read end is directly connected to the ECC decoder input end, and outputs 72-bit data to be decoded in real time when reading data, without the need for a cache module, ensuring real-time data input.

[0034] The ECC decoder is designed for 72-bit data to be decoded, and its sub-modules are as follows: Syndrome generator: It adopts hardware logic gate circuits, takes in 72-bit data to be decoded, and calculates and outputs an 8-bit first syndrome status signal within 1 clock cycle for preliminary judgment of error conditions.

[0035] Extended decoding modules: There are 72 modules in total, corresponding to each bit of the 72-bit data to be decoded. Each module receives the complete 72-bit data, only inverts the corresponding bit, and then calculates and outputs an 8-bit second synergistic state signal in parallel. The process is completed synchronously within one clock cycle with no serial delay.

[0036] Error location module: It adopts a high-speed logic comparison chip, receives 8-bit first accompaniment signal and 72 groups of 8-bit second accompaniment signals, compares the differences within 1 clock cycle, and accurately locates the error position.

[0037] Dual error detection module: Built-in counter and logic judgment unit, counts the number of error locations and determines the type. For 3-bit and above errors, output a high-level error indication signal to notify the system to handle the abnormality.

[0038] Data error correction module: It adopts hardware error correction logic to correct 1-bit and 2-bit errors, split the data, and extract the 64-bit original data for output; for 3-bit and above errors, it outputs a low-level error status signal to prohibit the output of erroneous data.

[0039] Beneficial effects: This embodiment specifies the exact bit width parameters, improves circuit feasibility, and is applicable to common storage devices such as Spinor flash memory; 72 extended decoding modules work in parallel, overcoming the limitation of the SECDED scheme in handling 2-bit errors; it can handle 3-bit and above multi-bit errors, has high storage density, high reliability in complex working environments, is fully hardware logic implemented, and requires only 3 clock cycles for decoding, achieving low-latency real-time decoding, and is suitable for high real-time storage products.

[0040] In one embodiment, the 72 extended decoding modules invert the corresponding bits of the 72-bit data to be decoded while keeping the remaining bits unchanged, and then output the generated second synergistic state signal to the dual error detection module.

[0041] Specifically, the 72 extended decoding modules correspond one-to-one with each bit of the 72-bit data to be decoded, numbered 1 to 72, corresponding to bits 1 to 72 of the data to be decoded. Each module receives the complete 72-bit data at its input and integrates an inversion unit and a decoding unit: the inversion unit only inverts the corresponding bit, leaving the other bits unchanged; the decoding unit uses the same algorithm as the syndrome generator to calculate and output an 8-bit second syndrome state signal.

[0042] Example: The extended decoding module 5 corresponds to the 5th bit of the data to be decoded. The inverting unit inverts this bit (0 becomes 1, 1 becomes 0), while the other bits remain unchanged. The decoding unit decodes the processed data to generate a second symptom signal, which is synchronously output to the error location module and the dual error detection module.

[0043] The inversion and decoding operations of all extended decoding modules are performed synchronously and completed within one clock cycle, ensuring real-time signal output and avoiding the impact of individual module delays on overall efficiency.

[0044] Beneficial effects: It clarifies the working mode of the extended decoding module, simplifies the processing logic, and reduces hardware complexity and latency; the second accompanying signal is synchronously output to the two modules to achieve error location and type determination coordination, improve decoding efficiency and accuracy, and ensure the reliability of 2-bit error correction.

[0045] In one embodiment, the 72 extended decoding modules operate in a parallel synchronous mode, and the processing clock of each extended decoding module is consistent with the processing clock of the synodal generator.

[0046] Specifically, the 72 extended decoding modules operate in parallel synchronous mode and are driven by the same clock signal. This clock is consistent with the processing clock of the synergistic generator and is set to 100MHz to ensure that the working rhythm of each module is synchronized and to avoid signal misalignment and delay.

[0047] Operating Process: The rising edge of the clock triggers the syndrome generator to calculate the first syndrome signal, simultaneously triggering 72 extended decoding modules to synchronously perform inversion and decoding operations. Within the same clock cycle, both complete the calculation and synchronously output signals to the error location module. To ensure stability, all extended decoding modules use the same hardware structure and parameters, and the output terminals use the same transmission lines to ensure that the signals arrive at the error location module synchronously without any transmission delay differences.

[0048] Beneficial effects: Parallel synchronous mode shortens the total decoding time and enables low-latency real-time decoding; clock synchronization avoids signal misalignment, improves circuit stability, simplifies timing design, reduces hardware complexity, and is suitable for high real-time and high-stability storage products.

[0049] In one embodiment, the determination logic of the error location module is as follows: based on the comparison results of the first and second synergistic state signals, identify the 1-bit / 2-bit error location; when the first synergistic state signal output by the synergistic generator is a 1-bit error and can be corrected, it is determined to be a 1-bit error; when the first synergistic state signal output by the synergistic generator is a 2-bit error detection, and there are at least two extended decoding modules outputting a second synergistic state signal that is a 1-bit error and can be corrected or has no error, it is determined to be a 2-bit error and an error correction command is sent to the data error correction module.

[0050] Specifically, the error location module has built-in preset comparison logic and judgment rules, and receives 8-bit first accompanying signals and 72 groups of 8-bit second accompanying signals in real time. It determines the error location and type through the following logic: If the first accompanying signal satisfies the "1-bit error can be corrected" condition (corresponding to a unique error bit), it is determined to be a 1-bit error, the error location is accurately located and output to the dual error detection module and the data error correction module.

[0051] If the first associated signal satisfies the "2-bit error detection" condition (cannot correspond to a unique error bit), then all second associated signals are compared; if at least two module output signals satisfy "1-bit error can be corrected" or "no error", then it is determined to be a 2-bit error, and the error location is determined and output according to the corresponding module.

[0052] If the first symmetric signal is "no error", then the data to be decoded is determined to be error-free, and an error-free signal is output. The data error correction module directly extracts the original data and outputs it.

[0053] For example, when the first accompanying signal indicates a 2-bit error, if the output signals of the extended decoding modules 3 and 15 satisfy the condition that "a 1-bit error can be corrected", then the 3rd and 15th bits of the data to be decoded are determined to be error bits and output.

[0054] Beneficial effects: The judgment logic is simple and efficient, completing the judgment in one clock cycle and ensuring low latency; through multi-module signal verification, the accuracy of 2-bit error judgment is improved, misjudgment is avoided, and the problem that existing solutions cannot accurately locate 2-bit errors is solved.

[0055] In one embodiment, the determination logic of the error location module is as follows: When the first symptom corresponds to a 1-bit error, it is determined to be a 1-bit error; If the first symptom corresponds to a 2-bit error, and the second symptom of at least two extended decoding modules corresponds to no error or a 1-bit error, it is determined to be a 2-bit error.

[0056] Specifically, the error localization module employs simplified judgment logic, quickly determining the error based on the core features of two types of accompanying signals, as follows: After receiving the first accompanying signal, if it meets the preset 1-bit error characteristics (which can locate the unique error bit), it is determined to be a 1-bit error, the position is located and output.

[0057] If the first accompanying signal meets the preset 2-bit error characteristics (unable to locate the unique error bit), then the second accompanying signal is detected; if at least two module output signals correspond to "no error" or "1-bit error", then it is determined to be a 2-bit error, the position is located and output.

[0058] If the first associated signal is "no error", then it is determined that there is no error; if the first associated signal indicates a 2-bit error, but less than 2 module output signals meet the requirements, then no determination is made for the time being, and the second verification feedback from the data error correction module is awaited.

[0059] Beneficial effects: While ensuring positioning accuracy, it reduces the amount of hardware computation, completes the judgment in one clock cycle, reduces the amount of hardware computation and design cost, improves decoding efficiency, avoids misjudgment through multi-module verification, ensures error correction reliability, and meets the high reliability requirements of memory chips.

[0060] In one embodiment, the data error correction module further includes a data verification feedback unit, which, after completing 2-bit error correction, feeds back the corrected 72-bit data to the synergistic generator for secondary verification. After confirming that the error correction result is correct, it outputs the restored original 64-bit data. If the secondary verification finds that there is still an error, it triggers the dual error detection module to output a 3-bit or higher error indication signal.

[0061] Specifically, the data error correction module includes an error correction unit and a data verification feedback unit: the error correction unit connects the dual error detection module and the error location module, and is responsible for correcting erroneous data; the data verification feedback unit connects the error correction unit and the accompanying generator, and is responsible for secondary verification of the data after error correction to ensure that the results are correct. The workflow is as follows: When the double error detection module determines that a 2-bit error has occurred, the error location module outputs the error location, and the error correction unit inverts the corresponding bit to correct it, thus obtaining the corrected 72-bit data. The error correction unit outputs the corrected data to the verification feedback unit, which then feeds it back to the syndrome generator to trigger a secondary verification and calculate the third syndrome signal. The verification feedback unit compares the third accompanying signal with the "no error" signal: if they match, it controls the error correction unit to split the data and extract the 64-bit original data for output; if they do not match, it triggers the dual error detection module to output a 3-bit or higher error indication signal. When a 1-bit error is detected, a secondary verification can be selectively performed after error correction; otherwise, the original data can be output directly.

[0062] Beneficial effects: Secondary verification requires only one clock cycle, does not increase the overall decoding latency, avoids incomplete error correction, and improves the accuracy and reliability of error correction; it does not affect the low latency characteristics, can detect hidden 3-bit and above errors in a timely manner, ensures data integrity, and is suitable for high storage density and complex working environment requirements.

[0063] In one embodiment, the ECC encoder employs the DEDSEC encoding mechanism.

[0064] Specifically, the ECC encoder adopts an improved DEDSEC (Double Error Detection and Single Error Correction) encoding mechanism, which optimizes the traditional DEDSEC encoding matrix, increases the redundancy of the parity bits, retains the advantages of simple encoding and fast decoding, and supports 2-bit error location and correction, while being compatible with traditional DEDSEC decoding logic.

[0065] The encoder encodes 64-bit raw data, calculates 8 ECC check bits, and completes the encoding in one clock cycle, making it easy to implement in hardware. The encoded 72-bit data can be used in the decoder of this embodiment and is also compatible with traditional DEDSEC decoding circuits, thus improving compatibility.

[0066] Specific encoding: The 64-bit original data is divided into 8 8-bit data blocks, each data block corresponds to 1 parity bit. The mapping relationship is determined by improving the encoding matrix to ensure that the parity bit covers the requirements of 2-bit error detection and location, while retaining the advantage of fast correction of 1-bit errors.

[0067] Beneficial effects: It overcomes the limitation of traditional DEDSEC, which can only detect 2-bit errors and cannot correct them, thus meeting the requirements for low latency; it is compatible with traditional decoding circuits, reducing product upgrade costs and is suitable for common storage devices.

[0068] A memory chip includes an ECC low-latency real-time decoding circuit supporting 2-bit error correction as described in any one of claims 1 to 8, the memory chip comprising a random-access memory device, the random-access memory device including at least one of Spinor flash memory and DRAM.

[0069] Specifically, the storage chip adopts a SOC integrated architecture, integrating the ECC encoder, decoder and storage device on the same chip, reducing external connections, reducing transmission latency, and improving integration and stability; the storage device uses SPINOR flash memory or DRAM, connected in parallel, and the storage medium can be selected as needed.

[0070] The ECC encoder input is connected to the chip's external data interface, receiving raw data, encoding it, and then outputting it to flash memory or DRAM storage. The flash memory and DRAM read ends are connected to the ECC decoder, which outputs encoded data in real time during reading. The decoder completes error detection, location, and correction according to the corresponding process, and outputs the raw data through the external interface.

[0071] The chip also includes a control module that connects to the core modules, controls the operating timing, receives decoder error signals, and triggers an alarm mechanism when a 3-bit or higher error is detected, notifying the external system for processing. This memory chip can be applied in fields such as the Internet of Things, industrial control, and consumer electronics, and is suitable for high real-time and high reliability scenarios.

[0072] Beneficial effects: Solves the bit error problem of existing memory chips, quickly corrects 1-bit and 2-bit errors, accurately detects 3-bit and above errors, and improves data reliability; suitable for different storage needs, with low decoding latency, high integration, reduced size and cost, and enhanced market competitiveness.

[0073] This invention optimizes the integrated design of ECC circuits and memory chips, solving the problems of high decoding latency, inability to correct 2-bit errors, and inaccurate positioning in existing technologies. It adopts hardware parallel logic and achieves fast 1-bit and 2-bit error correction and detection through the collaboration of a synergistic generator and an extended decoding module. It breaks through the limitations of traditional solutions, avoids the problem of insufficient real-time performance of BCH and LDPC codes, and is suitable for high real-time storage scenarios.

[0074] This invention employs a parallel architecture of adjoint comparison and multi-extension decoding. By extending the decoding module, it simplifies the hardware structure and improves circuit stability. Combined with dedicated error location logic, it can accurately achieve 2-bit error correction and identification of 3-bit and above uncorrectable errors. Simultaneously, it uses an improved DEDSEC scheme to reduce upgrade costs, adds a secondary verification mechanism to enhance error correction reliability, effectively reduces decoding latency, achieves real-time error correction, and boasts high circuit reusability and simple logic, requiring no modification to the existing application architecture. Using 55nm SPI NOR Flash technology, the chip area increases by only about 2%, while error correction capability is improved from 1-bit to 2-bit, and error detection capability is improved to 3-bit and above. Error detection performance, data durability, and retention time are all improved several times, meeting the high-real-time and high-reliability application requirements of high-speed memory chips and various fields.

[0075] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Under the concept of the present invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the present invention as described above. For the sake of brevity, they are not provided in detail. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-latency real-time ECC decoding circuit supporting 2-bit error correction, comprising an ECC encoder, a non-volatile memory, and an ECC decoder, characterized in that, The ECC encoder calculates the ECC check bit based on the original data, combines the original data and the ECC check bit to form encoded data, and writes it into the non-volatile memory. The non-volatile memory outputs the data to be decoded to the ECC decoder; the ECC decoder includes: The synergistic generator calculates and outputs the first synergistic state signal from the input data to be decoded; The extended decoding module inverts each bit of the data to be decoded and processes them in parallel. It uses the same ECC decoding algorithm as the syndrome generator to calculate and output the second syndrome state signal. The error location module is connected to the accompaniment generator and the extended decoding module, and receives and compares the first and second types of accompaniment state signals to identify the error location. A dual error detection module is connected to the error location module. It determines the error type based on the number of identified error locations. When the number of error locations exceeds 2 bits, it is determined to be a 3-bit or higher error and an error indication signal is output. The data error correction module is connected to the dual error detection module and outputs an error status signal when a 3-bit or higher error is detected.

2. The ECC low-latency real-time decoding circuit supporting 2-bit error correction according to claim 1, characterized in that, The ECC encoder calculates 8 ECC check bits based on the 64-bit raw data, combines them to form 72-bit encoded data, and writes it into the NOR flash memory; the NOR flash memory outputs the 72-bit data to be decoded to the ECC decoder; the ECC decoder includes: The synergistic generator calculates and outputs the first synergistic state signal from the input 72-bit data to be decoded. 72 extended decoding modules, each corresponding to one bit of the 72 bits of data to be decoded, invert the corresponding bits and process them in parallel, and use the same ECC decoding algorithm as the syndrome generator to calculate and output the second syndrome state signal. The error location module is connected to the accompaniment generator and 72 extended decoding modules, and receives and compares the first and second types of accompaniment state signals to identify the error location. A dual error detection module is connected to the error location module. It determines the error type based on the number of identified error locations. When the number of error locations exceeds 2 bits, it is determined to be a 3-bit or higher error and an error indication signal is output. The data error correction module is connected to the dual error detection module. When a 2-bit error is detected, the data is corrected and the original 64-bit data is restored according to the error location identified by the error location module. When a 3-bit or higher error is detected, an error status signal is output.

3. The ECC low-latency real-time decoding circuit supporting 2-bit error correction according to claim 2, characterized in that, The 72 extended decoding modules invert the corresponding bits of the 72-bit data to be decoded while keeping the remaining bits unchanged, and then output the generated second synergistic state signal to the dual error detection module.

4. The ECC low-latency real-time decoding circuit supporting 2-bit error correction according to claim 2, characterized in that, The 72 extended decoding modules adopt a parallel synchronous working mode, and the processing clock of each extended decoding module is consistent with the processing clock of the synodal generator.

5. The ECC low-latency real-time decoding circuit supporting 2-bit error correction according to claim 3, characterized in that, The error location module's judgment logic is as follows: based on the comparison results of the first and second syndication state signals, the 1-bit / 2-bit error location is identified; when the first syndication state signal output by the syndication generator is a 1-bit error and can be corrected, it is determined to be a 1-bit error; when the first syndication state signal output by the syndication generator is a 2-bit error detection, and there are at least two extended decoding modules whose second syndication state signals are 1-bit errors and can be corrected or have no errors, it is determined to be a 2-bit error and an error correction command is sent to the data error correction module.

6. The ECC low-latency real-time decoding circuit supporting 2-bit error correction according to claim 2, characterized in that, The error location module's determination logic is as follows: When the first symptom corresponds to a 1-bit error, it is determined to be a 1-bit error; If the first symptom corresponds to a 2-bit error, and the second symptom of at least two extended decoding modules corresponds to no error or a 1-bit error, it is determined to be a 2-bit error.

7. The ECC low-latency real-time decoding circuit supporting 2-bit error correction according to claim 2, characterized in that, The data error correction module also includes a data verification feedback unit. After completing the 2-bit error correction, the corrected 72-bit data is fed back to the synergistic generator for secondary verification. After confirming that the error correction result is correct, the recovered original 64-bit data is output. If the secondary verification finds that there is still an error, the dual error detection module is triggered to output a 3-bit or higher error indication signal.

8. The ECC low-latency real-time decoding circuit supporting 2-bit error correction according to claim 2, characterized in that, The ECC encoder uses the DEDSEC encoding mechanism.

9. A memory chip, characterized in that, The memory chip includes the ECC low-latency real-time decoding circuit supporting 2-bit error correction as described in any one of claims 1 to 8, wherein the memory chip includes a random-access memory device, and the random-access memory device includes at least one of Spinor flash memory and DRAM.

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