A high-temperature-resistant interface electric tree high-voltage power module packaging insulation design method

Abstract

The application belongs to the technical field of encapsulation insulation, and particularly relates to a high-temperature-resistant interface electric tree high-voltage power module encapsulation insulation design method, which is based on macroscopic and microscopic technical targets and considers the modulation effect of space charges on the growth process of IET to perform encapsulation insulation design; the encapsulation insulation design comprises the following steps: S1, designing an encapsulation module; S2, inspecting the microscopic molecular characteristics, processability, high-temperature encapsulation reliability, carrier mobility, intermolecular interaction force and high-temperature-resistant IET characteristics of the encapsulation module; if the inspection is passed, the encapsulation module is determined; if the inspection is not passed, the step S1 is returned and adjusted. Compared with the prior art, the application solves the problem that the prior art does not consider the high-temperature IET phenomenon and IET-resistant insulation design for the insulation encapsulation structure of the power module. The design method provided in the scheme can meet the encapsulation insulation design of the high-temperature-resistant IET characteristics.

Description

Technical Field

[0001] This invention belongs to the field of encapsulation and insulation technology, specifically relating to a high-voltage power module encapsulation and insulation design method for high-temperature resistant interface electrical trees. Background Technology

[0002] As wide-bandgap SiC power modules evolve towards higher temperatures (>150 °C) and voltages (>6.5 kV) and miniaturization to improve power density, the electric field at the three junction points in the package structure becomes more concentrated. This high electric field at the three junction points easily induces partial discharge and interface electrical trees, significantly degrading the dielectric properties of the packaging insulation material under high temperature and high electric field conditions, and making it prone to space charge injection, ultimately leading to module breakdown. The initiation voltage of interface electrical trees (IET) is much lower than the breakdown voltage of the packaged module, and its growth process requires a longer time to cause module breakdown. Furthermore, as the temperature increases, the initiation voltage of IET decreases, and the growth rate accelerates. Although partial discharge (PD) is difficult to detect in newly manufactured power modules in a short time, IET can still be initiated by accidental factors such as localized electrical stress concentration and insulation inhomogeneity in SiC power modules subjected to rated voltage for extended periods, especially at temperatures exceeding 175 °C. In such cases, because the power module can still operate normally during the initiation and growth stages of IET, timely detection of IET becomes difficult. If inter-electrode interference (IET) is not detected and addressed in a timely manner, it may ultimately lead to complete module failure. Furthermore, in the current manufacturing process of high-voltage, high-power modules, technical challenges such as the concentrated electric field near the triple junction and the extremely high electric field around random copper protrusions remain unresolved, making the prevention of IET extremely complex and difficult. These problems accelerate the degradation of the packaging insulation, thereby promoting the formation and growth of IET, putting the power module at risk of breakdown.

[0003] The selection of high-temperature encapsulation materials requires a balance between thermal stability and flexibility. Compared with other high-temperature encapsulation materials (such as polyimide, benzocyclobutene, and cyanate resins), silicone elastomers have lower hardness and storage modulus, and exhibit good mechanical compatibility with other components in power modules. Currently, research focuses on the interfacial discharge characteristics of silicone gel / ceramic substrates at lower temperatures, but these typically operate only at a few kV and below 150 °C (in the fields of high-voltage equipment external insulation and cable accessory insulation). Research on interfacial treeing and partial discharge characteristics at temperatures above 150 °C (SiC power module encapsulation) is still scarce. Furthermore, existing high-temperature encapsulation insulation designs primarily focus on improving thermal stability and breakdown field strength, without fully considering the formation mechanism, suppression strategies, and diagnostic methods of interfacial treeing. Therefore, it is necessary not only to conduct in-depth research on the electrical properties and space charge characteristics of silicone elastomer materials at high temperatures (>150 °C) and high electric fields, but also to focus on improving the electrical resistance and resistance to interfacial treeing under such extreme conditions.

[0004] Although current research has focused on designing novel packaging structures and optimizing packaging parameters to effectively reduce the electric field at the three-junction point, this also brings problems such as mechanical stress concentration, process complexity, decreased reliability, and difficulties in miniaturization. This is mainly because existing high-temperature packaging insulation designs primarily focus on improving thermal stability, enhancing dielectric strength, and achieving higher short-time PDIV. For example, CN118759327A discloses a method and apparatus for evaluating the dielectric properties of modified silicone rubber, as well as electronic equipment, to evaluate the dielectric properties of modified silicone rubber as a transformer insulation material. Additionally, there is a numerical prediction method for the electric tree development path of porous insulating materials disclosed in CN118280500A, which uses a phase-field simulation algorithm to simulate the electric tree development path. However, existing technologies still pay relatively little attention to the high-temperature IET phenomenon and IET-resistant insulation design.

[0005] The addition of nanofillers (such as boron nitride, alumina, aluminum nitride, zinc oxide, silica, and POSS) to encapsulation modules can effectively improve the insulation properties of polymers. Among them, cage-like polyhedral oligomeric silsesquioxane (POSS) is considered the smallest siloxane nanoparticle, measuring only 1-3 nanometers. The inorganic core of POSS is a highly symmetrical cage-like structure with a low real dielectric constant, high thermal stability, and good mechanical properties. Its apical active organic groups can serve as links between the polymer and POSS, thereby enhancing the compatibility between the polymer and POSS. Furthermore, the formed covalent bonds can modify its structure at the nanoscale, improving thermal conductivity and breakdown strength. In addition, compared to other ceramic nanoparticles, POSS molecules are more readily soluble in solvents, simplifying and controlling the processing of composite materials. Therefore, POSS exhibits better thermal and electrical properties than ceramic particles.

[0006] For example, octaaminophenyl POSS, triepoxyisobutyl POSS, and epoxy-based POSS form covalent bonds with epoxy resin due to their active organic groups, and are dispersed at the molecular level as part of a reinforcing cross-linking network. However, these POSS materials, when reacting directly with epoxy resin and curing agent at high filler contents, are prone to agglomeration, which reduces thermal and electrical properties. Furthermore, due to incompatibility, obvious agglomerated trisilanephenolic POSS at the interface between the POSS and the polypropylene matrix can be observed within the polypropylene matrix.

[0007] The prior art, CN109251423A, discloses a trap control method based on POSS-modified EPDM rubber. However, this method involves directly and physically doping high-content OVPOSS filler into silicone rubber. The filler has poor dispersibility and is prone to agglomeration, resulting in poor interfacial compatibility with the silicone rubber matrix. Consequently, its control over the trap distribution and micro-charge transport of silicone rubber is quite limited. Furthermore, it pays relatively little attention to high-temperature IET phenomena and IET-resistant insulation design.

[0008] Therefore, for the structural design and material formulation of encapsulation insulation, IET should be distinguished from electrical breakdown. That is, the design goal should not be limited to improving thermal stability and breakdown field strength, but should also give equal importance to improving the high-temperature IET characteristics. Summary of the Invention

[0009] The purpose of this invention is to provide a high-voltage power module packaging insulation design method resistant to high-temperature interfacial electrical trees (IET) to solve at least one of the aforementioned problems. This addresses the issues in existing technologies where the insulation packaging structure and material formulation of power modules do not consider the high-temperature IET phenomenon and the IET-resistant insulation design. The design method proposed in this solution covers the design principles of high-temperature IET resistance at both macroscopic and microscopic levels, and considers the modulation effect of space charge on the IET growth process, thus achieving a packaging insulation design that meets the high-temperature IET resistance requirements.

[0010] The objective of this invention is achieved through the following technical solution: A high-voltage power module packaging insulation design method with high-temperature resistant interface electrical trees is proposed. Based on macroscopic and microscopic technical objectives and considering the modulation effect of space charge on the IET growth process, the packaging insulation design is carried out. The technical objectives include electrical conductivity, mechanical strength, carrier mobility, and intermolecular interactions; The encapsulation insulation design is as follows: S1. Design of the packaging module: Filler is added to the packaging module; S2. Inspect the microscopic molecular properties, processability, high-temperature packaging reliability, carrier mobility, intermolecular interaction forces, and high-temperature IET resistance of the packaged module. If the inspection passes, the encapsulated module is confirmed; if the inspection fails, return to step S1 and adjust the manufacturing process and / or structural morphology and / or material formulation.

[0011] Preferably, the encapsulation module is filled with nano or sub-nano fillers, and the fillers are improved by nano-grafting technology to enhance dispersibility.

[0012] Preferably, the filler is prepared by grafting a cage-type polysilsesquioxane (POSS) onto a silicone elastomer (SE), followed by reaction with vinyl-terminated polydimethylsiloxane (VPDMS) to obtain a POSS-grafted silicone elastomer nanocomposite material. This method can prevent OV-POSS from participating in the silicone elastomer curing process and reduce the possibility of agglomeration.

[0013] Preferably, the microscopic molecular properties are obtained through quantum chemical calculations using density functional theory, including molecular orbital energy levels, molecular binding energy, surface electrostatic potential, and charge density. The verification of the microscopic molecular properties is as follows: compare the band gap and molecular binding energy of the optimized structure with those of the previous structure. If the band gap and molecular binding energy of the optimized structure exceed the level of the previous structure, the verification is passed.

[0014] Preferably, the processability and high-temperature packaging reliability testing includes: requiring adhesion and internal stress to meet preset target values, requiring no volume shrinkage, no interface delamination, no cross-linking byproducts and no bubbles, and requiring a balance between thermal stability and flexibility.

[0015] Specifically, the testing methods for processability and high-temperature encapsulation reliability are as follows: Before potting, the encapsulation insulating base material mixture solution can fully fill the target high-voltage power module and form an encapsulation structure. No uncovered areas or rapid solidification of the solution during flow are observed (visually detectable by the naked eye), indicating good processability. After potting and vacuum degassing, electron microscopy reveals no bubbles in the encapsulation structure, especially near the metallization layer edge. After curing, ultrasonic microscopy reveals no interface delamination, volume shrinkage, bubbles, impurities, or other cross-linking byproducts. After curing and long-term aging at 200 °C for 500 h, ultrasonic microscopy reveals no interface delamination, volume shrinkage, bubbles, or other abnormalities, indicating good high-temperature encapsulation reliability.

[0016] Preferably, the carrier mobility is tested by evaluating the insulation performance through electrical experiments, including conductivity, breakdown strength, space charge, dielectric spectrum, thermally stimulated depolarization current, and surface potential decay, thereby verifying whether there are deeper trap levels and lower charge mobility in the packaged module.

[0017] Preferably, the bipolar charge transport (BCT) model is used for analysis and verification.

[0018] Preferably, the intermolecular interaction force is tested by evaluating thermal and mechanical properties to determine whether the intermolecular interaction force has been enhanced. The thermal properties mentioned include thermal decomposition temperature (used to measure thermal stability), thermal conductivity, coefficient of thermal expansion, and relaxation behavior of molecular chain segments. The mechanical properties include tensile strength, elongation at break, Young's modulus, storage modulus, loss modulus, loss factor, degree of crosslinking, and hardness.

[0019] Preferably, the test for the high-temperature IET resistance is performed by applying the packaged module to a high-voltage power module and testing whether the packaged module has higher PDIV and stronger IET suppression capability.

[0020] Preferably, the effect of the packaging module on suppressing IET growth in the power module is verified by IET phase field simulation; wherein, the improved Allen-Cahn equation is used for IET phase field simulation.

[0021] The working principle of this invention is as follows: To improve the interfacial compatibility and dispersibility of nanofillers in silicone elastomers and avoid electrical defects caused by nano-agglomeration, the smallest nano-silicon-based compound—cage-type polysilsesquioxane—was selected. Through the chemical grafting reaction between the eight vertices of the active organic groups of POSS and the matrix molecular chains, a silicone elastomer nano-grafted composite material with extremely low content was prepared as a filler for the encapsulation module.

[0022] This scheme proposes two levels of high-temperature resistant IET design principles, covering both macroscopic and microscopic levels, and considers the modulation effect of space charge on the IET growth process. The macroscopic aspects mainly include reducing electrical conductivity and enhancing mechanical strength, while the microscopic aspects involve reducing carrier mobility and enhancing intermolecular interactions.

[0023] Compared with the prior art, the present invention has the following beneficial effects: The power module packaging insulation design method proposed in this invention analyzes the influence of microscopic charge transport on the electrical performance of packaging insulation and the growth of interface electrical trees. By combining bipolar carrier transport and interface electrical tree phase field simulation of the packaging module, it can identify weak links in the module design and weak points in the packaging insulation that may cause IET. The packaging module designed by this method can simultaneously meet the requirements of thermal stability, breakdown field strength and high temperature IET resistance, and is expected to provide theoretical support for the packaging insulation design of high temperature IET resistance.

[0024] This invention also proposes a POSS-grafted silicon elastomer nanocomposite material. The proposed nano-POSS grafting technology can achieve high dispersion and high interfacial compatibility of nanofillers at extremely low content, forming a uniform and dense nanostructure. By introducing dense cross-linking points and a rigid cage structure, it suppresses the relaxation motion and thermal degradation of molecular chain segments at high temperatures, strengthens the molecular cross-linking structure, and enhances the interaction between molecular chains. The nano-POSS-grafted composite material exhibits lower mass loss and better electrical properties after thermal aging. Compared with pure SE, the nano-grafted material has higher mechanical strength, lower coefficient of thermal expansion, stronger thermal stability, and better heat transfer efficiency. At high temperatures, it has lower electrical conductivity, higher breakdown field strength, lower dielectric constant, lower dielectric loss, and higher ion jumping barrier, exhibiting excellent aging resistance, thermal properties, mechanical strength, high-temperature electrical resistance, and dielectric properties. By introducing deeper charge traps, nano-POSS enhances the charge trapping ability at the electrode / dielectric interface, reduces charge mobility, and increases charge detrapping time, effectively suppressing charge injection and accumulation.

[0025] This invention further verifies the high-temperature encapsulation reliability of nano-grafted composite materials. Regardless of whether the encapsulation module is lateral or longitudinal, the nano-grafted composite material encapsulation module exhibits higher PDIV and breakdown voltage, with lower PD amplitude and repetition rate. Compared to pure SE, the IET side branches of the nano-grafted material are finer and denser. Its nanostructure disperses the high PD energy that would normally cause rapid growth of the IET trunk channel into a large number of low-energy side branch channels, converting it into low-amplitude PD, effectively suppressing IET growth and reducing the IET breakdown probability. The deep traps of the nano-grafted material capture injected charges and form a space charge shielding layer, thereby homogenizing the electric field near the three-junction point of the encapsulation module. As the temperature increases, PDIV decreases, the IET growth rate accelerates, and the IET trunk channel becomes thicker and more numerous. The lower the charge mobility and the stronger the intermolecular interactions of the encapsulation insulation, the more effectively the interfacial charge transport and IET growth of the encapsulation module are suppressed. Attached Figure Description

[0026] Figure 1 A flowchart illustrating the design method for high-voltage power module packaging insulation to withstand high-temperature interface electrical trees.

[0027] Figure 2 The structural model and parameters of the encapsulation module used for bipolar charge transport simulation.

[0028] Figure 3 The space charge (a) and electric field distribution (b) of a pure SE package module and the space charge (c) and electric field distribution (d) of an SE-P package module.

[0029] Figure 4 Structural models and IET phase field distributions of transversely packaged modules under different electrical conductivity conditions are presented.

[0030] Figure 5 SEM cross-sectional topography and EDS elemental composition ratios of pure SE(a) and SE-P(b).

[0031] Figure 6 Mechanical property testing (a) and dynamic thermomechanical analysis (b) for pure SE and SE-P.

[0032] Figure 7 Thermogravimetric analysis curves (a) and (b) for pure SE and SE-P.

[0033] Figure 8 Thermal conductivity of pure SE and SE-P (a) and infrared thermal imaging analysis (b).

[0034] Figure 9 The DC conductivity (a) and nonlinear conductivity (b) of pure SE and SE-P are given.

[0035] Figure 10 Weibull distribution of AC breakdown field strength for pure SE and SE-P (a) and its characteristic breakdown field strength (b).

[0036] Figure 11 Let be the real part of the dielectric constant of pure SE(a) and SE-P(b) at different temperatures.

[0037] Figure 12 Let be the imaginary part of the dielectric constant of pure SE(a) and SE-P(b) at different temperatures.

[0038] Figure 13 Analysis of dielectric relaxation characteristics of pure SE and SE-P based on the derived pair derivative method: (a) di of pure SE at 160 °C ε' / dln( f (b) d of pure SE and SE-P within 20~100 ℃ ε' / dln( f (c) Pure SE before and after translation d ε' / dln( f (d) SE-P before and after translation d ε' / dln( f (e) Ion jumping activation energies of pure SE and SE-P; (f) Relative interfacial region thickness of SE-P.

[0039] Figure 14 Surface potential decay characteristics and charge transport analysis for pure SE and SE-P: (a) SPD curves; (b) normalized SPD curves; (c) normalized SPD differential curves for SE; (d) normalized SPD differential curves for SE-P; (e) apparent charge mobility; (f) escape time distribution of trapped charges.

[0040] Figure 15 Thermally stimulated depolarization currents (a) and continuous trap distributions (b) for pure SE and SE-P.

[0041] Figure 16 The variation patterns of space charge distribution (a) and average charge density (b) for pure SE and SE-P are shown.

[0042] Figure 17 Leakage current (a) and DC conductance (b) of the horizontally packaged module.

[0043] Figure 18 AC breakdown voltage (a) and AC PDIV Weibull distribution (b) of the lateral package module.

[0044] Figure 19 The PD amplitude variation (a) and average discharge repetition rate (b) of the horizontally packaged module are shown.

[0045] Figure 20 The IET length variation (a) and IET breakdown probability (b) of the lateral package module are shown.

[0046] Figure 21 PRPD diagrams of pure SE and SE-P lateral packaged modules at different temperatures: (a) pure SE 30 ℃; (b) SE-P 30 ℃; (c) pure SE 160 ℃; (d) SE-P 160 ℃; (e) pure SE 200 ℃; (f) SE-P 200 ℃.

[0047] Figure 22 IET and breakdown morphologies of pure SE and SE-P lateral package modules at 200 °C: (a) pure SE at 200 °C; (b) SE-P at 200 °C; (c) slow IET breakdown; (d) fast electrical breakdown.

[0048] Figure 23 The IET morphology of pure SE and SE-P lateral packaged modules at different temperatures.

[0049] Figure 24 The preparation process of POSS-grafted silicon elastomer nanocomposite materials.

[0050] Figure 25 The diagram shows the distribution of (a) highest occupied molecular orbital (HOMO), lowest unoccupied molecular orbital (LUMO), band gap and electrostatic potential of SE and SE-P, and (b) charge trapping process.

[0051] Figure 26 The deformation charge density distributions for SE and SE-P are shown (red areas represent electron gain, and blue areas represent electron loss).

[0052] Figure 27 The electrode structure (a) and its geometric parameters (b) of the lateral packaging module, along with the offset of the copper metallization layer and the electrical connection method (c).

[0053] Figure 28 Ultrasonic scanning microscopy images of the packaged module before and after thermal aging and electrical breakdown: (a) before thermal aging; (b) after thermal aging; (c) after electrical breakdown. Detailed Implementation

[0054] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. Unless otherwise specified in the following description, all matters not covered herein are prior art.

[0055] Example 1 This scheme proposes a two-tiered design principle for high-temperature resistant IETs, covering both macroscopic and microscopic levels, and considers the modulation effect of space charge on the IET growth process. The macroscopic aspects mainly include reducing electrical conductivity and enhancing mechanical strength, while the microscopic aspects involve reducing carrier mobility and enhancing intermolecular interactions. For example... Figure 1 As shown, the specific process of the packaging insulation design to achieve high-temperature resistant IET characteristics is as follows, and the parameters involved are determined according to actual needs.

[0056] Step 1: Design encapsulation insulation material with high temperature resistant IET properties In the encapsulation and insulation design of high-temperature resistant IETs, nano or sub-nano fillers are more effective at hindering IET growth than micron fillers. These fillers suppress charge transport by introducing deep traps, and their high specific surface area generates an interfacial binding effect that enhances intermolecular interactions, thereby improving the mechanical strength and thermal stability of the encapsulation and insulation material. Therefore, this solution prefers nano or sub-nano fillers.

[0057] Furthermore, ensuring uniform dispersion of the filler and its high compatibility with the polymer is crucial for achieving optimal IET resistance. However, traditional filler dispersion methods, such as mechanical stirring and ultrasonic dispersion, are costly, time-consuming, and prone to filler agglomeration. Therefore, this solution also proposes a novel nanografting technology for effectively dispersing the filler in the matrix.

[0058] Step 2: Verify the superior microscopic molecular properties of the encapsulation insulation (verify the superior molecular properties through quantum chemical calculations). After determining the initial material composition and optimizing the molecular structure, density functional theory was used to perform quantum chemical calculations to obtain molecular properties including molecular orbital energy levels, molecular binding energy, surface electrostatic potential, and charge density. To verify the existence of deep trap energy levels and enhanced intermolecular electrostatic interactions, it was necessary to ensure that the band gap and molecular binding energy of the optimized molecular structure exceeded the levels achieved in the previous round of material optimization.

[0059] Step 3: Inspect the processability of the encapsulation insulation and the reliability of high-temperature encapsulation. The raw materials used for encapsulation insulation should have low viscosity, slow drying, and good flowability to completely fill complex encapsulation structures. After curing, the encapsulation insulation must have strong adhesion to firmly bond with other components / structures, maintain low residual internal stress, and avoid volume shrinkage, voids, bubbles, or cross-linking byproducts. After high-temperature thermal aging, the encapsulation insulation should ensure no interface separation from other components of the module, and its exposed surface should be free of cracks. Furthermore, high-temperature reliability requires a trade-off between thermal stability and flexibility. High-temperature encapsulation insulation should have an appropriate modulus of elasticity and coefficient of thermal expansion to ensure it does not cause severe thermomechanical stress to other components of the power module, thereby maintaining good encapsulation reliability under high temperature and high electric field conditions.

[0060] Step 4: Inspect the charge carrier mobility of the encapsulated insulation. After verifying superior microscopic molecular properties and encapsulation reliability, the encapsulation insulating material should undergo a series of electrical tests to evaluate its insulation performance, including conductivity, breakdown strength, space charge, dielectric spectrum, thermally stimulated depolarization current, and surface potential decay. These electrical tests can verify the existence of deeper trap levels and lower charge mobility within the encapsulation insulation. To further verify whether charge transport within the encapsulation module is effectively suppressed, this approach employs a bipolar charge transport model for analysis.

[0061] Step 5: Test the intermolecular interactions that strengthen the encapsulation insulation. After verifying lower charge mobility, the material properties of the encapsulated insulation need to be evaluated using thermal performance (thermal stability, coefficient of thermal expansion, etc.) and mechanical performance (mechanical strength, Young's modulus, etc.) testing systems to verify whether intermolecular interactions have been enhanced. The relaxation behavior of molecular chain segments at high temperatures can be analyzed by dielectric spectroscopy, and crosslinking degree and hardness tests can further verify the toughness of the material's molecular crosslinking structure.

[0062] Step 6: Inspect the high-temperature IET resistance of the encapsulation insulation. Finally, an encapsulation insulating material with lower charge mobility and stronger intermolecular interactions was applied to the power module, and the resulting module was tested to demonstrate higher PDIV and stronger IET suppression capabilities. Furthermore, phase-field simulations further validated the material's inhibitory effect on IET growth in the power module. If any step in the above process fails validation, step 1 should be returned to adjust the material preparation process and raw material formulation for the next round of optimization until all validations are passed.

[0063] The above simulation of bipolar charge transport in the package module is as follows: In order to verify the inhibitory effect of deep level traps and low apparent charge mobility on charge transport behavior in the package insulation, a bipolar charge transport (BCT) model was established to simulate the microscopic charge transport process and the electric field distribution of space charge modulation.

[0064] According to the BCT model, electrons and holes are injected from the cathode and anode, respectively. The injected charges migrate continuously within the insulating material through repeated trapping and detrapping, eventually being extracted from the opposite electrode or recombinating with charges of opposite polarity. When the injected charge is trapped in a trap within the insulator, space charge is formed. The BCT model can describe the dynamic behavior of microscopic charges, including processes such as charge injection, trapping, detrapping, recombination, migration, and extraction. This model simulates the dynamic evolution of charges by numerically solving partial differential equations, coupling position and time variables. The model includes the Poisson equation, the charge transport equation, and the continuity equation. ; The subscript 'a' indicates the type of charge, including free electrons, trapped electrons, free holes, and trapped holes. μ a For charge mobility, n a For the density of the corresponding charge type, j a For current density, ρ The net charge density at a specific location and time. ε r The relative permittivity, D fa Where is the charge diffusion coefficient. s a The source term represents the change in local space charge density caused by trapping, untrapping, and recombination.

[0065] The BCT model consists of partial differential equations and a charge-conserving electrostatic field model. The partial differential equations describe the behavior of different types of charges, and the calculated space charge distribution is imported into the electrostatic field model. The electric field distribution is then calculated using the Poisson equation.

[0066] In the above simulation of the interface electrical tree phase field of the packaging module: a lower microscopic carrier mobility corresponds to a lower macroscopic conductivity. In order to explore the inhibitory effect of lower conductivity on IET growth in the packaging module, this scheme simulates the IET growth process of the packaging module for the first time through a phase field model, considering the influence of various component materials of the packaging module on IET, rather than being limited to a single material.

[0067] In the phase-field model, a continuous phase-field variable is introduced. η ( r , t To describe the spatial and temporal evolution of the breakdown phase: η ( r , t )=1 indicates the breakdown phase. η ( r , t=0 indicates a non-breakdown phase, while values ​​between 0 and 1 represent the degree of insulation damage. IET growth mainly depends on the combined effects of electric field energy and Joule thermal energy. In the electric field calculation, the dielectric parameters of the encapsulation insulation, ceramic substrate, and copper metallization layer are considered simultaneously, while the IET phase field calculation only considers the electrical properties of the encapsulation insulation. This is because the ceramic substrate has high breakdown strength, making electrical breakdown difficult. The electric field energy depends on the dielectric constants of the encapsulation insulation and the ceramic substrate, while the Joule thermal energy depends on the conductivity of the encapsulation insulation. To describe the phase transition evolution of IET, a modified Allen-Cahn equation is used to simulate IET, as shown below: ; In the formula, f sep The free energy density that promotes phase separation f ele This refers to the electric field energy density. f joule This refers to the Joule heat energy density. f th It is the critical energy density for insulation degradation. L 0 is the kinetic coefficient characterizing the growth rate of electrical trees. H ( f ele + f joule - f th () is a unit step function. γ is the gradient energy coefficient.

[0068] The IET simulation method for the aforementioned packaged module can be extended to industrial applications of package insulation design. It can be used to identify weak points in the module design and potential IET vulnerabilities in the package insulation, potentially providing theoretical support for the design of high-temperature resistant IET packages. IET growth under AC voltage is influenced by both electric field energy and Joule thermal energy. The electric field energy is determined by the electric field strength and the dielectric constant of the package insulation, while the Joule thermal energy depends on the electric field strength and the conductivity of the package insulation. Since the AC electric field is affected by the applied voltage and the dielectric constant of the package insulation, and nanografting has a relatively small impact on the dielectric constant, keeping the applied voltage and the dielectric constant of the package insulation constant is crucial to maintaining a constant electric field energy. The Joule thermal energy is adjusted by changing the conductivity, ensuring that conductivity is the only factor affecting IET growth.

[0069] Example 2 In this embodiment, POSS grafted PMHS with mass fractions of 1 wt%, 2 wt%, and 3 wt% were used as novel crosslinking agents to prepare silicon elastomer nano-grafted composite materials with POSS mass fractions of 0.02 wt%, 0.04 wt%, and 0.06 wt%, respectively, which were named SE-P 0.02, SE-P 0.04, and SE-P 0.06, respectively.

[0070] The following preparation uses 2 wt% POSS grafted with PMHS as an example.

[0071] Step 1.1: Preparation of POSS-grafted PMHS 0.4 g of OV-POSS filler and 20 g of PMHS were stirred in toluene solvent (60 mL), and Karstedt catalyst (0.025 g) was added under dry nitrogen atmosphere. The mixture was refluxed through a condenser at 70 °C for 2 hours. Nano-POSS was grafted onto the PMHS molecular chain via hydrosilylation. The solvent in the resulting mixture was then removed by rotary evaporation to prepare a POSS-grafted PMHS solution. Uniform distribution of POSS in the solvent facilitates the formation of uniformly sized nanofillers and effectively prevents microscale agglomeration of the filler.

[0072] Step 1.2: Preparation method of POSS-grafted silicon elastomer nanocomposite material 12 g of VPDMS, 0.25 g of POSS-grafted PMHS, 0.05 g of Karstedt catalyst, and 0.025 g of inhibitor were stirred at 25 °C for 30 minutes and subjected to multiple cycles of vacuum degassing. The liquid mixture was then poured into a polytetrafluoroethylene mold and cured at 120 °C for 3 hours to obtain a POSS-grafted silicone elastomer nanocomposite sample, labeled SE-P0.04, while the pure silicone elastomer was labeled SE.

[0073] To investigate the effects of thermal aging on the mass change, crosslinking degree, DC conductivity, and AC breakdown field strength of silicon elastomers and their nanocomposites, this embodiment involved thermally aging the prepared samples in air at 200 °C for 500 hours. The crosslinking degree of the samples was determined using the equilibrium swelling method. First, samples with an initial mass of... m The sample with a mass of 0 was immersed in a toluene solution at 30 °C for 24 hours until it reached mass saturation. The sample surface was then wiped clean and weighed, and the final mass was recorded. m 1. Crosslinking degree through m 0 and mThe ratio of 1 was calculated. Based on the aging characteristics analysis, SE-P 0.04 exhibited the best aging resistance and was therefore considered the optimal material example for further research on thermal, mechanical, and high-temperature electrical properties. Pure SE and SE-P 0.04 were used to prepare packaging modules to test their high-temperature and high-electric-field packaging performance. In the following description, SE-P 0.04 will be referred to as SE-P.

[0074] Example 3 Step 1: Design encapsulation insulation material with high temperature resistant IET properties like Figure 24 As shown, in this embodiment, vinyl-terminated polydimethylsiloxane (VPDMS) (viscosity: 200 mPa·s) and polymethylhydrosiloxane (PMHS) (viscosity: 22 mPa·s) were selected as the silicone elastomer base materials (both were provided by Dow Chemical Company, USA). The crosslinking reaction was carried out through a Karstedt catalyst (concentration: 3000 ppm, provided by Beijing Huawi Ruike Chemical Co., Ltd.) and an inhibitor (1-ethynyl-1-cyclohexanol, provided by Shanghai Aladdin Biochemical Technology Co., Ltd.); the octavinyl POSS nanoparticles were provided by Shanghai Mairui Biochemical Technology Co., Ltd.

[0075] Step 2: Examine the microscopic molecular properties of the encapsulated insulation. To verify the optimized molecular properties and explore the microscopic mechanism of the low carrier mobility in SE-P, this study performed quantum chemical calculations based on density functional theory, obtaining the molecular energy level distribution, molecular binding energy, electrostatic potential, and deformation charge density of SE and SE-P. The calculation details for SE and SE-P are as follows: The molecular structures of SE and SE-P were designed and analyzed using the DMol3 toolkit (based on density functional theory) of the Materials Studio molecular dynamics simulation software. Geometric optimization was performed using the Perdew-Burke-Ernzerhof functional within the generalized gradient approximation framework, and the orbitals (highest occupied molecular orbital HOMO, lowest unoccupied molecular orbital LUMO) and electrostatic potential were calculated. The convergence criteria for geometric optimization were set as follows: energy 1×10⁻⁶. -5 Ha, maximum force 2×10 -3 Ha / Å, maximum displacement 5×10 -3 Å. The self-consistent field convergence tolerance used in the calculation is 1×10⁻⁶. -6 The basis set is selected using a double-numerical polarization function.

[0076] Figure 25Figure (a) shows that the LUMO of SE-P is increased while the HOMO is decreased, resulting in an increased band gap (Eg). This expanded band gap increases the trap depth in SE-P, thereby reducing carrier mobility. The molecular binding energies of SE and SE-P are 8013 Ha and 14229 Ha, respectively, indicating that SE-P has a more compact molecular structure and stronger molecular electrostatic interactions.

[0077] To further determine the origin of deep traps in SE-P, Figure 26 and Figure 25 Figure (a) shows the analysis results of deformation charge density and electrostatic potential. Figure 26 The results show that oxygen atoms act as electron traps by gaining electrons, while silicon atoms act as hole traps by losing electrons. On the SE molecular chain, the traps are relatively dispersed; however, the grafted POSS has a dense distribution of oxygen and silicon atoms, causing the deep traps to concentrate within the POSS group. Figure 25 The electrostatic potential distribution of SE-P in (a) indicates that the nano-POSS portion is negatively charged, which is conducive to trapping holes; its central region is positively charged, which is conducive to trapping electrons. Therefore, the grafted nano-POSS provides a deeper charge trap. Figure 25 Figure (b) illustrates the process of electron and hole trapping in SE and SE-P. In SE-P, electrons on the LUMO and holes on the HOMO are trapped in deeper traps, making it difficult for them to escape and migrate.

[0078] Based on the analysis of the above quantum chemical calculation results, the band gap and molecular binding energy of the SE-P molecular structure both exceed those of pure SE. The SE-P trap energy level is deeper and the intermolecular electrostatic interaction is stronger. Moreover, the deep trap of SE-P is located on the grafted nano-POSS, which proves that the microscopic molecular properties of SE-P are superior, and this is verified by step 2.

[0079] Step 3: Inspect the processability of the encapsulation insulation and the reliability of high-temperature encapsulation. To test the encapsulation reliability of the prepared silicon elastomer composite material in power modules, this scheme designs a simplified encapsulation module with a lateral copper metallization layer structure. This module is used to study the interface electrical treeing and partial discharge characteristics of the silicon elastomer encapsulation module under lateral electrical stress. The electrode structure and geometric parameters of the lateral encapsulation module are as follows: Figure 27 As shown, the geometric parameters were characterized using a 3D digital microscope. The copper metallization layer offset and electrical connection method of the packaged module are as follows: Figure 27As shown, the copper-clad ceramic substrate of the packaging module adopts a direct copper plating process. The edge of the copper metallization layer is inclined to form an angle of less than 90° with the plane of the ceramic substrate, and exhibits a metallic protrusion feature near the ceramic substrate. There is a triple bonding point at the junction of the packaging insulation layer, the copper metallization layer and the ceramic substrate. Due to the mismatch of dielectric parameters between the packaging insulation and the ceramic substrate, a high electric field is generated near the triple bonding point, which can easily induce partial discharge and interface electrical trees in the packaging insulation, and even lead to module breakdown.

[0080] In the lateral packaging module, the copper metallization layers for both high voltage and ground connections are located on the same side of the ceramic substrate. A rectangular copper metallization layer is used for grounding, while a triangular copper metallization layer with an acute-angled tip connects to the high-voltage source. This electrode tip has a radius of curvature of 8 μm and an included angle of 30°. Under high voltage, it generates a locally concentrated strong electric field, which is conducive to inducing severe partial discharge, thereby generating electrical trees that grow laterally along the interface between the packaging insulation / ceramic substrate, ultimately forming an interface electrical breakdown channel. Simultaneously, the copper metallization layer on the other side of the ceramic substrate is electrically levitated to avoid interference from the longitudinal electric field on the module's electrical testing.

[0081] Using SE-P as the encapsulation insulating material, the fabrication process of the lateral encapsulation module is as follows: (1) First, copper wire balls are soldered onto two copper metallization layers on the same side of the top of the ceramic substrate. Then, the bonded copper-clad ceramic substrate is placed in an ultrasonic bath at 40 °C and cleaned with isopropanol for 1 h to remove solder paste and grease residue. Then, the cleaned substrate is placed in a vacuum oven at 100 °C and dried for 2 h. After that, it is placed in a polytetrafluoroethylene mold to prepare for potting.

[0082] (2) Subsequently, the uniformly stirred and degassed silicone elastomer mixture was slowly poured into the mold to ensure that the encapsulation module was completely encapsulated. The mold was then placed in a degassing machine and degassed at room temperature until all air bubbles introduced during the encapsulation process were removed. Finally, the encapsulated module was placed in an oven and pre-cured at 80 °C for 1 h, and then cured at 120 °C for 3 h to obtain the silicone elastomer encapsulation module.

[0083] To test the interfacial adhesion between the silicone elastomer material and the ceramic substrate and copper metallization layer, the interfacial state of the encapsulated module before and after thermal aging at 200 °C for 500 h and electrical breakdown was characterized using ultrasonic scanning microscopy. Figure 28 As shown, the SE-P packaged module exhibits excellent interface adhesion and potting performance both before and after thermal aging, adhering tightly to the copper metallization layer and the ceramic substrate surface. No delamination, bubbles, voids, or impurities were found at the interface between the package insulation / copper layer and the package insulation / ceramic substrate before electrical breakdown. Interface delamination only appeared after electrical breakdown.

[0084] Based on the above packaging reliability analysis, SE-P has low viscosity, slow drying and good flowability, which can completely fill complex packaging structures. After curing, it has strong adhesion and can be firmly bonded to the ceramic substrate and copper metallization layer, while maintaining low residual internal stress. It does not produce volume shrinkage, voids, bubbles or cross-linking byproducts, and there is no interface separation with other components of the module after high-temperature thermal aging. Moreover, there are no cracks on its surface exposed to air. This proves that SE-P has excellent processability and high-temperature packaging reliability, and passes the verification in step 3.

[0085] Step 4: Inspect the charge carrier mobility of the encapsulated insulation. Figure 9 (a), (b), and (c) show the DC conductivity, nonlinear conductivity, and breakdown field strength of pure SE and SE-P at different temperatures (30 °C, 160 °C, and 200 °C), respectively. Conductivity was evaluated using a three-electrode setup under different electric fields of 5, 10, 15, and 20 kV / mm. Breakdown strength was measured using encapsulated ball-to-ball electrodes to avoid surface flashover, with a voltage rise rate of 1 kV / s. The breakdown field strength was analyzed using a two-parameter Weibull statistical method, and the breakdown field strength corresponding to a 63.2% breakdown probability was taken as the characteristic breakdown strength of the sample. At the same temperature, the DC conductivity of SE-P was lower than that of pure SE, and both the DC conductivity and nonlinear conductivity of both increased with increasing temperature. At 200 °C, since the nonlinear conductivity of both was close to 1, the conductivity was proportional to the electric field strength. Although the conductivity of SE-P is positively correlated with the electric field strength, its conductivity is still significantly lower than that of the ceramic substrate at the same temperature. Therefore, the electric field dependence of SE-P conductivity has little impact on the electric field near the triple junction of the power module. At 200 ℃ and 20 kV / mm, the DC conductivity of pure SE and SE-P are 6.8 × 10⁻⁶. -12 S / m and 1.8×10 -12 S / m indicates that nano-POSS grafting reduces the conductivity under high temperature and high electric field conditions to one-quarter of its original value. Lower conductivity helps improve package insulation performance and reduce power loss in the power module. Figure 9 The Weibull distribution and characteristic breakdown strength of the breakdown field strength in (c) are shown. At the same temperature, the breakdown strength of SE-P is higher than that of SE, and its breakdown strength decreases with increasing temperature. At 200 °C, the breakdown field strengths of SE and SE-P are 35.8 and 39.6 kV / mm, respectively. The breakdown field strength of SE-P is 3.8 kV / mm higher than that of SE. The higher breakdown field strength is beneficial for the reliable operation of high-temperature silicon carbide modules at higher voltages. SE-P has lower conductivity and higher breakdown strength at high temperatures, indicating that the grafted POSS nanofiller improves the high-temperature insulation performance of the silicon elastomer.

[0086] The Weibull distributions of AC breakdown field strengths for pure SE and SE-P and their characteristic breakdown field strengths are as follows: Figure 10 As shown in (a) and (b), the breakdown field strength of SE-P at the same temperature is higher than that of pure SE, and its breakdown field strength gradually decreases with increasing temperature. Furthermore, the AC breakdown field strength of SE-P at 160 °C is slightly higher than that of pure SE at 30 °C, while the AC breakdown field strength of SE-P at 200 °C is close to that of pure SE at 160 °C. This indicates that the grafted nano-POSS not only improves the high-temperature electrical properties of the silicon elastomer nanocomposite material but also mitigates the degradation of the dielectric strength of the composite material at high temperatures.

[0087] Under the combined influence of electric field and heat, dielectric relaxation processes, such as long / short-range ion hopping conduction, molecular chain segment relaxation, interfacial polarization, and dipole orientation polarization, can be analyzed using broadband wide-temperature dielectric spectroscopy. The real parts of the dielectric constants of pure SE and SE-P in the range of 20–200 °C are also available. ε' Each as Figure 11 As shown in (a) and (b), different frequency ranges. ε' The decrease represents different dielectric relaxation types. When the temperature exceeds 100 °C, the low frequency of pure SE... ε' As the frequency drops rapidly, the low frequency of SE-P... ε' The reduction trend is slower at high temperatures. Furthermore, SE-P's... ε' The dielectric constant value is consistently lower than that of pure SE, especially above 40 °C, indicating that the dielectric relaxation behavior in the nanografted composite is suppressed. Due to the matching dielectric parameters of the SE matrix and the nano-POSS, and the low polarity of the POSS, the MWS interface polarization in SE-P can be neglected. Furthermore, the hollow cage-like structure of the nano-POSS also helps to reduce the real part of the dielectric constant of SE-P.

[0088] Figure 12 In the diagram, (a) and (b) are the imaginary parts of the dielectric constant of pure SE and SE-P, respectively. ε'' As the frequency drops below 10 Hz, pure SE and SE-P... ε'' The dielectric loss of SE-P increased at 80 °C and 140 °C, indicating that SE-P exhibits lower low-frequency dielectric loss and better high-temperature stability below 140 °C, while the low-frequency dielectric loss of pure SE increases rapidly above 80 °C. When the temperature exceeds 140 °C, the rate of increase in dielectric loss of SE-P with decreasing frequency is lower than that of pure SE, and the rate of increase in dielectric loss of both increases significantly at higher temperatures. At 160 °C and 0.1 Hz, the dielectric losses of pure SE and SE-P are 4.35 and 1.14, respectively, indicating that grafting POSS can effectively reduce the high-temperature dielectric loss of silicon elastomer materials.

[0089] The dielectric properties of dielectric materials at high temperatures and low frequencies are crucial for studying the slow relaxation behavior over long polarization times, which typically reflects the long-range migration characteristics of internal ions. Although the imaginary part of the dielectric constant... ε'' The peak size and frequency of the relaxation peak can reflect the polarization intensity and relaxation time, but... ε'' In the high-temperature, low-frequency region, the DC conductivity component typically dominates and may even mask the dielectric relaxation peak, making it difficult to accurately identify its dielectric parameters. This is because DC conductivity significantly affects the real part of the low-frequency dielectric constant. ε' There is no impact; this solution uses the derived pair derivative method to analyze low frequencies. ε' To extract and analyze the slow dielectric relaxation behavior of silicon elastomer materials in the high-temperature, low-frequency region. This was achieved through... ε' Regarding ln( f The differential d) ε' / dln( f The real part of the dielectric constant can be expressed as follows: ε' The process of decreasing frequency transforms into a clear relaxation peak, thus revealing the dielectric relaxation behavior in different frequency ranges.

[0090] d of pure SE at 160 °C ε' / dln( f For example, Figure 13 As shown in (a). Exclude 10. -3 Electrode polarization below Hz and 10 3 Dipole orientation polarization above Hz, 0.1~1 Hz, 1~10 Hz and 10 Hz 2 ~10 4 Long-range ion hopping conduction, local ion hopping polarization, and molecular chain segment relaxation were observed in the Hz range. Figure 13 (b) represents the d values ​​of pure SE and SE-P within the temperature range of 20–100 °C. ε' / dln( f The changes were as follows: Pure SE exhibited significant ion hopping conduction below 1 Hz, while SE-P did not show significant ion hopping conduction, indicating that ion transport in the nano-grafted composite material was effectively suppressed at 100 ℃, thereby reducing DC conductivity and increasing AC breakdown field strength.

[0091] This scheme employs the frequency-temperature shift method to further investigate the dielectric properties of pure SE and SE-P in the high-temperature, low-frequency range. The frequency-temperature shift method originates from the frequency-temperature equivalence principle, which states that increasing the temperature or decreasing the electric field frequency has an equivalent effect on the mechanical relaxation behavior of polymers. Applying this principle to dielectric spectra, the relationship between dielectric relaxation at different temperatures can be established by shifting the dielectric spectrum. Specifically, the dielectric relaxation process at low frequency and low temperature is the same as that at high frequency and high temperature, causing the dielectric relaxation peak at high temperature to shift to a lower frequency as the temperature decreases. By analyzing the relationship between the spectral shift and temperature, the activation energy of dielectric relaxation behavior can be calculated. Therefore, decreasing the temperature or frequency is an equivalent method for characterizing dielectric relaxation. To evaluate long-range ion hopping relaxation behavior, based on the frequency-temperature shift method, the following equation is used to evaluate d... ε' / dln( f ) Spectrum shift: ; In the formula, α scaling It is the dielectric spectrum shift factor. T low and T high For different test temperatures ( T low < T high ).

[0092] For the same sample, the temperature of d can be adjusted. ε' / dln( f The curve shifts to the left to a lower frequency band, until it matches the low-temperature d... ε' / dln( f The curves coincide. Figure 13 (c) represents pure SE in the temperature range of 20~140℃. ε' / dln( f The changes before and after the curve was translated. Figure 13 (d) represents the d values ​​of SE-P from 140 °C to 200 °C. ε' / dln( f The changes in the curves before and after the shift are shown. The long-range ion transition conduction relaxation curves of pure SE and SE-P at different temperatures overlap well in the low-frequency range after the shift. Furthermore, at 0.1 Hz and 140 ℃, the di of SE-P... ε' / dln( f The concentration of POSS was significantly lower than that of pure SE, indicating that the grafted nanofiller effectively suppressed long-range ion conduction. However, due to the polarity of nano-POSS, SE-P exhibited dipole orientation at high temperatures.

[0093] Figure 13In the figure (e), represents the spectral shift factor of ion hopping relaxation for pure SE and SE-P at different temperatures. α scaling , α scaling logarithm and temperature T The reciprocals of and are linearly related, conforming to the Arrhenius equation, and can be obtained by fitting ln( α scaling ) and 1 / T The activation energy of ion jumping is calculated based on the relationship, as shown in the following formula: ; In the formula, A As a pre-factor, E a It is the activation energy for ion jumping, and is related to the height of the ion jumping barrier. k b This is the Boltzmann constant, i.e., 1.38 × 10⁻⁶. -23 J / K, T This refers to absolute temperature.

[0094] The long-range ion hopping barrier of pure SE below 140 °C is 0.38 eV, while that of SE-P above 140 °C reaches 0.65 eV. This higher hopping barrier effectively inhibits charge migration, making it difficult for impurity ions to overcome the barrier and migrate to the opposite electrode. Therefore, even at high temperatures, free charge transport in SE-P is hindered, resulting in lower conductivity. Furthermore, the ion hopping barrier is influenced by the molecular structure and the interface region between the nanofiller and the matrix. Physical defects (such as molecular chain entanglement and coiling), chemical bonds, and intermolecular forces in the interface region introduce numerous charge traps. Along the radial direction away from the filler, the trap depth in the interface region gradually decreases, and the interface region thickness is typically less than the mean free path of the charge. Therefore, free charges struggle to accumulate sufficient energy in the interface region to overcome the hopping barrier.

[0095] Furthermore, the interfacial region of the nanofiller restricts the relaxation motion of molecular chains, enhances intermolecular interactions, and increases the cross-linking degree of the matrix. The enhanced intermolecular interactions generate more induced charges opposite to the polarity of the ions at the molecular chain ends, thus forming a stronger electrostatic attraction between the molecular chains and ions, manifesting as a higher ion hopping barrier, and thereby inhibiting ion hopping conduction. The interfacial region not only contains multiple ion traps of varying depths but also influences the molecular structure through interfacial binding forces on the matrix molecular chains, thereby altering the depth of ion traps in the polymer matrix. Therefore, studying the thickness of the interfacial region of the nanofiller in SE-P is of great significance for evaluating the interfacial region's ability to bind molecular chains and its inhibitory effect on ion hopping.

[0096] The interfacial region in SE-P suppresses long-range ion hopping. Therefore, when the interfacial region thickness is large, the binding effect of the interfacial region on the molecular chain is stronger, resulting in weaker long-range ion hopping relaxation strength. This is achieved by using d at 0.1 Hz... ε' / dln( f The ratio of long-range ion transition relaxation intensity of SE-P to that of pure SE was calculated. ξ m If ion jumping is suppressed, then ξ m The thickness of the interface area will be less than 1. δ i The following formula can be used for calculation: ; In the formula, χ nano This represents the volume fraction of the nanofiller. r nano It is the radius of the nanofiller, approximately 28 nm.

[0097] The volume fraction of nanofillers can be calculated from their mass fraction and density. The relative interfacial thickness is the ratio of the interfacial thickness at a certain temperature to the interfacial thickness at 20 °C, reflecting the change in interfacial thickness with temperature. Figure 13 As shown in (f), the relative interfacial thickness of SE-P initially increases and then decreases with increasing temperature. The interfacial thickness of SE-P is largest at 160 °C, being 2.94 times that at 20 °C. This indicates that, compared to pure SE, the grafted nano-POSS interfacial region in SE-P exhibits the most significant binding ability on molecular chains and hindering ion jumping at 160 °C, thus enabling SE-P to exhibit superior thermal, mechanical, electrical, and dielectric properties compared to pure SE at high temperatures.

[0098] Under negative polarity charging voltage, the decay of the dielectric surface potential is closely related to the trapping and migration process of trapped electrons. By studying the decay law of the dielectric surface potential, the transport characteristics of trapped electrons can be effectively analyzed. The negative polarity SPD curves of pure SE and SE-P are shown below. Figure 14 As shown in Figure (a), at the same temperature, the initial surface potential of SE-P is higher than that of pure SE, and the initial surface potential of both pure SE and SE-P decreases with increasing temperature. To more intuitively compare the surface potential decay rates of pure SE and SE-P at different temperatures, the SPD curves of both were normalized, and the results are shown in Figure (b). Figure 14 As shown in (b), the surface potential decay rate at 30 s was calculated, and the specific data are shown in Table 1.

[0099] Table 1. Surface potential decay rate (%) of pure SE and SE-P at different temperatures after 30 s Table 1 shows that the surface potential decay rates of both pure SE and SE-P decrease with increasing temperature, and the decay rate of SE-P is consistently lower than that of pure SE. Even at 200 ℃, the surface potential decay rate of SE-P is still lower than that of pure SE at 30 ℃, indicating that the grafted nano-POSS has a significant inhibitory effect on surface potential decay. To investigate the charge transport characteristics of the samples during surface potential decay, the d values ​​of pure SE and SE-P at different temperatures were... U / d t The curves are respectively as follows Figure 14 As shown in (c) and (d). In the early stage of potential decay, U It exhibits a rapid linear decay, followed by a slow, curved decay; correspondingly, d U / d t The curve is nearly flat in the early stage, then reaches an inflection point, and subsequently decays rapidly. For d in a logarithmic coordinate system... U / d t Regarding time t The curve, whose inflection point is generated by linear fitting in the early and late stages, represents the time it takes for surface charge to migrate to the ground electrode. t T The apparent charge mobility during potential decay can be calculated using the following formula: ; Charge migration within dielectric materials is typically associated with charge trapping and detrapping processes. The longer the time required for trapped charges to escape, the greater the trap depth and the more difficult the detrapping process. Decay time t With d U / d t product t ·d U / d t This reflects the amount of trapped charge at different decay times, and the trapped charge density. N t and t ·d U / d t The values ​​are positively correlated. t Constant-time de-trapping charge density N t The calculation formula is as follows: ; In the formula, q e This is the elementary charge, i.e., 1.6 × 10⁻⁶. -19 C.

[0100] Apparent charge mobility of pure SE and SE-P via charge migration time of SPD differential curve tT Calculated, such as Figure 14 As shown in (e), compared to pure SE, SE-P exhibits a lower apparent charge mobility at the same temperature, and the apparent charge mobility of both increases with increasing temperature, indicating that increasing temperature promotes charge migration. Furthermore, from 30 °C to 200 °C, the apparent charge mobility of pure SE and SE-P increases by 17.6 times and 6.2 times, respectively, indicating that grafted nano-POSS effectively suppresses charge transport at high temperatures.

[0101] decay time t With potential decay rate d U / d t The product curve is as follows Figure 14 As shown in (f), the y-axis is t ·d U / d t , and time t The de-trapping charge density is proportional to the charge density, and t ·d U / d t The peak values ​​of the curves correspond to the time required for most trapped charges to escape. At the same temperature, the charge escaping time of SE-P is significantly longer than that of pure SE; even at a high temperature of 200 °C, the charge escaping time of SE-P is nearly seven times that of pure SE. Furthermore, the charge escaping times of both pure SE and SE-P gradually decrease with increasing temperature, indicating that the grafted nano-POSS in SE-P possesses strong charge trapping ability and quantum confinement effect, making it more difficult for charges to escape from the traps. However, the high temperature allows the trapped charges to acquire sufficient kinetic energy in a short time, thus facilitating rapid charge escaping. Figure 15 In Figure (a), the TSDC curves for pure SE and SE-P are shown. The calculated continuous trap density-level distribution is as follows: Figure 15 As shown in (b), pure SE has shallow traps with an energy level of 0.82 eV, while SE-P forms deep traps with an energy level of 1.17 eV. Furthermore, the charge density of the shallow traps in SE-P is significantly lower than that of pure SE, indicating that nano-POSS grafting transforms the shallow trap energy level in the SE matrix into the deep trap energy level. This is closely related to the regulatory effect of nano-POSS grafting on the microscopic molecular structure of the composite material.

[0102] To more intuitively study the microscopic charge behavior characteristics of pure SE and SE-P, the space charge distribution of both was measured under a DC electric field of 30 kV / mm, with a polarization time of 6 min and a test temperature of 30 ℃. Figure 16(a) shows the space charge distribution of pure SE and SE-P. Pure SE shows a significant accumulation of negative space charge near the anode, while no space charge was observed in the SE-P matrix or near the electrode. In pure SE, the negative charge is injected from the cathode and migrates to the anode, forming an accumulation of opposite-polarity space charge; however, in SE-P, nano-POSS introduces a deeper charge trap, inhibiting the injection and migration of negative charge. To investigate the effect of nano-POSS grafting on space charge characteristics, the average charge density of the samples was calculated to quantitatively analyze the space charge accumulation during polarization, such as... Figure 16 As shown in (b), the average charge density includes the induced charge at the electrode / sample interface and the space charge within the sample. Its calculation formula is as follows: ; In the formula, q ( t () represents the average charge density. L For the sample thickness, ρ ( x , t )for x Location and t The charge density at time t. Figure 16 As shown in (b), the average charge density of pure SE first increases rapidly with time, and then tends to 4 C / m. 3 The average charge density of SE-P remains slightly greater than 1 C / m 3 The lower level.

[0103] Based on the analysis of microscopic charge transport properties, the trap depths of pure SE and SE-P are 0.82 eV and 1.17 eV, respectively, and their apparent charge mobilities are 6.85 × 10⁻⁶. -13 and 7.40×10 -13 m 2 / (V·s). The structural model of the encapsulation module is as follows: Figure 2 As shown, a +5 kV DC voltage is applied to the copper metallization layer on the left, while the copper layers on the right and bottom are grounded to ensure that the packaged module undergoes continuous charge injection and transport under the long-term action of the same polarity electric field, thereby generating more significant space charge accumulation to highlight the influence of trap depth and apparent charge mobility on charge behavior.

[0104] Figure 3 These are simulation results of space charge and electric field distribution within pure SE and SE-P packaged modules based on a bipolar charge transport model. Figure 3 As shown in (a), in the pure SE module, a large amount of positive charge is injected from the high-voltage copper layer on the left and migrates along the interface between the encapsulation insulating / ceramic substrate to the ground copper layer on the right, resulting in a significant accumulation of opposite-polarity space charge near the ground copper layer, with a maximum charge density of 25.3 C / m.3 However, by Figure 3 As shown in (c), positive charges accumulate near the surface of the high-voltage copper layer of the SE-P module, forming a thin layer of space charge of the same polarity, with a maximum charge density of only 7.34 C / m. 3 This is consistent with the space charge test results of the thin film sample. Figure 3 (b) and Figure 3 As shown in Figure (d), the maximum electric fields at the triple junction points in the pure SE and SE-P modules are 56.5 kV / mm and 42.9 kV / mm, respectively. The results indicate that the deeper trap levels and lower carrier mobility in the SE-P module hinder charge injection and migration within the packaged module, thereby reducing the electric field strength near the triple junction points.

[0105] Based on the above electrical test and charge simulation results, the high-temperature insulation performance of SE-P is due to the pure SE and the fact that the molecular chain relaxation motion at high temperature is bound by nano-POSS, which leads to the suppression of charge transport behavior in SE-P and a lower charge carrier mobility, thus passing the electrical verification in step 4.

[0106] Step 5: Test the intermolecular interactions that strengthen the encapsulation insulation. SEM cross-sectional microstructure and EDS elemental analysis of pure SE and SE-P samples are as follows: Figure 5 As shown, the samples were characterized using a Hitachi SU-8010 scanning electron microscope. The pure SE sample had a smooth and impurity-free cross-section, while the SE-P sample exhibited a uniform and dense nanostructure with a rough surface. This indicates that the trace amount of POSS grafting affected the cross-linking process of the SE-P matrix molecular chains. The originally loose SE molecular chains were tightly cross-linked around the POSS, forming a nanospherical structure with the POSS cage structure as the core and the densely cross-linked SE molecular chains as the shell. Furthermore, SE-P has a higher proportion of Si and O atoms than pure SE, while its proportion of C atoms is lower than that of pure SE. The Si, C, and O atom ratio of POSS monomer is 1:1:2, and its C atom ratio is much lower than that of pure SE. In contrast, the molecular side chains of pure SE are rich in alkyl groups, and C atoms are mainly concentrated in the alkyl side chains. This indicates that the nanostructure of SE-P reduces the alkyl content by grafting POSS to replace some of the alkyl side chains of the matrix. The POSS monomer undergoes an addition reaction with the silane groups of the matrix through its eight vertices, connecting multiple silicon-oxygen backbones of the matrix and introducing dense cross-linking points in local areas, forming a dense and compact molecular cross-linking structure, which improves the cross-linking degree of SE-P.

[0107] The TGA and DTG curves of pure SE and SE-P are as follows: Figure 7As shown in (a) and (b), the thermogravimetric analysis (TGA) of the samples was performed in nitrogen using a TA Q500 thermogravimetric analyzer (TAQ500) and the corresponding derivative TGA curves were calculated to characterize the thermogravimetric rate of the samples. The test temperature range was 50–800 °C, and the heating rate was 10 °C / min. The temperature corresponding to 90% weight loss in the TGA curve was defined as the thermal decomposition temperature. The thermal decomposition temperature of SE-P was 26.9 °C higher than that of pure SE. In addition, the DTG peak temperature of SE-P was 35.1 °C higher than that of pure SE, and the absolute value of its DTG peak value was significantly reduced. This indicates that the nanostructure formed by POSS grafting improved the thermal stability of the SE-P molecular cross-linking network, reduced its thermal decomposition rate at high temperatures, inhibited the high-temperature relaxation motion and cyclization degradation of molecular chains, and strengthened the molecular cross-linking structure of SE-P at high temperatures.

[0108] Thermal conductivity of pure SE and SE-P at different temperatures, such as Figure 8 As shown in (a), the thermal conductivity of SE-P is higher than that of pure SE at different temperatures, indicating that the molecular structure of SE-P is more ordered and uniform, which promotes phonon transport and reduces phonon scattering. With increasing temperature, the free volume between molecular chains increases and the thermal motion of molecular chain segments intensifies, thus hindering phonon transport and leading to a decrease in thermal conductivity. To more intuitively demonstrate the heat transfer process of pure SE and SE-P, thin film samples of the same thickness were placed on a constant-temperature platform at 150℃, and their infrared thermal images and neutral point temperatures were recorded, as shown in (a). Figure 8 As shown in (b), the results indicate that the temperature rise rate of SE-P is greater than that of pure SE, exhibiting superior heat transfer efficiency and making it more suitable for high-temperature packaging applications of power modules.

[0109] Figure 6 In Figures (a) and (b), the mechanical tensile and dynamic thermomechanical analysis curves for pure SE and SE-P, respectively, are presented. Figure 6 As shown in (a), compared with pure SE, SE-P exhibits increased tensile strength, elongation at break, and Young's modulus by 0.34 MPa, 13.7%, and 0.31 MPa, respectively, demonstrating stronger mechanical toughness. Figure 6 As shown in (b), the CTE value of SE-P is 53 ppm / K lower than that of pure SE, indicating that the thermal motion of SE-P molecular chain segments is hindered at high temperatures. Furthermore, the hardness of pure SE and SE-P are 32 and 37 Shore A, respectively, and they exhibit low sensitivity to thermal aging. Although the CTE value of SE-P is higher than that of other rigid components in power electronic modules, its high flexibility prevents the generation of severe thermomechanical stress within the module. These results demonstrate that the relaxation and fracture processes of molecular chain segments in SE-P are suppressed, and the interactions between molecular chains are enhanced, confirming that grafted nano-POSS, acting as local mechanical reinforcing points, can effectively improve the mechanical properties of SE-P.

[0110] Based on the analysis of the above thermodynamic performance test results, SE-P has higher thermal decomposition temperature, thermal conductivity, tensile strength, hardness, elongation at break and Young's modulus, as well as lower alkyl content, CTE and DTG peak values, indicating that SE-P has better thermal stability and mechanical toughness, proving that its intermolecular interaction force is stronger, which is verified by step 5.

[0111] Step 6: Inspect the high-temperature IET resistance of the encapsulation insulation. The encapsulation insulation performance of pure SE and SE-P under horizontal localized electrical stress and different temperature conditions was evaluated using lateral encapsulation modules. Figure 17 (a) shows the leakage current of the lateral packaged module under +5 kV DC voltage. The leakage current during DC voltage polarization consists of steady-state conduction current and transient absorption current. Typically, the transient absorption current exhibits fast relaxation behavior due to a short polarization time (relaxation time < 10 kV). -11 s) and slow relaxation behavior with longer polarization time (10 -2 s < relaxation time < 10 4 s) is generated. Therefore, in order to eliminate transient absorption current and obtain accurate steady-state DC conduction current. I 0, using a double exponential decay function to reduce the leakage current of the horizontally packaged module. I ( t The following formula is used for fitting: ; In the formula, A 1 and τ 1. Polarization intensity and polarization time of the fast relaxation process, respectively. A 2 and τ 2. Polarization intensity and polarization time during the slow relaxation process. The DC conduction current obtained through fitting... I 0. Calculate the DC conductance of the horizontally packaged module at 30 ℃, 160 ℃, and 200 ℃, such as... Figure 17 As shown in (b), the DC conductance of the SE-P lateral package module is significantly lower than that of the pure SE, and decreases by 59.8% at 200 °C.

[0112] Figure 18(a) and (b) show the Weibull distributions of AC breakdown voltage and partial discharge inception voltage (PDIV), respectively. Compared to the pure SE module, the SE-P module exhibits higher AC breakdown voltage and PDIV, increasing by 17.6% and 9.2% respectively at 200 °C. This indicates that the grafted nano-POSS effectively suppresses leakage current in the packaged module at high temperatures and improves breakdown voltage and PDIV. Both breakdown voltage and PDIV decrease with increasing temperature. From 30 °C to 200 °C, the PDIV of the pure SE and SE-P packaged modules decreases by 35.2% and 29.8% respectively, indicating that high temperatures lead to degradation of package insulation performance, while POSS grafting mitigates this degradation.

[0113] IET was grown for 5 min at an AC voltage 1 kV higher than PDIV, and its growth length, breakdown probability, phase-resolved partial discharge (PRPD) spectrum and PD characteristic parameters were recorded. Figure 19 (a) shows the variation of PD amplitude over time during the IET growth process of the lateral packaged module. At 30 °C, the PD amplitude of the pure SE packaged module increases rapidly within the first 100 s; while at 30 °C and 160 °C, the PD amplitude of the SE-P packaged module initially increases and then gradually decreases to a low level of about 100 pC. In addition, the PD amplitude of the pure SE packaged module shows an upward trend at 200 °C, exceeding 2 nC at 300 s, while the PD amplitude of the SE-P packaged module remains relatively stable, fluctuating around 1 nC. Figure 19 In the middle (b), the average discharge repetition rate of the lateral packaged module during the IET growth process is shown. The average discharge repetition rate of the SE-P packaged module is lower than that of the pure SE at different temperatures. Even at 200 °C, the average discharge repetition rate of the SE-P module is still much lower than that of the pure SE.

[0114] The shortest distance between the IET end and the tip of the high-voltage copper metallization layer is defined as the IET length. The IET length of a lateral package module varies over time as follows: Figure 20As shown in Figure (a), at 30 °C, the IET of the pure SE module rapidly grows towards the ground copper layer, eventually leading to module breakdown; while at 30 °C and 160 °C, the IET length of the SE-P module initially increases and then stabilizes. Furthermore, at 200 °C, the IET length growth rate of the SE-P module is slower than that of the pure SE, and its IET length is still less than 1 mm at 300 s. Moreover, in the absence of rapid module breakdown, the IET growth rate increases with increasing temperature. The high amplitude PD after IET initiation is the main factor in IET growth. Nano-POSS grafting reduces the IET growth rate by decreasing the PD amplitude and discharge repetition rate, thus making the IET growth of the lateral module slower or even stagnant. For module samples with the same package insulation, repeated testing at the same temperature for 10 cycles resulted in the following breakdown probabilities: Figure 20 As shown in (b), due to the slower IET growth of the SE-P packaged module, its IET breakdown probability is significantly lower than that of the pure SE. Specifically, the IET breakdown probability of the SE-P module at 200 °C is reduced to half that of the pure SE.

[0115] Figure 21 PRPD patterns of lateral modules in pure SE and SE-P packages during the last 30 s of IET growth at different temperatures. IET is initiated at the tip of the high-voltage copper metallization layer with concentrated high electric field, a location intentionally designed as an electrical weak point, and then grows towards the ground electrode along the package insulating layer / ceramic substrate interface.

[0116] Depend on Figure 21 It can be seen that the pure SE lateral package module has higher PD amplitude and discharge repetition rate than the SE-P lateral package module at different temperatures. As the temperature increases, the repetition rate of high-amplitude PD in both modules increases significantly, while the IET degradation also intensifies accordingly. Taking the PRPD pattern and IET morphology at 200 ℃ as an example, the effects of nano-POSS grafting and high temperature on the IET and PD characteristics of the package module are analyzed.

[0117] Depend on Figure 21 As shown in (e), the PRPD pattern of the pure SE packaged module exhibits a "Г"-shaped distribution, characterized by a predominance of high-amplitude PDs and a lack of low-amplitude PDs, indicating the presence of tip discharge. High-amplitude PDs typically occur on the thicker IET main channel, while low-amplitude PDs are distributed on the thinner side channels, with the side branches growing from the sides of the main channel. The IET morphologies of the pure SE and SE-P packaged lateral modules at 200 °C are shown below. Figure 22As shown in (a) and (b), the IET growth process in a pure SE packaged module is mainly accompanied by a high-amplitude PD. The high electric field energy is concentrated in the main channel of the IET, resulting in a concentration of electric field intensity in the main channel and distortion of the electric field distribution in the surrounding area, thereby inhibiting the growth of side channels. Under the action of the electric field, the high-energy IET main channel extends rapidly towards the ground electrode and thickens, which can easily lead to IET breakdown.

[0118] Depend on Figure 21 (f) and Figure 22 As shown in (b), the SE-P packaged module generated a large number of low-amplitude PDs at 200 °C, while the amplitude of high-amplitude PDs decreased. Furthermore, the number of side branches in the IET increased and the main channel became thinner. This indicates that nano-POSS grafting dispersed the high energy of the main channel to a large number of side branches. Therefore, it can be inferred that POSS grafting forms a nanostructure that can effectively disperse high electric field energy. By dividing the main channel into more fine side branches, the high electric field energy originally concentrated in the main channel is dispersed to more side branches. The electric field energy within each side branch is quite limited, generating only lower-amplitude PDs, causing the side branch channels to grow slowly, thereby slowing down or even inhibiting the IET growth of the SE-P packaged module under high temperature and high electric field. In addition, PDs can be observed in both pure SE and SE-P packaged modules at 0° and 180° phases, indicating that the PD characteristics are jointly determined by the combined electric field formed by the applied electric field and the space charge near the IET. The PD characteristics at 0° and 180° phases are significantly affected by the built-in electric field formed by the accumulation of space charge during IET growth.

[0119] Figure 22 (c) and (d) show the lateral packaged modules after slow IET breakdown and fast electrical breakdown, respectively. The IET breakdown channel exhibits a certain curvature and several IET branches around it, with some channel surfaces appearing hollow and transparent. In contrast, the fast electrical breakdown channel shows a straighter carbonized path and no IET branches are observed. Compared to fast electrical breakdown, IET breakdown occurs at lower voltages and requires a longer breakdown time. Therefore, when designing high-temperature, high-electric-field packaged insulation, IET breakdown and fast electrical breakdown should be distinguished, and their different impacts on module performance should be considered separately in the design.

[0120] IET morphology of pure SE and SE-P lateral package modules at different temperatures is as follows: Figure 23As shown, compared to pure SE modules, the IET trunk channels in SE-P modules are shorter and thinner, but have more side channel channels, and the ends of the IET trunks transform into more fine side channel channels. Therefore, the growth rate of the IET trunk channels slows down or even stops. The decrease in PD amplitude of SE-P packaged modules at 30℃ and 160℃ further indicates that PD activity shifts from trunk channels to side channel channels, effectively inhibiting the growth of IET trunk channels and forming more slowly extending side channels with low PD amplitude. Therefore, the IET channels in SE-P lateral packaged modules become denser rather than longer over time, and their growth is suppressed. In addition, as the temperature increases, the IET channels become thicker and darker, and more trunk channels are generated.

[0121] Based on the phase-field method disclosed in Example 1, this scheme simulates the growth process of IET in a lateral packaging module. In the phase-field simulation, the influence of the conductivity of the packaging insulation on IET growth is studied by adjusting it. The length, width, and height of the phase-field region are set to 1 μm, 1 μm, and 0.3 μm, respectively, and the distance between the IET initiation point and the tip of the high-voltage copper layer is set to 1 μm to reduce the influence of the mesh generation method on the accuracy of the simulation results. A 10 kV AC voltage is applied to the high-voltage copper layer, and the relative permittivity of the packaging insulation and the ceramic substrate are set to 3 and 9, respectively. When the conductivity of the packaging insulation is 10 kV, the growth process is further simplified. -15 S / m and 10 -14 At S / m, the IET phase field side view of the horizontally packaged module at 10 s during simulation is as follows: Figure 4 As shown. The results indicate that at a conductivity of 10... -15 In the S / m encapsulation insulation, the IET length is shorter, indicating that encapsulation insulation with lower charge mobility and lower conductivity can more effectively suppress the growth of module IET.

[0122] Compared to pure SE, SE-P exhibits enhanced mechanical properties, indicating improved intermolecular interactions and cross-linking strength. The strengthened molecular structure is less susceptible to damage from high-energy charges, thus effectively inhibiting IET growth. It can be argued that reducing charge mobility helps mitigate the destructive effects of injected charges, while enhanced intermolecular interactions improve the material's resistance to charge collisions. Therefore, reducing charge mobility and enhancing intermolecular interactions are effective ways to improve PDIV and inhibit IET growth.

[0123] Based on the above high-temperature IET growth and partial discharge tests, as well as the analysis of IET phase field simulation results, compared with the pure SE packaged module, the SE-P packaged module has a higher IET initiation voltage, a slower growth rate, and lower accompanying partial discharge amplitude and density at 200 ℃. This indicates that the nano-POSS grafted SE-P package insulation has better high-temperature IET resistance characteristics, which is verified by step 6.

[0124] The proposed solution develops a low-content POSS-grafted silicon elastomer nanocomposite material, SE-P, which passed the full-cycle verification of steps 1 to 6. Compared with pure SE, SE-P has stronger resistance to high-temperature interface electrical treeing as an insulating material for high-voltage power module packaging.

[0125] In summary, this method developed a low-content POSS-grafted silicon elastomer nanocomposite material. The proposed nano-POSS grafting technology achieves high dispersion and high interfacial compatibility of the nanofiller at extremely low content, forming a uniform and dense nanostructure. By introducing dense cross-linking points and a rigid cage structure, the relaxation motion and thermal degradation of molecular chain segments at high temperatures are suppressed, strengthening the molecular cross-linking structure and enhancing the interaction between molecular chains. The nano-POSS-grafted composite material exhibits lower mass loss and better electrical properties after thermal aging. Compared with pure SE, the nano-grafted material has higher mechanical strength, lower coefficient of thermal expansion, stronger thermal stability, and better heat transfer efficiency. At high temperatures, it also exhibits lower electrical conductivity, higher breakdown field strength, lower dielectric constant, lower dielectric loss, and higher ion jumping barrier, demonstrating excellent aging resistance, thermal properties, mechanical strength, high-temperature electrical resistance, and dielectric properties. Nano-POSS enhances the charge trapping capability at the electrode / dielectric interface by introducing deeper charge traps, reduces charge mobility, and increases charge detrapping time, effectively suppressing charge injection and accumulation.

[0126] Furthermore, to verify the high-temperature encapsulation reliability of nano-grafted composite materials, this scheme used pure SE and nano-grafted composite materials as encapsulation insulation materials, and studied the high-temperature IET and PD characteristics of encapsulation modules with two copper metallization layer structures under horizontal and vertical electrical stress. Regardless of the lateral or vertical encapsulation module, the encapsulation module with nano-grafted composite materials exhibited higher PDIV and breakdown voltage, and its PD amplitude and repetition rate were lower. Compared with pure SE, the IET side branches of the nano-grafted material are finer and denser. Its nanostructure disperses the high PD energy that would normally cause rapid growth of the IET trunk channel into a large number of low-energy side branch channels and transforms it into low-amplitude PD, effectively suppressing IET growth and reducing the IET breakdown probability. The deep traps of the nano-grafted material capture injected charges and form a space charge shielding layer, thereby homogenizing the electric field near the three-junction point of the encapsulation module. As the temperature increases, PDIV decreases, the IET growth rate accelerates, and the IET trunk channel becomes thicker and its number increases. The lower the charge mobility of the encapsulation insulation and the stronger the intermolecular interaction, the more effectively it suppresses interfacial charge transport and IET growth in the encapsulation module. Combining bipolar charge transport simulation and IET phase field simulation of the packaging module, a packaging insulation design method with high temperature resistant IET characteristics is proposed.

[0127] The above description of the embodiments is provided to enable those skilled in the art to understand and use the invention. It will be apparent to those skilled in the art that various modifications can be made to these embodiments, and the general principles described herein can be applied to other embodiments without inventive effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made by those skilled in the art based on the disclosure of the present invention without departing from the scope of the invention should be within the protection scope of the present invention.

Claims

1. A high-voltage power module packaging insulation design method with high-temperature resistant interface electrical tree, characterized in that, Based on the technical objectives at both the macro and micro levels and considering the modulation effect of space charge on the IET growth process, we conduct encapsulation and insulation design. The technical objectives include electrical conductivity, mechanical strength, carrier mobility, and intermolecular interactions; The encapsulation insulation design is as follows: S1. Design of the packaging module: Filler is added to the packaging module; S2. Inspect the microscopic molecular properties, processability, high-temperature packaging reliability, carrier mobility, intermolecular interaction forces, and high-temperature IET resistance of the packaged module. If the inspection passes, the encapsulation module is determined; If the inspection fails, return to step S1 and adjust the preparation process and / or structural morphology and / or material formulation.

2. The high-voltage power module packaging insulation design method with high-temperature resistant interface electrical treeing according to claim 1, characterized in that, The encapsulation module incorporates nano or sub-nano fillers, and the fillers are improved in terms of dispersibility through nanografting technology.

3. The high-voltage power module packaging insulation design method with high-temperature resistant interface electrical treeing according to claim 2, characterized in that, The filler is prepared by grafting silicone elastomer SE with cage-type polysilsesquioxane (POSS), followed by reaction with vinyl-terminated polydimethylsiloxane (VPDMS) to obtain a POSS-grafted silicone elastomer nanocomposite material.

4. The high-voltage power module packaging insulation design method with high-temperature resistant interface electrical treeing according to claim 1, characterized in that, The aforementioned microscopic molecular properties are obtained through quantum chemical calculations using density functional theory, including molecular orbital energy levels, molecular binding energy, surface electrostatic potential, and charge density. The verification of the microscopic molecular properties is as follows: compare the band gap and molecular binding energy of the optimized structure with those of the previous structure. If the band gap and molecular binding energy of the optimized structure exceed the level of the previous structure, the verification is passed.

5. The high-voltage power module packaging insulation design method for high-temperature resistant interface electrical treeing according to claim 1, characterized in that, The aforementioned tests for processability and high-temperature packaging reliability include: requiring adhesion and internal stress to meet preset target values; requiring no volume shrinkage, no interface delamination, no cross-linking byproducts, and no bubbles; and requiring a balance between thermal stability and flexibility.

6. The high-voltage power module packaging insulation design method for high-temperature resistant interface electrical treeing according to claim 1, characterized in that, The carrier mobility is verified by evaluating the insulation performance through electrical experiments, including conductivity, breakdown strength, space charge, dielectric spectrum, thermal depolarization current, and surface potential decay, thereby verifying whether there are deeper trap levels and lower charge mobility in the packaged module.

7. The high-voltage power module packaging insulation design method for high-temperature resistant interface electrical treeing according to claim 6, characterized in that, The analysis and verification were performed using the bipolar charge transport (BCT) model.

8. The high-voltage power module packaging insulation design method for high-temperature resistant interface electrical treeing according to claim 1, characterized in that, The intermolecular interaction force is tested by evaluating thermal and mechanical properties to determine whether the intermolecular interaction force has been enhanced. The thermal properties mentioned include thermal decomposition temperature, thermal conductivity, coefficient of thermal expansion, and relaxation behavior of molecular chain segments; The mechanical properties include tensile strength, elongation at break, Young's modulus, storage modulus, loss modulus, loss factor, degree of crosslinking, and hardness.

9. The high-voltage power module packaging insulation design method for high-temperature resistant interface electrical treeing according to claim 1, characterized in that, The test for the high-temperature IET resistance is as follows: the packaged module is applied to a high-voltage power module, and the packaged high-voltage power module is tested to see if it has higher PDIV and stronger IET suppression capability.

10. The high-voltage power module packaging insulation design method for high-temperature resistant interface electrical trees according to claim 9, characterized in that, The effect of the encapsulation module on suppressing IET growth in the high-voltage power module was verified by IET phase field simulation; among which, the improved Allen-Cahn equation was used for IET phase field simulation.

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