3D stacked package structure and packaging method thereof

Abstract

A 3D stacked packaging structure and a packaging method thereof, the packaging structure comprising: a pair of stacked units; each of the stacked units comprising: a first substrate having a surface with a plurality of first metal structures, and a plurality of first interconnection structures and a plurality of first cavities penetrating through the first substrate; a second substrate located on the first substrate, and having a plurality of second interconnection structures and a second cavity penetrating through the second substrate, a transducer chip being placed in the second cavity, a particle incident surface of the transducer chip being located opposite to the radioactive source film; a third substrate located on the second substrate, a surface of the third substrate having a plurality of third metal structures, and a plurality of third interconnection structures penetrating through the third substrate, the third metal structures being located opposite to the transducer chip; in the pair of stacked units, two first substrates are located opposite to each other. The electrical connection between each of the stacked units is achieved through the interconnection structures, and the volume power density of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of nuclear energy technology, specifically to a 3D stacked packaging structure and its packaging method. Background Technology

[0002] With the rapid development of microelectromechanical systems (MEMS) technology, radiation-volt-ampere (RV) batteries have become a research hotspot in the field of micro-energy. The working principle of RV batteries is to utilize the radiation generated by the decay of radioactive isotopes to produce electrical energy through a transducer. Current RV batteries mostly adopt a single-cell integrated approach, primarily consisting of a radioactive source thin film, a transducer chip (such as a silicon carbide transducer chip), and a packaging substrate, resulting in low volumetric power density. Furthermore, the existing technology uses wire-bonded transducers and packaging substrates made of traditional PCB materials, leading to poor electrical interconnect stability and inadequate sealing of the radiation source. Summary of the Invention

[0003] The technical problem solved by this invention is to provide a 3D stacked packaging structure and packaging method, in which each stacked unit is vertically stacked through an interconnection structure to improve the volumetric power density of the device.

[0004] To address the aforementioned technical problems, this invention provides a 3D stacked packaging structure, comprising: paired stacked units; each stacked unit includes: a first substrate having a plurality of first metal structures on its surface, and having a plurality of first interconnect structures and a plurality of first slots extending through the first substrate along its thickness direction, each first metal structure surrounding a first slot, and each first slot containing a radiation source film; a second substrate located on the first substrate, the second substrate having a plurality of second interconnect structures and a second slot extending through the second substrate along its thickness direction, all the projections of the first metal structures and the first slots onto the surface of the second substrate being within the range of the second slots, and each second slot containing a radiation source film. The system includes a transducer chip with its particle incident surface facing the radiation source film, and several second interconnect structures distributed around the second slot; a third substrate located on the second substrate, the surface of the third substrate having several third metal structures, and the third substrate having several third interconnect structures penetrating the third substrate along its thickness direction, the third metal structures facing the transducer chip, each third metal structure covering a first slot and surrounding a first metal structure, and each second interconnect structure having one first interconnect structure and one third interconnect structure connected to its two ends along the thickness direction of the second substrate; in the paired stacked units, two first substrates are arranged facing each other.

[0005] Optionally, the interconnect structure includes: a first interconnect structure comprising a plurality of first pads and a plurality of first vias, wherein the plurality of first pads are arranged in pairs, each pair of first pads is located on two surfaces of the first substrate, each pair of first pads corresponds to one first via, the first via penetrating the first substrate and the corresponding first pad, and the first via being filled with conductive material; a second interconnect structure comprising a plurality of second pads and a plurality of second vias, wherein the plurality of second pads are arranged in pairs, each pair of second pads is located on two surfaces of the second substrate, each pair of second pads corresponds to one second via, the second via penetrating the second substrate and the corresponding second pad, and the second via being filled with conductive material; and a third interconnect structure comprising a plurality of third pads and a plurality of third vias, wherein the plurality of third pads are arranged in pairs, each pair of third pads is located on two surfaces of the third substrate, each pair of third pads corresponds to one third via, the third via penetrating the third substrate and the corresponding third pad, and the third via being filled with conductive material; the first interconnect structure, the second interconnect structure, and the third interconnect structure are connected by a conductive connection medium.

[0006] Optionally, the material of the first substrate includes at least one of aluminum nitride, aluminum oxide, and silicon carbide; the material of the second substrate includes at least one of aluminum nitride, aluminum oxide, and silicon carbide; and the material of the third substrate includes at least one of aluminum nitride, aluminum oxide, and silicon carbide.

[0007] Optionally, the thickness of the first substrate is 10 μm to 500 μm, the thickness of the second substrate is 10 μm to 500 μm, and the thickness of the third substrate is 10 μm to 500 μm.

[0008] Optionally, the first metal structure is a copper layer, a nickel layer and a tin layer stacked sequentially from the surface of the first substrate, and the third metal structure is a copper layer, a nickel layer and a tin layer stacked sequentially from the surface of the third substrate.

[0009] Optionally, the copper layer has a thickness of 1 μm to 20 μm, the nickel layer has a thickness of 0 μm to 20 μm, and the tin layer has a thickness of 1 μm to 20 μm.

[0010] Accordingly, the present invention also provides a packaging method for a 3D stacked packaging structure, comprising: preparing a first substrate, a second substrate, and a third substrate respectively; bonding the transducer chip to a first metal structure on the first substrate; placing the radiation source film in the plurality of first slots of the first substrate; stacking the first substrate, the second substrate, and the third substrate sequentially to form a stacked unit, wherein the particle incident surface of the transducer chip is disposed facing the radiation source film; and stacking two stacked units together, wherein the two first substrates of the two stacked units are disposed facing each other.

[0011] Optionally, the bonding includes thermocompression bonding, the bonding temperature is 100℃~400℃, and the bonding time is 10s~3600s.

[0012] Optionally, the method for preparing the first substrate includes: polishing and thinning a first ceramic substrate to form an initial first substrate; forming a plurality of first interconnect structures within the initial first substrate; after forming the plurality of first interconnect structures, forming a plurality of first metal structures on the surface of the initial first substrate; and after forming the plurality of first metal structures, forming a plurality of first slots within the initial first substrate to form the first substrate. The method for preparing the second substrate includes: polishing and thinning a second ceramic substrate to form an initial second substrate; forming a plurality of second interconnect structures within the initial second substrate; and after forming the plurality of second interconnect structures, forming a second slot within the initial second substrate to form the second substrate. The method for preparing the third substrate includes: polishing and thinning a third ceramic substrate to form an initial third substrate; forming a plurality of third interconnect structures within the initial third substrate; and after forming the plurality of third interconnect structures, forming a plurality of third metal structures on the surface of the initial third substrate to form the third substrate.

[0013] Optionally, the stacking connection process includes an integral welding process.

[0014] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In the 3D stacked packaging structure provided by this invention, the surface of the first substrate has several first metal structures, and the first substrate has several first slots penetrating the first substrate along its thickness direction. Each first metal structure surrounds one first slot. The second substrate has several second slots penetrating the second substrate along its thickness direction. The projections of all the first metal structures and first slots on the surface of the second substrate are located within the range of the second slots. The surface of the third substrate has several third metal structures, each third metal structure covering one first slot and surrounding one first metal structure. The third metal structures are arranged facing the transducer chip. The second substrate is located on the first substrate, and the third substrate is located on the second substrate. The transducer chip is placed in the second slot. Therefore, the transducer chip is electrically connected and fixed in the second slot through the first metal structures and the third metal structures. Furthermore, since a radiation source film is placed in each first slot, and the particle incident surface of the transducer chip is arranged facing the radiation source film, the physical distance between the radiation source film and the transducer chip is shortened, reducing the loss of radiation particles during transmission and thus improving the transduction efficiency of the device. Because the stacked units are arranged in pairs, with the two first substrates facing each other, the transducer chip is located in the second slots of the upper and lower second substrates, respectively, while the radiation source film is located in the first slot between the two stacked units. This achieves a self-supporting encapsulation structure, improving the energy utilization of the radiation source. Simultaneously, sealing the radiation source within the first slot between the two stacked units enhances its sealing performance. Furthermore, the first substrate has several first interconnect structures extending through it along its thickness direction, the second substrate has several second interconnect structures extending through it along its thickness direction, and these second interconnect structures are distributed around the second slots. The third substrate has several third interconnect structures extending through it along its thickness direction. Each second interconnect structure is connected to one first interconnect structure and one third interconnect structure at both ends along the thickness direction of the second substrate. Therefore, the interconnect structures are integrated with the substrate body, improving the mechanical strength of the interconnect structures. Additionally, the interconnect circuits between the substrates are physically isolated by the substrate body, improving the electrical interconnect stability of the device. In summary, the stacked units are electrically connected through interconnection structures, enabling the devices to be stacked in the vertical direction. This increases the integration of device units within a certain volume, thereby improving the volumetric power density of the devices.

[0015] The packaging method of the 3D stacked packaging structure provided by the technical solution of the present invention, which performs packaging through the above-mentioned 3D stacked packaging structure, also has the technical effects of the above-mentioned 3D stacked packaging structure, and will not be repeated here. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of the first substrate according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the second substrate according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the third substrate according to an embodiment of the present invention; Figures 4 to 5 This is a schematic diagram of each step in the packaging method of the 3D stacked packaging structure according to an embodiment of the present invention.

[0017] Explanation of reference numerals in the attached figures: 100, First substrate; 110, First metal structure; 120, First interconnect structure; 121, First pad; 122, First through-hole; 130, First slot; 200, Second substrate; 210, Second interconnect structure; 211, Second pad; 212, Second through-hole; 220, Second slot; 300, Third substrate; 310, Third interconnect structure; 311, Third pad; 312, Third via; 320, Third metal structure; 400, transducer chip; 401, particle incident surface of the transducer chip; 500, radioactive source thin film. Detailed Implementation

[0018] As described in the background section, poor electrical interconnection stability of devices, poor sealing of radiation sources, and low volumetric power density of devices are technical problems that need to be solved, which will be explained in detail below.

[0019] The low volumetric power density of the device is mainly affected by the integration method. Most nuclear batteries currently adopt a single-cell integration method, which mainly consists of a radioactive source thin film, a transducer (such as a silicon carbide transducer), and a packaging substrate. When the abundance, thickness, and size of the thin film are determined, the performance of the nuclear battery is already determined. The device performance is completely limited by the physical parameters of the radioactive source thin film.

[0020] The poor electrical interconnect stability of devices is mainly affected by the interconnection method. In traditional 3D stacking, leads are usually used to connect device units. On the one hand, as an introduction structure, leads need to be routed between substrates, which can easily lead to short circuits caused by lead crossing or contact. On the other hand, the lead material is fragile and is prone to breakage under high-frequency vibration and shock environments.

[0021] Poor sealing of the radiation source of the device is mainly affected by the packaging material and packaging method. On the one hand, the coefficient of thermal expansion (CTE) of the packaging material (such as ordinary PCB) and the transducer (silicon carbide) are quite different. When the ambient temperature changes or the nuclear battery itself decays and heats up, cyclic stress will be generated at the connection, which will cause the sealing layer to peel off or crack, thus causing the radiation source to leak. On the other hand, the lead connection method requires leaving channels for metal leads on the packaging shell. The existence of these physical apertures inherently reduces the sealing level of the structure.

[0022] To address the aforementioned technical problems, the present invention provides a packaging method for a 3D stacked packaging structure, wherein each stacked unit is vertically stacked through an interconnection structure to improve the volumetric power density of the device, while also improving the electrical interconnection stability and radiation source sealing of the device.

[0023] To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. Additionally, directional terms such as above, below, up, down, upward, downward, left, right, etc., are used relative to exemplary embodiments as they are shown in the figures, with upward or upper directions pointing towards the top of the corresponding figure and downward or lower directions pointing towards the bottom of the corresponding figure.

[0025] Please refer to Figures 1 to 3 The first substrate 100, the second substrate 200 and the third substrate 300 are prepared respectively.

[0026] Please refer to Figure 1The surface of the first substrate 100 has a plurality of first metal structures 110, and the first substrate 100 has a plurality of first interconnect structures 120 and a plurality of first slots 130 that penetrate the first substrate 100 along the thickness direction of the first substrate 100.

[0027] Please refer to the following: Figure 1 and Figure 4 Each first metal structure 110 surrounds a first slot 130, and a radioactive source film 500 is placed in each first slot 130.

[0028] In this embodiment, the thickness of the first substrate 100 is 10 μm to 500 μm.

[0029] In this embodiment, the first substrate 100 is made of ceramic material.

[0030] Specifically, the material of the first substrate 100 may include at least one of aluminum nitride, aluminum oxide, and silicon carbide.

[0031] In this embodiment, the first metal structure 110 is a copper layer, a nickel layer and a tin layer stacked sequentially from the surface of the first substrate 100.

[0032] In this embodiment, the first substrate 100 is made of ceramic material. The coefficient of thermal expansion of ceramic material is similar to that of the transducer chip. When the ambient temperature changes or the nuclear battery itself decays and generates heat, the integrity of the substrate structure is maintained, and the mechanical strength and reliability of the packaging structure are improved.

[0033] Specifically, the copper layer has a thickness of 1μm to 20μm, the nickel layer has a thickness of 0μm to 20μm, and the tin layer has a thickness of 1μm to 20μm.

[0034] Please continue to refer to this. Figure 1 The first interconnect structure 120 includes a plurality of first pads 121 and a plurality of first vias 122.

[0035] Among them, a number of first pads 121 are arranged in pairs, each pair of first pads 121 is located on two surfaces of the first substrate 100, each pair of first pads 121 corresponds to a first through hole 122, the first through hole 122 penetrates the first substrate 100 and the corresponding first pad 121, and the first through hole 122 is filled with conductive material.

[0036] Specifically, the conductive material can be tin.

[0037] Specifically, the method for forming the first substrate 100 may include: polishing and thinning a first ceramic substrate (not shown) to form an initial first substrate (not shown); forming a plurality of first interconnect structures 120 in the initial first substrate; after forming the plurality of first interconnect structures 120, forming a plurality of first metal structures 110 on the surface of the initial first substrate; after forming the plurality of first metal structures 110, forming a plurality of first slots 130 in the initial first substrate to form the first substrate 100.

[0038] Figure 2 This is a schematic diagram of the structure of the second substrate according to an embodiment of the present invention.

[0039] Please refer to Figure 2 The second substrate 200 has a plurality of second interconnect structures 210 and a second slot 220 extending through the second substrate 200 along the thickness direction of the second substrate 200, and the plurality of second interconnect structures 210 are distributed around the second slot 220.

[0040] Please refer to the following: Figure 2 and Figure 4 The second substrate 200 is located on the first substrate. The projections of all the first metal structures 110 and the first slots 130 on the surface of the second substrate 200 are located within the range of the second slots 220. A transducer chip 400 is placed in the second slot 220. The particle incident surface 401 of the transducer chip is arranged facing the radiation source film 500.

[0041] In this embodiment, the thickness of the second substrate 200 is 10μm to 500μm.

[0042] In this embodiment, the material of the second substrate 200 is ceramic.

[0043] Specifically, the material of the second substrate 200 may include at least one of aluminum nitride, aluminum oxide, and silicon carbide.

[0044] Please continue to refer to this. Figure 2 The second interconnect structure 210 includes a plurality of second pads 211 and a plurality of second vias 212.

[0045] Among them, a number of second pads 211 are arranged in pairs, each pair of second pads 211 is located on two surfaces of the second substrate 200, each pair of second pads 211 corresponds to a second through hole 212, the second through hole 212 penetrates the second substrate 200 and the corresponding second pad 211, and the second through hole 212 is filled with conductive material.

[0046] Specifically, the conductive material can be tin.

[0047] Specifically, the method for forming the second substrate 200 may include: polishing and thinning a second ceramic substrate (not shown) to form an initial second substrate (not shown); forming a plurality of second interconnect structures 210 in the initial second substrate; and after forming the plurality of second interconnect structures 210, forming a second cavity 220 in the initial second substrate to form the second substrate 200.

[0048] Figure 3 This is a schematic diagram of the structure of the third substrate 300 in an embodiment of the present invention.

[0049] Please refer to Figure 3 The surface of the third substrate 300 has a plurality of third metal structures 320, and the third substrate 300 has a plurality of third interconnect structures 310 that penetrate the third substrate 300 along the thickness direction of the third substrate 300.

[0050] Please refer to the following: Figure 3 and Figure 4 The third substrate 300 is located on the second substrate 200. The third metal structure 320 is arranged facing the transducer chip 400. Each third metal structure 320 covers a first slot 130 and a first metal structure 110 surrounding the first slot 130. Along the thickness direction of the second substrate 200, each second interconnect structure 210 is connected to a first interconnect structure 120 and a third interconnect structure 310 at both ends.

[0051] In this embodiment, the material of the third substrate 300 is ceramic.

[0052] Specifically, the material of the third substrate 300 may include at least one of aluminum nitride, aluminum oxide, and silicon carbide.

[0053] In this embodiment, the thickness of the third substrate 300 is 10μm to 500μm.

[0054] In this embodiment, the third metal structure 320 is a copper layer, a nickel layer and a tin layer stacked sequentially from the surface of the third substrate 300.

[0055] Specifically, the copper layer has a thickness of 1μm to 20μm, the nickel layer has a thickness of 0μm to 20μm, and the tin layer has a thickness of 1μm to 20μm.

[0056] Please continue to refer to this. Figure 3 The third interconnect structure 310 includes a plurality of third pads 311 and a plurality of third vias 312. The plurality of third pads 311 are arranged in pairs, and each pair of third pads 311 is located on two surfaces of the third substrate 300. Each pair of third pads 311 corresponds to a third via 312. The third via 312 penetrates the third substrate 300 and the corresponding third pad 311. The third via 312 is filled with conductive material.

[0057] Specifically, the conductive material can be tin.

[0058] Specifically, the method for forming the third substrate 300 may include: polishing and thinning a third ceramic substrate (not shown) to form an initial third substrate (not shown); forming a plurality of third interconnect structures 310 in the initial third substrate; and after forming the plurality of third interconnect structures 310, forming a plurality of third metal structures 320 on the surface of the initial third substrate to form the third substrate 300.

[0059] Please refer to the reference. Figure 4 and Figure 1 The transducer chip 400 is bonded to the first metal structure 110 of the first substrate 100; the radiation source film 500 is placed in a plurality of first slots 130 of the first substrate 100.

[0060] In this embodiment, the particle incident surface 401 of the transducer chip is bonded to the first metal structure 110 of the first substrate 100.

[0061] In this embodiment, the bonding process may include hot-press bonding.

[0062] Specifically, the bonding temperature is 100℃~400℃, and the bonding time is 10s~3600s.

[0063] Please continue to refer to this. Figure 4 The first substrate 100, the second substrate 200 and the third substrate 300 are stacked in sequence to form a stacked unit, and the particle incident surface 401 of the transducer chip is arranged facing the radiation source thin film 500.

[0064] In this embodiment, the process of forming the stacked units further includes: the first interconnect structure 120, the second interconnect structure 210 and the third interconnect structure 310 are connected by a conductive connection medium.

[0065] Specifically, the conductive connection medium may include solder paste.

[0066] Specifically, the method for forming a stacked unit may include: implanting solder paste onto the surfaces of a plurality of first metal structures 110 and a plurality of first pads 121 of a first substrate 100, implanting solder paste onto the surfaces of a plurality of second pads 211 of a second substrate 200, implanting solder paste onto the surfaces of a plurality of third metal structures 320 and a plurality of third pads 311 of a third substrate 300, and then sequentially stacking the first substrate 100, the second substrate 200 and the third substrate 300 with the solder paste implanted to form a stacked unit.

[0067] Specifically, methods for applying solder paste can include electroplating or printing.

[0068] Specifically, the process of forming stacked units can include integral welding process.

[0069] Please refer to Figure 5 Two stacked units are stacked and connected, with the two first substrates 100 of the two stacked units facing each other.

[0070] Specifically, the stacking connection process can include integral welding process.

[0071] Furthermore, the two stacking units are stacked together to form a stacking group consisting of a third substrate 300, a second substrate 200, a first substrate 100, a second substrate 200, and a third substrate 300 stacked sequentially from top to bottom. The stacking group can be stacked in the vertical direction to form a package structure that integrates more transducer chips and radiation source films.

[0072] In this embodiment, the first substrate 100 has a plurality of first metal structures 110 on its surface, and a plurality of first slots 130 extending through the first substrate 100 along its thickness direction, with each first metal structure 110 surrounding a first slot 130. The second substrate 200 has a plurality of second slots 220 extending through the second substrate 200 along its thickness direction. The projections of all the first metal structures 110 and first slots 130 on the surface of the second substrate 200 are located within the range of the second slots 220. The third substrate 3... The surface of the transducer chip 400 has several third metal structures 320. Each third metal structure 320 covers a first slot 130 and surrounds a first metal structure 110 around the first slot 130. The third metal structures 320 are disposed facing the transducer chip 400. The second substrate 200 is located on the first substrate 100, and the third substrate 300 is located on the second substrate 200. The transducer chip 400 is placed in the second slot 220. Therefore, the transducer chip 400 is electrically connected and fixed in the second slot 220 through the first metal structure 110 and the third metal structure 320. Since a radiation source film 500 is placed in each first slot 130, and the particle incident surface of the transducer chip 400 is disposed facing the radiation source film 500, the physical distance between the radiation source film 500 and the transducer chip 400 is shortened, reducing the loss of radiation particles during transmission and thus improving the transduction efficiency of the device. Since the stacked units are arranged in pairs and the two first substrates 100 are arranged facing each other, the transducer chip 400 is located in the second slot 220 of the upper and lower second substrates 200 respectively in the paired stacked units, and the radiation source film 500 is located in the first slot 130 between the two stacked units, realizing a self-supporting encapsulation structure that can improve the energy utilization rate of the radiation source. At the same time, sealing the radiation source in the first slot 130 located between the two stacked units can improve the sealing performance of the radiation source. Since the first substrate 100 has a plurality of first interconnect structures 120 penetrating the first substrate 100 along the thickness direction of the first substrate 100, the second substrate 200 has a plurality of second interconnect structures 210 penetrating the second substrate 200 along the thickness direction of the second substrate 200, and the plurality of second interconnect structures 210 are distributed around the second slot 220, and the third substrate 300 has a plurality of third interconnect structures 310 penetrating the third substrate 300 along the thickness direction of the third substrate 300, and each second interconnect structure 210 is connected to one first interconnect structure 120 and one third interconnect structure 310 at both ends along the thickness direction of the second substrate 200, the interconnect structure is integrated with the substrate body, improving the mechanical strength of the interconnect structure. Furthermore, the interconnect circuit between the substrates is physically isolated by the substrate body, improving the electrical interconnect stability of the device.In summary, the stacked units are electrically connected through interconnection structures, enabling the devices to be stacked in the vertical direction. This increases the integration of device units within a certain volume, thereby improving the volumetric power density of the devices.

[0073] Accordingly, the technical solution of the present invention also provides a 3D stacked packaging structure, please refer to the reference. Figures 1 to 3 as well as Figure 5 It includes a pair of stacked units, in which two first substrates 100 are arranged facing each other.

[0074] The stacking unit includes: a first substrate 100, a second substrate 200 and a third substrate 300.

[0075] In this embodiment, the surface of the first substrate 100 has a plurality of first metal structures 110, and the first substrate 100 has a plurality of first interconnect structures 120 and a plurality of first slots 130 that penetrate the first substrate along the thickness direction of the first substrate. Each first metal structure 110 surrounds a first slot 130, and a radiation source thin film 500 is placed in each first slot 130.

[0076] Specifically, the material of the first substrate 100 includes at least one of aluminum nitride, aluminum oxide, and silicon carbide.

[0077] Specifically, the thickness of the first substrate 100 is 10μm to 500μm.

[0078] Specifically, the first metal structure 110 consists of a copper layer, a nickel layer, and a tin layer stacked sequentially from the surface of the first substrate 100.

[0079] In this embodiment, the second substrate 200 is located on the first substrate. The second substrate 200 has a plurality of second interconnect structures 210 and a second slot 220 that penetrate the second substrate 200 along the thickness direction of the second substrate 200. The projections of all the first metal structures 110 and the first slots 130 on the surface of the second substrate 200 are located within the range of the second slot 220. A transducer chip 400 is placed in the second slot 220. The particle incident surface of the transducer chip 400 is arranged facing the radiation source film 500. The plurality of second interconnect structures 210 are distributed around the second slot 220.

[0080] Specifically, the material of the second substrate 200 includes at least one of aluminum nitride, aluminum oxide, and silicon carbide.

[0081] Specifically, the thickness of the second substrate 200 is 10μm to 500μm.

[0082] In this embodiment, the third substrate 300 is located on the second substrate 200. The surface of the third substrate 300 has a plurality of third metal structures 320, and the third substrate 300 has a plurality of third interconnect structures 310 that penetrate the third substrate 300 along the thickness direction of the third substrate 300. The third metal structures 320 are arranged facing the transducer chip 400. Each third metal structure 320 covers a first slot 130 and a first metal structure 110 surrounding the first slot 130. Along the thickness direction of the second substrate 200, each second interconnect structure 210 is connected to a first interconnect structure 120 and a third interconnect structure 310 at both ends.

[0083] Specifically, the material of the third substrate 300 includes at least one of aluminum nitride, aluminum oxide, and silicon carbide.

[0084] Specifically, the thickness of the third substrate 300 is 10μm to 500μm.

[0085] Specifically, the third metal structure 320 consists of a copper layer, a nickel layer, and a tin layer stacked sequentially from the surface of the third substrate 300.

[0086] Specifically, the copper layer has a thickness of 1μm to 20μm, the nickel layer has a thickness of 0μm to 20μm, and the tin layer has a thickness of 1μm to 20μm.

[0087] Specifically, the materials, forming process, working principle, specific implementation method and beneficial effects of the 3D stacked packaging structure in the embodiments of the present invention can be found in the packaging method of the 3D stacked packaging structure in the embodiments of the present invention, and will not be repeated here.

[0088] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A 3D stacked packaging structure, characterized in that, include: Stacked units arranged in pairs; The stacking unit includes: a first substrate having a plurality of first metal structures on its surface, and having a plurality of first interconnect structures and a plurality of first slots extending through the first substrate along its thickness direction, each first metal structure surrounding a first slot, and a radiation source film placed in each first slot; a second substrate located on the first substrate, having a plurality of second interconnect structures and a second slot extending through the second substrate along its thickness direction, the projections of all the first metal structures and the first slots on the surface of the second substrate being within the range of the second slots, a transducer chip placed in the second slot, the particle incident surface of the transducer chip being disposed facing the radiation source film, and a plurality of second interconnect structures being distributed around the second slots; A third substrate is located on the second substrate. The surface of the third substrate has a plurality of third metal structures, and the third substrate has a plurality of third interconnect structures that penetrate the third substrate along the thickness direction of the third substrate. The third metal structures are arranged facing the transducer chip. Each third metal structure covers a first slot and a first metal structure surrounding the first slot. Along the thickness direction of the second substrate, each end of the second interconnect structure is connected to one first interconnect structure and one third interconnect structure, respectively. In the paired stacked units, the two first substrates are arranged facing each other.

2. The packaging structure as described in claim 1, characterized in that, The interconnection structure includes: The first interconnect structure includes a plurality of first pads and a plurality of first vias. The plurality of first pads are arranged in pairs. Each pair of first pads is located on two surfaces of the first substrate. Each pair of first pads corresponds to one first via. The first via penetrates the first substrate and the corresponding first pad. The first via is filled with conductive material. The second interconnect structure includes a plurality of second pads and a plurality of second vias. The plurality of second pads are arranged in pairs, and each pair of second pads is located on two surfaces of the second substrate. Each pair of second pads corresponds to a second via. The second vias penetrate the second substrate and the corresponding second pads. The second vias are filled with conductive material. The third interconnect structure includes a plurality of third pads and a plurality of third vias. The plurality of third pads are arranged in pairs. Each pair of third pads is located on two surfaces of the third substrate. Each pair of third pads corresponds to one third via. The third via penetrates the third substrate and the corresponding third pad. The third via is filled with conductive material. The first interconnect structure, the second interconnect structure, and the third interconnect structure are connected by a conductive connection medium.

3. The packaging structure as described in claim 2, characterized in that, The material of the first substrate includes at least one of aluminum nitride, aluminum oxide, and silicon carbide; the material of the second substrate includes at least one of aluminum nitride, aluminum oxide, and silicon carbide; and the material of the third substrate includes at least one of aluminum nitride, aluminum oxide, and silicon carbide.

4. The packaging structure as described in claim 1, characterized in that, The thickness of the first substrate is 10 μm to 500 μm, the thickness of the second substrate is 10 μm to 500 μm, and the thickness of the third substrate is 10 μm to 500 μm.

5. The packaging structure as described in claim 1, characterized in that, The first metal structure is a copper layer, a nickel layer and a tin layer stacked sequentially from the surface of the first substrate, and the third metal structure is a copper layer, a nickel layer and a tin layer stacked sequentially from the surface of the third substrate.

6. The packaging structure as described in claim 5, characterized in that, The copper layer has a thickness of 1 μm to 20 μm, the nickel layer has a thickness of 0 μm to 20 μm, and the tin layer has a thickness of 1 μm to 20 μm.

7. A packaging method for a 3D stacked packaging structure, characterized in that, Forming a 3D stacked packaging structure as described in any one of claims 1 to 6, comprising: The first substrate, the second substrate, and the third substrate are respectively prepared; The transducer chip is bonded to the first metal structure of the first substrate; The radioactive source film is placed in the plurality of first slots of the first substrate; The first substrate, the second substrate, and the third substrate are stacked sequentially to form a stacked unit, and the particle incident surface of the transducer chip is arranged facing the radiation source film. The two stacked units are stacked and connected together, with the two first substrates of the two stacked units facing each other.

8. The packaging method as described in claim 7, characterized in that, The bonding includes thermocompression bonding, the bonding temperature is 100℃~400℃, and the bonding time is 10s~3600s.

9. The packaging method as described in claim 7, characterized in that, The method for preparing the first substrate includes: polishing and thinning a first ceramic substrate to form an initial first substrate; forming a plurality of first interconnect structures in the initial first substrate; after forming the plurality of first interconnect structures, forming a plurality of first metal structures on the surface of the initial first substrate; and after forming the plurality of first metal structures, forming a plurality of first slots in the initial first substrate to form the first substrate. The method for preparing the second substrate includes: polishing and thinning a second ceramic substrate to form an initial second substrate; forming a plurality of second interconnect structures in the initial second substrate; and after forming the plurality of second interconnect structures, forming a second cavity in the initial second substrate to form the second substrate. The method for preparing the third substrate includes: polishing and thinning a third ceramic substrate to form an initial third substrate; forming a plurality of third interconnect structures within the initial third substrate; and after forming the plurality of third interconnect structures, forming a plurality of third metal structures on the surface of the initial third substrate to form the third substrate.

10. The packaging method as described in claim 7, characterized in that, The stacking connection process includes an integral welding process.

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