Satellite-borne high-voltage direct-current solid-state circuit breaker and spacecraft power distribution system
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHENGDU UNIVERSITY OF TECHNOLOGY
- Filing Date
- 2026-04-17
- Publication Date
- 2026-07-14
Smart Images
Figure CN122393856A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of spaceborne high-voltage systems, and in particular to a spaceborne high-voltage DC solid-state circuit breaker and a spacecraft power distribution system. Background Technology
[0002] The spaceborne high-voltage system is the core support for spacecraft to achieve high-power payload power supply and long-distance energy transmission. Its working environment is filled with galactic cosmic rays, solar cosmic rays and charged particles from the Earth's radiation belts. These particles can cause single-event effects, total ionization dose effects and displacement damage effects in electronic devices, seriously threatening the reliability of the power distribution system.
[0003] Traditional mechanical circuit breakers have inherent defects in the vacuum environment of space, such as difficulty in extinguishing electric arcs, slow response speed (millisecond level), and large size and weight, and can no longer meet the requirements of high efficiency, speed and radiation resistance for power distribution protection of the new generation of spacecraft.
[0004] Domestic and international research indicates that silicon carbide MOSFETs (SiC MOSFETs) possess good resistance to total radiation dose, typically reaching 3000 Gy. According to available data, experimental ion... In single-particle experiments, LET in Si represents the average energy deposited per unit mass thickness of an incident particle in silicon (Si) material, which is LET = 75.4 MeV·cm⁻¹. 2 / mg; According to the information found, test ions were used. During single-event experiments, a higher LET (Leakage Tolerance) makes it easier to deposit sufficient charge in the high-field region, triggering local avalanche, parasitic transistor conduction, or thermal runaway. The test subjects were 1200V SiS MOSFET products already released domestically and internationally, focusing on the 200V-300V drain-source voltage region. The test results showed that SiS MOSFETs can be used normally. Currently, 600V spaceborne high-voltage scenarios place higher demands on the radiation resistance and voltage withstand capabilities of circuit breakers. A single SiS MOSFET cannot simultaneously meet the requirements of radiation redundancy and high-voltage operation; therefore, multi-MOSFET series topologies have become the mainstream choice.
[0005] However, in series applications, issues such as differences in device parasitic parameters and asynchronous drive pulses can easily lead to voltage distribution imbalances, resulting in localized overvoltage breakdown. To address this problem, existing solutions mainly include active voltage equalization techniques such as active delay regulation, active gate voltage synchronization, and gate voltage and current compensation, as well as passive voltage equalization methods using static equalization resistors. However, active voltage equalization requires the design of complex gate and power supply circuits, significantly increasing system complexity and cost; simple passive voltage equalization methods struggle to cope with dynamic voltage imbalances during switching transients, resulting in limited overvoltage suppression. Furthermore, existing topologies often employ multi-gate drive architectures, further increasing hardware integration difficulty and on-orbit maintenance risks, thus limiting their large-scale application in spaceborne scenarios. Summary of the Invention
[0006] The purpose of this application is to provide a spaceborne high-voltage DC solid-state circuit breaker and a spacecraft power distribution system that can achieve efficient drive and improve the response speed of overcurrent protection while reducing cost and complexity.
[0007] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides a spaceborne high-voltage DC solid-state circuit breaker, including: a main power circuit, a single-gate drive circuit, a capacitively coupled drive network, a static voltage equalization and gate protection network, a dynamic voltage buffer network, and an overcurrent protection and control circuit. The main power circuit includes a first silicon carbide MOSFET, a second silicon carbide MOSFET, a third silicon carbide MOSFET, and a fourth silicon carbide MOSFET connected in series. The output terminal of the single-gate drive circuit is electrically connected to the gate of the fourth silicon carbide MOSFET. The capacitive coupling drive network is used to drive the gates of the first silicon carbide MOSFET, the second silicon carbide MOSFET, and the third silicon carbide MOSFET through three sets of coupling capacitors; the first end of each coupling capacitor is connected to the gate of the corresponding silicon carbide MOSFET, and the second end of each coupling capacitor is connected to the source of the adjacent next-stage silicon carbide MOSFET. The static voltage equalization and gate protection network is connected in parallel between the drain and source of each silicon carbide MOSFET. The dynamic voltage buffer network is connected in parallel between the drain and source of each silicon carbide MOSFET to balance the voltage of the silicon carbide MOSFET. The overcurrent protection and control circuit is coupled to the current path of the main power circuit and is used to detect the current of the main power circuit in real time. When an overcurrent condition is detected, a shutdown control signal is generated and sent to the control input terminal of the single-gate drive circuit to control the shutdown of the main power circuit.
[0008] Optionally, the static voltage equalization and gate protection network includes: a static voltage equalization resistor connected in parallel and a gate protection circuit; The static voltage equalization resistor and the gate protection circuit are respectively connected in parallel between the drain and source of each silicon carbide MOSFET in the main power circuit.
[0009] Optionally, the gate protection circuit includes: a first Zener diode and a second Zener diode connected in reverse series.
[0010] Optionally, the dynamic voltage buffer network includes: a buffer capacitor, a buffer resistor, and a buffer diode; The anode of the buffer diode and one end of the buffer resistor are both connected to the source of the silicon carbide MOSFET. The cathode of the buffer diode is connected to one end of the buffer capacitor and the other end of the buffer resistor, respectively. The other end of the buffer capacitor is connected to the drain of the silicon carbide MOSFET.
[0011] Optionally, the overcurrent protection and control circuit includes: a current sampling resistor, a signal conditioning module, a threshold comparison module, a latch module, and a logic control module; The current sampling resistor is connected in series with the ground terminal or the low potential side of the main power circuit; The signal conditioning module is used to amplify and filter out switching noise in the voltage across the current sampling resistor; The threshold comparison module is used to compare the conditioned voltage signal with a preset overcurrent threshold, detect the overcurrent state when the limit is exceeded, and output a switching level. The latch module is connected to the threshold comparison module and is used to receive the transition level and output the latch signal; The logic control module is used to receive the latch signal of the latch module and the external on / off control pulse signal, and output a drive enable signal to the single gate drive circuit after performing a logical AND operation.
[0012] Optionally, the latch module is also connected to a reset circuit; The reset circuit is used to clear the latch signal after the fault condition is cleared in order to restore the normal drive control of the circuit breaker's reset circuit.
[0013] Optionally, the signal conditioning module, threshold comparison module, latch module, and logic control module integrate the INA300 overcurrent protection chip.
[0014] Optionally, the resistance of the current sampling resistor is 5mΩ.
[0015] Optionally, the logic control module includes: an AND gate and a driver chip.
[0016] Secondly, this application provides a spacecraft power distribution system, including: the aforementioned spaceborne high-voltage DC solid-state circuit breaker.
[0017] According to the specific embodiments provided in this application, this application has the following technical effects: This application provides a spaceborne high-voltage DC solid-state circuit breaker and a spacecraft power distribution system. It enhances the system's radiation redundancy and high-voltage withstand capability through a four-phase silicon carbide MOSFET series topology. The main topology is designed based on an enhanced single-gate drive voltage-balanced stacked structure, achieving efficient drive while reducing cost and complexity. Simultaneously, a fast-response overcurrent protection mechanism is constructed by coupling overcurrent protection and control circuits with the current path of the main power circuit. This application solves the problems of difficult arc extinguishing, slow response, large size, and poor radiation resistance in spaceborne high-voltage scenarios, providing a highly radiation-resistant and fast-response power distribution protection scheme. It can achieve μs-level shutdown under 600V conditions and provides further possibilities for future spaceborne high-voltage applications. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic diagram of a spaceborne high-voltage DC solid-state circuit breaker in one embodiment of this application; Figure 2 This is a schematic diagram of the conduction stage of a silicon carbide MOSFET in a spaceborne high-voltage DC solid-state circuit breaker. Figure 3 This is a schematic diagram of the first stage of the conduction state; Figure 4 This is a schematic diagram of the second-stage conduction state; Figure 5 This is a schematic diagram of the three-stage conduction state; Figure 6 This is a schematic diagram of the four-stage conduction state; Figure 7 This is a schematic diagram of the equivalent model based on silicon carbide MOSFETs corresponding to Phase 3; Figure 8 This is a schematic diagram of the turn-off phase of the silicon carbide MOSFET in a spaceborne high-voltage DC solid-state circuit breaker. Figure 9 This is a schematic diagram of the five-stage shutdown process; Figure 10 This is a schematic diagram of the six-stage shutdown. Figure 11 This is a schematic diagram of the seven-stage shutdown; Figure 12 This is a schematic diagram of the eight stages; Figure 13 Simulation results for 600V: Schematic diagram of current id and Vds during conduction; Figure 14 Simulation results for 600V: Schematic diagram of current id and Vds during the turn-off process; Figure 15 This is a schematic diagram of the simulation results at 600V; Figure 16 This is a schematic diagram of the total voltage simulation results for a DC solid-state circuit breaker. Figure 17 This is a schematic diagram of an overcurrent protection and control circuit. Figure 18 Oscilloscope diagram showing the turn-on and turn-off of a silicon carbide MOSFET. Detailed Implementation
[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0021] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0022] In one exemplary embodiment, such as Figure 1 As shown, a spaceborne high-voltage DC solid-state circuit breaker is provided. The circuit breaker includes: a main power circuit, a single-gate drive circuit, a capacitively coupled drive network, a static voltage equalization and gate protection network, a dynamic voltage buffer network, and an overcurrent protection and control circuit. The main power circuit includes a first silicon carbide MOSFET (Q1), a second silicon carbide MOSFET (Q2), a third silicon carbide MOSFET (Q3), and a fourth silicon carbide MOSFET (Q4) connected in series. According to the data, the 1200V silicon carbide MOSFET operates in the range of 200V under the radiation of single-event effect and total dose effect. In order to cope with the use of 600V bus high voltage in high radiation environment and to reserve space, the number of silicon carbide MOSFETs is 4. The output terminal of the single-gate drive circuit is electrically connected to the gate of the fourth silicon carbide MOSFET. The capacitive coupling drive network is used to drive the gates of the first silicon carbide MOSFET, the second silicon carbide MOSFET, and the third silicon carbide MOSFET through three sets of coupling capacitors (Cai, i=1, 2, 3); the first end of each coupling capacitor is connected to the gate of the corresponding silicon carbide MOSFET, and the second end of each coupling capacitor is connected to the source of the adjacent next-stage silicon carbide MOSFET. The static voltage equalization and gate protection network is connected in parallel between the drain and source of each silicon carbide MOSFET. The dynamic voltage buffer network is connected in parallel between the drain and source of each silicon carbide MOSFET to balance the voltage of the silicon carbide MOSFET. The overcurrent protection and control circuit is coupled to the current path of the main power circuit and is used to detect the current of the main power circuit in real time. When an overcurrent condition is detected, a shutdown control signal is generated and sent to the control input terminal of the single-gate drive circuit to control the shutdown of the main power circuit.
[0023] Specifically, the static voltage equalization and gate protection network includes: parallel static voltage equalization resistors (Rsi, i=1, 2, 3, 4) and a gate protection circuit; The static voltage equalization resistor and the gate protection circuit are respectively connected in parallel between the drain and source of each silicon carbide MOSFET in the main power circuit.
[0024] The gate protection circuit includes: a first Zener diode (Dai, i = 1, 2, 3, 4) and a second Zener diode (Dbi, i = 1, 2, 3, 4) connected in reverse series.
[0025] The dynamic voltage buffer network includes: a buffer capacitor (Cdi, i = 1, 2, 3, 4), a buffer resistor (Rdi, i = 1, 2, 3, 4), and a buffer diode (Ddi, i = 1, 2, 3, 4). The anode of the buffer diode and one end of the buffer resistor are both connected to the source of the silicon carbide MOSFET. The cathode of the buffer diode is connected to one end of the buffer capacitor and the other end of the buffer resistor, respectively. The other end of the buffer capacitor is connected to the drain of the silicon carbide MOSFET.
[0026] like Figure 2 As shown, the conduction process of a spaceborne high-voltage DC solid-state circuit breaker can be divided into four stages, from stage one to stage four, and as follows: Figures 3-6 As shown; Figure 2As shown, stage one is [t0-t1]. During this stage, it can be seen that the single-gate drive circuit (gate driver) has not yet received a turn-on signal, and the gate-source voltage (red) Vgs4 of Q4 is equal to 0V. Therefore, as... Figure 3 As shown, by appropriately setting the Zener voltage of Dbi and the value of Rsi, Vgsi (i=1—3) is also equal to - (The voltage of the Zener diode Dbi), and the drain-source voltage Vgsi of Qi is in a static equilibrium state. Therefore, the spaceborne high-voltage DC solid-state circuit breaker is in a reliable closed state, but since the static voltage division of Q2-Q4 depends on Rsi and The static voltage division of Q1 depends on Rs1, so after voltage balance, the voltage of Q1 is slightly lower than that of Q2-Q4.
[0027] like Figure 2 As shown, stage two is [t1-t2]. At t1, the single-gate drive circuit switches to 18V. At this time, Vgs4 starts rising from 0V, charging Cgs of Q4 until it reaches the Miller plateau. After reaching the Miller plateau, it charges Cgd until it leaves the Miller plateau, continuing to charge Cgs until it reaches the drive voltage of 18V. When the Miller plateau ends, Vgs4 drops to its minimum value. When Q4 enters the saturation region, if no clamping circuit is configured, voltage imbalance will occur because Qi (i=1-3) is still in the cutoff region. For example... Figure 4 As shown, the load current will flow through Cdi (i=1-3).
[0028] like Figure 2 As shown, stage three is [t2-t3], during which the load current increases, and Vds4 begins to decrease, forming a new current loop on the gate side of Q3, as follows. Figure 5 As shown. To estimate The analysis during this transient period is based on an equivalent model of a silicon carbide MOSFET, such as... Figure 7 As shown, the following relationship exists: ; Where igd4 and ids4 represent the currents flowing through the drain-source capacitance Cgd4 and Miller capacitance Cds4, respectively, ig3 represents the gate current flowing through Rg3, Cin3 represents the gate capacitance of Q3, and iM4 represents the channel current of Q4. By introducing the conductance parameter GM and the threshold voltage Vth, the following relationship is obtained: ; ; ; Solving for the given information - ; From the above formula, we can see that The rise in Vgs3 is related to the fact that by setting the value of the coupling capacitor Ca3, Vgs3 will eventually be fixed at a specific voltage value. Once Q3 enters the saturation region, the current flowing through Cd3 will be diverted to Q3, resulting in an increase in the drain current of Q3.
[0029] like Figure 2 As shown, stage four is [t3–t5]. At time t3, id3 reaches the load current state, and the silicon carbide MOSFET series structure switches to... Figure 6 The state shown indicates that Vds3 subsequently decreases. Using the same method, the gate loop and power loop of Qi (i=1–3) are similar to those of Q4. Afterwards, Vds2 also decreases, followed by Vds1, at which point the solution can be obtained. (i=1–3): - - ; It can be seen that the rate of decrease of Vgs1 in Q1 is slightly faster than that in Q2-Q4. At time t5, IL has completely flowed through Qi (i=1-4), and Vgs4 reaches 18V, which means that the opening process of the DC solid-state circuit breaker is over.
[0030] like Figure 8 As shown, stage five is [t6—t7]. At time t6, the DC solid-state circuit breaker is in the conducting state as follows: Figure 9 As shown. Subsequently, the gate driver receives a turn-off signal. Discharge begins, the drive voltage changes from 18V to 0V, and Q4 reaches the Miller plateau at time t7. Discharge begins, Vds4 starts to rise, and at the end of the Miller plateau, Vds4 rises to its limit. Continue discharging.
[0031] like Figure 8 As shown, stage six is [t7-t8]. At time t8, Q3 enters the Miller plateau, and Vds3 begins to rise. As the Vgs4 voltage decreases, Q4 enters the saturation region from the linear region, thus triggering the gate discharge phenomenon of Q3, as shown... Figure 10 As shown. By setting the Zener voltage of Dbi, Vgs3 is ultimately constrained to a voltage level of -5V.
[0032] like Figure 8 As shown, stage seven is [t8—t9], where the rise of Vds3 lags behind Vds4. The rise slope of Vds3 can be estimated using the previous formula, which will create a current loop on the gate side of Q2. When Vds4 reaches its limit (i.e., Vdc / 4), the load current will flow through Cd4 instead of Q4, as... Figure 11As shown, since Cd4 can be considered a voltage source, Vds4 will no longer continue to rise, thus avoiding voltage imbalance.
[0033] like Figure 8 As shown, stage eight is [t9—t11]: At time t9, Q2 enters the Miller plateau, Vds2 begins to rise, and its rise rate lags behind Vds3. At this time, the circuit breaker will switch to Figure 12 The state is shown. Since the voltage imbalance is limited to within Vdc / 4, therefore... Voltage imbalance is thus avoided. After time t10, Vds1 will also begin to rise, and the rising slopes of Vds1 and Vds2 can be estimated using the previous formula. Therefore, voltage balance of the circuit breaker is well achieved. Finally, the circuit breaker's turning-off process is completed at time t11.
[0034] Based on the above analysis, a single voltage-balanced gate drive circuit containing four silicon carbide MOSFETs connected in series was simulated and verified in LTspice simulation software. The silicon carbide MOSFETs were commercially available NTH4L013N120M3S (1200V / 151A), and their LTspice model was provided by their manufacturer, Onsemi.
[0035] 1) Parameter design of static voltage equalization and gate protection network The parameter design references the datasheet for NTH4L013N120M3S. The recommended operating gate-source voltage is -10 / +22 V, so Vcc is set to 18V. To reduce gate oscillation, it is recommended that Rg1, Rg2, Rg3, and Rg4 all be 10Ω. With a drain-source voltage Vds of 1200 V, the typical drain current is 100μA; therefore, the turn-off equivalent resistance is set to 1.2 MΩ.
[0036] Therefore, in order to balance Vds1, Vds2, Vds3, and Vds4 in steady state, considering power dissipation, Rs1, Rs2, Rs3, and Rs4 are set to 100kΩ, which is less than one-tenth of the equivalent resistance in the off state. In addition, there are some other component parameters that are quite important in our design, which will be introduced below.
[0037] To prevent mis-conduction of Q1-Q3 during static balancing, a second Zener diode is used. The voltage is set to 5V to ensure that the gate-source voltage of Q1-Q3 is -5V during static turn-off, and a first Zener diode is also included. It is 18V, protecting the gate and source when on.
[0038] 2) Coupling capacitor parameter settings Because the gate charge of Q3 during the turn-on process is almost entirely composed of... Provided, therefore in the off state The stored charge should be greater than the total gate charge Qg of Q3, that is... ; The typical Qg of NTH4L013N120M3S at Vds = 800 V, id = 75A, and Vgs = -3 / 18V is 254 nC. According to the above formula, Ca3 should be greater than 1.69 nF. Here, Ca3 is set to 1.8 nF because a larger Ca3 will lead to a longer discharge or charge time during switching transients. Ca1 and Ca2 are also set to 1.8 nF.
[0039] 3) RCD buffer circuit parameter design In practical applications, since Cdi cannot be increased indefinitely (otherwise it would also lead to excessive size), specific design standards need to be set. When Vds4 reaches its limit, instead of forcibly clamping Vds4, it is better to allow a larger Cd4 value to decay naturally, which can effectively slow down the voltage rise process. Figure 7 Adding the Cd4 branch allows you to... The expression simplifies to: - ; Then, after the turn-off time toff, a further increment of Vds4 is expected to be a small value ΔV, which will lead to voltage imbalance. It can be described as follows: ; Cd4 can be selected together with the same Cdi (i=1-3). Regarding the selection of the buffer capacitance (Cdi, i=1,2,3,4), the equivalent discharge model of the buffer capacitor and buffer resistor in the on-state is the natural response of the RC circuit. The voltage drop for (i=1–4) is relatively small, thus allowing for further simplification. Based on The same principle applies after restoring to Vlim (limit voltage). Within a switching cycle, this relationship is as follows: , i = 1-4; Therefore, Rdi is selected. Use 500nF and Rdi = 10kΩ.
[0040] Next, the circuit will be simulated under 600V / 30A conditions to analyze the Vds and iL waveforms during the turn-on and turn-off processes.
[0041] (1) 600V / 30A conduction stage Under the condition of VDC=600V, the current id flowing through the series branch during the conduction process, and the drain-source voltages Vds1, Vds2, Vds3, and Vds4 are as follows: Figure 13 As shown, the green curve is Vds4, the blue curve is Vds3, the red curve is Vds2, and the cyan curve is Vds1.
[0042] like Figure 13 As shown, the four silicon carbide MOSFETs can conduct normally under 600V conditions. The conduction process can be completed without significant voltage imbalance.
[0043] (2) 600V / 30A shutdown stage Under the condition of VDC=600V, the current id flowing through the series branch during the turn-off process, and the drain-source voltages Vds1, Vds2, Vds3, and Vds4. For example... Figure 14 As shown, the green curve is Vds4, the blue curve is Vds3, the red curve is Vds2, and the cyan curve is Vds1.
[0044] like Figure 14 As shown, the four silicon carbide MOSFETs can be turned off normally under 600V / 30A conditions, and the turn-off response time is 0.1μs. Therefore, the turn-off process can be completed without significant voltage imbalance.
[0045] like Figure 15 As shown, when a pulse of 18V driving voltage is applied to the lower transistor, Q1-Q3 are synchronously turned on and off through coupling capacitors. Vgsi (i=2,3,4) is 8-9V when it is turned on.
[0046] like Figure 16 As shown, the balanced voltage is normal before and after conduction, each silicon carbide MOSFET is 150V, the load current reaches 30A and then turns off, the turn-off time is 0.1μs, the total voltage has no spikes, and the main topology performance of the circuit breaker is excellent.
[0047] The overcurrent protection and control circuit includes: a current sampling resistor (L1), a signal conditioning module, a threshold comparison module, a latch module, and a logic control module; The current sampling resistor is connected in series with the ground terminal or the low potential side of the main power circuit; The signal conditioning module is used to amplify and filter out switching noise in the voltage across the current sampling resistor; The threshold comparison module is used to compare the conditioned voltage signal with a preset overcurrent threshold, detect the overcurrent state when the limit is exceeded, and output a switching level. The latch module is connected to the threshold comparison module and is used to receive the transition level and output the latch signal; The logic control module is used to receive the latch signal of the latch module and the external on / off control pulse signal, and output a drive enable signal to the single gate drive circuit after performing a logical AND operation.
[0048] To quickly restore normal operation, the latch module is also connected to a reset circuit; The reset circuit is used to clear the latch signal after the fault condition is cleared in order to restore the normal drive control of the circuit breaker's reset circuit.
[0049] The signal conditioning module, threshold comparison module, latching module, and logic control module integrate the INA300 overcurrent protection chip.
[0050] The logic control module includes: AND gates and driver chips.
[0051] like Figure 17 As shown, a 5mΩ sampling resistor is connected in series at the ground terminal. An instrumentation amplifier is used to amplify the sampled voltage. Due to noise interference from the switching transistor, a filtering circuit is required. A threshold is set by a comparator for comparison. If an overcurrent occurs, the comparator output level will be pulled low. To avoid the comparator repeatedly switching due to hysteresis, the low level after the overcurrent is latched by a latch signal. Then, the control signal is passed through an AND gate to give a drive signal to the driver chip. The output signal of the driver chip finally controls the Q4 to turn on and off to realize the on and off of the main topology switch.
[0052] In practical applications, the INA300 overcurrent protection chip (integrating a sampling voltage amplifier, threshold comparator, and latch) is directly used. When there is no overcurrent, it outputs a high level of 5V through open drain; after an overcurrent, it outputs a low level of 0V and latches it. The comparator output voltage and the pulse voltage pass through an AND gate. When there is no overcurrent, the AND gate outputs a high level, driving the chip. After an overcurrent, even if the pulse is high, the AND gate will output a low level, meaning the chip will not operate, thus achieving overcurrent protection. The sampling voltage is filtered for noise interference by an RC filter circuit, and a reset button is added to the latch terminal of the INA300 overcurrent protection chip.
[0053] Simulations showed that the four silicon carbide MOSFETs exhibited uniform voltage division and effectively suppressed total voltage spikes during turn-off, achieving turn-off in the μs range. Therefore, their performance was verified through physical testing. The experimental platform used a 4mH air-core inductor as the load port and a 600V DC power supply as the voltage port. Pulses were input via a signal generator, and the switching frequency was 2333Hz to simulate the circuit breaker's on / off process. The four MOSFETs were connected in series, with each MOSFET connected in parallel with test points. The on / off process of each MOSFET was observed using an oscilloscope.
[0054] During the turn-on and turn-off processes of Q1-Q4, the voltage equalization is stable and normal. Under a total voltage of 600V, each silicon carbide MOSFET has an equal voltage of 150V, and there is no obvious voltage spike during the turn-off process. A μs-level turn-off can be achieved when the load current rises to approximately 28A, with 28A being the set threshold. When the driver chip is not controlled by a comparator, turn-off is achieved within 225μs based on the current, with a maximum current of 31.7083A. The comparator output detects overcurrent early and achieves turn-off, thus verifying the overcurrent protection logic. After using a comparator to control the driver chip, turn-off is achieved within 200μs based on the current, with a maximum current of 28.6250A, and turn-off is achieved after 200μs. With overcurrent protection added, even with a longer pulse conduction time, turn-off can be controlled within 200μs, and the maximum current is controlled at 28A. Repeated attempts consistently maintain the current at 28A, thus achieving overcurrent protection. At room temperature, the bus voltage is boosted to 600V, and a pulse signal is sent via a function generator. The drain-source voltage (Vds) and drain-source current (id) waveforms of the SiC MOSFET are recorded using an oscilloscope. This application achieves static voltage balance. Due to the voltage-equalizing resistor and the high-voltage power supply, the high-side MOSFET voltage first rises to the equalizing voltage value and then remains stable. Subsequently, the low-side MOSFET reaches the equalizing voltage value of 150V. The drain current rises to 28A and then quickly turns off. During the startup of the switching transistor, there is a significant spike due to noise interference. After turn-off, the spike is effectively suppressed, and the voltage distribution gradually tends to balance as the bus voltage increases. The drain current rises approximately linearly. During the turn-off phase at 600V, the overvoltage spike of Q1 to Q4 is 722.5V, and the current fall time is 1.85μs, demonstrating good performance. The overcurrent protection chip turns off early, and the threshold current of 28A achieves overcurrent protection. Figure 18 The conduction and turn-off diagrams of a single silicon carbide MOSFET can be seen. The peak voltage is within 150V, which is consistent with the simulation results. The current is around 28A due to the overcurrent protection chip.
[0055] In one exemplary embodiment, a spacecraft power distribution system is provided, including the aforementioned onboard high-voltage DC solid-state circuit breaker.
[0056] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0057] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A spaceborne high-voltage DC solid-state circuit breaker, characterized in that, include: Main power circuit, single-gate drive circuit, capacitively coupled drive network, static voltage equalization and gate protection network, dynamic voltage buffer network, and overcurrent protection and control circuit; The main power circuit includes a first silicon carbide MOSFET, a second silicon carbide MOSFET, a third silicon carbide MOSFET, and a fourth silicon carbide MOSFET connected in series. The output terminal of the single-gate drive circuit is electrically connected to the gate of the fourth silicon carbide MOSFET. The capacitive coupling drive network is used to drive the gates of the first silicon carbide MOSFET, the second silicon carbide MOSFET, and the third silicon carbide MOSFET through three sets of coupling capacitors; the first end of each coupling capacitor is connected to the gate of the corresponding silicon carbide MOSFET, and the second end of each coupling capacitor is connected to the source of the adjacent next-stage silicon carbide MOSFET. The static voltage equalization and gate protection network is connected in parallel between the drain and source of each silicon carbide MOSFET. The dynamic voltage buffer network is connected in parallel between the drain and source of each silicon carbide MOSFET to balance the voltage of the silicon carbide MOSFET. The overcurrent protection and control circuit is coupled to the current path of the main power circuit and is used to detect the current of the main power circuit in real time. When an overcurrent condition is detected, a shutdown control signal is generated and sent to the control input terminal of the single-gate drive circuit to control the shutdown of the main power circuit.
2. The spaceborne high-voltage DC solid-state circuit breaker according to claim 1, characterized in that, The static voltage equalization and gate protection network includes: a static voltage equalization resistor connected in parallel and a gate protection circuit. The static voltage equalization resistor and the gate protection circuit are respectively connected in parallel between the drain and source of each silicon carbide MOSFET in the main power circuit.
3. The spaceborne high-voltage DC solid-state circuit breaker according to claim 1, characterized in that, The gate protection circuit includes: a first Zener diode and a second Zener diode connected in reverse series.
4. The spaceborne high-voltage DC solid-state circuit breaker according to claim 1, characterized in that, The dynamic voltage buffer network includes: a buffer capacitor, a buffer resistor, and a buffer diode; The anode of the buffer diode and one end of the buffer resistor are both connected to the source of the silicon carbide MOSFET. The cathode of the buffer diode is connected to one end of the buffer capacitor and the other end of the buffer resistor, respectively. The other end of the buffer capacitor is connected to the drain of the silicon carbide MOSFET.
5. The spaceborne high-voltage DC solid-state circuit breaker according to claim 1, characterized in that, The overcurrent protection and control circuit includes: a current sampling resistor, a signal conditioning module, a threshold comparison module, a latch module, and a logic control module; The current sampling resistor is connected in series with the ground terminal or the low potential side of the main power circuit; The signal conditioning module is used to amplify and filter out switching noise in the voltage across the current sampling resistor; The threshold comparison module is used to compare the conditioned voltage signal with a preset overcurrent threshold, detect the overcurrent state when the limit is exceeded, and output a switching level. The latch module is connected to the threshold comparison module and is used to receive the transition level and output the latch signal; The logic control module is used to receive the latch signal of the latch module and the external on / off control pulse signal, and output a drive enable signal to the single gate drive circuit after performing a logical AND operation.
6. The spaceborne high-voltage DC solid-state circuit breaker according to claim 5, characterized in that, The latch module is also connected to a reset circuit; The reset circuit is used to clear the latch signal after the fault condition is cleared in order to restore the normal drive control of the circuit breaker's reset circuit.
7. The spaceborne high-voltage DC solid-state circuit breaker according to claim 5, characterized in that, The signal conditioning module, threshold comparison module, latching module, and logic control module integrate the INA300 overcurrent protection chip.
8. The spaceborne high-voltage DC solid-state circuit breaker according to claim 5, characterized in that, The resistance of the current sampling resistor is 5mΩ.
9. The spaceborne high-voltage DC solid-state circuit breaker according to claim 5, characterized in that, The logic control module includes: AND gates and driver chips.
10. A spacecraft power distribution system, characterized in that, include: The spaceborne high-voltage DC solid-state circuit breaker as described in any one of claims 1-9.