High-reliability short-circuit protection circuit and circuit system thereof

Abstract

The application provides a high-reliability short-circuit protection circuit and a circuit system thereof, and solves the problem of bidirectional current detection, and comprises an inverter loop and a PWM controller, and further comprises the high-reliability short-circuit protection circuit, a current detection module is connected in series at a DC bus input end of the inverter loop, and a buffer U15 in a PWM output circuit is connected between an output end of the PWM controller and a driving end of the inverter loop. The application has the advantages of good safety, fast response rate and the like.

Description

Technical Field

[0001] This invention belongs to the field of short-circuit protection circuit technology, specifically relating to a highly reliable short-circuit protection circuit and its circuit system. Background Technology

[0002] In power electronics applications, especially in inverter systems, short-circuit fault protection at the DC bus port is a key technology for ensuring the safe and reliable operation of equipment. During operation, inverters may experience positive or negative overcurrent faults on the DC bus due to power device breakdown, load short circuits, line insulation damage, or malfunctions. Negative short-circuit currents typically occur under conditions of sudden load changes, motor emergency stops, or energy feedback, with current flowing back from the inverter circuit to the DC bus, posing a serious threat to the upstream power supply and bus capacitors. Traditional current detection schemes often use unidirectional current sensors or unidirectional sampling resistor amplifier circuits, which can only respond to positive overcurrents. When a negative short-circuit fault occurs, the detection circuit cannot effectively identify it, leading to protection failure, and power devices or bus capacitors are easily damaged by reverse overcurrent. Some schemes rely on digital signal processors or microcontrollers to sample current values ​​through analog-to-digital conversion, and then use software algorithms to determine whether an overcurrent has occurred and execute PWM blocking. This process is limited by ADC sampling time, software interrupt response time, and instruction execution cycle, typically requiring a delay of more than 10 microseconds. In high-voltage, high-current applications, such a long delay is enough to cause overcurrent failure or even explosion of power switching devices.

[0003] Furthermore, existing protection circuits often require manual reset or software reinitialization to restore operation after activation. For transient short-circuit faults caused by grid fluctuations or load transient impacts, this manual intervention mechanism increases system maintenance costs and reduces equipment availability in unattended scenarios. While some hardware protection solutions are fast, their circuit structures are complex, with numerous components, and once protection thresholds and blocking times are set, they are difficult to adjust, making them inflexible for inverter systems of different power levels or application scenarios.

[0004] To address the shortcomings of existing technologies, people have conducted long-term explorations and proposed various solutions. For example, Chinese patent literature discloses a bidirectional overcurrent protection method and device for a bidirectional DC / DC converter [202011561756.5], which includes a front-stage inverter circuit, an isolation transformer, and a rear-stage rectifier circuit connected in sequence. The rectifier circuit includes a current sampling unit, a voltage comparison unit, a PWM wave generation unit, a logic processing unit, and a switching device driving unit. The current sampling unit is connected in series on the busbars of the front-stage inverter circuit and the rear-stage rectifier circuit, respectively.

[0005] The above solution addresses the overcurrent protection issue to some extent, but it still has many shortcomings, such as the lack of bidirectional current detection and slow response speed. Summary of the Invention

[0006] The purpose of this invention is to address the above-mentioned problems by providing a reasonably designed, fast-responding, and highly reliable short-circuit protection circuit.

[0007] Another objective of this invention is to provide a circuit system capable of bidirectional current detection in response to the aforementioned problems.

[0008] To achieve the above objectives, the present invention employs the following technical solution: a highly reliable short-circuit protection circuit, comprising: The current detection module is used to detect the DC bus current in real time and convert it into a voltage signal. The current detection module uses a precision sampling resistor R52 connected in series in the DC bus. When the bus current flows through the sampling resistor, according to Ohm's law V=I×R, a weak differential voltage signal proportional to the current is generated across the resistor. This signal directly reflects the real-time change of the bus current and provides the original basis for subsequent protection.

[0009] The signal amplification module includes a first operational amplifier U12A and a second operational amplifier U12B, which together form a differential amplifier. The input of the signal amplification module is connected to the output of the current detection module. It is used to differentially amplify and level-bias the voltage signal, outputting a detection voltage reflecting the bidirectional current. Since the signal across the sampling resistor is a weak differential signal and may contain common-mode noise, a differential amplifier composed of U12A and U12B is used for amplification. A 1.45V bias voltage is introduced to the reference terminal of the differential amplifier. When the bus current is positive and flows from the bus to the inverter, the amplified detection voltage is higher than 1.45V; when the bus current is negative and flows back from the inverter to the bus, such as in energy feedback mode, the detection voltage is lower than 1.45V. In this way, the bidirectional positive / negative current signal, which cannot be directly processed by a single-supply system, is mapped to a unipolar voltage signal centered at 1.45V, laying the hardware foundation for subsequent bidirectional comparison and solving the detection blind zone problem of negative short circuits in traditional solutions.

[0010] The bidirectional current protection trigger circuit includes a second comparator U13A and a third comparator U13B, both of whose inputs are connected to the output of the signal amplification module. The second comparator U13A has a positive threshold voltage, used to output a positive trigger signal when the detected voltage exceeds the positive threshold voltage. The third comparator U13B has a negative threshold voltage, used to output a negative trigger signal when the detected voltage is below the negative threshold voltage. The non-inverting input of the second comparator U13A is connected to the detected voltage, and the inverting input is connected to the positive threshold voltage set by a resistor divider, corresponding to the maximum allowable positive current. The inverting input of the third comparator U13B is connected to the detected voltage, and the non-inverting input is connected to the negative threshold voltage set by a resistor divider, corresponding to the maximum allowable reverse current. Once the detected voltage exceeds the safety threshold set in either direction, the corresponding comparator immediately outputs a high-level trigger signal. This purely hardware parallel comparison architecture, without software intervention, achieves instantaneous fault detection.

[0011] The 2ms protection and automatic reset circuit includes logic gate U14 and an RC timing network. The input of logic gate U14 is connected to the outputs of the second comparator U13A and the third comparator U13B, used to receive trigger signals and generate a blocking signal. The RC timing network is connected to logic gate U14, used to set the timing width of the blocking signal to 2ms, and automatically cancels the blocking signal after the timing ends. This 2ms protection and automatic reset circuit is the core of the automatic recovery function. Logic gate U14 synthesizes the trigger signals from the second comparator U13A and the third comparator U13B. Once a trigger signal is received, logic gate U14 outputs a blocking signal. This signal is sent to the PWM output circuit for shutdown and simultaneously starts the RC timing network composed of R50 and C57 for charging. During RC charging, the time constant is determined by the product of R50 and C57, with a designed value of 2ms, and U14 remains in a blocked state. When capacitor C57 is charged to the logic threshold voltage, the RC network discharges through its internal circuitry, automatically canceling the blocking signal output by logic gate U14. If the fault has been eliminated, the system will automatically recover; if the fault still exists, the second comparator U13A and the third comparator U13B will output trigger signals again, and the circuit will immediately re-enter the next 2ms blocking cycle to achieve cyclic detection protection.

[0012] The PWM output circuit includes a buffer U15, whose input is connected to the output of the PWM controller, its output is connected to the drive terminal of the inverter circuit, and its enable terminal is connected to the output of logic gate U14. Buffer U15 shuts down the PWM output upon receiving a blocking signal and resumes PWM output after the blocking signal is removed. Buffer U15 acts as the final gate in hardware execution. During normal operation, its enable terminal is active, allowing the PWM signal to pass through and drive the inverter circuit. When the protection and automatic reset circuit outputs a blocking signal to its enable terminal, buffer U15 immediately enters a high-impedance state or forces a low-level output, directly cutting off the PWM signal transmission path from the physical link, thereby turning off the power switch. This hardware-level direct shutdown method avoids the instruction cycle delay caused by software blocking and is key to achieving microsecond-level fast protection.

[0013] The inverter circuit has its bus input terminal connected in series with the current detection module to form a closed-loop monitoring circuit. This creates a complete closed-loop monitoring system: the current detection module monitors the operating current of the inverter circuit, and in the event of an overcurrent, the protection circuit activates instantaneously, shutting off the inverter circuit via the PWM output circuit, thereby protecting the power devices from damage.

[0014] In the aforementioned high-reliability short-circuit protection circuit, the current detection module includes a sampling resistor R52 connected in series with the DC bus and an RC filter network connected across the sampling resistor R52. The RC filter network has resistors R53 and R55 and a capacitor C56. The output of the RC filter network is connected to the output of the first operational amplifier U12A and the input of the second operational amplifier U12B. This RC filter network forms a low-pass filter to filter out high-frequency noise spikes on the sampling resistor, preventing false triggering of the protection circuit due to noise interference, while not affecting the accurate acquisition of short-circuit fault characteristics.

[0015] In the aforementioned high-reliability short-circuit protection circuit, the reference terminal of the differential amplifier in the signal amplification module is connected to a bias voltage source that provides a 1.45V bias voltage to map the bidirectional current signal into a voltage signal centered at 1.45V.

[0016] In the aforementioned high-reliability short-circuit protection circuit, in the bidirectional current protection trigger circuit, the non-inverting input of the second comparator U13A is connected to the detection voltage and the inverting input is connected to the positive threshold voltage setting resistor voltage divider node; the inverting input of the third comparator U13B is connected to the detection voltage and the non-inverting input is connected to the negative threshold voltage setting resistor voltage divider node.

[0017] In the aforementioned high-reliability short-circuit protection circuit, the 2ms protection and automatic reset circuit uses an RC timing network consisting of a resistor R50 and a capacitor C57 connected in series, with one end connected to the feedback or reset terminal of logic gate U14. The blocking time is adjusted by adjusting the values ​​of the resistor and capacitor.

[0018] The blocking time Tblock is mainly determined by the RC time constant, and the approximate formula is Tblock≈k×R50×C57, where k is a constant related to the logic gate threshold. By changing the value of R50 or C57, the protection blocking time can be flexibly adjusted to meet the needs of inverter systems with different power levels and device characteristics.

[0019] In the aforementioned high-reliability short-circuit protection circuit, logic gate U14 is a single-channel three-input positive AND gate. Its input is connected to the output of the second comparator U13A, the output of the third comparator U13B, and a high-level signal. Its output is connected to the enable terminal of buffer U15. Connecting one input of U14 to a high level simplifies circuit design by enabling logic synthesis using a three-input AND gate with only two comparator trigger signals.

[0020] In the aforementioned high-reliability short-circuit protection circuit, after the blocking signal is removed, if the second comparator U13A or the third comparator U13B still outputs a trigger signal, the 2ms protection and automatic reset circuit will re-trigger to generate the next 2ms blocking signal, thereby achieving cyclic detection protection.

[0021] In the aforementioned high-reliability short-circuit protection circuit, buffer U15 is a tri-state output buffer. When its enable terminal is low, the PWM output is turned off, and when the enable terminal is high, the PWM output is enabled.

[0022] In the aforementioned high-reliability short-circuit protection circuit, the response time is less than or equal to 2 microseconds. This response time refers to the total delay from the occurrence of a fault to the hardware shutdown of the PWM output, mainly including: current detection and filtering delay, comparator toggling delay, logic gate transmission delay, and buffer shutdown delay. The extremely low delay of the pure hardware signal link ensures that the overall response time can be controlled within 2μs, which is faster than traditional software protection schemes, thus shutting down the power device before it fails.

[0023] A circuit system includes an inverter circuit and a PWM controller, and also includes the aforementioned high-reliability short-circuit protection circuit. A current detection module is connected in series at the DC bus input terminal of the inverter circuit, and a buffer U15 in the PWM output circuit is connected between the output terminal of the PWM controller and the drive terminal of the inverter circuit.

[0024] Compared with existing technologies, the advantages of this invention are as follows: the bidirectional current protection trigger circuit realizes hardware-level identification of short-circuit faults in both positive and negative directions, eliminating the protection blind zone of negative short circuits; the short-circuit protection response time can be controlled within 2 microseconds, which improves the response speed compared with traditional software protection schemes, and can reliably shut down before power devices are damaged, significantly improving system safety; for transient short-circuit faults, the system can automatically resume operation without manual intervention, reducing maintenance costs and improving reliability in unattended scenarios; the positive / negative protection threshold can be flexibly set by changing the voltage divider resistor of the comparator reference voltage, which can be easily adapted to inverter systems of different power levels. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the system structure of the present invention; Figure 2 This is a schematic diagram of the protection circuit of the present invention; In the diagram, the components are: 1. Current detection module; 2. Signal amplification module; 3. Bidirectional current protection trigger circuit; 4. 2ms protection and automatic reset circuit; 5. PWM output circuit; 6. Inverter circuit; and 7. PWM controller. Detailed Implementation

[0026] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Example 1

[0027] like Figure 1-2 As shown, in this embodiment, the signal amplification module 2 implements bidirectional current detection. The current detection module 1 includes a sampling resistor R52 connected in series on the DC-bus, and an RC filter network composed of resistors R53 and R55 and capacitor C56. This RC filter network performs low-pass filtering on the differential voltage across the sampling resistor, filtering out high-frequency noise before outputting it to the signal amplification module 2.

[0028] Signal amplification module 2 consists of a differential amplifier structure composed of a first operational amplifier U12A and a second operational amplifier U12B. The reference terminal of the differential amplifier is connected to a 1.45V bias voltage source. This bias voltage source can be obtained from the system power supply by a resistor divider network and buffered by a voltage follower. The output terminal of signal amplification module 2 is connected to a bidirectional current protection trigger circuit 3, providing a detection voltage that reflects the magnitude of the bidirectional current.

[0029] The purpose of introducing a 1.45V bias voltage is to map the bidirectional current signal into a voltage signal centered at 1.45V. When the bus current is in the positive direction, the amplified detection voltage is higher than 1.45V; when the bus current is in the negative direction, the detection voltage is lower than 1.45V. In this way, the bipolar current signal, which cannot be directly processed by a single-supply system, is converted into a unipolar voltage signal, providing the hardware foundation for subsequent bidirectional comparison and solving the detection blind zone problem of negative short circuits. Example 2

[0030] This embodiment specifically illustrates the structure and working principle of the bidirectional current protection trigger circuit 3. The bidirectional current protection trigger circuit 3 includes two independent high-speed comparators: a second comparator U13A and a third comparator U13B. The input terminals of both are connected to the output terminal of the signal amplification module 2 to receive the detection voltage.

[0031] In the forward protection channel, the non-inverting input of the second comparator U13A is connected to the detection voltage, and the inverting input is connected to the forward threshold voltage set by the resistor divider node. This forward threshold voltage corresponds to the maximum allowable forward current value of the system. When the detection voltage exceeds the forward threshold voltage, it indicates that a forward overcurrent has occurred, and U13A outputs a high level as a forward trigger signal.

[0032] In the negative protection channel, the inverting input of the third comparator U13B is connected to the detection voltage, and the non-inverting input is connected to the negative threshold voltage set by the resistor divider node. This negative threshold voltage corresponds to the maximum allowable reverse current value of the system. When the detection voltage is lower than the negative threshold voltage, it indicates that a negative overcurrent has occurred, and U13B outputs a high level as a negative trigger signal.

[0033] The architecture, with dual comparators and separate positive and negative thresholds, enables parallel monitoring of bidirectional short-circuit faults. The outputs of the two comparators are connected via a logical OR relationship, triggering protection actions regardless of which direction the fault occurs in. Because the comparators perform pure hardware comparisons, the latency is extremely low, typically only tens of nanoseconds, eliminating the need for ADC sampling or software intervention and ensuring a fast response time of ≤2μs. Example 3

[0034] In this embodiment, the 2ms protection and automatic reset circuit 4 includes a logic gate U14 and an RC timing network consisting of a resistor R50 and a capacitor C57 connected in series. The logic gate U14 is a single-channel three-input positive AND gate, with its three inputs connected to the outputs of the second comparator U13A, the third comparator U13B, and a fixed high-level signal, such as the power supply VCC. Connecting one input of U14 to a high level simplifies the circuit design by enabling logic synthesis using a three-input AND gate when only two comparator trigger signals are available. The RC timing network, consisting of a resistor R50 and a capacitor C57 connected in series, has one end connected to the feedback or reset terminal of the logic gate U14.

[0035] When U13A or U13B outputs a high-level trigger signal, the output of U14 changes from high to low, generating a blocking signal. This blocking signal is sent to PWM output circuit 5 to turn off the PWM output, and simultaneously starts RC timing network charging. During charging by R50 and C57, U14 remains in a low-level blocking state.

[0036] When capacitor C57 charges to the logic threshold voltage, the RC network discharges through the internal circuit, and the output of U14 automatically returns from low to high, thus canceling the blocking signal. If the fault persists after the blocking signal is canceled, U13A or U13B will output a trigger signal again, and the circuit will immediately re-enter the next 2ms blocking cycle, achieving cyclic detection protection.

[0037] The blocking time Tblock is primarily determined by the RC time constant, approximated by the formula Tblock≈k×R50×C57, where k is a constant related to the logic gate threshold. By changing the values ​​of R50 or C57, the protection blocking time can be flexibly adjusted to adapt to the needs of inverter systems with different power levels and device characteristics. This hardware automatic reset mechanism allows the system to automatically recover from transient short-circuit faults, such as load surges or grid fluctuations, without requiring manual intervention, thus reducing operation and maintenance costs. Example 4

[0038] In this implementation, the PWM output circuit 5 includes a buffer U15. U15 is a tri-state output buffer. Its input terminal is connected to the PWM output terminal of the PWM controller 7, and its output terminal is connected to the drive terminal of the power switching transistor, such as an IGBT or MOSFET, of the inverter circuit 6. Its enable terminal is connected to the output terminal of the logic gate U14.

[0039] When logic gate U14 outputs a high level and there is no fault, the enable pin of buffer U15 is active, and U15 operates normally, allowing the PWM signal to pass through and drive the power switch of inverter circuit 6. When a short-circuit fault occurs, logic gate U14 outputs a low level to block the signal to the enable pin of U15. U15 immediately enters a high-impedance state or is forced to output a low level, directly cutting off the PWM signal transmission path from the physical link, thereby turning off the power switch. When the 2ms timer ends, logic gate U14 returns to a high-level output, the enable pin of U15 becomes active again, and the PWM signal output resumes.

[0040] This hardware-level direct shutdown method avoids the instruction cycle delay caused by software blocking, achieving fast protection at the ≤2μs microsecond level. The buffer U15, as the execution element, typically has a shutdown delay of only nanoseconds, ensuring the immediacy of the protection action. Example 5

[0041] This embodiment is a highly reliable short-circuit protection circuit, comprising six core modules connected in sequence to form a closed-loop monitoring circuit: The current detection module 1 is connected in series at the DC bus input terminal of the inverter circuit 6. It converts the bus current into a voltage signal through sampling resistor R52, which is then filtered by R53, R55, and C56 before being output to the signal amplification module 2. The signal amplification module 2 consists of a differential amplifier composed of U12A and U12B. A 1.45V bias voltage is connected to the reference terminal, and the output voltage reflecting the bidirectional current is sent to the bidirectional current protection trigger circuit 3. The bidirectional current protection trigger circuit 3 includes two comparators, U13A and U13B, connected to the positive and negative threshold voltage divider nodes, respectively. When the detected voltage exceeds the positive threshold or falls below the negative threshold, the corresponding comparator outputs a trigger signal to the 2ms protection and automatic reset circuit 4. The 2ms protection and automatic reset circuit 4 includes logic gate U14 and an RC timing network R50 and C57. After receiving the trigger signal, U14 outputs a blocking signal, and simultaneously, R50 and C57 begin charging, setting a 2ms blocking width. The blocking signal is automatically removed after the timing period ends. The PWM output circuit 5 includes a buffer U15, whose input is connected to the PWM controller 7 and whose output is connected to the drive terminal of the inverter circuit 6. Its enable terminal is controlled by U14, and the PWM output is hardware-shutdowned upon receiving a blocking signal. The bus current of the inverter circuit 6 is monitored in real time by the current detection module 1, forming a complete closed-loop protection circuit.

[0042] Changing the voltage division ratio of the resistor connected to the inverting input of U13A adjusts the positive protection threshold; changing the voltage division ratio of the resistor connected to the non-inverting input of U13B adjusts the negative protection threshold. Changing the values ​​of resistor R50 and / or capacitor C57 adjusts the blocking time. For example, increasing R50 or C57 prolongs the blocking time; decreasing it shortens it.

[0043] The specific embodiments described herein are merely illustrative of the spirit of the invention. Those skilled in the art to which this invention pertains may make various modifications or additions to the described specific embodiments or use similar methods to substitute them, without departing from the spirit of the invention or exceeding the scope defined by the appended claims.

[0044] Although this paper frequently uses terms such as current detection module 1, signal amplification module 2, bidirectional current protection trigger circuit 3, 2ms protection and automatic reset circuit 4, PWM output circuit 5, inverter circuit 6, and PWM controller 7, the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of this invention; interpreting them as any additional limitation would contradict the spirit of this invention.

Claims

1. A highly reliable short-circuit protection circuit, characterized in that, include: The current detection module (1) is used to detect the DC-bus current in real time and convert it into a voltage signal; The signal amplification module (2) includes a first operational amplifier U12A and a second operational amplifier U12B, which together constitute a differential amplifier. The input terminal of the signal amplification module (2) is connected to the output terminal of the current detection module (1) for differential amplification and level biasing of the voltage signal, and outputting a detection voltage that reflects the bidirectional current. The bidirectional current protection trigger circuit (3) includes a second comparator U13A and a third comparator U13B, both of which have their input terminals connected to the output terminal of the signal amplification module (2). The second comparator U13A is provided with a positive threshold voltage, which is used to output a positive trigger signal when the detection voltage exceeds the positive threshold voltage. The third comparator U13B is provided with a negative threshold voltage, which is used to output a negative trigger signal when the detection voltage is lower than the negative threshold voltage. The 2ms protection and automatic reset circuit (4) includes a logic gate U14 and an RC timing network. The input of the logic gate U14 is connected to the output of the second comparator U13A and the third comparator U13B to receive the trigger signal and generate the blocking signal. The RC timing network is connected to the logic gate U14 to set the timing width of the blocking signal to 2ms and automatically cancel the blocking signal after the timing ends. The PWM output circuit (5) includes a buffer U15, whose input terminal is connected to the output terminal of the PWM controller (7), whose output terminal is connected to the drive terminal of the inverter circuit (6), and whose enable terminal is connected to the output terminal of the logic gate U14; the buffer U15 shuts off the PWM output when it receives a blocking signal, and resumes the PWM output after the blocking signal is removed. The inverter circuit (6) has its bus input terminal connected in series with the current detection module (1) to form a closed-loop monitoring circuit.

2. The high-reliability short-circuit protection circuit according to claim 1, characterized in that, The current detection module (1) includes a sampling resistor R52 connected in series on the DC bus and an RC filter network connected across the sampling resistor R52. The RC filter network has resistors R53 and R55 and a capacitor C56. The output of the RC filter network is connected to the output of the first operational amplifier U12A and the input of the second operational amplifier U12B.

3. The high-reliability short-circuit protection circuit according to claim 1, characterized in that, The reference terminal of the differential amplifier in the signal amplification module (2) is connected to a bias voltage source that provides a 1.45V bias voltage to map the bidirectional current signal into a voltage signal centered at 1.45V.

4. The high-reliability short-circuit protection circuit according to claim 1, characterized in that, In the bidirectional current protection trigger circuit (3), the non-inverting input of the second comparator U13A is connected to the detection voltage and the inverting input is connected to the positive threshold voltage setting resistor voltage divider node; the inverting input of the third comparator U13B is connected to the detection voltage and the non-inverting input is connected to the negative threshold voltage setting resistor voltage divider node.

5. A high-reliability short-circuit protection circuit according to claim 1, characterized in that, In the 2ms protection and automatic reset circuit (4), the RC timing network is composed of resistor R50 and capacitor C57 connected in series and one end is connected to the feedback or reset terminal of logic gate U14. The blocking time is adjusted by adjusting the values ​​of resistor and capacitor.

6. A high-reliability short-circuit protection circuit according to claim 1, characterized in that, The logic gate U14 is a single-channel three-input positive AND gate. Its input is connected to the output of the second comparator U13A, the output of the third comparator U13B, and a high-level signal. Its output is connected to the enable terminal of the buffer U15.

7. A high-reliability short-circuit protection circuit according to claim 1, characterized in that, The 2ms protection and automatic reset circuit (4) will re-trigger the next 2ms blocking signal if the second comparator U13A or the third comparator U13B still outputs a trigger signal after the blocking signal is removed, thus realizing cyclic detection protection.

8. A high-reliability short-circuit protection circuit according to claim 1, characterized in that, The buffer U15 is a tri-state output buffer. When its enable terminal is low, the PWM output is turned off, and when the enable terminal is high, the PWM output is enabled.

9. A high-reliability short-circuit protection circuit according to claim 1, characterized in that, The response time of this short-circuit protection circuit is less than or equal to 2 microseconds.

10. A circuit system comprising an inverter circuit (6) and a PWM controller (7), characterized in that, It also includes a high-reliability short-circuit protection circuit as described in any one of claims 1 to 9, wherein the current detection module (1) is connected in series at the DC bus input terminal of the inverter circuit (6), and the buffer U15 in the PWM output circuit (5) is connected between the output terminal of the PWM controller (7) and the drive terminal of the inverter circuit (6).

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