A method and device for evaluating power loss of a direct current bus capacitor of a flexible interconnection device, a terminal device and a computer readable storage medium

Abstract

The application discloses a kind of flexible interconnection device DC bus capacitor power loss evaluation method, device, terminal equipment and computer readable storage medium, belong to electric power distribution technical field.Method includes: obtaining real-time working condition and carrier time delay;SPWM switching function model is constructed, and the number of harmonic truncation is determined using normalized energy index and the fitting mapping of modulation ratio and loss coefficient is established;Time delay correction function is constructed;Real-time modulation ratio is determined according to reactive power using Taylor series linear model and real-time loss coefficient is obtained;Loss is calculated in combination with fundamental current, loss coefficient and time delay correction function.The present application effectively solves the problems that existing model cannot consider high precision and low complexity, calculation iteration is slow and cannot handle double-machine parallel harmonic coupling through harmonic truncation, fitting mapping and Taylor linearization.

Description

Technical Field

[0001] This invention relates to the field of power distribution technology, and in particular to a method, apparatus, terminal equipment, and computer-readable storage medium for evaluating the power loss of DC bus capacitors in a flexible interconnection device. Background Technology

[0002] In flexible interconnect devices, the DC bus capacitor plays a crucial role in smoothing voltage and buffering energy. However, the high-frequency ripple current generated during device operation flows through the equivalent series resistance of the capacitor, resulting in heat loss. If this loss is not accurately assessed, it can easily lead to capacitor overheating and failure, thereby threatening the safe operation of the device. However, existing technologies struggle to balance assessment accuracy and computational efficiency. Low-frequency models tend to underestimate results due to neglecting high-frequency ripple, while time-domain models cannot handle the characteristics of capacitor impedance changing with frequency. Theoretically accurate frequency-domain models require handling infinite series summations and involve complex nonlinear equation iterations when back-calculating the modulation ratio, resulting in enormous computational load and slow convergence. Furthermore, existing models fail to consider the carrier delay and its resulting harmonic coupling effects when two flexible interconnect devices are connected in parallel, leading to significant errors in the assessment of system-level capacitor losses. Summary of the Invention

[0003] This invention provides a method for evaluating the power loss of DC bus capacitors in flexible interconnection devices, which can solve the problems in the existing capacitor loss evaluation models that are difficult to balance high computational accuracy and low computational complexity, have poor real-time performance, and cannot accurately handle the harmonic coupling effect of dual-machine parallel operation.

[0004] An embodiment of the present invention provides a method for evaluating the power loss of the DC bus capacitor in a flexible interconnect device, comprising: Obtain the circuit parameters and real-time operating conditions of the flexible interconnection device. The real-time operating conditions include the active power and reactive power of a single T-type three-level inverter and the time delay of the carrier signal between two T-type three-level inverters. Construct the switching function model of each of the T-type three-level inverters under SPWM modulation, and determine the number of harmonic cutoff terms used to characterize the main harmonic components; Based on the number of harmonic cutoff terms, a fitting mapping relationship between the modulation ratio and the capacitor loss coefficient is established. Based on the switching function model, the harmonic interaction of the two inverters in parallel operation is determined, and a time delay correction function is constructed to characterize the weight of the time delay on the harmonic energy based on the harmonic interaction. Based on the reactive power and the linear relationship model used to characterize the modulation ratio increment and reactive power, the current modulation ratio increment is calculated. Based on the current modulation ratio increment and the reference modulation ratio determined by the circuit parameters, the real-time modulation ratio under the current operating condition is determined. Based on the real-time modulation ratio, the corresponding real-time capacitor loss coefficient is obtained through the fitting mapping relationship. In constructing the linear relationship model, Taylor series expansion is used to establish a linear relationship between the modulation ratio increment and reactive power. The power loss value of the DC bus capacitor is determined based on the real-time capacitor loss coefficient, the time delay correction function, and the effective value of the fundamental current determined by the active power and reactive power.

[0005] Furthermore, the construction of the switching function model of the T-type three-level inverter used in the flexible interconnect device under SPWM modulation includes: The modulation ratio is taken as the ratio of the modulation amplitude to the carrier amplitude of the SPWM modulation. Based on the double Fourier series theory, a series expansion formula containing carrier phase variables and fundamental phase variables is constructed. The series expansion formula includes: DC component, fundamental component, carrier harmonic component and sideband harmonic component. Based on the modulation ratio and the first type of Bessel function, the amplitude coefficients of the DC component, fundamental component, carrier harmonic component, and sideband harmonic component are calculated; the calculated amplitude coefficients are substituted into the series expansion formula for weighted summation to obtain the switching function model.

[0006] Further, the step of determining the number of harmonic cutoff terms used to characterize the principal harmonic components includes: The sum of the harmonic cutoff terms is initialized to serve as the initial harmonic cutoff term number; Based on the initial number of harmonic cutoff terms, repeat the harmonic energy analysis operation until the termination condition is met, and determine the final number of harmonic cutoff terms. The harmonic energy analysis operation includes: Obtain the current harmonic truncation term count; wherein, the current harmonic truncation term count when the harmonic energy analysis operation is performed for the first time is the initial harmonic truncation term count; The normalized energy index of the sum of the current harmonic cutoff terms is calculated using the following formula. : ; Determine the normalized energy index obtained from the calculation. Is it greater than the preset precision threshold? If so, then stop performing the harmonic energy analysis operation and determine the current number of harmonic cutoff terms as the final number of harmonic cutoff terms; If not, the value of the current harmonic truncation term is increased by a preset step size to obtain the updated harmonic truncation term, and the updated harmonic truncation term is used as the current harmonic truncation term for the next execution of the harmonic energy analysis operation. Where m and n are the carrier harmonic order and the fundamental harmonic order, respectively. The number of carrier harmonic cutoff terms. The number of fundamental harmonic cutoff terms. The harmonic coefficients of the double Fourier series in the switching function model are given. The upper limit for summation of carrier harmonics is set. The upper limit for summation of the fundamental harmonic order.

[0007] Further, establishing the fitting mapping relationship between the modulation ratio and the capacitor loss coefficient based on the number of harmonic cutoff terms includes: Based on the physical characteristics of capacitors, the equivalent series resistance of capacitors is divided into low-frequency resistance and high-frequency resistance. Multiple sampling modulation ratios are selected within a preset modulation ratio range. For each sampling modulation ratio, based on the switching function model and the number of harmonic cutoff terms, the low-frequency energy coefficient and high-frequency energy coefficient corresponding to the sampling modulation ratio are calculated. The low-frequency energy coefficient, the high-frequency energy coefficient, the low-frequency resistance, and the high-frequency resistance are then weighted using a preset formula. Further, determining the power loss value of the DC bus capacitor includes: The effective value of the fundamental current is calculated using the active power and reactive power of the single T-type three-level inverter. Substitute the time delay between the carrier signals of the two T-type three-level inverters into the time delay correction function to calculate the current time delay correction factor. Obtain the number of parallel capacitors and the low-frequency resistance value of the capacitors; The power loss of the DC bus capacitor is calculated using the following formula: in, This refers to the probabilistic loss of a single capacitor. This refers to the number of capacitors connected in parallel. The effective value of the fundamental current is given, and ; The real-time capacitor loss coefficient is; the time delay correction function is. , Let P be the resistance of the capacitor in the low-frequency range, and Q be the active power and reactive power.

[0008] Another embodiment of the present invention provides a power loss assessment device for DC bus capacitors of flexible interconnection devices, including: a parameter acquisition module, a harmonic truncation determination module, a fitting relationship establishment module, a time delay correction construction module, a real-time coefficient determination module, and a power loss calculation module; The parameter acquisition module is used to acquire the circuit parameters and real-time operating conditions of the flexible interconnection device. The real-time operating conditions include the active power and reactive power of a single T-type three-level inverter and the time delay of the carrier signal between two T-type three-level inverters. The harmonic cutoff determination module is used to construct the switching function model of each of the T-type three-level inverters under SPWM modulation, and to determine the number of harmonic cutoff terms used to characterize the main harmonic components. The fitting relationship establishment module is used to establish a fitting mapping relationship between the modulation ratio and the capacitor loss coefficient based on the number of harmonic cutoff terms. The time delay correction construction module is used to determine the harmonic interaction of two inverters operating in parallel based on the switching function model, and to construct a time delay correction function that characterizes the weight of the time delay on the harmonic energy based on the harmonic interaction. The real-time coefficient determination module is used to calculate the current modulation ratio increment based on the reactive power and the linear relationship model characterizing the modulation ratio increment and reactive power; determine the real-time modulation ratio under the current operating condition based on the current modulation ratio increment and the reference modulation ratio determined by the circuit parameters; and obtain the corresponding real-time capacitor loss coefficient based on the real-time modulation ratio through the fitting mapping relationship; wherein, when constructing the linear relationship model, Taylor series expansion is used to establish the linear relationship between the modulation ratio increment and reactive power. The power loss calculation module is used to determine the power loss value of the DC bus capacitor based on the real-time capacitor loss coefficient, the time delay correction function, and the effective value of the fundamental current determined by the active power and reactive power.

[0009] Another embodiment of the present invention provides a terminal device, including: a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, it implements the steps of the power loss assessment method for DC bus capacitor of a flexible interconnect device according to the present invention.

[0010] Another embodiment of the present invention provides a computer-readable storage medium item, including: a stored computer program, wherein, when the computer program is running, the device where the computer-readable storage medium is located executes the power loss assessment method for DC bus capacitors of a flexible interconnect device according to the present invention.

[0011] The embodiments of the present invention have the following beneficial effects: This invention proposes a method for evaluating the power loss of the DC bus capacitor in a flexible interconnection device. First, it acquires real-time operating conditions including the active power and reactive power of a single T-type three-level inverter and the carrier delay between the two units. A switching function model of the T-type three-level inverter under SPWM modulation is constructed. By calculating the normalized energy index under different truncation orders and comparing it with a preset accuracy threshold, the number of harmonic truncation terms that can characterize the main harmonic components is determined, thus achieving scientific dimensionality reduction of the model. Simultaneously, based on this switching function model, the harmonic interaction when two inverters are connected in parallel is determined, and a time delay correction function characterizing the weight of the time delay on the harmonic energy is constructed. A fitting mapping relationship between the modulation ratio and the capacitor loss coefficient is pre-established based on the number of harmonic truncation terms. Furthermore, this invention innovatively utilizes Taylor series expansion to construct a linear relationship model characterizing the relationship between the modulation ratio increment and reactive power. The modulation ratio increment is quickly calculated based on the real-time reactive power, and the real-time modulation ratio is determined. The real-time capacitor loss coefficient is obtained by fitting the mapping relationship. Finally, the power loss value of the DC bus capacitor is calculated by combining the time delay correction function, the real-time capacitor loss coefficient, and the effective value of the fundamental current. This method significantly reduces model complexity while preserving the accuracy of high-frequency ripple analysis through scientific harmonic truncation and fitting mapping. In particular, it replaces the traditional complex nonlinear back-calculation with a Taylor series linearization model, enabling rapid solution of the modulation ratio based on real-time operating conditions. At the same time, the introduced time delay correction function can accurately quantify the harmonic coupling effect brought about by the parallel connection of two machines, significantly improving the accuracy and real-time performance of capacitor loss assessment of flexible interconnection devices under complex dynamic operating conditions. Attached Figure Description

[0012] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0013] Figure 1 This is a flowchart illustrating a method for evaluating the power loss of a DC bus capacitor in a flexible interconnect device, according to an embodiment of the present invention.

[0014] Figure 2 This is a schematic diagram of the structure of a device for evaluating the power loss of a DC bus capacitor in a flexible interconnection device according to an embodiment of the present invention. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0017] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0018] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0019] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0020] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0021] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0022] To address the problems of existing capacitor loss assessment models, such as difficulty in balancing high computational accuracy and low computational complexity, poor real-time performance, and inability to accurately handle harmonic coupling effects in parallel dual-machine setups, an embodiment of the present invention provides a method for assessing the power loss of DC bus capacitors in flexible interconnect devices, comprising: Step S1: Obtain the circuit parameters and real-time operating conditions of the flexible interconnection device. The real-time operating conditions include the active power and reactive power of a single T-type three-level inverter and the time delay of the carrier signal between two T-type three-level inverters. Specifically, the flexible interconnection device employs two identical T-type three-level grid-connected inverters, connected back-to-back via a DC bus, with several supporting capacitors connected in parallel on the DC bus; the circuit parameters mainly include the rated voltage of the DC bus (…). ), the effective value of the grid phase voltage on the inverter's grid-connected side ( ), the inductance value (L) of the LCL filter on the AC side of the inverter, and the fundamental angular frequency of the power grid ( ) and the carrier angular frequency used in the SPWM modulation strategy ( In addition, for the DC bus capacitor that is being evaluated, the number of parallel capacitors also needs to be obtained. ) and the equivalent series resistance (ESR) characteristic of the capacitor, and this ESR characteristic has been pre-classified into low-frequency band resistance values ​​according to frequency band differences ( ) and high-frequency band resistance ( ).

[0023] Simultaneously, the system collects or reads real-time operating condition data reflecting the current load level and control status of the device. This real-time operating condition includes the current AC active power (P) and AC reactive power (Q) output by a single inverter, as well as the carrier delay between the SPWM carrier signals used by the two inverters (i.e., the rectifier side and the inverter side). The static parameters and dynamic variables obtained in step S1 provide the necessary data input foundation for the subsequent construction of an accurate switching function model and rapid calculation of power loss.

[0024] Step S2: Construct the switching function model of each of the T-type three-level inverters under SPWM modulation, and determine the number of harmonic cutoff terms used to characterize the main harmonic components; In a preferred embodiment, the construction of the switching function model of the T-type three-level inverter used in the flexible interconnect device under SPWM modulation includes: The modulation ratio is taken as the ratio of the modulation amplitude to the carrier amplitude of the SPWM modulation. Based on the double Fourier series theory, a series expansion formula containing carrier phase variables and fundamental phase variables is constructed. The series expansion formula includes: DC component, fundamental component, carrier harmonic component and sideband harmonic component. Based on the modulation ratio and the first type of Bessel function, the amplitude coefficients of the DC component, fundamental component, carrier harmonic component, and sideband harmonic component are calculated; the calculated amplitude coefficients are substituted into the series expansion formula for weighted summation to obtain the switching function model.

[0025] Specifically, the construction of the switching function model depends on the determination of the modulation ratio M of the SPWM modulation, i.e., the ratio of the modulation amplitude to the carrier amplitude; the specific form of the analytical expression is constructed by including the carrier phase variable. and fundamental phase variable The general formula for the series expansion of is as follows: ; The amplitude coefficients of each harmonic component are calculated based on the Bessel function of the first kind. In practice, for different combinations of values ​​of m and n, their physical meanings have a clear correspondence: when m=0 and n=0, it represents the DC component; when m=1 and n=±1, it represents the fundamental component; when m=±1 and n=0, it represents the carrier harmonic component; when m=±1 and n=±1, it represents the sideband harmonic component. By substituting the calculated amplitude coefficients into the series expansion formula for weighted summation, a switching function model that can accurately describe the full-band output characteristics of the inverter is obtained.

[0026] Regarding the number of harmonic cutoff terms, in a preferred embodiment, determining the number of harmonic cutoff terms used to characterize the principal harmonic component includes: The sum of the harmonic cutoff terms is initialized to serve as the initial harmonic cutoff term number; Based on the initial number of harmonic cutoff terms, repeat the harmonic energy analysis operation until the termination condition is met, and determine the final number of harmonic cutoff terms. The harmonic energy analysis operation includes: Obtain the current harmonic truncation term count; wherein, the current harmonic truncation term count when the harmonic energy analysis operation is performed for the first time is the initial harmonic truncation term count; The normalized energy index of the sum of the current harmonic cutoff terms is calculated using the following formula. : ; Determine the normalized energy index obtained from the calculation. Is it greater than the preset precision threshold? If so, then stop performing the harmonic energy analysis operation and determine the current number of harmonic cutoff terms as the final number of harmonic cutoff terms; If not, the value of the current harmonic truncation term is increased by a preset step size to obtain the updated harmonic truncation term, and the updated harmonic truncation term is used as the current harmonic truncation term for the next execution of the harmonic energy analysis operation. Where m and n are the carrier harmonic order and the fundamental harmonic order, respectively. The number of carrier harmonic cutoff terms. The number of fundamental harmonic cutoff terms. The harmonic coefficients of the double Fourier series in the switching function model are given. The upper limit for summation of carrier harmonics is set. The upper limit for summation of the fundamental harmonic order.

[0027] Specifically, based on the switching function model, the normalized energy index under different cutoff orders is calculated and compared with a preset accuracy threshold to determine the number of harmonic cutoff terms used to characterize the main harmonic components. The specific process for determining the number of harmonic cutoff terms includes: Carrier truncation order and fundamental cutoff order Perform initialization; Perform harmonic energy analysis for the current truncation order and calculate the normalized energy index using the above formula. The normalized energy index was calculated. Next, it is necessary to determine whether it is greater than a preset precision threshold (e.g., 99%); if so, it means that the harmonic energy within the current cutoff range is sufficient to represent the total energy, so the traversal stops and the current value is set to zero. and The final number of harmonic cutoff terms is determined (e.g., in the experiments of this application, when...). =8, =8 is sufficient to meet the accuracy requirements); otherwise, increase according to the preset step size. and The value is used to proceed to the next iteration of the calculation; This method avoids the computational burden of dealing with infinite series in traditional frequency domain models. Through scientific energy truncation, it achieves effective dimensionality reduction while ensuring model accuracy.

[0028] Step S3: Based on the number of harmonic cutoff terms, establish a fitting mapping relationship between the modulation ratio and the capacitor loss coefficient; In a preferred embodiment, establishing a fitting mapping relationship between the modulation ratio and the capacitor loss coefficient based on the number of harmonic cutoff terms includes: Based on the physical characteristics of capacitors, the equivalent series resistance of capacitors is divided into low-frequency resistance and high-frequency resistance. Multiple sampling modulation ratios are selected within a preset modulation ratio range. For each sampling modulation ratio, based on the switching function model and the number of harmonic cutoff terms, the low-frequency energy coefficient and high-frequency energy coefficient corresponding to the sampling modulation ratio are calculated respectively. The uniform loss coefficient of the sampling modulation ratio is calculated by using a preset weighting formula based on the low-frequency energy coefficient, the high-frequency energy coefficient, the low-frequency resistance value, and the high-frequency resistance value. Using the sampling modulation ratio as the independent variable and the uniform loss coefficient as the dependent variable, a functional relationship is established using a quadratic curve fitting method, and the functional relationship is used as the fitting mapping relationship. The weighting formula is as follows: , This is the resistance value for the low-frequency range. The high-frequency resistance value is [value], and the low-frequency energy coefficient corresponding to the low-frequency harmonic components is [value]. The high-frequency energy coefficient corresponding to the high-frequency harmonic components is .

[0029] Specifically, establishing a fitting mapping relationship between the modulation ratio and the capacitor loss coefficient generally includes the following steps: The first step is to define the equivalent series resistance (ESR) in frequency bands based on the physical characteristics of the capacitor, and to calculate the energy coefficient of each frequency band based on the sampling modulation ratio. Considering that the ESR value of a real capacitor is not a fixed constant, but a nonlinear physical quantity that varies with frequency, in order to improve the evaluation accuracy, the equivalent series resistance of the capacitor is divided into low-frequency resistance values. (Mainly corresponding to the fundamental and low harmonic frequency bands) and high-frequency band resistance values (Mainly corresponds to switching frequency and harmonic frequency band); Within a preset modulation ratio range (e.g., 0 to 1.15), multiple discrete values ​​are selected as sampling modulation ratios. For each sampling modulation ratio, it is substituted into the switching function model constructed in step S2, and combined with the determined number of harmonic cutoff terms, the low-frequency energy coefficients corresponding to the low-frequency harmonic components are calculated respectively. High-frequency energy coefficient corresponding to high-frequency harmonic components The low-frequency energy coefficient is composed of the fundamental wave and its nearby sideband harmonic energy within the cutoff range, while the high-frequency energy coefficient is composed of the carrier wave and its nearby sideband harmonic energy within the cutoff range.

[0030] Next, combining the frequency domain distribution characteristics and the resistance frequency characteristics, the aforementioned unified loss coefficient is constructed using a weighted summation method. The calculation formula is used to obtain the fitting mapping relationship between the modulation ratio and the capacitor loss coefficient; Under a uniform loss coefficient In the formula, the resistance ratio is introduced as a weighting factor for high-frequency energy, which physically characterizes the sum of normalized heat losses generated by different frequency band current components on their respective corresponding resistors. It should be noted that, in order to avoid repeating the above-mentioned complex energy coefficient calculation in subsequent real-time evaluations, this step uses the sampling modulation ratio as the independent variable and the calculated corresponding uniform loss coefficient. As the dependent variable, the fitting model can be expressed as a quadratic polynomial in terms of the modulation ratio M: In subsequent processing of real-time tasks, only the real-time modulation ratio needs to be substituted to obtain a high-precision capacitor loss coefficient, which greatly reduces the complexity of online calculation.

[0031] Step S4: Based on the switching function model, determine the harmonic interaction when the two inverters are running in parallel, and construct a time delay correction function that characterizes the weight of the time delay on the harmonic energy based on the harmonic interaction; In a preferred embodiment, the delay correction function includes: ; in, The energy weights for each subharmonic are... The carrier angular frequency, denoted as the fundamental angular frequency, and m and n as the carrier harmonic order and fundamental harmonic order, respectively.

[0032] Specifically, the basis for constructing the time delay correction function is further explained as follows: Based on the switching function model constructed in step S2, the output current spectrum characteristics of a single inverter in the frequency domain can be determined. This is because the ripple current of the DC bus capacitor originates from the product of the three-phase AC load current and the switching function. Since the switching function model in step S2 has accurately analyzed the amplitude coefficients of each harmonic through double Fourier series, the switching function model directly determines the energy distribution characteristics of the DC side current in each frequency band. Considering that the flexible interconnect device consists of two identical inverters connected in parallel, and that the carrier signal of the second inverter has a time delay relative to the first inverter. Based on the time-shift property of the Fourier transform, the switching function and corresponding current spectrum of the second inverter are equivalent in the frequency domain to the switching function of the first inverter multiplied by a phase rotation factor. ,in ω is the harmonic angular frequency, and j is the imaginary unit.

[0033] Specifically, the process of determining the harmonic interactions when two inverters are operating in parallel is as follows: Due to the total ripple current flowing into the DC bus capacitor The sum of the DC-side currents of the two inverters is usually expressed as the difference between the two inverters. In the frequency domain, the spectral amplitude of the total current With the amplitude of the single-machine current spectrum The following complex number operations are satisfied: ; According to Euler's formula, using trigonometric identities: ; It can be deduced that the square of the total current spectrum amplitude after the two machines are connected in parallel satisfies a specific multiple with the square of the current spectrum amplitude of a single machine, and the expression characterizing the harmonic interaction is constructed as follows: ; The expression for the harmonic interaction explains the time delay. The modulation law of harmonic energy at different frequencies: that is, harmonics of certain frequencies will cancel each other out due to phase inversion. The term approaches 0), while harmonics of other frequencies will superimpose due to their similarity ( The term approaches 1); Furthermore, based on the aforementioned harmonic interaction laws, the analysis for a single frequency is extended to the energy assessment of the entire system, and the aforementioned normalized time delay correction function is constructed. , used to characterize the weight of the effect of time delay on the overall harmonic energy; By constructing the aforementioned time delay correction function, the complex dual-machine harmonic coupling effect can be decoupled into an independent mathematical correction term related to time delay. This eliminates the need for time-consuming full-circuit current superposition simulations in system-level loss assessment. Instead, a correction factor is added to the single-machine loss calculation. This not only significantly reduces the computational dimension and complexity of multi-machine systems but also significantly improves the robustness and accuracy of the model's evaluation results under various carrier control strategies.

[0034] Step S5: Calculate the current modulation ratio increment based on the reactive power and the linear relationship model used to characterize the modulation ratio increment and reactive power. Determine the real-time modulation ratio under the current operating condition based on the current modulation ratio increment and the reference modulation ratio determined by the circuit parameters. Obtain the corresponding real-time capacitor loss coefficient based on the real-time modulation ratio through the fitting mapping relationship. Specifically, when constructing the linear relationship model, Taylor series expansion is used to establish the linear relationship between the modulation ratio increment and reactive power. In a preferred embodiment, the linear relationship between the modulation ratio increment and reactive power satisfies the following formula: , in, The grid angular frequency is L, where L is the AC side filter inductance of the inverter, and the grid voltage is... DC side voltage is The reference modulation ratio is The reactive power is Q; Specifically, the nonlinear modulation ratio equation is simplified using Taylor series to construct the linear relationship model: First, the modulation ratio is calculated based on the voltage vector relationship of the grid-connected inverter: and make the reference modulation ratio microparameters ,in accordance with , and Establish the physical equation for the modulation ratio: ;in, For grid voltage phasors Plus the voltage drop across the inductor , This is the effective value of the fundamental current. The power factor angle; Specifically, in constructing the linear relationship model, to eliminate the square root operation in the equation for the modulation ratio M, a Taylor series is used for approximate expansion to establish a linear relationship between the modulation ratio increment and reactive power: According to the Taylor expansion formula... The terms in the physical equation for the modulation ratio ( Considering it as a tiny quantity x, the expanded result is as follows: ; At this time, the modulation ratio increment is: ; Considering grid connection conditions These are usually minute quantities, and second-order and higher-order terms are ignored. Retaining the first-order dominant term, we obtain an approximate expression for the modulation ratio increment: ; Based on the definition of reactive power in a three-phase system ,as well as and After eliminating the current variable, the final linear relationship model representing the modulation ratio increment and reactive power is obtained: ; In a preferred embodiment, the real-time capacitor loss coefficient corresponding to the current operating condition is calculated based on the linear relationship model representing the modulation ratio increment and reactive power. The steps are as follows: The system collects reactive power Q in real time, and substitutes it into the above linear relationship model to calculate the result. Then calculate the real-time modulation ratio. + ;Will Substitute the fitting mapping relationship determined in step S3 In the calculation, the real-time capacitor loss coefficient corresponding to the current operating condition is obtained. .

[0035] It is worth noting that by using this Taylor series linearization-based processing method, the complex process of solving nonlinear equations based on power in the traditional method can be avoided, reducing the computational complexity of solving the modulation ratio to the O(1) level, making it possible to perform millisecond-level real-time loss assessment in a microcontroller.

[0036] Step S6: Determine the power loss value of the DC bus capacitor based on the real-time capacitor loss coefficient, the time delay correction function, and the effective value of the fundamental current determined by the active power and reactive power.

[0037] In a preferred embodiment, the effective value of the fundamental current flowing through the AC side of the inverter is first calculated based on the real-time power data, and then combined with the effective value of the grid phase voltage. Derive the effective value of the fundamental current The calculation formula is: ; Specifically, the effective value of the fundamental current obtained above is... The real-time capacitor loss coefficient obtained in step S5 And the delay correction factor calculated by substituting the real-time delay into the delay correction function in step S4. Substituting into the system-level loss assessment model, the power loss value of the DC bus capacitor is obtained, and the calculation formula is as follows: ; in, This refers to the probabilistic loss of a single capacitor. This refers to the number of capacitors connected in parallel. This represents the effective value of the fundamental current. The real-time capacitor loss coefficient is given; the time delay correction function is given. , Let P be the resistance of the capacitor in the low-frequency range, and Q be the active power and reactive power.

[0038] By employing the aforementioned comprehensive formula, the complex capacitor loss assessment process involving high-frequency ripple analysis, ESR nonlinear characteristics, and dual-machine time-delay coupling can be condensed into a highly simplified algebraic product form. This approach ensures high accuracy of the assessment results while streamlining the entire calculation process, involving only simple arithmetic operations. It effectively avoids the complex integration and iteration processes in traditional methods, making it suitable for operation in resource-constrained embedded controllers. This enables real-time and accurate output of capacitor thermal loss data, providing core data support for the thermal management, reliability prediction, and fault early warning of flexible interconnect devices.

[0039] like Figure 2 As shown, another embodiment of the present invention also provides a power loss assessment device for the DC bus capacitor of a flexible interconnection device, including: a parameter acquisition module, a harmonic truncation determination module, a fitting relationship establishment module, a time delay correction construction module, a real-time coefficient determination module, and a power loss calculation module; The parameter acquisition module is used to acquire the circuit parameters and real-time operating conditions of the flexible interconnection device. The real-time operating conditions include the active power and reactive power of a single T-type three-level inverter and the time delay of the carrier signal between two T-type three-level inverters. The harmonic cutoff determination module is used to construct the switching function model of each of the T-type three-level inverters under SPWM modulation, and to determine the number of harmonic cutoff terms used to characterize the main harmonic components. The fitting relationship establishment module is used to establish a fitting mapping relationship between the modulation ratio and the capacitor loss coefficient based on the number of harmonic cutoff terms. The time delay correction construction module is used to determine the harmonic interaction of two inverters operating in parallel based on the switching function model, and to construct a time delay correction function that characterizes the weight of the time delay on the harmonic energy based on the harmonic interaction. The real-time coefficient determination module is used to calculate the current modulation ratio increment based on the reactive power and the linear relationship model characterizing the modulation ratio increment and reactive power; determine the real-time modulation ratio under the current operating condition based on the current modulation ratio increment and the reference modulation ratio determined by the circuit parameters; and obtain the corresponding real-time capacitor loss coefficient based on the real-time modulation ratio through the fitting mapping relationship; wherein, when constructing the linear relationship model, Taylor series expansion is used to establish the linear relationship between the modulation ratio increment and reactive power. The power loss calculation module is used to determine the power loss value of the DC bus capacitor based on the real-time capacitor loss coefficient, the time delay correction function, and the effective value of the fundamental current determined by the active power and reactive power.

[0040] It is understood that the above-described device embodiments correspond to the method embodiments of the present invention, and can realize the power loss assessment method for the DC bus capacitor of a flexible interconnect device provided by any of the above-described method embodiments of the present invention.

[0041] It should be noted that the device embodiments described above are merely illustrative, and some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can specifically be implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0042] Based on the above-described embodiment of the power loss assessment method for DC bus capacitors of a flexible interconnect device, another embodiment of the present invention provides a terminal device, which includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the power loss assessment method for DC bus capacitors of a flexible interconnect device according to any embodiment of the present invention.

[0043] For example, in this embodiment, the computer program can be divided into one or more modules, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the terminal device.

[0044] The terminal device may be a desktop computer, laptop, handheld computer, or cloud server, etc. The terminal device may include, but is not limited to, a processor and a memory.

[0045] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting all parts of the terminal device via various interfaces and lines.

[0046] Based on the above-described method embodiments, another embodiment of the present invention provides a computer-readable storage medium including a stored computer program, wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to execute the power loss assessment method for DC bus capacitors of a flexible interconnect device as described in any of the above-described method embodiments of the present invention.

[0047] The modules / units integrated in the device / terminal equipment, if implemented as software functional units and sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.

[0048] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for evaluating the power loss of a DC bus capacitor in a flexible interconnect device, characterized in that, include: Obtain the circuit parameters and real-time operating conditions of the flexible interconnection device. The real-time operating conditions include the active power and reactive power of a single T-type three-level inverter and the time delay of the carrier signal between two T-type three-level inverters. Construct the switching function model of each of the T-type three-level inverters under SPWM modulation, and determine the number of harmonic cutoff terms used to characterize the main harmonic components; Based on the number of harmonic cutoff terms, a fitting mapping relationship between the modulation ratio and the capacitor loss coefficient is established. Based on the switching function model, the harmonic interaction of the two inverters in parallel operation is determined, and a time delay correction function is constructed to characterize the weight of the time delay on the harmonic energy based on the harmonic interaction. Based on the reactive power and the linear relationship model used to characterize the modulation ratio increment and reactive power, the current modulation ratio increment is calculated. Based on the current modulation ratio increment and the reference modulation ratio determined by the circuit parameters, the real-time modulation ratio under the current operating condition is determined. Based on the real-time modulation ratio, the corresponding real-time capacitor loss coefficient is obtained through the fitting mapping relationship. In constructing the linear relationship model, Taylor series expansion is used to establish the linear relationship between the modulation ratio increment and reactive power. The power loss value of the DC bus capacitor is determined based on the real-time capacitor loss coefficient, the time delay correction function, and the effective value of the fundamental current determined by the active power and reactive power.

2. The method for evaluating the power loss of the DC bus capacitor in a flexible interconnect device as described in claim 1, characterized in that, The construction of the switching function model of the T-type three-level inverter used in the flexible interconnect device under SPWM modulation includes: The modulation ratio is taken as the ratio of the modulation amplitude to the carrier amplitude of the SPWM modulation. Based on the double Fourier series theory, a series expansion formula containing carrier phase variables and fundamental phase variables is constructed. The series expansion formula includes: DC component, fundamental component, carrier harmonic component and sideband harmonic component. Based on the modulation ratio and the first type of Bessel function, the amplitude coefficients of the DC component, fundamental component, carrier harmonic component, and sideband harmonic component are calculated; the calculated amplitude coefficients are substituted into the series expansion formula for weighted summation to obtain the switching function model.

3. The method for evaluating the power loss of the DC bus capacitor in a flexible interconnection device as described in claim 2, characterized in that, Determining the number of harmonic cutoff terms used to characterize the principal harmonic components includes: The sum of the harmonic cutoff terms is initialized to serve as the initial harmonic cutoff term number; Based on the initial number of harmonic cutoff terms, repeat the harmonic energy analysis operation until the termination condition is met, and determine the final number of harmonic cutoff terms. The harmonic energy analysis operation includes: Obtain the current harmonic truncation term count; wherein, the current harmonic truncation term count when the harmonic energy analysis operation is performed for the first time is the initial harmonic truncation term count; The normalized energy index of the sum of the current harmonic cutoff terms is calculated using the following formula. : Determine the normalized energy index obtained from the calculation. Is it greater than the preset precision threshold? If so, then stop performing the harmonic energy analysis operation and determine the current number of harmonic cutoff terms as the final number of harmonic cutoff terms; If not, the value of the current harmonic truncation term is increased by a preset step size to obtain the updated harmonic truncation term, and the updated harmonic truncation term is used as the current harmonic truncation term for the next execution of the harmonic energy analysis operation. Where m and n are the carrier harmonic order and the fundamental harmonic order, respectively. The number of carrier harmonic cutoff terms. The number of fundamental harmonic cutoff terms. The harmonic coefficients of the double Fourier series in the switching function model are given. The upper limit for summation of carrier harmonics is set. The upper limit for summation of the fundamental harmonic order.

4. The method for evaluating the power loss of the DC bus capacitor in a flexible interconnection device as described in claim 3, characterized in that, The step of establishing a fitting mapping relationship between the modulation ratio and the capacitor loss coefficient based on the number of harmonic cutoff terms includes: Based on the physical characteristics of capacitors, the equivalent series resistance of capacitors is divided into low-frequency resistance and high-frequency resistance. Multiple sampling modulation ratios are selected within a preset modulation ratio range. For each sampling modulation ratio, based on the switching function model and the number of harmonic cutoff terms, the low-frequency energy coefficient and high-frequency energy coefficient corresponding to the sampling modulation ratio are calculated respectively. The uniform loss coefficient of the sampling modulation ratio is calculated by using a preset weighting formula based on the low-frequency energy coefficient, the high-frequency energy coefficient, the low-frequency resistance value, and the high-frequency resistance value. Using the sampling modulation ratio as the independent variable and the uniform loss coefficient as the dependent variable, a functional relationship is established using a quadratic curve fitting method, and the functional relationship is used as the fitting mapping relationship. The weighting formula is as follows: , This is the resistance value for the low-frequency range. The high-frequency resistance value is [value], and the low-frequency energy coefficient corresponding to the low-frequency harmonic components is [value]. The high-frequency energy coefficient corresponding to the high-frequency harmonic components is .

5. The method for evaluating the power loss of the DC bus capacitor in a flexible interconnection device as described in claim 4, characterized in that, The delay correction function includes: in, The energy weights for each subharmonic are... The carrier angular frequency, denoted as the fundamental angular frequency, and m and n as the carrier harmonic order and fundamental harmonic order, respectively.

6. The method for evaluating the power loss of a DC bus capacitor in a flexible interconnect device as described in claim 5, characterized in that, The linear relationship between the modulation ratio increment and reactive power satisfies the following formula: ， in, The grid angular frequency is L, where L is the filter inductance value on the AC side of the T-type three-level inverter, and the grid voltage is... DC side voltage is The reference modulation ratio is The reactive power is Q.

7. The method for evaluating the power loss of the DC bus capacitor in a flexible interconnection device as described in claim 6, characterized in that, Determining the power loss value of the DC bus capacitor includes: The effective value of the fundamental current is calculated using the active power and reactive power of the single T-type three-level inverter. Substitute the time delay between the carrier signals of the two T-type three-level inverters into the time delay correction function to calculate the current time delay correction factor. The number of parallel capacitors and the low-frequency resistance value of the capacitors are obtained from the circuit parameters. The power loss of the DC bus capacitor is calculated using the following formula: in, This refers to the probabilistic loss of a single capacitor. The number of parallel capacitors; The effective value of the fundamental current is given, and ; The real-time capacitor loss coefficient is; the time delay correction function is. , Let P be the resistance of the capacitor in the low-frequency range, and Q be the active power and reactive power.

8. A power loss assessment device for DC bus capacitors in a flexible interconnection device, characterized in that, include: The module includes a parameter acquisition module, a harmonic truncation determination module, a fitting relationship establishment module, a time delay correction construction module, a real-time coefficient determination module, and a power loss calculation module. The parameter acquisition module is used to acquire the circuit parameters and real-time operating conditions of the flexible interconnection device. The real-time operating conditions include the active power and reactive power of a single T-type three-level inverter and the time delay of the carrier signal between two T-type three-level inverters. The harmonic cutoff determination module is used to construct the switching function model of each of the T-type three-level inverters under SPWM modulation, and to determine the number of harmonic cutoff terms used to characterize the main harmonic components. The fitting relationship establishment module is used to establish a fitting mapping relationship between the modulation ratio and the capacitor loss coefficient based on the number of harmonic cutoff terms. The time delay correction construction module is used to determine the harmonic interaction of two inverters operating in parallel based on the switching function model, and to construct a time delay correction function that characterizes the weight of the time delay on the harmonic energy based on the harmonic interaction. The real-time coefficient determination module is used to calculate the current modulation ratio increment based on the reactive power and the linear relationship model characterizing the modulation ratio increment and reactive power; determine the real-time modulation ratio under the current operating condition based on the current modulation ratio increment and the reference modulation ratio determined by the circuit parameters; and obtain the corresponding real-time capacitor loss coefficient based on the real-time modulation ratio through the fitting mapping relationship; wherein, when constructing the linear relationship model, Taylor series expansion is used to establish the linear relationship between the modulation ratio increment and reactive power. The power loss calculation module is used to determine the power loss value of the DC bus capacitor based on the real-time capacitor loss coefficient, the time delay correction function, and the effective value of the fundamental current determined by the active power and reactive power.

9. A terminal device, characterized in that, The device includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein, when the processor executes the computer program, it implements the power loss assessment method for the DC bus capacitor of the flexible interconnect device as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, include: A stored computer program, wherein, when the computer program is executed, the device containing the computer-readable storage medium is controlled to perform the power loss assessment method for the DC bus capacitor of the flexible interconnect device as described in any one of claims 1-7.

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