Control method, control circuit and switching power supply applying the same

Abstract

The application discloses a switching power supply, when the output voltage greatly deviates from the expected value due to load jump, the amplitude of the voltage reference signal is adaptively adjusted, so that the output voltage is actively chased, the error signal of the control loop is instantaneously reduced, the control circuit can exit the maximum or minimum power output state earlier, the recovery time is significantly shortened, and the voltage overshoot or oscillation is reduced. Further, when the system returns to the vicinity of the steady state, the voltage reference signal is forced to return to the fixed reference value, so that the cumulative error introduced by the adaptive adjustment process is eliminated, and the accuracy and stability of the output voltage are ensured.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more specifically, to a control method and control circuit. Background Technology

[0002] Most electronic products, such as laptops, desktop computers, and PDAs, require DC power supplies to provide regulated power to various functional modules. DC-DC converters employing constant on-time (COT) control offer advantages such as fast transient response and simple structure, and are widely used in these fields.

[0003] In existing COT DC-DC converters, when the load changes, the output voltage drops sharply, causing the circuit's feedback control loop to generate a series of switching pulses within a short period. These pulses cause a rapid increase in the inductor current, resulting in a pumped-up output voltage when the load change begins to stabilize, easily leading to overshoot. Therefore, it is necessary to control this overshoot to improve the load transient response. Summary of the Invention

[0004] In view of this, the present invention provides a control method to solve the problem of large fluctuations in output voltage when the load changes.

[0005] In a first aspect, the present invention provides a control method applied in a switching power supply, characterized in that it includes:

[0006] Acquire a voltage sampling signal that represents the instantaneous value of the output voltage of the switching power supply;

[0007] When the load current switches, the voltage reference signal is adjusted according to the changing trend of the voltage sampling signal so that the changing trend of the voltage reference signal is the same as that of the voltage sampling signal; and a switching control signal is generated based on the voltage reference signal, the voltage sampling signal and the current sampling signal representing the instantaneous value of the inductor current of the switching power supply to periodically control the switching state of the power devices of the switching power supply, thereby reducing the fluctuation of the output voltage.

[0008] Preferably, the method further includes acquiring the voltage difference between the voltage reference signal and the voltage sampling signal; and determining the relationship between the absolute value of the voltage difference and a preset value.

[0009] When the absolute value of the voltage difference is less than the preset value, the voltage reference signal remains unchanged; when the absolute value of the voltage difference is greater than the preset value, the voltage reference signal is adjusted periodically until the absolute value of the voltage difference is less than the preset value.

[0010] Preferably, when the absolute value of the difference voltage is greater than the preset value and the difference voltage is positive, the voltage reference signal is decreased; when the absolute value of the difference voltage is greater than the preset value and the difference voltage is negative, the voltage reference signal is increased.

[0011] Preferably, when the absolute value of the difference voltage is less than the preset value, the voltage reference signal is maintained at a reference value that characterizes the expected value of the output voltage.

[0012] Preferably, an adjustment signal is generated based on the relationship between the difference voltage and the preset value, and the sign of the difference. The adjustment signal is then superimposed on a reference value that characterizes the desired value of the output voltage to adjust the voltage reference signal.

[0013] Preferably, when the absolute value of the difference voltage is greater than the preset value and the difference is positive, the adjustment signal is negative; when the absolute value of the difference voltage is greater than the preset value and the difference is negative, the adjustment signal is positive.

[0014] Preferably, an adjustment signal is generated based on the relationship between the difference voltage and the preset value, and the sign of the difference. The adjustment signal is then superimposed on the voltage reference signal at the current moment to generate the voltage reference signal at the next moment.

[0015] Preferably, the setting signal of the power device in the switching power supply is generated based on the current sampling signal and the first voltage, wherein the first voltage is positively correlated with both the difference voltage and the integral signal of the difference voltage.

[0016] Preferably, the first voltage is the sum of the difference voltage, the integral signal of the difference voltage, and a ramp signal.

[0017] Preferably, the set signal is valid when the current sampling signal reaches the first voltage.

[0018] Preferably, the power device in the switching power supply is turned off based on a fixed time signal.

[0019] Preferably, when the current sampling signal is less than the minimum value of the first voltage, the switching power supply operates based on the minimum off time to output maximum power.

[0020] Preferably, when the current sampling signal is greater than the maximum value of the first voltage, the set signal remains in an invalid state.

[0021] Preferably, the preset value is also related to a drop voltage, the value of which has the same trend as the load current of the switching power supply.

[0022] Preferably, the preset value is the sum of a first preset value and the drop voltage.

[0023] Secondly, the present invention provides a control circuit for use in a switching power supply, characterized in that it includes:

[0024] A voltage sampling circuit is used to acquire a voltage sampling signal that represents the instantaneous value of the output voltage of the switching power supply;

[0025] A voltage reference signal adjustment circuit is used to adjust the voltage reference signal according to the changing trend of the voltage sampling signal when the load current switches, so that the changing trend of the voltage reference signal is the same as the changing trend of the voltage sampling signal; and

[0026] A set signal generation circuit is used to generate a switch control signal based on the voltage reference signal, the voltage sampling signal, and the current sampling signal characterizing the instantaneous value of the inductor current of the switching power supply, so as to periodically control the switching state of the power devices of the switching power supply, thereby reducing the fluctuation of the output voltage.

[0027] Preferably, the voltage reference adjustment circuit is further configured to acquire the voltage difference between the voltage reference signal and the voltage sampling signal, and determine the relationship between the absolute value of the voltage difference and a preset value.

[0028] When the absolute value of the voltage difference is less than the preset value, the voltage reference signal adjustment circuit maintains the voltage reference signal unchanged; when the absolute value of the voltage difference is greater than the preset value, the voltage reference signal adjustment circuit adjusts the voltage reference signal cycle by cycle until the absolute value of the voltage difference is less than the preset value.

[0029] Preferably, when the absolute value of the difference voltage is greater than the preset value and the difference voltage is positive, the voltage reference signal adjustment circuit decreases the voltage reference signal; when the absolute value of the difference voltage is greater than the preset value and the difference voltage is negative, the voltage reference signal adjustment circuit increases the voltage reference signal.

[0030] Preferably, when the absolute value of the difference voltage is less than the preset value, the voltage reference signal adjustment circuit maintains the voltage reference signal at a reference value that characterizes the desired value of the output voltage.

[0031] Preferably, the voltage reference signal adjustment circuit generates an adjustment signal based on the relationship between the difference voltage and the preset value, and the sign of the difference, and superimposes the adjustment signal with a reference value that characterizes the desired value of the output voltage to adjust the voltage reference signal.

[0032] Preferably, when the absolute value of the difference voltage is greater than the preset value and the difference is positive, the adjustment signal is negative; when the absolute value of the difference voltage is greater than the preset value and the difference is negative, the adjustment signal is positive.

[0033] Preferably, the voltage reference signal adjustment circuit generates an adjustment signal based on the relationship between the difference voltage and the preset value, and the sign of the difference, and superimposes the adjustment signal with the voltage reference signal at the current moment to generate the voltage reference signal at the next moment.

[0034] Preferably, the setting signal generation circuit generates a setting signal for the power device in the switching power supply based on the current sampling signal and the first voltage, wherein the first voltage is positively correlated with both the difference voltage and the integral signal of the difference voltage.

[0035] Preferably, the first voltage is the sum of the difference voltage, the integral signal of the difference voltage, and a ramp signal.

[0036] Preferably, the set signal generation circuit includes a comparator, the first input terminal of the comparator receives the first voltage, the second input terminal receives the current sampling signal, and when the current sampling signal reaches the first voltage, the comparator outputs a set signal indicating a valid state.

[0037] Preferably, the control circuit generates a turn-off signal for the power devices in the switching power supply based on a fixed time signal.

[0038] Preferably, when the current sampling signal is less than the minimum value of the first voltage, the set signal generation circuit outputs an invalid set signal so that the switching power supply operates based on the minimum off time to output maximum power.

[0039] Preferably, when the current sampling signal is greater than the maximum value of the first voltage, the set signal generation circuit keeps the set signal in an invalid state.

[0040] Preferably, the preset value is also related to a drop voltage, the value of which has the same trend as the load current of the switching power supply.

[0041] Preferably, the preset value is the sum of a first preset value and the drop voltage.

[0042] Thirdly, the present invention provides a switching power supply, characterized in that it comprises:

[0043] The power stage circuit, and the control circuit described above.

[0044] The beneficial effects of this invention are as follows:

[0045] Fast dynamic response: When the output voltage deviates significantly from the expected value due to load fluctuations (the absolute value of the voltage difference is greater than the preset value), the voltage reference signal is adaptively adjusted to "actively catch up" with the output voltage. This is equivalent to instantly reducing the error signal of the control loop, thereby enabling the control circuit to exit the maximum or minimum power output state earlier, significantly shortening the recovery time and reducing voltage overshoot or oscillation.

[0046] High steady-state accuracy: When the system returns to near steady state (the absolute value of the voltage difference is less than the preset value), the voltage reference signal is forced to recover to a fixed reference value, thereby eliminating the cumulative error that may be introduced by the adaptive adjustment process and ensuring the long-term accuracy and stability of the output voltage. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of the switching power supply according to the first embodiment of the present invention;

[0049] Figure 2 This is a flowchart of the voltage reference signal adjustment method of the present invention;

[0050] Figure 3 This is a schematic diagram of the switching power supply according to the second embodiment of the present invention;

[0051] Figure 4 This is a waveform diagram of a switching power supply according to a second embodiment of the present invention.

[0052] Figure 5 The waveform diagram of the switching power supply is a comparative example of the present invention.

[0053] Figure 6 This is another operating waveform diagram of the switching power supply according to the second embodiment of the present invention;

[0054] Figure 7 This is a schematic diagram of the switching power supply according to the third embodiment of the present invention;

[0055] Figure 8 The waveform diagram of the switching power supply according to the third embodiment of the present invention is shown. Detailed Implementation

[0056] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0057] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0058] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0059] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."

[0060] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0061] Figure 1 This is a schematic diagram of a switching power supply according to a first embodiment of the present invention. Figure 1 In the illustrated embodiment, the switching power supply includes a power switching circuit 11 and a control circuit 12. The power switching circuit 11 is periodically turned on and off to convert the input voltage Vin into an output voltage Vo to supply power to the load. Figure 1 In the illustrated embodiment, the power switching circuit 11 includes at least a power device S1. When the power device S1 is turned on, the current flowing through the power switching circuit 11 increases; and when the power device S1 is turned off, the current flowing through the power switching circuit 11 decreases. The power switching circuit 11 may further include a secondary power transistor S2, which is controlled to conduct in a non-overlapping manner with the power device S1.

[0062] In one embodiment, the set signal Vs triggers the switch control signal PWM to turn on the power device S1. In one embodiment, the power switch circuit 11 being turned on indicates that the power device S1 is turned on, and the power switch circuit 11 being turned off indicates that the power device S1 is turned off.

[0063] The control circuit 12 is used to generate a switching control signal PWM based at least on the current sampling signal ILs, which characterizes the instantaneous value of the inductor current in the power switching circuit 11, and the voltage sampling signal Vs, which characterizes the output voltage Vo of the power switching circuit 11.

[0064] In this embodiment of the invention, the control circuit 12 includes a voltage reference signal adjustment circuit 121. The core function of the voltage reference signal adjustment circuit 121 is to dynamically generate a voltage reference signal Vref based on the instantaneous state of the output voltage Vo. Specifically, the voltage reference signal adjustment circuit 121 adjusts the voltage reference signal according to the changing trend of the voltage sampling signal Vs, so that the changing trend of the voltage reference signal is the same as the changing trend of the voltage sampling signal.

[0065] In a preferred embodiment, the voltage reference signal adjustment circuit 121 is configured to set a preset value Vth, acquire the voltage difference Vd between the current voltage reference signal Vref and the voltage sampling signal Vs, and then adjust the current voltage reference signal Vref based on a comparison between the absolute value of the voltage difference Vd and the preset value Vth to generate the voltage reference signal Vref for the next time step, such that the absolute value of the voltage difference Vd is less than the preset value Vth. Here, the voltage reference signal Vref represents the expected value of the output voltage of the switching power supply, and the voltage sampling signal Vs represents the instantaneous value of the output voltage.

[0066] When the absolute value of the voltage difference Vd is greater than the preset value Vth, the voltage reference signal Vref is adjusted so that its changing trend is the same as that of the voltage sampling signal Vs. Furthermore, when the absolute value of the voltage difference Vd is greater than the preset value Vth and the voltage difference Vd is positive, the voltage reference signal Vref is decreased; when the absolute value of the voltage difference Vd is greater than the preset value Vth and the voltage difference Vd is negative, the voltage reference signal Vref is increased.

[0067] When the absolute value of the voltage difference Vd is adjusted to be less than the preset value Vth, and the voltage reference signal Vref is not equal to the reference value Vref_0 representing the expected value of the output voltage, the voltage reference signal Vref is adjusted to be consistent with the reference value Vref_0. In a preferred embodiment, the reference value Vref_0 is a fixed expected voltage value. Both the reference value Vref_0 and the voltage reference signal Vref are used to represent the output voltage, representing different expected values. When the absolute value of the voltage difference Vd is greater than the preset value Vth, the voltage reference signal adjustment circuit 121 adjusts the output voltage by dynamically adjusting the voltage reference signal Vref. When the absolute value of the voltage difference Vd is adjusted to be less than the preset value Vth, the voltage reference signal adjustment circuit 121 adjusts the voltage reference signal Vref to the reference value Vref_0, at which point the output voltage and the reference value Vref_0 are consistent.

[0068] Optionally, the voltage reference signal Vref and the output voltage sampling signal Vs are used to calculate the difference voltage Vd, and the difference voltage Vd satisfies Vd = Vref - Vs.

[0069] Furthermore, the voltage reference signal adjustment circuit 121 generates an adjustment signal Vt based on the relationship between the difference voltage Vd and the preset value Vth, as well as the sign of the difference voltage Vd. The voltage reference signal Vref is adjusted according to the adjustment signal Vt so that the changing trend of the voltage reference signal Vref is the same as the changing trend of the voltage sampling signal Vs.

[0070] Preferably, when the absolute value of the difference voltage Vd is greater than the preset value Vth and the difference voltage Vd is positive, the adjustment signal Vt is negative; when the absolute value of the difference voltage Vd is greater than the preset value Vth and the difference voltage Vd is negative, the adjustment signal Vt is positive. In one embodiment, the adjustment signal Vt is superimposed on a reference value Vref_0 representing the desired value of the output voltage to generate the voltage reference signal Vref for the next time step. In another embodiment, the adjustment signal Vt is superimposed on the voltage reference signal Vref for the current time step to generate the voltage reference signal Vref for the next time step.

[0071] If a sudden increase in load causes a sharp drop in the voltage sampling signal Vs, such that |Vd| > Vth and Vd > 0, then the amplitude of the voltage reference signal Vref needs to be reduced to decrease the difference voltage Vd. If a sudden decrease in load causes a sharp increase in the voltage sampling signal Vs, such that |Vd| > Vth and Vd < 0, then the amplitude of the voltage reference signal Vref needs to be increased to decrease the absolute value of the difference voltage Vd.

[0072] When the absolute value of the difference voltage Vd is made less than the preset value Vth by adjusting the voltage reference signal Vref, the control circuit 12 exits the maximum power output or minimum power output state. Through the control of the loop, the output voltage Vo follows the voltage sampling signal Vref. At this time, the average value of the inductor current is the load current, thus avoiding output voltage overshoot or oscillation.

[0073] When the differential voltage Vd is adjusted back to an absolute value less than the preset value Vth, the voltage reference signal adjustment circuit 121 makes the voltage reference signal Vref exactly equal to the fixed reference value Vref_0, so as to further ensure the accuracy of the system in steady state.

[0074] Figure 2 The flowchart of the voltage reference signal Vref adjustment method of the present invention specifically includes:

[0075] Step S21: Determine if the absolute value of the voltage difference Vd between the voltage reference signal Vref and the voltage sampling signal Vs is greater than the preset value Vth, and if the voltage difference Vd is positive, then decrease the voltage reference signal Vref; otherwise, proceed to step S22.

[0076] Step S22: Determine if the absolute value of the voltage difference Vd between the voltage reference signal Vref and the voltage sampling signal Vs is greater than a preset value Vth, and if the voltage difference Vd is negative. If so, increase the voltage reference signal Vref; otherwise, proceed to step S23.

[0077] Step S23: Determine whether the voltage reference signal Vref is not equal to its reference value Vref_0. If yes, restore the amplitude of the voltage reference signal Vref to the reference value Vref_0; otherwise, keep the amplitude of the voltage reference signal Vref at the current moment unchanged.

[0078] Therefore, in this embodiment of the switching power supply, when the output voltage deviates significantly from the expected value due to load fluctuations (the absolute value of the voltage difference is greater than the preset value), the amplitude of the voltage reference signal is adaptively adjusted to "actively catch up" with the output voltage. This is equivalent to instantaneously reducing the error signal of the control loop, thereby enabling the control circuit to exit the maximum or minimum power output state earlier, significantly shortening the recovery time and reducing voltage overshoot or oscillation. Furthermore, when the system returns to near steady state (the absolute value of the voltage difference is less than the preset value), the voltage reference signal is forced to recover to a fixed reference value, thereby eliminating the cumulative error that may be introduced by the adaptive adjustment process and ensuring the accuracy and stability of the output voltage.

[0079] It is understandable that the sequence of steps for adjusting the voltage reference signal Vref is not limited to... Figure 2In other embodiments, the order shown may be: first step S22, then step S21, and finally step S23; or, first step S23, then step S21, and finally step S22.

[0080] Figure 3 This is a schematic diagram of a switching power supply according to a second embodiment of the present invention. Figure 4 This is a waveform diagram of a switching power supply according to a second embodiment of the present invention. Figure 3 In the illustrated embodiment, the switching power supply includes a power switching circuit 11 and a control circuit 32. The control circuit 32 is used to generate a switching control signal PWM based at least on a current sampling signal ILs characterizing the instantaneous value of the inductor current in the power switching circuit 11 and a voltage sampling signal Vs characterizing the output voltage Vo of the power switching circuit 11.

[0081] In this embodiment of the invention, the control circuit 32 includes a voltage reference signal adjustment circuit 321, a set signal generation circuit 322, and a logic circuit 323.

[0082] The voltage reference signal conditioning circuit 321 and the voltage reference signal conditioning circuit 121 have the same circuit structure, connection relationship and working principle, and will not be described again here.

[0083] The set signal generation circuit 322 is based on the adaptively generated voltage reference signal Vref, the voltage sampling signal Vs representing the instantaneous value of the output voltage Vo, and the inductor current i. L The current sampling signal ILs and a ramp signal Vramp are used to generate a set signal Vs to indicate that the power device S1 in the power switch circuit 11 is turned on.

[0084] The set signal generation circuit 322 generates a set signal Vs for the power device S1 in the switching power supply based on the current sampling signal ILs and the first voltage V1. Optionally, the first voltage V1 is positively correlated with the difference voltage Vd and the integral signal Vint of the difference voltage Vd. In one embodiment, the first voltage V1 is the sum of the difference voltage Vd between the voltage reference voltage Vref and the voltage sampling signal Vs, the integral signal Vint of the difference voltage Vd, and a ramp signal Vramp. When the current sampling signal ILs reaches the threshold set by the first voltage V1, a valid set signal Vs is generated.

[0085] In a preferred embodiment, the set signal generation circuit 322 includes an error circuit G1, a proportional circuit 3221, an integral circuit 3222, a superposition circuit 3223, and a comparator circuit 3224. The error circuit G1 receives an adaptively generated voltage reference signal Vref and a voltage sampling signal Vs, and generates a difference voltage Vd based on the error between them. The proportional circuit 3221 multiplies the difference voltage Vd by a predetermined gain Kp to obtain a proportional signal Kp*Vd, where the gain Kp can be greater than or less than 1. The integral circuit 3222 integrates the difference voltage Vd to obtain an integral signal Vint, which represents the average value of the error between the voltage reference signal Vref and the voltage sampling signal Vs. The superposition circuit 3223 superimposes the proportional signal Kp*Vd, the integral signal Vint of the difference voltage Vd, and a ramp signal Vramp to obtain a first voltage V1. The comparator circuit 3224 receives the current sampling signal ILs and the first voltage V1 to generate a set signal Vs, which is valid when the current sampling signal ILs drops to the first voltage V1.

[0086] The logic circuit 323 generates the turn-on signal of the power device S1 in the switching power supply, i.e., the PWM signal in the effective state, based on the set signal Vs; and generates the turn-off signal of the power device S1 in the switching power supply, i.e., the PWM signal in the ineffective state, based on a fixed time signal COT.

[0087] The following is combined with Figure 4 The waveform diagram shown illustrates the working principle of control circuit 32:

[0088] During the t0~t1 phase, the load current Io remains constant at the first threshold, and the voltage reference signal Vref remains constant at the reference value Vref_0. When the current sampling signal ILs drops to the first voltage V1, which is jointly set by the proportional signal Kp*Vd of the voltage difference voltage Vd between the voltage reference signal Vref and the voltage sampling signal Vs, the integral signal Vint of the voltage difference voltage Vd, and a ramp signal Vramp, the set signal Vs becomes valid. When the set signal Vs is valid, the switch control signal PWM is in an active state (e.g., high level). In each switching cycle, when the time when the switch control signal PWM is in an active state (e.g., high level) lasts until the fixed on-time characterized by the fixed time signal COT, the switch control signal PWM jumps to an inactive state (e.g., low level).

[0089] When the output voltage fluctuates slightly, for example, when it increases to a value greater than that corresponding to the voltage reference signal Vref, the voltage difference Vd between the voltage reference signal Vref and the voltage sampling signal Vs decreases, causing the first voltage V1 to decrease. This lengthens the time it takes for the current sampling signal ILs to drop to the first voltage V1, thereby lengthening the switching cycle. This is equivalent to reducing the switching frequency, thus reducing the output voltage to maintain a constant output voltage by frequency reduction. The same principle applies when the output voltage decreases.

[0090] During the t1~t2 phase: At time t1, the load current Io jumps from the first threshold to the second threshold, switching from a light load to a heavy load. At this time, the output voltage Vo decreases rapidly, and the voltage difference Vd between the voltage reference signal Vref and the voltage sampling signal Vs increases. The current sampling signal ILs is less than the minimum value of the first voltage V1. During this time, the set signal Vs remains active, and the system outputs at maximum power. Since switching power supplies usually have a minimum off-time (Toff-min) setting, the power devices are not always on during this phase, but operate at the highest frequency. This causes the current sampling signal ILs to rise rapidly. When the inductor current i L When the output voltage Vo drops to its lowest value, equal to the load current Io, the system still operates at maximum power output, further increasing the output voltage Vo and the inductor current i. L The voltage gradually increases beyond the load current Io. Because the present invention uses an adaptive voltage reference signal Vref, the amplitude of the voltage reference signal Vref decreases synchronously with the changing trend of the output voltage Vo. Therefore, when the inductor current i... L After the load current Io exceeds the current, the output voltage Vo will quickly recover to the expected value represented by the voltage reference signal Vref. At this time, the system exits the maximum power output state, the inductor current IL stops rising, and remains at its current value. Because this invention uses an adaptive voltage reference signal Vref, when the load changes at time t1, due to the sudden drop in output voltage Vo, the voltage reference signal adjustment circuit 321 causes the voltage reference signal Vref to decrease synchronously with the changing trend of output voltage Vo. This advances the time when the output voltage Vo recovers to the expected value represented by the voltage reference signal Vref, reducing the time the system operates in the maximum power output state. Therefore, the inductor current I... L The peak value is reduced, thus reducing the energy required to charge the output capacitor Co of the switching power supply. This prevents the output voltage Vo from rising above the voltage value represented by the reference value Vref_0, thereby avoiding overshoot of the output voltage Vo. At time t2, the amplitude of the voltage reference signal Vref gradually recovers to the reference value Vref_0, and the output voltage Vo follows the gradual change of the voltage reference signal Vref until it stabilizes at the voltage value represented by the reference value Vref_0.

[0091] Here, it should be noted that the reason why the first voltage V1 has a minimum value and a maximum value is that the ramp signal Vramp changes periodically. It rises from a predetermined value in each period and then resets to the predetermined value when the next period arrives. Therefore, the moments of the minimum value and the maximum value of the first voltage V1 correspond to the moments of the minimum value and the maximum value of the ramp signal Vramp, respectively.

[0092] It should also be noted that during the dynamic process, although the current sampling signal ILs and the integral signal Vint of the differential voltage Vd also change, the differential voltage Vd between the voltage reference signal Vref and the voltage sampling signal Vs dominates the dynamic regulation process. That is, the proportional signal Kp*Vd dominates the dynamic regulation process. Therefore, when the load current Io suddenly increases and causes the output voltage Vo to suddenly drop, the differential voltage Vd between the voltage reference signal Vref and the voltage sampling signal Vs increases. As a result, the first voltage V1 increases, causing the current sampling signal ILs to be less than the minimum value of the first voltage. At this time, the set signal Vs remains in the valid state, and the on / off of the power device is controlled by the minimum off-time. Therefore, the inductor current i L rises rapidly. When the voltage reference signal Vref and the voltage sampling signal Vs are close, the power device will end the control of the minimum off-time. Because the technical solution of the present invention will cause the voltage reference signal Vref to decrease synchronously with the output voltage Vo, the time for the output voltage Vo to return to the voltage value corresponding to the voltage reference signal Vref becomes shorter. That is, the power device ends the control of the minimum off-time, which means that the moment when the system exits the maximum power output state is earlier than the prior art.

[0093] It should also be noted that the value of the preset value Vth in the embodiment of the present invention needs to satisfy: when switching from light load to heavy load, the decrease of the voltage reference signal Vref needs to make ILs - Kp∙(Vref - Vs) - Vint < Vramp_min hold; when switching from heavy load to light load, the increase of the voltage reference signal Vref needs to make ILs - Kp∙(Vref - Vs) - Vint > Vramp_max hold. Here, Vramp_min and Vramp_max are the minimum value and the maximum value of the ramp signal Vramp, respectively, and the frequency of the ramp signal Vramp is the same as the frequency of the switching control signal PWM.

[0094] Figure 5 This is the working waveform diagram of the switching power supply of the comparative example of the present invention. It is assumed that the switching power supply of the comparative example has a fixed voltage reference signal Vref.

[0095] During the t0~t1 phase: At time t0, the load switches from light load to heavy load, causing the output voltage Vo to drop rapidly. Because the voltage difference Vd between the voltage reference signal Vref and the voltage sampling signal Vs increases, the current sampling signal ILs becomes less than the minimum value of the first voltage V1. At this time, the system operates at maximum power output, and the inductor current IL rises rapidly. At time t1, when the inductor current IL equals the load current Io, the output voltage Vo drops to its lowest value.

[0096] t1~t2 stage: During this stage, the output voltage Vo is still lower than the expected value represented by the voltage reference signal Vref, and the system still operates at maximum power output, causing the output voltage Vo to gradually increase, and the inductor current i L The voltage gradually exceeds the load current Io. When the output voltage Vo rises to the voltage reference signal Vref, the system exits the maximum power output state, at which point the inductor current i L Rise to the maximum value;

[0097] During the t2~t3 phase: At time t2, the voltage reference signal Vref is equal to the output voltage Vo, and the inductor current i L The excess energy in the inductor, exceeding the load current Io, charges the output capacitor Co, causing the output voltage Vo to continue increasing. This results in the current sampling signal ILs exceeding the maximum value of the first voltage V1. Until the output voltage Vo drops to the expected value represented by the voltage reference signal Vref, the system does not generate a valid switching control signal PWM. Therefore, it is evident that existing control methods pump the output voltage Vo high during load transitions, easily leading to overshoot.

[0098] Figure 6 Here is another operating waveform diagram of the switching power supply according to the second embodiment of the present invention:

[0099] During the t0~t1 stage: At time t0, the load current jumps from the first threshold to the second threshold, switching from a light load to a heavy load. At this time, the output voltage Vo decreases rapidly. As the differential voltage Vd increases, the current sampling signal ILs is less than the minimum value of the first voltage V1. The system outputs at maximum power, and the current sampling signal ILs rises rapidly. When the inductor current i L When the voltage Vo is equal to the load current Io, the output voltage Vo drops to its lowest value.

[0100] t1~t2: During this stage, the output voltage Vo is still lower than the expected value represented by the voltage reference signal Vref. The system continues to operate at maximum power output, causing the output voltage Vo to gradually increase, and the inductor current i L The current gradually exceeds the load current Io. When the voltage reference signal Vref rises to equal the voltage sampling signal Vs, the system exits the maximum power output state. At time t2, the inductor current iL The voltage rises to its maximum value; since the voltage reference signal Vref also decreases as the output voltage Vo decreases, the control method of this invention advances time t2 compared to the traditional control method, thus the inductor current i L The peak current is reduced, so the energy used to charge the output capacitor Co of the switching power supply is reduced, which prevents the output voltage Vo from rising above the voltage value represented by the reference value Vref_0, thus avoiding overshoot of the output voltage Vo.

[0101] t2~t3: During this stage, the output voltage Vo is still lower than the voltage value represented by the reference value Vref_0, and the inductor current i L The voltage reference signal Vref gradually decreases until it equals the load current Io. The voltage reference signal Vref slowly recovers to its reference value Vref_0, and the output voltage Vo slowly recovers to the voltage value represented by the reference value Vref_0, so as to maintain the constant output voltage Vo. It can be seen that the switching power supply of the present invention avoids overshoot of the output voltage Vo by adaptively adjusting the amplitude of the voltage reference signal Vref, without affecting the stability of the output voltage Vo in steady state.

[0102] Similarly, when the load suddenly switches from heavy load to light load, the switching power supply of the present invention can also avoid the situation where the system operates in the minimum power output state for too long due to the current sampling signal ILs being greater than the maximum value of the first voltage V1 for a long time, which would lead to the output voltage Vo oscillation (when the output voltage Vo drops from the peak value to the voltage value represented by the reference value Vref_0, it continues to drop to a voltage value lower than the voltage value represented by the reference value Vref_0, and then recovers to the voltage value represented by the reference value Vref_0).

[0103] like Figure 7 The diagram shown is a structural schematic of a switching power supply according to a third embodiment of the present invention. Figure 7 The diagram shown is a waveform diagram of the switching power supply according to the third embodiment of the present invention. In some applications, it is required that the output voltage Vo changes with the output current to reduce the peak-to-peak value of the output voltage during load changes, thereby improving stability. Based on this requirement, the structure of the switching power supply according to the third embodiment of the present invention is proposed.

[0104] refer to Figure 7The switching power supply includes a power switching circuit 71 and a control circuit 72. The control circuit 72 includes a voltage reference signal conditioning circuit 721, a set signal generation circuit 722, and a logic circuit 723. The structures and operating principles of the power switching circuit 71, the voltage reference signal conditioning circuit 721, and the logic circuit 723 are the same as those of the power switching circuit 11, the voltage reference signal conditioning circuit 321, and the logic circuit 323 in the second embodiment, and will not be repeated here. The focus here is on the structure and operating principle of the set signal generation circuit 722. In this embodiment, the set signal generation circuit changes the integral signal by adjusting the output characteristics of the output voltage to improve the transient response capability of the switching power supply and reduce load losses. Specifically, the set signal generation circuit 722 adjusts the voltage sampling signal by increasing the dropout voltage Vdroop to achieve the above-described function.

[0105] In this embodiment of the invention, the set signal generation circuit 722 generates a set signal Vs for the power device S1 in the switching power supply based on the current sampling signal ILs and the first voltage V1. Optionally, the first voltage V1 is positively correlated with both the difference voltage Vd and the integral signal Vint1 of the first difference voltage Vd1. In one embodiment, the first voltage V1 is the sum of the difference voltage Vd between the voltage reference voltage Vref and the voltage sampling signal Vs, the integral signal Vint1 of the first difference voltage Vd1, and a ramp signal Vramp. When the current sampling signal ILs reaches the threshold set by the first voltage V1, a valid set signal Vs is generated.

[0106] It should be noted that, in this embodiment of the invention, the first differential voltage Vd1 is the difference between the voltage reference signal Vref and the voltage sampling signal Vs at the current moment, and a drop voltage Vdroop, i.e., Vd1 = Vref - Vs - Vdroop. Furthermore, the value of the drop voltage Vdroop follows the same trend as the load current Io, meaning it is positively correlated with the load current Io. This aims to ensure that when the load current Io is small, the output voltage Vo remains stable at a higher reference value; and when the load current Io is large, the output voltage Vo remains stable at a lower reference value. Thus, when the load current Io switches from a light load to a heavy load, the output voltage Vo will drop sharply from the higher reference value. Subsequently, when the load current Io switches from a light load to a light load again, the output voltage Vo will rise sharply from the lower reference value. This configuration allows the peak-to-peak value of the output voltage Vo to be reduced during multiple load changes.

[0107] In a preferred embodiment, the set signal generation circuit 722 includes an error circuit G1, an error circuit G2, a proportional circuit 7221, an integral circuit 7222, a superposition circuit 7223, and a comparator circuit 7224. The error circuit G1 receives an adaptively generated voltage reference signal Vref and a voltage sampling signal Vs, and generates a difference voltage Vd based on the error between them. The error circuit G2 receives the adaptively generated voltage reference signal Vref, the voltage sampling signal Vs, and a drop voltage Vdroop, and generates a first difference voltage Vd1 based on the difference between the voltage reference signal Vref and the drop voltage Vdroop, and the error between the voltage sampling signal Vs and the difference Vd1. The proportional circuit 7221 multiplies the difference voltage Vd by a predetermined gain Kp to obtain a proportional signal Kp*Vd, where the gain Kp can be greater than 1 or less than 1. Integrating circuit 7222 integrates the first difference voltage Vd1 to obtain an integrated signal Vint1. Vint1 represents the average error between the voltage reference signal Vref and the drop voltage Vdroop, and the voltage sampling signal Vs. Superposition circuit 7223 superimposes the proportional signal Kp*Vd, the integrated signal Vint1 of the first difference voltage Vd1, and a ramp signal Vramp to obtain the first voltage V1. Comparison circuit 7224 receives the current sampling signal ILs and the first voltage V1 to generate a set signal Vs. The set signal is valid when the current sampling signal ILs drops to the first voltage V1. Those skilled in the art should understand that in this embodiment, the drop voltage can adjust the voltage sampling signal Vs or the voltage reference signal Vref; therefore, the drop voltage can also be placed at the negative input of the error circuit G2. Compared with the second embodiment, the technical solution of this embodiment can be equivalent to a preset value Vth' also being related to a drop voltage Vdroop. In a preferred embodiment, the preset range Vth' is the sum of the first preset range Vth1 and the drop voltage Vdroop. This is actually equivalent to the difference between the differential voltage Vd and the drop voltage Vdroop being controlled within the first preset range Vth1. Here, the first preset range Vth1 is the design value without considering the drop voltage Vdroop.

[0108] When the output voltage of the switching power supply in this embodiment of the invention deviates significantly from the expected value due to load fluctuations, such as... Figure 8As shown, by adaptively adjusting the amplitude of the voltage reference signal, the difference between it and the voltage drop "actively catches up" with the output voltage. This is equivalent to instantaneously reducing the error signal of the control loop, allowing the control circuit to exit the maximum or minimum power output state earlier, significantly shortening the recovery time and reducing voltage overshoot or oscillation. Furthermore, when the system returns to near steady state, the voltage reference signal is forced to recover to a fixed reference value, thereby eliminating the cumulative error that may be introduced by the adaptive adjustment process, ensuring the accuracy and stability of the output voltage. Even further, this causes the output voltage to decrease as the load current increases, reducing the peak-to-peak value of the output voltage during load changes.

[0109] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A control method applied in a switching power supply, characterized in that, include: Acquire a voltage sampling signal that represents the instantaneous value of the output voltage of the switching power supply; When the load current switches, the voltage reference signal is adjusted according to the changing trend of the voltage sampling signal so that the changing trend of the voltage reference signal is the same as that of the voltage sampling signal; and a switching control signal is generated based on the voltage reference signal, the voltage sampling signal and the current sampling signal representing the instantaneous value of the inductor current of the switching power supply to periodically control the switching state of the power devices of the switching power supply, thereby reducing the fluctuation of the output voltage.

2. The control method according to claim 1, characterized in that, It also includes, Obtain the voltage difference between the voltage reference signal and the voltage sampling signal; and determine the relationship between the absolute value of the voltage difference and a preset value. When the absolute value of the difference voltage is less than the preset value, the voltage reference signal remains unchanged; When the absolute value of the voltage difference is greater than the preset value, the voltage reference signal is adjusted periodically until the absolute value of the voltage difference is less than the preset value.

3. The control method according to claim 2, characterized in that, When the absolute value of the voltage difference is greater than the preset value and the voltage difference is positive, the voltage reference signal is decreased; when the absolute value of the voltage difference is greater than the preset value and the voltage difference is negative, the voltage reference signal is increased.

4. The control method according to claim 2, characterized in that, When the absolute value of the difference voltage is less than the preset value, the voltage reference signal is maintained at a reference value that characterizes the expected value of the output voltage.

5. The control method according to claim 2, characterized in that, Based on the relationship between the difference voltage and the preset value, and the sign of the difference, an adjustment signal is generated. The adjustment signal is then superimposed on a reference value that represents the desired value of the output voltage to adjust the voltage reference signal.

6. The control method according to claim 5, characterized in that, When the absolute value of the difference voltage is greater than the preset value and the difference is positive, the adjustment signal is negative; when the absolute value of the difference voltage is greater than the preset value and the difference is negative, the adjustment signal is positive.

7. The control method according to claim 2, characterized in that, Based on the relationship between the voltage difference and the preset value, and the sign of the voltage difference, an adjustment signal is generated. The adjustment signal is then superimposed on the voltage reference signal at the current moment to generate the voltage reference signal at the next moment.

8. The control method according to any one of claims 2-7, characterized in that, The set signal of the power device in the switching power supply is generated based on the current sampling signal and the first voltage, wherein the first voltage is positively correlated with the difference voltage and the integral signal of the difference voltage.

9. The control method according to claim 8, characterized in that, The first voltage is the sum of the difference voltage, the integral signal of the difference voltage, and a ramp signal.

10. The control method according to claim 9, characterized in that, When the current sampling signal reaches the first voltage, the set signal is in an active state.

11. The control method according to claim 1, characterized in that, The power device in the switching power supply is turned off based on a fixed-time signal.

12. The control method according to claim 8, characterized in that, When the current sampling signal is less than the minimum value of the first voltage, the switching power supply operates based on the minimum off time to output maximum power.

13. The control method according to claim 8, characterized in that, When the current sampling signal is greater than the maximum value of the first voltage, the set signal remains in an invalid state.

14. The control method according to claim 2, characterized in that, The preset value is also related to a drop voltage, the value of which has the same trend as the load current of the switching power supply.

15. The control method according to claim 14, characterized in that, The preset value is the sum of the first preset value and the drop voltage.

16. A control circuit applied to a switching power supply, characterized in that, include: A voltage sampling circuit is used to acquire a voltage sampling signal that represents the instantaneous value of the output voltage of the switching power supply; A voltage reference signal adjustment circuit is used to adjust the voltage reference signal according to the changing trend of the voltage sampling signal when the load current switches, so that the changing trend of the voltage reference signal is the same as the changing trend of the voltage sampling signal. as well as A set signal generation circuit is used to generate a switch control signal based on the voltage reference signal, the voltage sampling signal, and the current sampling signal characterizing the instantaneous value of the inductor current of the switching power supply, so as to periodically control the switching state of the power devices of the switching power supply, thereby reducing the fluctuation of the output voltage.

17. The control circuit according to claim 16, characterized in that, The voltage reference adjustment circuit is also used to obtain the voltage difference between the voltage reference signal and the voltage sampling signal, and to determine the relationship between the absolute value of the voltage difference and a preset value. When the absolute value of the difference voltage is less than the preset value, the voltage reference signal adjustment circuit maintains the voltage reference signal unchanged; When the absolute value of the difference voltage is greater than the preset value, the voltage reference signal adjustment circuit adjusts the voltage reference signal cycle by cycle until the absolute value of the difference voltage is less than the preset value.

18. The control circuit according to claim 17, characterized in that, When the absolute value of the difference voltage is greater than the preset value and the difference voltage is positive, the voltage reference signal adjustment circuit decreases the voltage reference signal; when the absolute value of the difference voltage is greater than the preset value and the difference voltage is negative, the voltage reference signal adjustment circuit increases the voltage reference signal.

19. The control circuit according to claim 17, characterized in that, When the absolute value of the difference voltage is less than the preset value, the voltage reference signal adjustment circuit maintains the voltage reference signal at a reference value that characterizes the desired value of the output voltage.

20. The control circuit according to claim 17, characterized in that, The voltage reference signal adjustment circuit generates an adjustment signal based on the relationship between the difference voltage and the preset value, as well as the sign of the difference. The adjustment signal is then superimposed on a reference value that represents the desired value of the output voltage to adjust the voltage reference signal.

21. The control circuit according to claim 20, characterized in that, When the absolute value of the difference voltage is greater than the preset value and the difference is positive, the adjustment signal is negative; when the absolute value of the difference voltage is greater than the preset value and the difference is negative, the adjustment signal is positive.

22. The control method according to claim 17, characterized in that, The voltage reference signal adjustment circuit generates an adjustment signal based on the relationship between the difference voltage and the preset value, as well as the sign of the difference. The adjustment signal is then superimposed on the voltage reference signal at the current moment to generate the voltage reference signal at the next moment.

23. The control circuit according to any one of claims 17-22, characterized in that, The set signal generation circuit generates a set signal for the power device in the switching power supply based on the current sampling signal and the first voltage. The first voltage is positively correlated with both the difference voltage and the integral signal of the difference voltage.

24. The control circuit according to claim 23, characterized in that, The first voltage is the sum of the difference voltage, the integral signal of the difference voltage, and a ramp signal.

25. The control circuit according to claim 24, characterized in that, The set signal generation circuit includes a comparator. The first input terminal of the comparator receives the first voltage, and the second input terminal receives the current sampling signal. When the current sampling signal reaches the first voltage, the comparator outputs a set signal indicating a valid state.

26. The control circuit according to claim 23, characterized in that, The control circuit generates a turn-off signal for the power devices in the switching power supply based on a fixed time signal.

27. The control circuit according to claim 23, characterized in that, When the current sampling signal is less than the minimum value of the first voltage, the set signal generation circuit outputs an invalid set signal so that the switching power supply operates based on the minimum off time to output maximum power.

28. The control circuit according to claim 23, characterized in that, When the current sampling signal is greater than the maximum value of the first voltage, the set signal generation circuit keeps the set signal in an invalid state.

29. The control circuit according to claim 17, characterized in that, The preset value is also related to a drop voltage, the value of which has the same trend as the load current of the switching power supply.

30. The control circuit according to claim 29, characterized in that, The preset value is the sum of the first preset value and the drop voltage.

31. A switching power supply, characterized in that, include: Power stage circuits, and The control circuit according to any one of claims 16-30.

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