Load current sampling circuit, buck converter and power supply chip

Abstract

The disclosure provides a load current sampling circuit, a Buck converter and a power supply chip, comprising an inductor current sampling circuit and a filtering circuit. The resistance value of the filtering resistor can be adjusted based on the duty cycle of the Buck converter through the filtering circuit to compensate for the sampling bandwidth. When the lower tube is turned on, the current flowing through the lower tube is sampled through the inductor current sampling circuit to obtain an inductor current sampling voltage. The inductor current sampling voltage is filtered by the filtering circuit based on the adjusted filtering resistor to determine the average value of the inductor current sampling voltage to obtain a load current sampling voltage. Since the resistance value of the filtering resistor is negatively related to the duty cycle, the resistance value of the filtering resistor can be reduced at a large duty cycle to compensate for the influence of the duty cycle on the sampling bandwidth, thereby ensuring the current sampling speed and the stability of the control loop.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more particularly to a load current sampling circuit, a Buck converter, and a power supply chip. Background Technology

[0002] The buck converter is one of the basic topologies of direct current (DC) to DC converters. In the constant current control architecture of the buck converter, the load current needs to be sampled, and the buck converter is controlled based on the sampled load current. Typically, the inductor current of the buck converter can be sampled for a full cycle or half a cycle to obtain the load current sampling voltage. Half-cycle sampling refers to sampling the current flowing through the lower transistor, while full-cycle sampling refers to sampling the current flowing through both the lower and upper transistors. Half-cycle sampling circuits can minimize design complexity and chip area.

[0003] In existing technologies, a half-cycle sampling circuit samples the current flowing through the lower transistor to obtain the inductor current sampling voltage. This voltage is then filtered by a filter circuit to obtain the average value of the inductor current sampling voltage, which is the load current sampling voltage. However, the time constant of this filter circuit is affected by the duty cycle of the Buck converter, resulting in a lower sampling bandwidth at large duty cycles, which in turn affects the current sampling speed and the stability of the control loop. Summary of the Invention

[0004] This disclosure provides a load current sampling circuit, a Buck converter, and a power supply chip that can compensate for the influence of duty cycle on sampling bandwidth, thereby ensuring current sampling speed and the stability of the control loop.

[0005] In a first aspect, this disclosure provides a load current sampling circuit applied to a Buck converter. The Buck converter includes an upper transistor connected between a voltage input terminal and a switching node, a lower transistor connected between the switching node and ground, and an inductor connected between the switching node and a voltage output terminal. The load current sampling circuit includes an inductor current sampling circuit and a filtering circuit.

[0006] The inductor current sampling circuit is configured to sample the current flowing through the lower transistor when the lower transistor is turned on, and obtain the inductor current sampling voltage.

[0007] The filtering circuit is configured to adjust the resistance value of the filter resistor based on the duty cycle of the Buck converter to compensate for the sampling bandwidth, and when the lower transistor is turned on, filter the inductor current sampling voltage based on the adjusted filter resistor to determine the average value of the inductor current sampling voltage and obtain the load current sampling voltage; wherein the resistance value of the filter resistor is negatively correlated with the duty cycle.

[0008] In some embodiments of this disclosure, the filtering circuit includes a filter control switch, a resistor adjustment circuit, and a filter capacitor. The control terminal of the filter control switch is connected to the control terminal of the lower transistor. The input terminal of the filter control switch is connected to the output terminal of the inductor current sampling circuit. The output terminal of the filter control switch is connected to the first plate of the filter capacitor and the output terminal of the load current sampling circuit through the resistor adjustment circuit. The second plate of the filter capacitor is grounded.

[0009] The resistor adjustment circuit is configured to determine the duty cycle based on the input voltage and output voltage of the Buck converter, and to connect at least one resistor based on the duty cycle to adjust the resistance value of the filter resistor.

[0010] In some embodiments of this disclosure, the resistor adjustment circuit includes a voltage sampling circuit, an adjustment control circuit, a base resistor, and an adjustment resistor unit. The first input terminal of the voltage sampling circuit is connected to the voltage input terminal, the second input terminal of the voltage sampling circuit is connected to the voltage output terminal, the output terminal of the voltage sampling circuit is connected to the input terminal of the adjustment control circuit, the output terminal of the adjustment control circuit is connected to the control terminal of the adjustment resistor unit, and the base resistor and the adjustment resistor unit are connected in series between the output terminal of the filter control switch and the output terminal of the load current sampling circuit.

[0011] The voltage sampling circuit is configured to sample the input voltage to obtain an input sampling voltage; and to sample the output voltage to obtain an output sampling voltage.

[0012] The adjustment control circuit is configured to determine the duty cycle range in which the duty cycle is located based on the output sampling voltage and the input sampling voltage, and generate a corresponding indication signal.

[0013] The adjustment resistor unit is configured to connect a corresponding adjustment resistor based on the indication signal, so as to form the filter resistor together with the base resistor.

[0014] In some embodiments of this disclosure, the voltage sampling circuit includes a first voltage sampling circuit and a second voltage sampling circuit. The input terminal of the first voltage sampling circuit is connected to the voltage input terminal. The plurality of output terminals of the first voltage sampling circuit are connected one-to-one with the plurality of first input terminals of the adjustment control circuit. The input terminal of the second voltage sampling circuit is connected to the voltage output terminal, and the output terminal of the second voltage sampling circuit is connected to the second input terminal of the adjustment control circuit.

[0015] The first voltage sampling circuit is configured to sample the input voltage based on multiple different first sampling coefficients to obtain multiple different input sample voltages.

[0016] The second voltage sampling circuit is configured to sample the output voltage based on a second sampling coefficient to obtain the output sampled voltage, wherein the second sampling coefficient is greater than the first sampling coefficient.

[0017] In some embodiments of this disclosure, the trimming control circuit includes a plurality of comparators, the inverting input terminals of the plurality of comparators being connected one-to-one with a plurality of output terminals of the first voltage sampling circuit, the non-inverting input terminals of the plurality of comparators being connected to the output terminals of the second voltage sampling circuit, and the output terminals of the plurality of comparators being connected one-to-one with a plurality of control terminals of the trimming resistor unit.

[0018] In some embodiments of this disclosure, the trimming resistor unit includes a plurality of trimming resistors and a plurality of trimming switching transistors. The plurality of trimming resistors are connected in series between the base resistor and the output terminal of the load current sampling circuit. The control terminals of the plurality of trimming switching transistors are connected one-to-one with the output terminals of the plurality of comparators. The plurality of trimming resistors and the plurality of trimming switching transistors are connected in parallel one-to-one.

[0019] In some embodiments of this disclosure, the first voltage sampling circuit includes a plurality of voltage sampling resistors, which are connected in series between the voltage input terminal and ground, and the connection point of two adjacent voltage sampling resistors is one output terminal of the first voltage sampling circuit.

[0020] In some embodiments of this disclosure, the inductor current sampling circuit includes a sampling transistor, an operational amplifier, a transistor, a current mirror, and a current sampling resistor. The control terminal of the sampling transistor is connected to the control terminal of the lower transistor. The first terminal of the sampling transistor is connected to the inverting input terminal of the operational amplifier and the first terminal of the transistor. The second terminal of the sampling transistor is connected to the switching node. The output terminal of the operational amplifier is connected to the control terminal of the transistor. The second terminal of the transistor is connected to the input terminal of the current mirror. The output terminal of the current mirror is connected to the first terminal of the current sampling resistor and the input terminal of the filter circuit. The second terminal of the current sampling resistor and the non-inverting input terminal of the operational amplifier are grounded.

[0021] Secondly, this disclosure provides a Buck converter including an upper transistor, a lower transistor, an inductor, and any of the load current sampling circuits provided in the first aspect.

[0022] The upper transistor is connected between the voltage input terminal and the switching node, the lower transistor is connected between the switching node and ground, and the inductor is connected between the switching node and the voltage output terminal.

[0023] Thirdly, this disclosure provides a power supply chip, including any of the load current sampling circuits provided in the first aspect.

[0024] In the technical solution of this embodiment, the load current sampling circuit includes an inductor current sampling circuit and a filter circuit. The filter circuit adjusts the resistance value of the filter resistor based on the duty cycle of the Buck converter to compensate for the sampling bandwidth. When the down transistor is turned on, the inductor current sampling circuit samples the current flowing through the down transistor to obtain the inductor current sampling voltage. The filter circuit filters the inductor current sampling voltage based on the adjusted filter resistor to determine the average value of the inductor current sampling voltage, thus obtaining the load current sampling voltage. Since the resistance value of the filter resistor is negatively correlated with the duty cycle, the resistance value can be reduced at large duty cycles to compensate for the influence of the duty cycle on the sampling bandwidth, thereby ensuring the current sampling speed and the stability of the control loop.

[0025] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein: Figure 1 A circuit diagram of a Buck converter provided for the prior art.

[0027] Figure 2 This is a circuit diagram of a lower transistor current sampling circuit provided by the prior art.

[0028] Figure 3 for Figure 2 The diagram shows the voltage waveform of a key node in the lower transistor current sampling circuit.

[0029] Figure 4 for Figure 2 The equivalent circuit diagram of the small-signal model of the lower transistor current sampling circuit is shown.

[0030] Figure 5 (a) and Figure 5 (b) is Figure 2 The diagram shows the response time of the lower transistor current sampling circuit under different duty cycles.

[0031] Figure 6 This is a schematic diagram of the structure of a Buck converter provided in an embodiment of this disclosure.

[0032] Figure 7 This is a circuit diagram of a load current sampling circuit provided in an embodiment of the present disclosure.

[0033] Figure 8 This is a circuit diagram of a resistor adjustment circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0035] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement “connecting” two or more parts together shall mean that the parts are joined directly together or joined through one or more intermediate components.

[0036] In this disclosure, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure can be combined with other embodiments.

[0037] Furthermore, the terms "first," "second," etc., in the specification, claims, or the accompanying drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0038] In this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three possibilities: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0039] In the description of this disclosure, unless otherwise stated, "multiple" and "at least two" mean two or more (including two), and similarly, "multiple groups" and "at least two groups" mean two or more (including two groups).

[0040] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0041] Figure 1 A circuit diagram of a Buck converter provided for the prior art, such as... Figure 1 As shown, the Buck converter 100 includes an upper transistor MH, a lower transistor ML, an inductor L, and an output capacitor Cout. The upper transistor MH and the lower transistor ML are connected in series between the voltage input terminal of the Buck converter 100 and ground. The connection point of the upper transistor MH and the lower transistor ML is the switching node SW. The switching node SW is connected to the voltage output terminal of the Buck converter 100 through the inductor L. The output capacitor Cout is connected between the voltage output terminal and ground.

[0042] The Buck converter 100 also includes a constant current control loop, which includes a lower transistor current sampling circuit 110, a loop operational amplifier 120, a pulse width modulation circuit 130, and a drive control circuit 140. The input terminal of the lower transistor current sampling circuit 110 is connected to the switching node SW, the output terminal of the lower transistor current sampling circuit 110 is connected to the first input terminal of the loop operational amplifier 120, the second input terminal of the loop operational amplifier 120 is connected to the reference voltage Vref, the output terminal of the loop operational amplifier 120 is connected to the input terminal of the drive control circuit 140 through the pulse width modulation circuit 130, the first output terminal of the drive control circuit 140 is connected to the control terminal of the upper transistor MH, and the second output terminal of the drive control circuit 140 is connected to the control terminal of the lower transistor ML.

[0043] When the lower transistor ML is turned on, the lower transistor current sampling circuit 110 samples the current flowing through the lower transistor ML, that is, samples the inductor current IL, obtains the inductor current sampling voltage VCS_L, and determines the average value of the inductor current sampling voltage VCS_L. Since the average value of the inductor current IL is equal to the load current ILOAD, the average value of the inductor current sampling voltage VCS_L is equal to the load current sampling voltage VCS_LOAD.

[0044] The loop operational amplifier 120 receives the load current sampling voltage VCS_LOAD and determines the voltage signal Vcomp based on the load current sampling voltage VCS_LOAD and the reference voltage Vref. The pulse width modulation circuit 130 modulates the voltage signal Vcomp into a pulse signal VPWM. The drive control circuit 140 generates the upper MOSFET control signal VGH and the lower MOSFET control signal VGL based on the pulse signal VPWM. Based on the upper MOSFET control signal VGH, it controls the upper MOSFET MH to turn on or off, and based on the lower MOSFET control signal VGL, it controls the lower MOSFET ML to turn on or off, thereby realizing the constant current control of the Buck converter 100.

[0045] Since the lower transistor current sampling circuit 110 obtains the load current sampling voltage VCS_LOAD by only sampling the current flowing through the lower transistor ML, the lower transistor current sampling circuit 110 is a half-cycle sampling. Compared with the conventional full-cycle sampling (sampling the current flowing through the lower transistor ML when it is turned on, and sampling the current flowing through the upper transistor MH when it is turned on), the implementation circuit of half-cycle sampling is simpler and can minimize the circuit design difficulty and chip area.

[0046] Figure 2 A circuit diagram of a lower transistor current sampling circuit is provided for the prior art, such as... Figure 2 As shown, the lower transistor current sampling circuit 110 includes a sampling transistor MLS, an operational amplifier OPA, a first transistor M1, a current mirror 111, a current sampling resistor RCS, and a filter circuit 112. Combined with... Figure 1 and Figure 2As shown, the control terminal of the sampling transistor MLS is connected to the control terminal of the lower transistor ML. The first terminal of the sampling transistor MLS is connected to the inverting input terminal of the operational amplifier OPA and the first terminal of the first transistor M1. The second terminal of the sampling transistor MLS is connected to the switching node SW. The output terminal of the operational amplifier OPA is connected to the control terminal of the first transistor M1. The second terminal of the first transistor M1 is connected to the input terminal of the current mirror 111. The output terminal of the current mirror 111 is connected to the first terminal of the current sampling resistor RCS and the input terminal of the filter circuit 112. The second terminal of the current sampling resistor RCS and the non-inverting input terminal of the operational amplifier OPA are grounded.

[0047] The current mirror 111 includes a second transistor M2 and a third transistor M3. The first terminal of the second transistor M2 and the first terminal of the third transistor M3 are connected to the power supply voltage VDD. The control terminal of the second transistor M2 is connected to the second terminal of the second transistor M2, the control terminal of the third transistor M3 and the second terminal of the first transistor M1. The second terminal of the third transistor M3 is connected to the first terminal of the current sampling resistor RCS and the input terminal of the filter circuit 112.

[0048] When the lower transistor ML is turned on, the sampling transistor MLS is turned on and forms a mirror circuit with the lower transistor ML. The sampling transistor MLS can mirror the inductor current IL into the inductor sampling current IL_SNS. The operational amplifier OPA and the current mirror 111 work together to inject the inductor sampling current IL_SNS into the current sampling resistor RCS, and generate a voltage at the first end of the current sampling resistor RCS (the input end of the filter circuit 112), which is the inductor current sampling voltage VCS_L.

[0049] The filter circuit 112 includes a filter control switch M4, a filter resistor RF, and a filter capacitor CF. The control terminal of the filter control switch M4 is connected to the control terminal of the lower transistor ML. The input terminal of the filter control switch M4 is connected to the output terminal of the current mirror 111. The output terminal of the filter control switch M4 is connected to the first plate of the filter capacitor CF and the output terminal of the lower transistor current sampling circuit 110 through the filter resistor RF. The second plate of the filter capacitor CF is grounded.

[0050] When the down transistor ML is turned on, the filter control switch M4 is also turned on, and the filter circuit 112 is in operation to perform low-pass filtering on the inductor current sampling voltage VCS_L. When the down transistor ML is turned off, the filter control switch M4 is turned off, and the filter circuit 112 stops working. The on-resistance of the filter control switch M4 is much smaller than the resistance of the filter resistor RF.

[0051] Figure 3 for Figure 2 The waveform diagram of the key node of the lower transistor current sampling circuit is shown below. Figure 3As shown, during time T1 of each switching cycle Tsw, the lower transistor control signal VGL is high, the lower transistor ML is in the on state, the inductor current IL decreases linearly, and the corresponding inductor current sampling voltage VCS_L decreases linearly. During time T2 of each switching cycle Tsw, the lower transistor control signal VGL is low, the lower transistor ML is in the off state, and the inductor current sampling voltage VCS_L is 0.

[0052] Figure 4 for Figure 2 The equivalent circuit diagram of the small-signal model of the lower transistor current sampling circuit shown is as follows: Figure 4 As shown, from the perspective of small signals, the time constant of the filter circuit 112 is modulated by the duty cycle D of the Buck converter 10, forming a duty cycle filtering effect. The bandwidth of the lower transistor current sampling circuit 110 is (1-D) / R. F C F Among them, R F C is the resistance value of the filter resistor RF. F The value of the filter capacitor CF is given. The physical meaning of the 1-D term is that the filter circuit 112 composed of the filter resistor RF and the filter capacitor CF only performs filtering at time T1 of each switching cycle Tsw. Therefore, the bandwidth of the lower transistor current sampling circuit 110 will decrease as the duty cycle D increases, which will affect the dynamic performance of the lower transistor current sampling circuit 110.

[0053] Figure 5 (a) and Figure 5 (b) is Figure 2 The diagram shows the response time of the lower transistor current sampling circuit under different duty cycles, as shown below. Figure 5 As shown in (a), when the duty cycle D is small, the bandwidth of the lower tube current sampling circuit 110 is high when the inductor current IL undergoes a step change. Therefore, the time Tsettle required for the load current sampling voltage VCS_LOAD to reach steady state after the inductor current IL undergoes a step change is short.

[0054] like Figure 5 As shown in (b), when the duty cycle D is large, the bandwidth of the lower tube current sampling circuit 110 is low when the inductor current IL undergoes a step change. Therefore, the time Tsettle required for the load current sampling voltage VCS_LOAD to reach steady state after the inductor current IL undergoes a step change is relatively long.

[0055] In summary, the bandwidth of the lower transistor current sampling circuit 110 is affected by the duty cycle D, resulting in a lower bandwidth of the lower transistor current sampling circuit 110 when the duty cycle D is large, which affects the sampling speed of the load current ILOAD and the stability of the constant current control loop.

[0056] In view of this, this disclosure provides a load current sampling circuit, including an inductor current sampling circuit and a filter circuit. The filter circuit adjusts the resistance value of the filter resistor based on the duty cycle of the Buck converter to compensate for the sampling bandwidth. When the down transistor is turned on, the inductor current sampling circuit samples the current flowing through the down transistor to obtain the inductor current sampling voltage. The filter circuit filters the inductor current sampling voltage based on the adjusted filter resistor to determine the average value of the inductor current sampling voltage, thus obtaining the load current sampling voltage. Since the resistance value of the filter resistor is negatively correlated with the duty cycle, the resistance value can be reduced at large duty cycles to compensate for the influence of the duty cycle on the sampling bandwidth, thereby ensuring the current sampling speed and the stability of the control loop.

[0057] The technical solutions provided in this disclosure are described in detail below with reference to several specific embodiments.

[0058] Figure 6 This is a schematic diagram of the structure of a Buck converter provided in an embodiment of this disclosure, as shown below. Figure 6 As shown, the Buck converter 200 includes an upper transistor MH, a lower transistor ML, an inductor L, a voltage input terminal, a voltage output terminal, an output capacitor Cout, and a load current sampling circuit 300. The connection point of the upper transistor MH, the lower transistor ML, and the inductor L is the switching node SW. The voltage input terminal is used to receive the input voltage Vin, and the voltage output terminal is used to provide the output voltage Vout and the load current ILoad to the load.

[0059] The upper transistor MH is connected between the voltage input terminal and the switching node SW, the lower transistor ML is connected between the switching node SW and ground, the inductor L is connected between the switching node SW and the voltage output terminal, and the output capacitor Cout is connected in parallel with the load between the voltage output terminal and ground. The input terminal of the load current sampling circuit 300 is connected to the switching node SW, the output terminal of the load current sampling circuit 300 is connected to the first input terminal of the loop operational amplifier, the second input terminal of the loop operational amplifier is connected to the reference voltage Vref, the output terminal of the loop operational amplifier is connected to the input terminal of the drive control circuit through the pulse width modulation circuit, the first output terminal of the drive control circuit is connected to the control terminal of the upper transistor MH, and the second output terminal of the drive control circuit is connected to the control terminal of the lower transistor ML.

[0060] Figure 7 A circuit diagram of a load current sampling circuit provided in an embodiment of this disclosure is shown below. Figure 7 As shown, the load current sampling circuit 300 includes an inductor current sampling circuit 310 and a filter circuit 320. The input terminal of the inductor current sampling circuit 310 is connected to the switch node SW, and the output terminal of the inductor current sampling circuit 310 is connected to the output terminal of the load current sampling circuit 300 through the filter circuit 320.

[0061] The inductor current sampling circuit 310 is configured to sample the current flowing through the lower transistor ML when the lower transistor ML is turned on, and obtain the inductor current sampling voltage VCS_L.

[0062] The filter circuit 320 is configured to adjust the resistance value of the filter resistor based on the duty cycle D of the Buck converter 200 to compensate for the sampling bandwidth. When the down transistor ML is turned on, it filters the inductor current sampling voltage VCS_L based on the adjusted filter resistor to determine the average value of the inductor current sampling voltage VCS_L, thereby obtaining the load current sampling voltage VCS_LOAD. The resistance value of the filter resistor is negatively correlated with the duty cycle D.

[0063] For example, such as Figure 7 As shown, the inductor current sampling circuit 310 includes a sampling transistor MLS, an operational amplifier OPA, a first transistor M1, a current mirror, and a current sampling resistor RCS. The control terminal of the sampling transistor MLS is connected to the control terminal of the lower transistor ML. The first terminal of the sampling transistor MLS is connected to the inverting input terminal of the operational amplifier OPA and the first terminal of the first transistor M1. The second terminal of the sampling transistor MLS is connected to the switching node SW. The output terminal of the operational amplifier OPA is connected to the control terminal of the first transistor M1. The second terminal of the first transistor M1 is connected to the input terminal of the current mirror. The output terminal of the current mirror is connected to the first terminal of the current sampling resistor RCS and the input terminal of the filter circuit 320. The second terminal of the current sampling resistor RCS and the non-inverting input terminal of the operational amplifier OPA are grounded.

[0064] The current mirror includes a second transistor M2 and a third transistor M3. The first terminal of the second transistor M2 and the first terminal of the third transistor M3 are connected to the power supply voltage VDD. The control terminal of the second transistor M2 is connected to the second terminal of the second transistor M2, the control terminal of the third transistor M3 and the second terminal of the first transistor M1. The second terminal of the third transistor M3 is connected to the first terminal of the current sampling resistor RCS and the input terminal of the filter circuit 320.

[0065] When the lower transistor ML is turned on, the sampling transistor MLS is turned on and forms a mirror circuit with the lower transistor ML to mirror the inductor current IL as the inductor sampling current IL_SNS. The operational amplifier OPA and the current mirror work together to inject the inductor sampling current IL_SNS into the current sampling resistor RCS, and generate the inductor current sampling voltage VCS_L at the first terminal of the current sampling resistor RCS (the input terminal of the filter circuit 320).

[0066] See also Figure 7The filter circuit 320 includes a filter control switch M4, a resistor adjustment circuit 321, and a filter capacitor CF. The control terminal of the filter control switch M4 is connected to the control terminal of the lower switch ML. The input terminal of the filter control switch M4 is connected to the output terminal of the inductor current sampling circuit 310. The output terminal A of the filter control switch M4 is connected to the first plate of the filter capacitor CF and the output terminal B of the load current sampling circuit 300 through the resistor adjustment circuit 321. The second plate of the filter capacitor CF is grounded.

[0067] The resistor adjustment circuit 321 includes multiple resistors connected in series between the output terminal of the inductor current sampling circuit 310 and the output terminal of the load current sampling circuit 300. Among the multiple resistors, there is a base resistor and multiple adjustment resistors. The base resistor is continuously connected to the circuit, while the adjustment resistor connected to the circuit depends on the duty cycle D of the Buck converter 200. Therefore, the adjustment resistor connected to the circuit and the base resistor together constitute the filter resistor in the filter circuit 320.

[0068] In the Buck converter 200, the duty cycle D can be expressed as Vout / Vin. The resistor adjustment circuit 321 can determine the duty cycle D based on the input voltage Vin and the output voltage Vout, and connect at least one resistor based on the duty cycle D to adjust the resistance value of the filter resistor. Specifically, when one resistor is connected, the connected resistor is the base resistor, and the filter resistor is the base resistor; the resistance value of the filter resistor is the same as the resistance value of the base resistor. When multiple resistors are connected, including the base resistor and at least one adjustment resistor, the filter resistor is formed by connecting the base resistor and all the adjustment resistors in the connected circuit in series. The resistance value of the filter resistor is the sum of the resistance value of the base resistor and the resistance values ​​of each of the connected adjustment resistors.

[0069] For example, the resistance value of the base resistor can be R / 2. n The resistance values ​​of the multiple adjustment resistors are R / 2 respectively. n R / 2 n -1 ..., R / 2, where n is an integer greater than or equal to 2, and R is the resistance of the filter resistor when all resistors are connected in the circuit, i.e., the maximum resistance of the filter resistor. When the duty cycle D is small, the base resistor and all adjustment resistors are connected in the circuit, and the resistance of the filter resistor reaches its maximum value R. As the duty cycle D increases, the number of adjustment resistors connected gradually decreases, and the corresponding resistance of the filter resistor gradually decreases until only the base resistor is connected. At this point, the resistance of the filter resistor reaches its minimum value R / 2. n .

[0070] Obviously, the resistance value of the filter resistor is negatively correlated with the duty cycle D. Therefore, when the duty cycle is large, the resistance value of the filter resistor can be reduced to compensate for the sampling bandwidth, so that the sampling bandwidth is kept at a relatively high level, thereby ensuring the current sampling speed and the stability of the control loop.

[0071] During the process of duty cycle D changing from 0% to 95%, simulations were performed on the lower tube current sampling circuit 110 in the prior art and the load current sampling circuit 300 provided in this disclosure. The simulation results show that the bandwidth of the lower tube current sampling circuit 110 will decrease by 20 times, while the bandwidth of the load current sampling circuit 300 will only decrease by 2 times.

[0072] In summary, the filter circuit 320 provided in this embodiment can adjust the resistance value of the filter resistor based on the duty cycle D of the Buck converter 200 to compensate for the sampling bandwidth. When the down transistor ML is turned on, the inductor current sampling voltage VCS_L is filtered based on the adjusted filter resistor to determine the average value of the inductor current sampling voltage VCS_L and obtain the load current sampling voltage VCS_LOAD. Since the resistance value of the filter resistor is negatively correlated with the duty cycle D, the resistance value of the filter resistor can be reduced when the duty cycle is large to compensate for the influence of the duty cycle D on the sampling bandwidth, thereby ensuring the current sampling speed and the stability of the control loop.

[0073] In some embodiments, Figure 8 A circuit diagram of a resistor adjustment circuit provided in an embodiment of this disclosure is shown below. Figure 8 As shown, the resistor adjustment circuit 321 includes a voltage sampling circuit 410, an adjustment control circuit 420, a base resistor RB, and an adjustment resistor unit 430.

[0074] The voltage sampling circuit 410 has its first input terminal connected to the voltage input terminal, its second input terminal connected to the voltage output terminal, its output terminal connected to the input terminal of the adjustment control circuit 420, and its output terminal connected to the control terminal of the adjustment resistor unit 430. The base resistor RB and the adjustment resistor unit 430 are connected in series between the output terminal A of the filter control switch M4 and the output terminal B of the load current sampling circuit 300.

[0075] The voltage sampling circuit 410 is configured to sample the input voltage Vin to obtain the input sampling voltage and to sample the output voltage Vout to obtain the output sampling voltage.

[0076] The tuning control circuit 420 is configured to determine the duty cycle range in which the duty cycle D is located based on the output sampling voltage and the input sampling voltage, and generate a corresponding indication signal.

[0077] The trimming resistor unit 430 is configured to connect the corresponding trimming resistor Rtrim based on the indication signal, so as to form a filter resistor together with the base resistor RB.

[0078] For example, such as Figure 8 As shown, the voltage sampling circuit 410 includes a first voltage sampling circuit 411 and a second voltage sampling circuit 412. The input terminal of the first voltage sampling circuit 411 is connected to the voltage input terminal, and the multiple output terminals of the first voltage sampling circuit 411 are connected one-to-one with the multiple first input terminals of the adjustment control circuit 420. The input terminal of the second voltage sampling circuit 412 is connected to the voltage output terminal, and the output terminal of the second voltage sampling circuit 412 is connected to the second input terminal of the adjustment control circuit 420.

[0079] The first voltage sampling circuit 411 includes multiple voltage sampling resistors Rs1, which are connected in series between the voltage input terminal and ground. The connection point of two adjacent voltage sampling resistors Rs1 is one output terminal of the first voltage sampling circuit 411. Different output terminals correspond to different first sampling coefficients. The first voltage sampling circuit 411 can sample the input voltage Vin based on multiple different first sampling coefficients to obtain multiple different input sample voltages.

[0080] For example, such as Figure 8 As shown, the first voltage sampling circuit 411 includes four voltage sampling resistors Rs1 and three output terminals. The first sampling coefficients corresponding to the three output terminals are 91‰, 79‰ and 63‰ respectively, and the three input sampling voltages obtained are 91‰×Vin, 79‰×Vin and 63‰×Vin.

[0081] See also Figure 8 The second voltage sampling circuit 412 includes multiple voltage sampling resistors Rs2, which are connected in series between the voltage output terminal and ground. The connection point of any two adjacent voltage sampling resistors Rs2 can be used as the output terminal of the second voltage sampling circuit 412. The sampling coefficient of the second voltage sampling circuit 412 is a second sampling coefficient, and the second sampling coefficient is greater than the first sampling coefficient. For example, ... Figure 8 As shown, the second voltage sampling circuit 412 includes four voltage sampling resistors Rs2, the second sampling coefficient is 100‰, and the obtained output sampling voltage is 100‰×Vout.

[0082] See also Figure 8The adjustment control circuit 420 includes multiple comparators CMP, wherein the inverting input terminals of the multiple comparators CMP are connected one-to-one with the multiple output terminals of the first voltage sampling circuit 411, the non-inverting input terminals of the multiple comparators CMP are all connected to the output terminals of the second voltage sampling circuit 412, and the output terminals of the multiple comparators CMP are connected one-to-one with the multiple control terminals of the adjustment resistor unit 430.

[0083] For example, such as Figure 8 As shown, the adjustment control circuit 420 includes a first comparator CMP1, a second comparator CMP2, and a third comparator CMP3. The non-inverting input terminals of the first comparator CMP1, the second comparator CMP2, and the third comparator CMP3 are connected to the output terminal of the second voltage sampling circuit 412 to receive the output sampling voltage 100‰×Vout.

[0084] The inverting input of the first comparator CMP1 is connected to the first output of the first voltage sampling circuit 411 to receive the first input sampling voltage 91‰×Vin. The inverting input of the second comparator CMP2 is connected to the second output of the first voltage sampling circuit 411 to receive the second input sampling voltage 79‰×Vin. The inverting input of the third comparator CMP3 is connected to the third output of the first voltage sampling circuit 411 to receive the third input sampling voltage 63‰×Vin.

[0085] The first comparator CMP1 compares the output sampling voltage 100‰×Vout with the first input sampling voltage 91‰×Vin to determine the first indication signal; the second comparator CMP2 compares the output sampling voltage 100‰×Vout with the second input sampling voltage 79‰×Vin to determine the second indication signal; and the third comparator CMP3 compares the output sampling voltage 100‰×Vout with the third input sampling voltage 63‰×Vin to determine the third indication signal.

[0086] Specifically, when the duty cycle D is greater than 91%, the first, second, and third indicator signals are all at a high level; when the duty cycle D is greater than 79% and less than 91%, the first indicator signal is at a low level, and the second and third indicator signals are at a high level; when the duty cycle D is greater than 63% and less than 79%, the first and second indicator signals are at a low level, and the third indicator signal is at a high level; when the duty cycle D is less than 63%, the first, second, and third indicator signals are all at a low level.

[0087] See also Figure 8The trimming resistor unit 430 includes multiple trimming resistors Rtrim and multiple trimming switching transistors Mtrim. The multiple trimming resistors Rtrim are connected in series between the base resistor RB and the output terminal B of the load current sampling circuit 300. The control terminals of the multiple trimming switching transistors Mtrim are connected one-to-one with the output terminals of multiple comparators CMP. The multiple trimming resistors Rtrim and the multiple trimming switching transistors Mtrim are connected in parallel one-to-one.

[0088] For example, such as Figure 8 As shown, the trimming resistor unit 430 includes three trimming resistors Rtrim, namely the first trimming resistor Rtrim1, the second trimming resistor Rtrim2 and the third trimming resistor Rtrim3, and three trimming switching transistors Mtrim, namely the first trimming switching transistor Mtrim1, the second trimming switching transistor Mtrim2 and the third trimming switching transistor Mtrim3.

[0089] In this configuration, the first trimming switch Mtrim1 is connected in parallel with the first trimming resistor Rtrim1, the second trimming switch Mtrim2 is connected in parallel with the second trimming resistor Rtrim2, and the third trimming switch Mtrim3 is connected in parallel with the third trimming resistor Rtrim3. The control terminal of the first trimming switch Mtrim1 is connected to the output terminal of the first comparator CMP1, the control terminal of the second trimming switch Mtrim2 is connected to the output terminal of the second comparator CMP2, and the control terminal of the third trimming switch Mtrim3 is connected to the output terminal of the third comparator CMP3.

[0090] When the first, second, and third indicator signals are all high, the first trimming switch Mtrim1, the second trimming switch Mtrim2, and the third trimming switch Mtrim3 are all turned on, short-circuiting the first trimming resistor Rtrim1, the second trimming resistor Rtrim2, and the third trimming resistor Rtrim3. At this time, only the base resistor RB is connected to the circuit. Therefore, when the duty cycle D is greater than 91%, the filter resistor is the base resistor RB.

[0091] When the first indicator signal is low and the second and third indicator signals are high, the first trimming switch Mtrim1 is turned off, and the second and third trimming switches Mtrim2 and Mtrim3 are turned on, short-circuiting the second and third trimming resistors Rtrim2 and Rtrim3. At this time, the base resistor RB and the first trimming resistor Rtrim1 are connected in series in the circuit. Therefore, when the duty cycle D is greater than 79% and less than 91%, the filter resistor includes the base resistor RB and the first trimming resistor Rtrim1 connected in series.

[0092] When the first and second indicator signals are low and the third indicator signal is high, the first trimming switch Mtrim1 and the second trimming switch Mtrim2 are turned off, and the third trimming switch Mtrim3 is turned on, short-circuiting the third trimming resistor Rtrim3. At this time, the base resistor RB, the first trimming resistor Rtrim1, and the second trimming resistor Rtrim2 are connected in series in the circuit. Therefore, when the duty cycle D is greater than 63% and less than 79%, the filter resistor includes the base resistor RB, the first trimming resistor Rtrim1, and the second trimming resistor Rtrim2 connected in series.

[0093] When the first, second, and third indicator signals are all low, the first trimming switch Mtrim1, the second trimming switch Mtrim2, and the third trimming switch Mtrim3 are all turned off. At this time, the base resistor RB, the first trimming resistor Rtrim1, the second trimming resistor Rtrim2, and the third trimming resistor Rtrim3 are connected in series in the circuit. Therefore, when the duty cycle D is less than 63%, the filter resistor includes the base resistor RB, the first trimming resistor Rtrim1, the second trimming resistor Rtrim2, and the third trimming resistor Rtrim3 connected in series.

[0094] It should be noted that, Figure 8 This example only illustrates dividing the duty cycle D into four duty cycle intervals. In practical applications, the number of duty cycle intervals can be flexibly set, and the number of comparator CMP, trimming resistor Rtrim, voltage sampling resistor RS1, and trimming switch Mtrim can be adaptively adjusted.

[0095] This disclosure also provides a power supply chip, including the load current sampling circuit 300 provided in any of the above embodiments.

[0096] The power chip provided in this disclosure includes the load current sampling circuit 300 provided in any of the above embodiments, and has the functional modules and beneficial effects of the load current sampling circuit 300, which will not be described in detail here.

[0097] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” are to be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” should be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, the “example” is merely exemplary and illustrative, and should not be considered exclusive or extensive.

[0098] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0099] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A load current sampling circuit, characterized in that, The Buck converter is applied to a Buck converter, which includes an upper transistor connected between the voltage input terminal and the switching node, a lower transistor connected between the switching node and ground, and an inductor connected between the switching node and the voltage output terminal. The load current sampling circuit includes an inductor current sampling circuit and a filtering circuit. The inductor current sampling circuit is configured to sample the current flowing through the lower transistor when the lower transistor is turned on, and obtain the inductor current sampling voltage. The filtering circuit is configured to adjust the resistance value of the filter resistor based on the duty cycle of the Buck converter to compensate for the sampling bandwidth, and when the lower transistor is turned on, filter the inductor current sampling voltage based on the adjusted filter resistor to determine the average value of the inductor current sampling voltage and obtain the load current sampling voltage; wherein the resistance value of the filter resistor is negatively correlated with the duty cycle.

2. The load current sampling circuit according to claim 1, characterized in that, The filter circuit includes a filter control switch, a resistor adjustment circuit, and a filter capacitor. The control terminal of the filter control switch is connected to the control terminal of the lower switch, the input terminal of the filter control switch is connected to the output terminal of the inductor current sampling circuit, the output terminal of the filter control switch is connected to the first plate of the filter capacitor and the output terminal of the load current sampling circuit through the resistor adjustment circuit, and the second plate of the filter capacitor is grounded. The resistor adjustment circuit is configured to determine the duty cycle based on the input voltage and output voltage of the Buck converter, and to connect at least one resistor based on the duty cycle to adjust the resistance value of the filter resistor.

3. The load current sampling circuit according to claim 2, characterized in that, The resistor adjustment circuit includes a voltage sampling circuit, an adjustment control circuit, a base resistor, and an adjustment resistor unit. The first input terminal of the voltage sampling circuit is connected to the voltage input terminal, the second input terminal of the voltage sampling circuit is connected to the voltage output terminal, the output terminal of the voltage sampling circuit is connected to the input terminal of the adjustment control circuit, the output terminal of the adjustment control circuit is connected to the control terminal of the adjustment resistor unit, and the base resistor and the adjustment resistor unit are connected in series between the output terminal of the filter control switch and the output terminal of the load current sampling circuit. The voltage sampling circuit is configured to sample the input voltage to obtain an input sample voltage; The output voltage is sampled to obtain the output sample voltage; The adjustment control circuit is configured to determine the duty cycle range in which the duty cycle is located based on the output sampling voltage and the input sampling voltage, and generate a corresponding indication signal. The adjustment resistor unit is configured to connect a corresponding adjustment resistor based on the indication signal, so as to form the filter resistor together with the base resistor.

4. The load current sampling circuit according to claim 3, characterized in that, The voltage sampling circuit includes a first voltage sampling circuit and a second voltage sampling circuit. The input terminal of the first voltage sampling circuit is connected to the voltage input terminal, and the multiple output terminals of the first voltage sampling circuit are connected one-to-one with the multiple first input terminals of the adjustment control circuit. The input terminal of the second voltage sampling circuit is connected to the voltage output terminal, and the output terminal of the second voltage sampling circuit is connected to the second input terminal of the adjustment control circuit. The first voltage sampling circuit is configured to sample the input voltage based on multiple different first sampling coefficients to obtain multiple different input sample voltages; The second voltage sampling circuit is configured to sample the output voltage based on a second sampling coefficient to obtain the output sampled voltage, wherein the second sampling coefficient is greater than the first sampling coefficient.

5. The load current sampling circuit according to claim 4, characterized in that, The adjustment control circuit includes multiple comparators; The inverting input terminals of the plurality of comparators are connected one-to-one with the plurality of output terminals of the first voltage sampling circuit, the non-inverting input terminals of the plurality of comparators are all connected to the output terminals of the second voltage sampling circuit, and the output terminals of the plurality of comparators are connected one-to-one with the plurality of control terminals of the trimming resistor unit.

6. The load current sampling circuit according to claim 5, characterized in that, The trimming resistor unit includes multiple trimming resistors and multiple trimming switch transistors. The multiple trimming resistors are connected in series between the base resistor and the output terminal of the load current sampling circuit. The control terminals of the multiple trimming switch transistors are connected one-to-one with the output terminals of the multiple comparators. The multiple trimming resistors and multiple trimming switch transistors are connected in parallel one-to-one.

7. The load current sampling circuit according to claim 4, characterized in that, The first voltage sampling circuit includes multiple voltage sampling resistors; The plurality of voltage sampling resistors are connected in series between the voltage input terminal and ground, and the connection point of two adjacent voltage sampling resistors is one output terminal of the first voltage sampling circuit.

8. The load current sampling circuit according to any one of claims 2-7, characterized in that, The inductor current sampling circuit includes a sampling tube, an operational amplifier, a transistor, a current mirror, and a current sampling resistor; The control terminal of the sampling tube is connected to the control terminal of the lower transistor. The first terminal of the sampling tube is connected to the inverting input terminal of the operational amplifier and the first terminal of the transistor. The second terminal of the sampling tube is connected to the switching node. The output terminal of the operational amplifier is connected to the control terminal of the transistor. The second terminal of the transistor is connected to the input terminal of the current mirror. The output terminal of the current mirror is connected to the first terminal of the current sampling resistor and the input terminal of the filter circuit. The second terminal of the current sampling resistor and the non-inverting input terminal of the operational amplifier are grounded.

9. A Buck converter, characterized in that, Includes an upper transistor, a lower transistor, an inductor, and a load current sampling circuit as described in any one of claims 1-8; The upper transistor is connected between the voltage input terminal and the switching node, the lower transistor is connected between the switching node and ground, and the inductor is connected between the switching node and the voltage output terminal.

10. A power supply chip, characterized in that, The load current sampling circuit according to any one of claims 1-8.

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