Parallel interleaved differential boost inverter based on carrier phase-shift and its soft switching implementation method

Abstract

The application discloses a parallel staggered differential boost inverter based on carrier phase shift and a soft switching implementation method thereof, and relates to the field of power electronic converters. Each phase of the inverter comprises a first bridge arm and a second bridge arm in parallel with each other. The first bridge arm comprises a first high-side switch tube and a first low-side switch tube, and the second bridge arm comprises a second high-side switch tube and a second low-side switch tube. The midpoint of the first bridge arm is connected in series with a first differential mode inductor, and the midpoint of the second bridge arm is connected in series with a second differential mode inductor. The other ends of the first differential mode inductor and the second differential mode inductor are connected in parallel and then connected to a main inductor of the phase. The main inductor is connected to an output filter capacitor. A digital controller is used to dynamically control the driving carrier of the first bridge arm and the second bridge arm to excite a controlled in-phase quadrilateral circulating current on the first differential mode inductor or the second differential mode inductor, thereby achieving zero voltage switching of power devices. The application can achieve zero voltage switching in a full load range.

Description

Technical Field

[0001] This application relates to the field of power electronic converters, and in particular to a parallel interleaved differential boost inverter based on carrier phase shift and its soft-switching implementation method. Background Technology

[0002] Operating GaN-based DBI inverters at high frequencies under hard-switching conditions presents significant challenges. The power switches in the DBI topology must withstand the boosted output voltage. Since the energy dissipation of the GaN HEMT's storage capacitor increases dramatically and non-linearly with increasing blocking voltage, this extreme voltage stress leads to substantial turn-on losses. More seriously, the voltage stress of hard switching exacerbates charge trapping within the device, causing an irreversible increase in dynamic on-resistance. Therefore, for DBI inverters, achieving full-range zero-voltage switching (ZVS) is not only a means to improve efficiency but also a necessary prerequisite for unlocking their high-frequency operating potential.

[0003] To mitigate these switching losses, researchers have proposed various hardware-based soft-switching techniques. For example, passive lossless absorbers and quasi-resonant networks, while achieving zero-voltage switching (ZVS), significantly increase the number of components and impose excessively high voltage and current stresses on the circuit. Another approach is to introduce auxiliary active switches, but these active soft-switching topologies require floating gate drivers and extremely complex timing control logic, severely reducing the overall system reliability and power density.

[0004] To reduce reliance on auxiliary hardware, modulation-based soft-switching strategies are widely adopted. For example: 1) Triangular Current Mode (TCM): It can achieve ZVS, but it inherently has the problem of variable switching frequency and huge current ripple, which not only aggravates conduction loss, but also greatly increases the design difficulty of electromagnetic interference (EMI) filters.

[0005] 2) Quadrilateral Current Mode (QCM): ZVS is guaranteed by optimizing ripple, but traditional QCM control usually requires high-bandwidth zero-crossing detection (ZCD) hardware peripherals or extremely complex digital algorithms to solve the problem of multiple solutions for duty cycle, which greatly increases the computational burden.

[0006] Therefore, how to develop a single-stage boost inverter topology and its modulation strategy that can operate at a fixed switching frequency, without complex zero-crossing detection hardware and large algorithms, and achieve ZVS across the entire load range has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] The purpose of this application is to provide a parallel interleaved differential boost inverter based on carrier phase shift and its soft-switching implementation method. This method integrates a parallel interleaved topology with carrier phase shift pulse width modulation (PWM) technology, actively generating an intra-phase quadrilateral circulating current by dynamically adjusting the phase shift angle between carriers. This circulating current can completely discharge the junction capacitance of the GaN device within the dead time before switching operation, thereby achieving zero-voltage switching across the entire load range at a fixed switching frequency.

[0008] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides a parallel interleaved differential boost inverter based on carrier phase shift, comprising: The system comprises a DC input power supply, a three-phase inverter circuit, three-phase output filter capacitors, and a digital controller. Each phase includes a first bridge arm and a second bridge arm connected in parallel. The first bridge arm includes a first high-side switch and a first low-side switch, and the second bridge arm includes a second high-side switch and a second low-side switch. A first differential-mode inductor is connected in series at the midpoint of the first bridge arm, and a second differential-mode inductor is connected in series at the midpoint of the second bridge arm. The other ends of the first and second differential-mode inductors are connected in parallel and then connected to the main inductor of their respective phases. The main inductor is connected to the output filter capacitor. The digital controller is used to dynamically phase-shift the driving carrier of the first and second bridge arms to excite a controlled intra-phase quadrilateral circulating current on the first or second differential-mode inductor, thereby achieving zero-voltage switching of the power devices.

[0009] Secondly, this application provides a soft-switching implementation method for a parallel interleaved differential boost inverter based on carrier phase shift, including: Obtain the AC output voltage and main inductor current of the parallel interleaved differential boost inverter; Based on the modulation principle of parallel interleaved differential boost inverters, calculate the basic duty cycle that satisfies the requirements of sinusoidal output and DC bias. Based on the equivalent parasitic capacitance of the switching transistor and the set dead time, the zero-voltage switching critical current threshold required to complete the charging and discharging of the junction capacitance is calculated. Based on the basic duty cycle and zero-voltage switching critical current threshold, and based on the inductor volt-second balance principle, the phase shift angle between the first bridge arm carrier and the second bridge arm carrier in the parallel interleaved differential boost inverter is calculated to obtain the voltage difference at the midpoint of the first bridge arm and the second bridge arm, thereby generating an amplitude-controlled intraphase quadrilateral circulating current on the first differential mode inductor and the second differential mode inductor. Based on the phase shift angle, the phase-shifted first bridge arm carrier and the phase-shifted second bridge arm carrier are compared with the modulation wave to generate a PWM drive signal containing dead time; During the dead time, the junction capacitance voltage of the first high-side switch, the first low-side switch, the second high-side switch, or the second low-side switch corresponding to the quadrilateral circulating current in the phase is discharged to zero, thus completing zero-voltage turn-on.

[0010] According to the specific embodiments provided in this application, this application has the following technical effects: This application provides a parallel interleaved differential boost inverter based on carrier phase shift and its soft-switching implementation method. By employing a carrier phase shift control strategy to achieve parallel operation of multiple modules, it solves the problems of limited power rating and large output current ripple in traditional single-module inverters, thereby expanding the system power capacity and improving the output power quality. By dynamically adjusting the phase shift angle between the driving carriers of the first and second bridge arms, a quadrilateral circulating current with controllable amplitude and waveform can be actively generated on the differential-mode inductor. This circulating current can effectively extract the charge from the junction capacitance of the switching transistor during the dead time, causing the junction capacitance voltage of the switching transistor to be turned on to discharge to zero before the arrival of the drive signal, thus achieving zero-voltage turn-on of the power device. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A schematic diagram of the overall topology of a parallel interleaved differential boost inverter based on carrier phase shifting is provided for one embodiment of this application. Figure 2 A simplified equivalent circuit and current diagram of any one phase (phase A) of an inverter provided in an embodiment of this application; Figure 3 Transient waveform diagrams of the quadrilateral circulating current, differential mode inductor current, and drive signal excited within a phase during one switching cycle, provided as an embodiment of this application; Figure 4 An equivalent circuit diagram showing the eight consecutive operating stages of ZVS implemented using circulating current within one switching cycle, provided as an embodiment of this application; Figure 5 A comparison curve of the loss and efficiency of a soft-switching implementation method and a traditional differential boost inverter as a function of switching frequency, provided in an embodiment of this application. Figure 6 A waveform diagram showing the change of dynamic phase offset time over time in a simulation verification provided for an embodiment of this application; Figure 7A waveform diagram of the main inductor and interleaved branch high-frequency inductor currents of an inverter under steady-state operation, provided in an embodiment of this application; Figure 8 Transient verification waveforms of drain-source voltage, drive signal, and inductor current at different times for a single switch transistor to achieve zero-voltage turn-on (ZVS) according to an embodiment of this application; Figure 9 A comparison chart showing the total system loss and efficiency as a function of output power in an embodiment of this application using a soft-switching method; Figure 10 This is a schematic flowchart of a soft-switching implementation method provided in an embodiment of this application. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0014] With the continuous development of industrial applications, the demand for power inverters with higher efficiency and higher power density is increasing. Employing gallium nitride (GaN) high electron mobility transistors (HEMTs) to increase the switching frequency is a technology of great interest in the industry, as GaN devices possess excellent electron mobility, zero reverse recovery characteristics, and extremely low parasitic output capacitance. To meet the needs of modern power conversion, the differential boost inverter (DBI), as a single-stage topology with buck-boost capability and avoidance of bridge arm shoot-through faults, has become a highly attractive solution.

[0015] The purpose of this application is to provide a parallel interleaved differential boost inverter based on carrier phase shift and its soft-switching implementation method. This method integrates a parallel interleaved topology with carrier phase shift pulse width modulation (PWM) technology, actively generating an intra-phase quadrilateral circulating current by dynamically adjusting the phase shift angle between carriers. This circulating current can completely discharge the junction capacitance of the GaN device within the dead time before switching operation, thereby achieving zero-voltage switching across the entire load range at a fixed switching frequency.

[0016] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] Example 1 like Figure 1As shown, this embodiment provides a parallel interleaved differential boost inverter based on carrier phase shift, including: The system comprises a DC input power supply, a three-phase inverter circuit, three-phase output filter capacitors, and a digital controller. Each phase includes a first bridge arm and a second bridge arm connected in parallel. The first bridge arm includes a first high-side switch and a first low-side switch, and the second bridge arm includes a second high-side switch and a second low-side switch. A first differential-mode inductor is connected in series at the midpoint of the first bridge arm, and a second differential-mode inductor is connected in series at the midpoint of the second bridge arm. The other ends of the first and second differential-mode inductors are connected in parallel and then connected to the main inductor of their respective phases. The main inductor is connected to the output filter capacitor. The digital controller is used to dynamically phase-shift the driving carrier of the first and second bridge arms to excite a controlled intra-phase quadrilateral circulating current on the first or second differential-mode inductor, thereby achieving zero-voltage switching of the power devices.

[0018] The first high-side switch, the first low-side switch, the second high-side switch, and the second low-side switch are all gallium nitride high-frequency power devices. The digital controller is used to calculate the phase shift angle between the first bridge arm carrier and the second bridge arm carrier by sampling the AC output voltage and the main inductor current in real time, obtain the voltage difference at the midpoint of the first and second bridge arms, and induce a controlled-amplitude in-phase quadrilateral circulating current in the first and second differential-mode inductors. The inductance values ​​of the first and second differential-mode inductors are equal and less than the inductance value of the main inductor.

[0019] In some embodiments, such as Figure 1 and Figure 2 As shown, the parallel interleaved differential boost inverter (DBI) in this embodiment is powered by a DC input power supply. The power supply is divided into a three-phase symmetrical structure of A, B, and C. Taking phase A as an example: This line consists of a first H-bridge branch and a second H-bridge branch connected in parallel. The switching transistors use transistors with extremely low output capacitance. GaN devices. The switching pair of the first bridge arm is defined as... (First high-side switch) and (First low-side switch), the switch pair of the second bridge arm is defined as follows: (Second high-side switch) and (Second low-side switch).

[0020] Differential-mode inductors are connected in series at the output terminals of the two branches. and These two differential-mode inductors merge with the main inductor. Connected. and Its inductance value is extremely small, and its main function is to assist ZVS commutation.

[0021] Define the voltage at the midpoint of the first bridge arm as The voltage at the midpoint of the second bridge arm is Because there is a set time delay (i.e., phase shift angle) in the switching action between bridge arms. and A voltage difference is generated between them, and according to Kirchhoff's current law, a differential mode circulating current is induced within the phase. The branch currents satisfy the following mathematical relationship: ; The slope of the circulating current is determined by both the voltage difference and the differential-mode inductance. ; in, This is the differential mode inductance value.

[0022] Example 2 like Figure 10 As shown, this embodiment provides a soft-switching implementation method based on the aforementioned carrier phase-shift-based parallel interleaved differential boost inverter, including: Step S1: Obtain the AC output voltage and main inductor current of the parallel interleaved differential boost inverter; Step S2: Calculate the basic duty cycle that satisfies the requirements of sinusoidal output and DC bias based on the modulation principle of the parallel interleaved differential boost inverter; Step S3: Based on the equivalent parasitic capacitance of the switching transistor and the set dead time, calculate the zero-voltage switching critical current threshold required to complete the charging and discharging of the junction capacitance. Step S4: Based on the basic duty cycle and zero-voltage switching critical current threshold, and based on the inductor volt-second balance principle, calculate the phase shift angle between the first bridge arm carrier and the second bridge arm carrier in the parallel interleaved differential boost inverter, obtain the voltage difference at the midpoint of the first bridge arm and the second bridge arm, and excite an amplitude-controlled intraphase quadrilateral circulating current on the first differential mode inductor and the second differential mode inductor. Step S5: Based on the phase shift angle, compare the phase-shifted first bridge arm carrier and the phase-shifted second bridge arm carrier with the modulation wave to generate a PWM drive signal containing dead time; Step S6: During the dead time, discharge the junction capacitance voltage of the first high-side switch, the first low-side switch, the second high-side switch, or the second low-side switch corresponding to the quadrilateral circulating current in the phase to zero, thereby completing zero-voltage turn-on.

[0023] In some embodiments, the parameter calculation principle of the soft switch (ZVS) during steps S1-S4 is as follows: To ensure zero-voltage switching, the junction capacitance voltage across the switching transistor must be discharged to zero before the transistor receives the gate-on signal (i.e., during the dead time).

[0024] With the first high-side switch transistor and the second high-side switch transistor ( , ) and the first low-side switch transistor, the second low-side switch transistor ( , For example, the system needs to meet the following critical current determination conditions: ; Among them, the critical current The calculation formula is: ; In the formula, To preset the dead time, The output capacitor voltage is considered as a time-varying threshold related to the transient output voltage in practical applications. Coss This is the output capacitor.

[0025] The calculation and allocation of the phase shift angle are as follows: The core component of the controller lies in dynamically calculating the carrier phase shift angle. To ensure that the circulating current amplitude just meets the conditions required for soft switching, based on the volt-second balance principle of differential mode inductors, the phase shift angle function that varies with time is derived as follows: ; To prevent the phase shift angle from being too large and causing the switching transistors on the same side to conduct simultaneously, a differential mode inductor... The selection must satisfy the following constraints: ; In the formula, For phase shift angle, i Lx The main inductor current, L m This is the differential mode inductance value. T s For the switching cycle, d x Based on duty cycle.

[0026] Specifically, in actual design, the value of the differential mode inductor should be taken close to the upper limit of its allowable range in order to fully consider the impact of dead time.

[0027] Specifically, during the dead time, the junction capacitance voltage of the first high-side switch, the first low-side switch, the second high-side switch, or the second low-side switch corresponding to the in-phase quadrilateral circulating current is discharged to zero, completing zero-voltage turn-on. This includes: Within one switching cycle, the switching transistors to be turned on in the first and second bridge arms are turned on at zero voltage through resonance and circulating current control in eight continuous operating stages; wherein, by utilizing the resonance between the inductor current and the output capacitor during the dead time, the junction capacitance voltage of the switching transistor to be turned on is discharged to zero before the drive signal arrives; the switching transistor to be turned on is a first high-side switching transistor, a first low-side switching transistor, a second high-side switching transistor, or a second low-side switching transistor.

[0028] The inverter has eight consecutive operating phases in one switching cycle (ZVS simulation) including: the first dead zone resonance phase, the phase-intraphase circulating current decrease phase, the second dead zone resonance phase, the first circulating current holding phase, the third dead zone resonance phase, the phase-intraphase circulating current increase phase, the fourth dead zone resonance phase, and the second circulating current holding phase. like Figure 3 and Figure 4 As shown, when the steady-state main inductor current In this embodiment, a complete switching cycle contains 8 precise timing stages: Phase 1 [ (First dead zone resonance stage): First high-side switch transistor Turn off. At this time, the branch current... The reverse current draws charge and supplies it to the first high-side switch. junction capacitance Charging, while simultaneously supplying power to the first low-side switch transistor. junction capacitance Discharge. The parasitic capacitance resonates with the inductive network until... The circuit is fully discharged to zero, the phase ends, and the first low-side switch begins. It created the perfect ZVS environment.

[0029] Phase 2 [ (Intraphase circulation decline phase): First low-side switch transistor Zero-loss turn-on (ZVS). Differential-mode inductors withstand negative voltage. This leads to intraphase circulation. Linear decrease. Linear increase, Linear decrease until the second high-side switch transistor A shutdown signal has been received.

[0030] Phase 3 [ (Second dead zone resonance): Second highest side switch transistor Turn off. At this time, the branch current... Reverse current causes Charge, Discharge. Resonance causes The voltage drops to zero, and the phase ends.

[0031] Phase 4 [ (First circulation maintenance phase): Second low-side switch transistor Turn-on under ZVS. At this time, the first low-side switch... Second low-side switching transistor Both are in the conducting state. The voltage difference between the midpoints of the two bridge arms is zero, and there is circulating current within the phase. Maintain a constant state. This state continues until... Turn off.

[0032] Phase 5 [ (Third dead zone resonance stage): First low-side switch transistor Shut down. At this time. Forward current gives Charge, Discharge. Resonance causes... Once completely discharged to zero, the phase ends.

[0033] Phase 6 [ (Intraphase circulation rising phase): First high-side switch transistor Lossless turn-on under ZVS conditions. At this time, the differential-mode inductor withstands a forward voltage. Intraphase circulation Linear rise until the second low-side switch transistor Turn off.

[0034] Phase 7 [ (Fourth dead zone resonance stage): Second low-side switch transistor Shut down. At this time. Forward current gives Charge, Discharge until the second high-side switch transistor is discharged. The junction capacitance voltage is cleared to zero, and the phase ends.

[0035] Phase 8 [ (Second circulation maintenance phase): Second highest side switch transistor Turn-on under ZVS conditions. First high-side switch. Second high-side switching transistor Simultaneous conduction. With no voltage difference at the midpoint, the circulating current remains constant again until the cycle ends. End, proceed to the next loop.

[0036] Through the above-mentioned precise timing modulation, this embodiment completes the ZVS operation of all GaN switches entirely by relying on the internally constructed circulating current without requiring any external absorption circuits or zero-crossing detection hardware.

[0037] In some embodiments, to verify the effectiveness of the above control strategy, a power loss analysis model based on the characteristics of GaN devices is constructed. Since GaN devices do not have a body diode (no reverse recovery loss) and achieve full-range ZVS (zero turn-on loss), the total loss of a single GaN switch is simplified to: ; That is: average conduction loss, reverse channel conduction loss during dead time, and hard turn-off loss.

[0038] To verify the effectiveness of the aforementioned modulation strategy and control algorithm, this application built a physical-level system simulation embodiment in the PLECS software platform. The embodiment used a real gallium nitride (GaN) high electron mobility transistor (specifically, the GS66508B) and directly imported a real thermodynamic loss model provided by the device manufacturer to ensure a high degree of consistency between theoretical analysis and actual operating conditions.

[0039] Example: Setting DC input voltage AC output voltage amplitude AC power grid frequency By comprehensively considering the trade-off between total harmonic distortion (THD) and switching losses in the inverter, the system is set to a fixed switching frequency. The passive parameters of the topology are configured as follows: main inductor The first and second differential mode inductors used to assist ZVS Output filter capacitor To meet the dead-time discharge requirements, the system has a preset dead-time. Theoretically calculated ZVS critical current .

[0040] Specifically, such as Figures 6-7 Simulation results show that the carrier phase shift angle calculated in real time by the controller is... The conduction time is always strictly maintained within the safety constraints defined by the formula (i.e., the conduction time corresponding to the phase shift angle does not exceed the conduction time of the switch on the same side), thus fundamentally eliminating the risk of shoot-through short circuits between the interleaved bridge arms. In steady-state high-frequency switching, the high-frequency current in the interleaved branches ( and It can accurately achieve the target reverse current in both the positive and negative half-cycles. Furthermore, considering the parasitic output capacitance of the device under actual operating conditions... The system incorporates nonlinear characteristics that dynamically change with the output voltage into its actual modulation algorithm. The dynamic margin ensures that the intraphase circulation has sufficient charge pumping capability in any transient range.

[0041] Figure 8 This indicates that for a single switching transistor (such as the first high-side switching transistor) By amplifying and analyzing the microscopic transient waveform, it can be clearly observed that: at the gate drive signal (which controls the gate to turn on) Before reaching its destination, the inductor current driven by the intra-phase differential mode voltage... It has precisely climbed to the theoretically set soft-switching threshold ( ). Subsequently, in the set During the dead time, the controlled circulating current rapidly and completely drains the output junction capacitance charge of the switch transistor, causing the drain-source voltage ( Before the control signal is turned on, the voltage not only smoothly drops to zero, but is even clamped to a negative threshold voltage. This transient process confirms that the system achieves zero-voltage turn-on (ZVS) without any auxiliary buffer circuitry.

[0042] like Figure 5 and Figure 9 As shown, based on the aforementioned GaN precise loss model (eliminating turn-on loss and reverse recovery loss, retaining only dead-time conduction and hard-turn-off losses), this application extracted loss data at different switching frequencies. The data shows that, with increasing frequency, the theoretically calculated values ​​and the simulated measured values ​​exhibit a highly consistent U-shaped curve distribution. Under high-frequency operation, compared with a single-stage differential boost inverter (DBI) using traditional hard-switching control, the total power loss of this application is significantly reduced by more than 30%. Meanwhile, efficiency verification across the full load power range shows that in the low-to-medium power range, the simulated efficiency almost perfectly matches the theoretical limit. As the output power gradually approaches full load, although the proportion of current losses in passive components such as the main inductor and differential-mode inductor naturally increases, leading to a slight expected decrease in overall system efficiency, the overall efficiency performance still exhibits a good level.

[0043] In summary, this application has the following advantages: 1) Full-range fixed-frequency ZVS: This application ensures that the inverter can achieve zero-voltage turn-on across the entire load range by precisely controlling the quadrilateral circulating current within the phase. Furthermore, the entire system operates at a fixed switching frequency, greatly simplifying the design of the subsequent EMI filter and reducing its size.

[0044] 2) A minimalist control system, eliminating hardware dependence: This application completely eliminates the reliance of traditional technologies on high-bandwidth zero-crossing detection (ZCD) hardware circuits or complex numerical solution algorithms. The formula for calculating the carrier phase shift angle is simple and analytical, significantly reducing the computational burden on the digital controller.

[0045] 3) Perfectly adapted to GaN devices, eliminating switching losses: This application combines the physical characteristics of GaN devices, which have no reverse recovery loss (majority carrier conduction), to achieve ZVS turn-on, thereby completely eliminating turn-on loss and reverse recovery loss, enabling the system to maintain extremely high efficiency at high frequencies of tens or even hundreds of kHz.

[0046] 4) Dispersion of current stress and thermal stress: This application adopts a double-bridge arm staggered parallel structure, which reduces the dynamic conduction loss of the device and effectively alleviates the problem of heat concentration, significantly improving the service life and reliability of high power density inverter system.

[0047] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0048] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A parallel interleaved differential boost inverter based on carrier phase shift, characterized in that, include: The system comprises a DC input power supply, a three-phase inverter circuit, three-phase output filter capacitors, and a digital controller. Each phase includes a first bridge arm and a second bridge arm connected in parallel. The first bridge arm includes a first high-side switch and a first low-side switch, and the second bridge arm includes a second high-side switch and a second low-side switch. A first differential-mode inductor is connected in series at the midpoint of the first bridge arm, and a second differential-mode inductor is connected in series at the midpoint of the second bridge arm. The other ends of the first and second differential-mode inductors are connected in parallel and then connected to the main inductor of their respective phases. The main inductor is connected to the output filter capacitor. The digital controller is used to dynamically phase-shift the driving carrier of the first and second bridge arms to excite a controlled intra-phase quadrilateral circulating current on the first or second differential-mode inductor, thereby achieving zero-voltage switching of the power devices.

2. The parallel interleaved differential boost inverter based on carrier phase shift according to claim 1, characterized in that, The first high-side switch, the first low-side switch, the second high-side switch, and the second low-side switch are all gallium nitride high-frequency power devices.

3. The parallel interleaved differential boost inverter based on carrier phase shift according to claim 1, characterized in that, The digital controller is used to calculate the phase shift angle between the first bridge arm carrier and the second bridge arm carrier by sampling the AC output voltage and the main inductor current in real time, obtain the voltage difference at the midpoint of the first bridge arm and the second bridge arm, and generate an amplitude-controlled intraphase quadrilateral circulating current on the first differential mode inductor and the second differential mode inductor.

4. The parallel interleaved differential boost inverter based on carrier phase shift according to claim 1, characterized in that, The inductance values ​​of the first differential mode inductor and the second differential mode inductor are equal and less than the inductance value of the main inductor.

5. A soft-switching implementation method for a parallel interleaved differential boost inverter based on carrier phase shift as described in any one of claims 1-4, characterized in that, include: Obtain the AC output voltage and main inductor current of the parallel interleaved differential boost inverter; Based on the modulation principle of parallel interleaved differential boost inverters, calculate the basic duty cycle that satisfies the requirements of sinusoidal output and DC bias. Based on the equivalent parasitic capacitance of the switching transistor and the set dead time, the zero-voltage switching critical current threshold required to complete the charging and discharging of the junction capacitance is calculated. Based on the basic duty cycle and zero-voltage switching critical current threshold, and based on the inductor volt-second balance principle, the phase shift angle between the first bridge arm carrier and the second bridge arm carrier in the parallel interleaved differential boost inverter is calculated to obtain the voltage difference at the midpoint of the first bridge arm and the second bridge arm, thereby generating an amplitude-controlled intraphase quadrilateral circulating current on the first differential mode inductor and the second differential mode inductor. Based on the phase shift angle, the phase-shifted first bridge arm carrier and the phase-shifted second bridge arm carrier are compared with the modulation wave to generate a PWM drive signal containing dead time; During the dead time, the junction capacitance voltage of the first high-side switch, the first low-side switch, the second high-side switch, or the second low-side switch corresponding to the quadrilateral circulating current in the phase is discharged to zero, thus completing zero-voltage turn-on.

6. The soft-switching implementation method according to claim 5, characterized in that, The formula for calculating the critical current threshold of the zero-voltage switch is as follows: ； in, To preset the dead time, is the output capacitor voltage; Coss is the output capacitance.

7. The soft-switching implementation method according to claim 6, characterized in that, The formula for calculating the phase shift angle is: ； in, For phase shift angle, i Lx The main inductor current, L m This is the differential mode inductance value. T s The switching cycle.

8. The soft-switching implementation method according to claim 7, characterized in that, The constraint condition for the differential mode inductance value is: ； in, d x Based on duty cycle.

9. The soft-switching implementation method according to claim 8, characterized in that, During the dead time, the junction capacitance voltage of the first high-side switch, the first low-side switch, the second high-side switch, or the second low-side switch corresponding to the in-phase quadrilateral circulating current is discharged to zero, completing zero-voltage turn-on, specifically including: Within one switching cycle, the switching transistors to be turned on in the first and second bridge arms are turned on at zero voltage through resonance and circulating current control in eight continuous operating stages; wherein, by utilizing the resonance between the inductor current and the output capacitor during the dead time, the junction capacitance voltage of the switching transistor to be turned on is discharged to zero before the drive signal arrives; the switching transistor to be turned on is a first high-side switching transistor, a first low-side switching transistor, a second high-side switching transistor, or a second low-side switching transistor.

10. The soft-switching implementation method according to claim 9, characterized in that, The eight continuous operating stages include: the first dead zone resonance stage, the phase-internal circulation current decrease stage, the second dead zone resonance stage, the first circulation current holding stage, the third dead zone resonance stage, the phase-internal circulation current increase stage, the fourth dead zone resonance stage, and the second circulation current holding stage. During the first dead-zone resonance phase, the first high-side switch is turned off, and reverse current is used to extract charge, discharging the junction capacitance voltage of the first low-side switch to zero. During the phase-internal circulating current decrease phase, the first low-side switch is turned on with zero voltage, the first differential-mode inductor bears a negative voltage, and the phase-internal circulating current decreases linearly. During the second dead-zone resonance phase, the second high-side switch is turned off, and reverse current is used to discharge the junction capacitance voltage of the second low-side switch to zero. During the first circulating current holding phase, both the second low-side switch and the first low-side switch are turned on with zero voltage, and the phase-internal circulating current remains constant. During the third dead-zone resonance phase, the first low-side switch is turned off, and the junction capacitance voltage of the first high-side switch is discharged to zero using the forward current. During the phase-internal circulating current rise phase, the first high-side switch is turned on with zero voltage, the first differential-mode inductor bears a forward voltage, and the phase-internal circulating current rises linearly. During the fourth dead-zone resonance phase, the second low-side switch is turned off, and the junction capacitance voltage of the second high-side switch is discharged to zero using the forward current. During the second circulating current holding phase, the second high-side switch and the first high-side switch are turned on with zero voltage, and the phase-internal circulating current remains constant until the end of the cycle.

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