Sensor interface comprising a discrete-time amplifier
By using a discrete-time amplifier sensor interface and employing a noise storage capacitor to eliminate sampling noise, the dependence of noise on switching frequency and capacitor size in existing technologies is resolved. This achieves current and power consumption optimization under low-noise conditions and is suitable for biomedical signal acquisition.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- UNIV OF MACAU
- Filing Date
- 2026-04-17
- Publication Date
- 2026-07-14
AI Technical Summary
Existing low-noise analog front-end amplifier solutions have an inherent trade-off between transconductance and current consumption, resulting in high supply voltage requirements. Furthermore, discrete-time amplifiers require excessively high sampling frequencies and large capacitors, leading to high power consumption and making them unsuitable for long-term operation.
A sensor interface including a discrete-time amplifier is adopted. Through the first and second stage amplification circuits, noise cancellation network and buffer circuit, sampling noise is stored and eliminated by noise storage capacitor, reducing the switching frequency and capacitor size, and optimizing the balance between current and noise efficiency factor and power consumption and power efficiency factor.
It achieves a reduction in switching frequency and capacitor size under low noise conditions, optimizes the balance between current and noise efficiency factors and power consumption and power efficiency factors, reduces power consumption, and is suitable for biomedical signal acquisition.
Smart Images
Figure CN122394508A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of sensor interface circuit technology, and in particular to a sensor interface including a discrete-time amplifier. Background Technology
[0002] With the widespread adoption of the Internet of Things (IoT) technology, various smart sensor nodes have been extensively integrated into fields such as industrial monitoring and healthcare. As a crucial hub between sensors and digital signal processing modules, the performance of the analog front-end (AFE) directly determines the detection accuracy and power consumption level of the entire sensing system. In biomedical applications, biological signals typically exhibit low bandwidth and small amplitude characteristics, thus placing stringent requirements on the noise performance and power efficiency of the analog front-end amplifier.
[0003] Current low-noise analog front-end amplifier solutions include continuous-time amplifiers (CTAs), which are widely used in analog signal processing. To overcome the inherent trade-off between transconductance and current consumption of MOS (Metal-Oxide-Semiconductor) transistors in CTAs, which limits the noise efficiency factor (NEF), transconductance enhancement techniques such as stacked amplifiers and input enhancement methods are typically introduced. By reusing current, the effective transconductance is increased, thereby optimizing the noise efficiency factor.
[0004] However, in practical applications, transconductance boosting technology usually requires high supply voltage, which limits the optimization of the power efficiency factor (PEF). In addition, even if the above problems are solved by using existing discrete-time switched-capacitor series-parallel amplifiers (SPA), although passive gain can be provided in front of the continuous-time amplifier, excessively high sampling frequency and large sampling capacitor are required to achieve low input reference noise, resulting in power consumption reaching the microwatt level, which is not conducive to long-term operation. Summary of the Invention
[0005] The main objective of this application is to propose a sensor interface that includes a discrete-time amplifier, aiming to break the dependence of discrete-time amplifier noise on switching frequency and capacitor size, while reducing switching frequency and capacitor size, and achieving a trade-off optimization between current and noise efficiency factor and between power consumption and power efficiency factor.
[0006] In a first aspect, the present invention provides a sensor interface including a discrete-time amplifier, comprising: a first-stage amplifier circuit, a second-stage amplifier circuit, a noise cancellation network, and a buffer circuit; the noise cancellation network includes: multiple sets of noise storage capacitors; Wherein, the non-inverting input port of the second-stage amplifier circuit is connected to the non-inverting output port of the first-stage amplifier circuit, and the inverting input port of the second-stage amplifier circuit is connected to the inverting output port of the first-stage amplifier circuit. The first-stage amplifier circuit is used to receive differential input voltage at the input port and generate a first differential voltage signal, and the second-stage amplifier circuit is used to amplify the first differential voltage signal and generate a second differential voltage signal. The non-inverting input port of the buffer circuit and the non-inverting output port of the second-stage amplifier circuit are connected through a set of noise storage capacitors. The inverting input port of the buffer circuit and the inverting output port of the second-stage amplifier circuit are connected through a set of noise storage capacitors. The buffer circuit is used to output a differential output voltage, which corresponds to the difference between the first output voltage at the non-inverting output node and the second output voltage at the inverting output node.
[0007] In an optional implementation, the noise cancellation network is used to store and cancel the sampling noise generated by the first-stage amplifier circuit.
[0008] In an optional implementation, the first-stage amplifier circuit includes: a first switched-capacitor series-parallel amplifier and a second switched-capacitor series-parallel amplifier; The output of the first switched capacitor series-parallel amplifier is connected in parallel with the output of the second switched capacitor series-parallel amplifier, and the sampling and holding phases of the first switched capacitor series-parallel amplifier and the second switched capacitor series-parallel amplifier operate in opposite phases.
[0009] In an optional embodiment, the first switched capacitor series-parallel amplifier includes: multiple sets of sampling capacitors, multiple sets of signal sampling switches, multiple sets of reference sampling switches, and multiple sets of signal holding switches; The signal sampling switch is connected between the signal input terminal and the first terminal of the sampling capacitor, the reference sampling switch is connected between the reference signal input terminal and the second terminal of the sampling capacitor, the signal holding switch is connected between adjacent sampling capacitors, and the second terminal of the last set of sampling capacitors is connected between the non-inverting output port of the first stage amplifier circuit or the inverting output port of the first stage amplifier circuit.
[0010] In an optional implementation, the noise cancellation network further includes: multiple sets of auxiliary amplifiers; The input terminal of each auxiliary amplifier is connected to the second terminal of a corresponding sampling capacitor in the first stage amplifier circuit, the output terminal of each auxiliary amplifier is connected to the first terminal of a corresponding noise storage capacitor, and the last noise storage capacitor is connected to the non-inverting output port and the inverting output port of the second stage amplifier circuit.
[0011] In an optional implementation, the circuit structure of the auxiliary amplifier is the same as that of the second-stage amplifier circuit, and the auxiliary amplifier and the corresponding second-stage amplifier circuit work alternately.
[0012] In an optional implementation, the second-stage amplifier circuit includes: a differential input transistor pair, a tail current source, and a common-mode feedback circuit; The differential input transistor pair includes a first P-channel metal-oxide-semiconductor field-effect transistor (PMOS), a second PMOS, a first N-channel metal-oxide-semiconductor field-effect transistor (NMOS), and a second NMOS. The gate of the first PMOS transistor is connected to the gate of the first NMOS transistor to form the non-inverting input port of the second-stage amplifier circuit, and the gate of the second PMOS transistor is connected to the gate of the second NMOS transistor to form the inverting input port of the second-stage amplifier circuit. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor to form the inverting output port of the second-stage amplifier circuit, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor to form the non-inverting output port of the second-stage amplifier circuit.
[0013] In an optional embodiment, the second-stage amplifier circuit further includes: a first tail transistor, a second tail transistor, a third tail transistor, a fourth tail transistor, and a common-mode control circuit. The source of the first tail transistor is connected to the source of the second tail transistor, the drain of the first tail transistor is connected to the source of the first PMOS transistor, the drain of the second tail transistor is connected to the source of the second PMOS transistor, and the gate of the second tail transistor is connected to the gate of the first tail transistor. The common-mode control circuit includes a first pair of series common-mode pseudo resistors. The two ends of the first pair of series common-mode pseudo resistors are respectively connected to the non-inverting output port and the inverting output port of the second-stage amplifier circuit. The middle node of the first pair of series common-mode pseudo resistors is connected to the gate of the third tail transistor and the gate of the fourth tail transistor. The drain of the third tail transistor is connected to the source of the first NMOS transistor, the drain of the fourth tail transistor is connected to the source of the second NMOS transistor, the source of the third tail transistor and the source of the fourth tail transistor are grounded, and the gate of the third tail transistor is connected to the gate of the fourth tail transistor for receiving common-mode feedback voltage signals.
[0014] In an optional implementation, the sensor interface further includes: a first control switch; The first control switch is a PMOS transistor. The source of the first control switch is connected to the power supply. The gate of the first control switch is connected to the enable signal output terminal of the control circuit to receive the enable control signal. The drain of the first control switch is connected to the connection node between the source of the first tail transistor and the source of the second tail transistor. The first control switch is used to turn on when the enable control signal is valid, so as to enable the second stage amplifier circuit; and to turn off when the enable control signal is invalid, so as to disable the second stage amplifier circuit and reset the output of the second stage amplifier circuit to the common-mode voltage.
[0015] In an optional implementation, the non-inverting input node of the sensor interface is connected to the non-inverting input port of the first-stage amplifier circuit, and the inverting input node of the sensor interface is connected to the inverting input port of the first-stage amplifier circuit. The non-inverting output port of the first-stage amplifier circuit is connected to the non-inverting input port of the second-stage amplifier circuit, and the inverting output port of the first-stage amplifier circuit is connected to the inverting input port of the second-stage amplifier circuit. The non-inverting output port of the second-stage amplifier circuit is connected to the non-inverting input port of the buffer circuit through a set of noise storage capacitors, and the inverting output port of the second-stage amplifier circuit is connected to the inverting input port of the buffer circuit through a set of noise storage capacitors. The non-inverting output port of the buffer circuit is the non-inverting output node of the sensor interface, and the inverting output port of the buffer circuit is the inverting output node of the sensor interface.
[0016] The beneficial effects of the embodiments of this application are: The sensor interface including a discrete-time amplifier provided in this application embodiment includes: a first-stage amplifier circuit, a second-stage amplifier circuit, a noise cancellation network, and a buffer circuit; the noise cancellation network includes multiple sets of noise storage capacitors. Specifically, the non-inverting input port of the second-stage amplifier circuit is connected to the non-inverting output port of the first-stage amplifier circuit, and the inverting input port of the second-stage amplifier circuit is connected to the inverting output port of the first-stage amplifier circuit; the non-inverting input port of the buffer circuit is connected to the non-inverting output port of the second-stage amplifier circuit through one set of the noise storage capacitors, and the inverting input port of the buffer circuit is connected to the inverting output port of the second-stage amplifier circuit through another set of the noise storage capacitors. The sensor interface receives the differential input voltage and generates a first differential signal through a first-stage amplifier circuit. The second-stage amplifier circuit amplifies the first differential signal to generate a second differential signal. The noise storage capacitor stores and eliminates the sampling noise generated by the first-stage amplifier circuit and then transmits it to the buffer circuit. The buffer circuit outputs a differential output voltage, which realizes the elimination of sampling noise while effectively amplifying the signal. This breaks the dependence of discrete-time amplifier noise on switching frequency and capacitor size, while reducing the switching frequency and capacitor size, and optimizing the balance between current and noise efficiency factor and between power consumption and power efficiency factor. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A schematic diagram of a sensor interface including a discrete-time amplifier is provided for an embodiment of this application; Figure 2 This is a schematic diagram of noise cancellation simulation results provided in an embodiment of this application; Figure 3 This is a schematic diagram comparing the measurement results of frequency response and input noise power spectral density provided in an embodiment of this application. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0020] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0021] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0022] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0023] In the description of this application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0024] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0025] Current low-noise analog front-end amplifier solutions include continuous-time amplifiers (CTAs), which are widely used in analog signal processing. To overcome the inherent trade-off between transconductance and current consumption of MOS (Metal-Oxide-Semiconductor) transistors in CTAs, which limits the noise efficiency factor (NEF), transconductance enhancement techniques such as stacked amplifiers and input enhancement methods are typically introduced. By reusing current, the effective transconductance is increased, thereby optimizing the noise efficiency factor.
[0026] However, in practical applications, transconductance boosting technology usually requires high supply voltage, which limits the optimization of the power efficiency factor (PEF). In addition, even if the above problems are solved by using existing discrete-time switched-capacitor series-parallel amplifiers (SPA), although passive gain can be provided in front of the continuous-time amplifier, excessively high sampling frequency and large sampling capacitor are required to achieve low input reference noise, resulting in power consumption reaching the microwatt level, which is not conducive to long-term operation.
[0027] To address the aforementioned issues, the main objective of this application is to propose a sensor interface that includes a discrete-time amplifier. This aims to break the dependence of noise in the discrete-time amplifier on the switching frequency and capacitor size, while simultaneously reducing the switching frequency and capacitor size, thereby achieving a trade-off optimization between current and noise efficiency factors, as well as between power consumption and power efficiency factors.
[0028] Figure 1 This application provides a schematic diagram of a sensor interface including a discrete-time amplifier, as an embodiment of the present application. This sensor interface including the discrete-time amplifier can be used, for example, in a biomedical signal acquisition device. When applied to a biomedical signal acquisition device, the device may include, for example, at least a controller with communication and data processing functions. This controller can, for example, connect to an external sensor through the sensor interface including the discrete-time amplifier to receive acquisition signals or data from the external sensor. It is understood that the above is merely a possible example, and the actual application scenarios of the sensor interface including the discrete-time amplifier are not limited to the above examples. Instead, it can be applied to different scenarios according to actual needs. Please refer to [reference needed]. Figure 1 The sensor interface includes: The circuit consists of a first-stage amplifier, a second-stage amplifier, a noise cancellation network, and a buffer circuit. The noise cancellation network includes multiple sets of noise storage capacitors.
[0029] The non-inverting input port of the second-stage amplifier circuit is connected to the non-inverting output port of the first-stage amplifier circuit, and the inverting input port of the second-stage amplifier circuit is connected to the inverting output port of the first-stage amplifier circuit. The first-stage amplifier circuit is used to receive differential input voltage at the input port and generate a first differential voltage signal, and the second-stage amplifier circuit is used to amplify the first differential voltage signal and generate a second differential voltage signal.
[0030] The non-inverting input port of the buffer circuit and the non-inverting output port of the second-stage amplifier circuit are connected through a set of noise storage capacitors. The inverting input port of the buffer circuit and the inverting output port of the second-stage amplifier circuit are connected through a set of noise storage capacitors. The buffer circuit is used to output a differential output voltage, which corresponds to the difference between the first output voltage at the non-inverting output node and the second output voltage at the inverting output node.
[0031] Furthermore, the noise cancellation network described above can be used to store and eliminate the sampling noise generated by the first-stage amplifier circuit.
[0032] For example, the first-stage amplifier circuit described above can be composed of a switched-capacitor series-parallel amplifier (SPA). This SPA provides passive gain to the input signal, thereby reducing the noise contribution of subsequent circuits. The second-stage amplifier circuit described above can be a transconductance amplifier to provide sufficient gain and bandwidth. The noise cancellation network described above includes multiple sets of noise storage capacitors, such as the first to tenth noise storage capacitors, for storing the sampling noise generated by the first-stage amplifier circuit (e.g., kT / C noise, which is a thermal noise whose magnitude is determined by the Boltzmann constant k, absolute temperature T, and sampling capacitance C, also known as Johnson-Nyquist noise, but not limited thereto). The buffer circuit described above can be a unity-gain buffer for outputting a differential output voltage to facilitate testing or driving subsequent loads.
[0033] In practical applications, biomedical signals (such as ECG and EEG) typically have low bandwidth and small amplitude, therefore the noise performance of the sensor interface directly affects the accuracy of biomedical signal acquisition. The sampling capacitor in the first-stage amplifier circuit generates kT / C noise during switching operations. If this noise is not eliminated, it will significantly degrade the input reference noise. This application addresses this issue by setting the aforementioned noise cancellation network in the sensor interface. This noise is treated as a fixed voltage offset and stored in noise storage capacitors at different time slots. It is then transmitted along with the signal during the amplification stage and cancels each other out, thus achieving noise cancellation.
[0034] Specifically, a SP with kT / C noise cancellation can use N switched-capacitor units as the input stage (e.g., N=10) to achieve a low noise level, while introducing N times passive voltage gain to reduce noise in subsequent stages. To ensure the output is always driven, two time-interleaved SPs operate in opposite phases. During the noise pre-storage stage, the kT / C noise of the sampling capacitors at the SP input is sequentially stored in the noise storage capacitor at different time slots with a voltage offset sampled at a fixed time on the falling edge of the clock. During the amplification stage, the noise of the sampling capacitors is canceled by the series-connected noise storage capacitors. However, due to limited bandwidth, the auxiliary amplifier is not fully stable during the corresponding time slot, which may lead to incomplete noise cancellation. The residual noise that is not completely canceled can be represented by, for example, the following formula:
[0035] Among them, the above This indicates residual noise that was not completely eliminated, as mentioned above. Indicating noise cancellation efficiency, the above The number of switched capacitor units (i.e., the number of sampling capacitors) mentioned above Where is the Boltzmann constant, the above For absolute temperature, the above The capacitance value of a single sampling capacitor, as described above. This refers to the switching frequency of the SPA.
[0036] The above noise cancellation efficiency It is approximately the ratio of the pre-stored noise voltage to the output amplified noise voltage of the second-stage amplifier circuit, and can therefore be calculated using the following formula:
[0037] Among them, the above For the gain of the auxiliary amplifier, the above For the gain of the second-stage amplifier circuit, the above The sampling time of the noise storage capacitor, as described above The above is the settling time constant of the auxiliary amplifier. It is a natural constant.
[0038] Figure 2 This is a schematic diagram of noise cancellation simulation results provided in an embodiment of this application. Please refer to... Figure 2An ideal noise storage amplifier achieves near-complete noise cancellation (approximately 96%) across all sampling capacitor values. With a single sampling capacitor of 1.5 pF and noise storage via a second-stage amplifier, the noise cancellation efficiency reaches 92% and 72% for storage times of 2 microseconds and 1 microsecond, respectively. Furthermore, the noise cancellation efficiency also depends on the gain matching between the second-stage amplifier and the auxiliary amplifier. Monte Carlo simulations (200 runs) show an average gain error of 1 and a standard deviation of 0.02, indicating that device mismatch has a significantly low impact on noise cancellation efficiency. The amplifier's dominant pole is located at the output of the SPA and increases proportionally with the SPA switching frequency. The analog bandwidth is 2.5 kHz, and the switching frequency is 10 kHz. Due to the short sampling time (2 microseconds), input distortion voltage caused by leakage at the inputs of the second-stage amplifier and the auxiliary amplifier is negligible.
[0039] Based on this, without noise cancellation, the mean square value of the input reference noise can be expressed as follows:
[0040] Among them, the above That is, the mean square value of the input reference noise mentioned above. The above represents the mean square noise value equivalent to the input of the second-stage amplifier circuit. For the passive voltage gain of SPA, based on the above, for example it could be... .
[0041] Based on the above noise cancellation principle, in the case of multi-path kT / C noise cancellation, the mean square value of the input reference noise can be expressed as follows:
[0042] When multipath kT / C noise cancellation reaches the ideal state (i.e., the noise cancellation efficiency mentioned above) When the value is close to 1, the mean square value of the input reference noise is approximately:
[0043] Based on this, and according to the calculation formulas for the noise efficiency factor (NEF) and power efficiency factor (PEF) shown below, the final NEF and PEF values can be calculated:
[0044]
[0045] Among them, the above The effective value of the input reference noise can be calculated using the following formula:
[0046] The above The above refers to the total current of the entire sensor interface. Thermoelectric voltage, Boltzmann's constant, as mentioned above , The absolute temperature mentioned above, For bandwidth, This is the power supply voltage. Since the multipath kT / C noise eliminates the sampling noise of the SPA, the effective value of the input reference noise is... Therefore, the above is reduced. and This process can be reduced accordingly, thus achieving optimization.
[0047] Figure 3 This diagram illustrates a comparison of frequency response and input noise power spectral density measurement results according to an embodiment of this application. The diagram compares the changes and comparisons of frequency response and input noise power spectral density (PSD) before and after noise cancellation. The measurement results are obtained using a multipath noise cancellation discrete-time amplifier implemented with a 180nm CMOS process, a SPA ratio of 1:10 (i.e., N=10), a switching frequency of 10kHz, a unit sampling capacitance of 1.5pF, and a noise storage capacitance of 0.2pF. This multipath noise cancellation discrete-time amplifier can, for example, use a 0.8V power supply and consumes 36nm current. Figure 3 As shown, Figure 3 In the first image (the one at the top), the vertical axis represents gain in decibels (dB), and the horizontal axis represents frequency in hertz (Hz). Figure 3 In the second graph (below), the vertical axis represents the noise power spectral density in volts per square hertz (V / √Hz), and the horizontal axis represents frequency in hertz. This amplifier achieves a gain of 43.5 dB over a 2 kHz bandwidth. The measured common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are 60 dB and 58 dB, respectively. The input impedance reaches approximately 56 megohms, meeting the high impedance requirements of biosensors. The reference noise level is significantly reduced from 300 nanovolts per square hertz (nV / √Hz). The integrated input reference noise (IRN) is 1.98 microvolts RMS (μVrms), corresponding to a NEF of 0.32 and a PEF of 0.08.
[0048] The sensor interface including a discrete-time amplifier provided in this application includes: a first-stage amplifier circuit, a second-stage amplifier circuit, a noise cancellation network, and a buffer circuit. The noise cancellation network includes multiple sets of noise storage capacitors. The non-inverting input port of the second-stage amplifier circuit is connected to the non-inverting output port of the first-stage amplifier circuit, and the inverting input port of the second-stage amplifier circuit is connected to the inverting output port of the first-stage amplifier circuit. The non-inverting input port of the buffer circuit is connected to the non-inverting output port of the second-stage amplifier circuit through one set of the noise storage capacitors, and the inverting input port of the buffer circuit is connected to the inverting output port of the second-stage amplifier circuit through another set of the noise storage capacitors. The sensor interface receives the differential input voltage and generates a first differential signal through a first-stage amplifier circuit. The second-stage amplifier circuit amplifies the first differential signal to generate a second differential signal. The noise storage capacitor stores and eliminates the sampling noise generated by the first-stage amplifier circuit. The buffer circuit outputs a differential output voltage, which realizes the elimination of sampling noise while effectively amplifying the signal. This breaks the dependence of discrete-time amplifier noise on switching frequency and capacitor size, while reducing the switching frequency and capacitor size, and optimizing the balance between current and noise efficiency factor and between power consumption and power efficiency factor.
[0049] Further, please continue to refer to Figure 1 In the aforementioned Figure 1 Based on the embodiment, the first-stage amplifier circuit mentioned above includes: a first switched-capacitor series-parallel amplifier and a second switched-capacitor series-parallel amplifier.
[0050] The output terminal of the first switched capacitor series-parallel amplifier is connected in parallel with the output terminal of the second switched capacitor series-parallel amplifier, and the sampling and holding phases of the first switched capacitor series-parallel amplifier and the second switched capacitor series-parallel amplifier operate in opposite phases.
[0051] For example, the first and second switched-capacitor series-parallel amplifiers described above can be of the same structure. Connecting the output terminals of the first and second switched-capacitor series-parallel amplifiers in parallel ensures that the first-stage amplifier circuit has a stable signal output at any time.
[0052] Specifically, the sampling and hold phases of the first and second switched-capacitor series-parallel amplifiers operate in reverse phase. For example, when the first switched-capacitor series-parallel amplifier is in the sampling phase, the second switched-capacitor series-parallel amplifier is in the hold phase, and vice versa. This time-staggered inverse operation ensures that the two switched-capacitor amplifiers work alternately, maintaining effective drive at all times for the output of the first-stage amplifier circuit, thus avoiding the problem of a single switched-capacitor amplifier being unable to output a signal during the sampling phase.
[0053] It is understood that the specific circuit structure, number of sampling capacitors, and switching timing of the first and second switched capacitor series-parallel amplifiers can be adjusted and determined according to the actual situation, and are not restricted here.
[0054] Furthermore, such as Figure 1 As shown, based on the above embodiments, the first switched capacitor series-parallel amplifier includes: multiple sets of sampling capacitors, multiple sets of signal sampling switches, multiple sets of reference sampling switches, and multiple sets of signal holding switches.
[0055] The signal sampling switch is connected between the signal input terminal and the first terminal of the sampling capacitor, the reference sampling switch is connected between the reference signal input terminal and the second terminal of the sampling capacitor, the signal holding switch is connected between adjacent sampling capacitors, and the second terminal of the last set of sampling capacitors is connected between the non-inverting output port of the first-stage amplifier circuit or the inverting output port of the first-stage amplifier circuit.
[0056] For example, the aforementioned multiple sampling capacitors may include 10 sampling capacitors, from group 1 to group 10, each sampling capacitor having a first terminal and a second terminal. A signal sampling switch is connected between the signal input terminal (e.g., a differential signal from an external sensor) and the first terminal of the sampling capacitor, used to control the charging sampling of the sampling capacitor by the input signal. A reference sampling switch is connected between the reference signal input terminal (e.g., common-mode voltage or reference ground) and the second terminal of the sampling capacitor, used to connect the second terminal of the sampling capacitor to a reference level during the sampling phase. Signal hold switches are connected between adjacent sampling capacitors and between the second terminal of the last sampling capacitor and the output port of the first-stage amplifier circuit. Because the first-stage amplifier circuit uses a differential structure, some signal hold switches connect the second terminal of the sampling capacitor to the non-inverting output port, and some connect it to the inverting output port; however, the specific connection method depends on whether the sampling capacitor is processing a non-inverting or inverting signal.
[0057] During the sampling phase, the signal sampling switch and the reference sampling switch are turned on, while the signal hold switch is turned off. The first terminal of the sampling capacitor receives the input signal, and the second terminal is connected to the reference level, thus completing signal sampling. During the hold phase, the signal sampling switch and the reference sampling switch are turned off, while the signal hold switch is turned on. The sampling capacitors are connected in series, and the second terminal of the last set of sampling capacitors is connected to the output port of the first-stage amplifier circuit. At this time, multiple sampling capacitors discharge in series, forming a passively amplified signal at the output port. Through this switching timing control, the first switched-capacitor series-parallel amplifier realizes the sampling, holding, and passive amplification of the input signal.
[0058] It is understood that the aforementioned signal sampling switch, reference sampling switch, and signal holding switch can be implemented using MOS transistors, and the specific dimensions, on-resistance, and clock control timing of the signal sampling switch, reference sampling switch, and signal holding switch can be adjusted and determined according to the sampling frequency and accuracy requirements, without any restrictions here.
[0059] Further, please continue to refer to Figure 1 Based on the above embodiments, the noise cancellation network further includes multiple sets of auxiliary amplifiers.
[0060] The input terminal of each auxiliary amplifier is connected to the second terminal of the corresponding sampling capacitor in the first-stage amplifier circuit, the output terminal of each auxiliary amplifier is connected to the first terminal of the corresponding noise storage capacitor, and the last noise storage capacitor is connected to the non-inverting output port and the inverting output port of the second-stage amplifier circuit.
[0061] For example, the aforementioned multiple sets of auxiliary amplifiers may include 10 sets of auxiliary amplifiers, from set 1 to set 10, with the number of auxiliary amplifiers corresponding to the number of sampling capacitor sets (i.e., the number N of switched capacitor units). Taking one set of auxiliary amplifiers as an example, the non-inverting and inverting input terminals of this auxiliary amplifier are respectively connected to the second terminals of the corresponding set of sampling capacitors in the first-stage amplifier circuit. Specifically, for the sampling capacitor that processes the non-inverting signal, the second terminal of the sampling capacitor is connected to the non-inverting input terminal of the auxiliary amplifier. For the sampling capacitor that processes the inverting signal, the second terminal of the sampling capacitor is connected to the inverting input terminal of the auxiliary amplifier. The non-inverting and inverting output terminals of this auxiliary amplifier are connected to the first terminals of the corresponding set of noise storage capacitors, and the non-inverting and inverting output terminals of the last set of auxiliary amplifiers are respectively connected to the non-inverting and inverting output ports of the second-stage amplifier circuit. Furthermore, the aforementioned sampling capacitors can be differential sampling capacitors, but are not limited thereto.
[0062] In the actual noise pre-storage stage, the auxiliary amplifier is enabled, amplifying the kT / C noise voltage sampled from the sampling capacitor and storing the amplified noise voltage in the corresponding noise storage capacitor. In the subsequent signal amplification stage, the second-stage amplifier circuit is enabled. At this time, the noise voltage stored in the noise storage capacitor cancels out the noise components in the signal path, thus achieving noise cancellation. By setting multiple sets of auxiliary amplifiers, the noise from each sampling capacitor can be processed, improving the noise cancellation efficiency.
[0063] Furthermore, the circuit structure of the auxiliary amplifier can be the same as that of the second-stage amplifier circuit to ensure that the gain of the auxiliary amplifier matches the gain of the second-stage amplifier circuit, thereby improving noise cancellation efficiency. The specific timing control method of the auxiliary amplifier and the second-stage amplifier circuit can be adjusted and determined according to actual needs, and is not limited here.
[0064] Furthermore, based on the above embodiments, the circuit structure of the auxiliary amplifier is the same as that of the second-stage amplifier circuit, and the auxiliary amplifier and the corresponding second-stage amplifier circuit work alternately.
[0065] For example, the circuit structure of the auxiliary amplifier is the same as that of the second-stage amplifier circuit. For instance, it can mean that both the circuit structure of the auxiliary amplifier and the circuit structure of the second-stage amplifier circuit can adopt a transconductance amplifier (OTA) structure and have the same transistor size and bias current setting.
[0066] By making the circuit structure of the auxiliary amplifier identical to that of the second-stage amplifier, it is ensured that the gain of the auxiliary amplifier matches that of the second-stage amplifier, thereby achieving high noise cancellation efficiency during noise storage and cancellation. Simultaneously, the auxiliary amplifier and the corresponding second-stage amplifier operate alternately; that is, during the noise pre-storage phase, the auxiliary amplifier is enabled while the second-stage amplifier is disabled. During the signal amplification phase, the second-stage amplifier is enabled while the auxiliary amplifier is disabled. This alternating operation enables time multiplexing, avoiding the additional power consumption caused by simultaneous amplifier operation, thus improving the overall energy efficiency of the sensor interface.
[0067] Additionally, when the auxiliary amplifier or second-stage amplifier circuit is disabled, the corresponding output is reset to the common-mode voltage to quickly stabilize the output state upon reactivation and minimize interference with pre-stored noise.
[0068] Alternatively, please continue to refer to Figure 1 In the aforementioned Figure 1 Based on the embodiment, the above-mentioned second-stage amplifier circuit includes: a differential input transistor pair, a tail current source, and a common-mode feedback circuit.
[0069] The aforementioned differential input transistor pair includes a first P-channel metal-oxide-semiconductor field-effect transistor (PMOS), a second PMOS, a first N-channel metal-oxide-semiconductor field-effect transistor (NMOS), and a second NMOS.
[0070] The gate of the first PMOS transistor is connected to the gate of the first NMOS transistor to form the non-inverting input port of the second-stage amplifier circuit, and the gate of the second PMOS transistor is connected to the gate of the second NMOS transistor to form the inverting input port of the second-stage amplifier circuit.
[0071] The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor to form the inverting output port of the second-stage amplifier circuit, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor to form the non-inverting output port of the second-stage amplifier circuit.
[0072] For example, the aforementioned differential input transistor pair employs a complementary structure, meaning it simultaneously includes a PMOS transistor and an NMOS transistor as the input stage. The gates of the first PMOS transistor and the first NMOS transistor are connected to form a non-inverting input port, used to receive signals from the non-inverting output port of the first-stage amplifier circuit. The gates of the second PMOS transistor and the second NMOS transistor are connected to form an inverting input port, used to receive signals from the inverting output port of the first-stage amplifier circuit. This complementary input structure can improve the transconductance efficiency of the second-stage amplifier circuit.
[0073] The drains of the first PMOS and the first NMOS transistors are connected to form an inverting output port, while the drains of the second PMOS and the second NMOS transistors are connected to form a non-inverting output port. This connection method enhances the transconductance of the PMOS and NMOS transistors, simultaneously improving noise and bandwidth performance. A tail current source provides bias current to the differential input transistor pair, and a common-mode feedback circuit stabilizes the common-mode level at the output port, ensuring the stability of the second-stage amplifier circuit at its operating point.
[0074] It is understandable that the dimensions (such as the width-to-length ratio) of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor can be adjusted and determined according to the gain and bandwidth requirements. The current value of the tail current source and the specific implementation method of the common-mode feedback circuit can also be selected and determined according to actual needs, and no specific restrictions are imposed here.
[0075] Furthermore, based on the above embodiments, the second-stage amplifier circuit further includes: a first tail transistor, a second tail transistor, a third tail transistor, a fourth tail transistor, and a common-mode control circuit.
[0076] The source of the first tail transistor is connected to the source of the second tail transistor, the drain of the first tail transistor is connected to the source of the first PMOS transistor, the drain of the second tail transistor is connected to the source of the second PMOS transistor, and the gate of the second tail transistor is connected to the gate of the first tail transistor.
[0077] The common-mode control circuit includes a first pair of series common-mode pseudo resistors. The two ends of the first pair of series common-mode pseudo resistors are respectively connected to the non-inverting output port and the inverting output port of the second-stage amplifier circuit. The middle node of the first pair of series common-mode pseudo resistors is connected to the gate of the third tail transistor and the gate of the fourth tail transistor.
[0078] The drain of the third tail transistor is connected to the source of the first NMOS transistor, the drain of the fourth tail transistor is connected to the source of the second NMOS transistor, the source of the third tail transistor and the source of the fourth tail transistor are grounded, and the gate of the third tail transistor is connected to the gate of the fourth tail transistor for receiving common-mode feedback voltage signals. like Figure 1 As shown, the first tail transistor and the second tail transistor constitute a current mirror structure. The source of the first tail transistor and the source of the second tail transistor are connected. The first tail transistor and the second tail transistor can, for example, serve as part of the tail current source, providing a stable bias current to the differential input transistor pair in the form of a current mirror.
[0079] The aforementioned common-mode control circuit includes a first pair of series common-mode pseudo-resistors. The two ends of this first pair of series common-mode pseudo-resistors are connected to the non-inverting output port and the inverting output port of the second-stage amplifier circuit, respectively. The middle node of this first pair of series common-mode pseudo-resistors is connected to the gates of the third and fourth tail transistors. The pseudo-resistors can be implemented, for example, using two back-to-back PMOS transistors, which have high resistance characteristics and can extract the common-mode level of the output port at low frequencies without introducing additional DC power consumption. The voltage at the middle node of the first pair of series common-mode pseudo-resistors is approximately equal to the common-mode level of the non-inverting and inverting output ports. This voltage is sent to the gates of the third and fourth tail transistors to control their conduction levels.
[0080] The third and fourth tail transistors form the common-mode feedback adjustment branch. When the output common-mode level is too high, the voltage at the intermediate node of the first pair of series common-mode pseudo-resistors rises, causing the gate voltages of the third and fourth tail transistors to rise. This increases the current flowing through the third and fourth tail transistors, pulling the output common-mode level down. Conversely, when the output common-mode level is too low, the voltage at the intermediate node of the first pair of series common-mode pseudo-resistors drops, causing the gate voltages of the third and fourth tail transistors to drop. This reduces the current flowing through the third and fourth tail transistors, pulling the output common-mode level up, thus stabilizing the output common-mode level.
[0081] However, it should be noted that the specific types (such as PMOS or NMOS), dimensions, and bias conditions of the first, second, third, and fourth tail transistors can be adjusted and determined according to the power supply voltage and process requirements. The specific implementation of the first pair of series common-mode pseudo resistors is not limited to back-to-back PMOS transistors, but can be adjusted and determined according to actual needs.
[0082] In addition, based on the foregoing embodiments, the sensor interface may further include a first control switch.
[0083] The first control switch is a PMOS transistor. The source of the first control switch is connected to the power supply. The gate of the first control switch is connected to the enable signal output terminal of the control circuit to receive the enable control signal. The drain of the first control switch is connected to the connection node between the source of the first tail transistor and the source of the second tail transistor.
[0084] The first control switch is turned on when the enable control signal is valid, thereby enabling the second-stage amplifier circuit. When the enable control signal is invalid, it is turned off to disable the second-stage amplifier circuit and reset the output of the second-stage amplifier circuit to a common-mode voltage.
[0085] For example, the first control switch is a PMOS transistor. The source of the first control switch is connected to the power supply, and the drain of the first control switch is connected to the junction of the source of the first tail transistor and the source of the second tail transistor. The gate of the first control switch is connected to the enable signal output terminal of the control circuit to receive the enable control signal.
[0086] When the enable control signal is low (i.e., active), the first control switch is turned on, and the power supply voltage flows through the first control switch to power the power source and the tail current source. The tail current source is activated, providing bias current to the differential input transistor pair, thereby enabling the second-stage amplifier circuit, which then enters normal operation. When the enable control signal is high (i.e., inactive), the first control switch is turned off, the tail current source is disconnected from the power supply, and the tail current source is turned off, disabling the second-stage amplifier circuit. Simultaneously with the second-stage amplifier circuit being disabled, its outputs (including the non-inverting and inverting output ports) are reset to common-mode voltage. This reset function can be achieved through auxiliary circuitry (e.g., a switch shorting the outputs to the common-mode voltage) to ensure rapid stabilization upon re-enabling the second-stage amplifier circuit and to minimize interference with pre-stored noise in the noise storage capacitor.
[0087] Of course, the effective level (active low or active high) of the above-mentioned enable control signal can be adjusted according to the actual PMOS transistor and peripheral circuit design. The specific size of the first control switch (such as the width-to-length ratio) can be determined according to the parasitic capacitance of the tail current source control terminal and the switching speed requirements, and is not limited here.
[0088] Optionally, in the foregoing Figure 1 Based on the embodiment, the non-inverting input node of the sensor interface is connected to the non-inverting input port of the first-stage amplifier circuit, and the inverting input node of the sensor interface is connected to the inverting input port of the first-stage amplifier circuit.
[0089] The non-inverting output port of the first-stage amplifier circuit is connected to the non-inverting input port of the second-stage amplifier circuit, and the inverting output port of the first-stage amplifier circuit is connected to the inverting input port of the second-stage amplifier circuit.
[0090] The non-inverting output port of the second-stage amplifier circuit is connected to the non-inverting input port of the buffer circuit through a set of noise storage capacitors, and the inverting output port of the second-stage amplifier circuit is connected to the inverting input port of the buffer circuit through a set of noise storage capacitors.
[0091] The non-inverting output port of the buffer circuit is the non-inverting output node of the sensor interface, and the inverting output port of the buffer circuit is the inverting output node of the sensor interface.
[0092] For example, the non-inverting input node of the aforementioned sensor interface is connected to the non-inverting input port of the first-stage amplifier circuit, and the inverting input node is connected to the inverting input port of the first-stage amplifier circuit. This could be to enable external differential input signals to be input into the first-stage amplifier circuit. After sampling and passively gaining the received differential input voltage, the first-stage amplifier circuit connects its non-inverting and inverting output ports to the non-inverting and inverting input ports of the second-stage amplifier circuit, respectively, transmitting the first differential voltage signal to the second-stage amplifier circuit. After amplifying the first differential voltage signal, the second-stage amplifier circuit connects its non-inverting output port to the non-inverting input port of the buffer circuit through a set of noise storage capacitors, and its inverting output port is connected to the inverting input port of the buffer circuit through another set of noise storage capacitors. The noise storage capacitors here not only serve as AC coupling but also store and transmit the sampled noise cancellation signal. Finally, the non-inverting output port of the buffer circuit acts as the non-inverting output node of the sensor interface, and the inverting output port of the buffer circuit acts as the inverting output node of the sensor interface, outputting a differential output voltage.
[0093] It is understandable that the connections between the aforementioned ports can be implemented using printed circuit board traces or internal metal interconnects within the chip. The specific routing method can be adjusted and determined based on the layout design and signal integrity requirements. Figure 1 The circuit shown is for illustrative purposes only and is not intended to limit the connection method between the ports mentioned above.
[0094] It should be noted that the above description is only a preferred embodiment of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the inventive concept of this application using the content of this application's specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.
Claims
1. A sensor interface including a discrete-time amplifier, characterized in that, include: First-stage amplifier circuit, second-stage amplifier circuit, noise cancellation network, buffer circuit; The noise cancellation network includes: multiple sets of noise storage capacitors; Wherein, the non-inverting input port of the second-stage amplifier circuit is connected to the non-inverting output port of the first-stage amplifier circuit, and the inverting input port of the second-stage amplifier circuit is connected to the inverting output port of the first-stage amplifier circuit. The first-stage amplifier circuit is used to receive differential input voltage at the input port and generate a first differential voltage signal, and the second-stage amplifier circuit is used to amplify the first differential voltage signal and generate a second differential voltage signal. The non-inverting input port of the buffer circuit and the non-inverting output port of the second-stage amplifier circuit are connected through a set of noise storage capacitors. The inverting input port of the buffer circuit and the inverting output port of the second-stage amplifier circuit are connected through a set of noise storage capacitors. The buffer circuit is used to output a differential output voltage, which corresponds to the difference between the first output voltage at the non-inverting output node and the second output voltage at the inverting output node.
2. The sensor interface according to claim 1, characterized in that, The noise cancellation network is used to store and eliminate sampling noise generated by the first-stage amplifier circuit.
3. The sensor interface according to claim 1, characterized in that, The first-stage amplifier circuit includes: a first switched-capacitor series-parallel amplifier and a second switched-capacitor series-parallel amplifier; The output of the first switched capacitor series-parallel amplifier is connected in parallel with the output of the second switched capacitor series-parallel amplifier, and the sampling and holding phases of the first switched capacitor series-parallel amplifier and the second switched capacitor series-parallel amplifier are in reverse phase.
4. The sensor interface according to claim 3, characterized in that, The first switched capacitor series-parallel amplifier includes: multiple sets of sampling capacitors, multiple sets of signal sampling switches, multiple sets of reference sampling switches, and multiple sets of signal hold switches; The signal sampling switch is connected between the signal input terminal and the first terminal of the sampling capacitor, the reference sampling switch is connected between the reference signal input terminal and the second terminal of the sampling capacitor, the signal holding switch is connected between adjacent sampling capacitors, and the second terminal of the last set of sampling capacitors is connected between the non-inverting output port of the first stage amplifier circuit or the inverting output port of the first stage amplifier circuit.
5. The sensor interface according to claim 4, characterized in that, The noise cancellation network also includes: multiple sets of auxiliary amplifiers; The input terminal of each auxiliary amplifier is connected to the second terminal of a corresponding sampling capacitor in the first stage amplifier circuit, the output terminal of each auxiliary amplifier is connected to the first terminal of a corresponding noise storage capacitor, and the last noise storage capacitor is connected to the non-inverting output port and the inverting output port of the second stage amplifier circuit.
6. The sensor interface according to claim 5, characterized in that, The circuit structure of the auxiliary amplifier is the same as that of the second-stage amplifier circuit, and the auxiliary amplifier and the corresponding second-stage amplifier circuit work alternately.
7. The sensor interface according to claim 1, characterized in that, The second-stage amplifier circuit includes: a differential input transistor pair, a tail current source, and a common-mode feedback circuit; The differential input transistor pair includes a first P-channel metal-oxide-semiconductor field-effect transistor (PMOS), a second PMOS, a first N-channel metal-oxide-semiconductor field-effect transistor (NMOS), and a second NMOS. The gate of the first PMOS transistor is connected to the gate of the first NMOS transistor to form the non-inverting input port of the second-stage amplifier circuit, and the gate of the second PMOS transistor is connected to the gate of the second NMOS transistor to form the inverting input port of the second-stage amplifier circuit. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor to form the inverting output port of the second-stage amplifier circuit, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor to form the non-inverting output port of the second-stage amplifier circuit.
8. The sensor interface according to claim 7, characterized in that, The second-stage amplifier circuit also includes: a first tail transistor, a second tail transistor, a third tail transistor, a fourth tail transistor, and a common-mode control circuit; The source of the first tail transistor is connected to the source of the second tail transistor, the drain of the first tail transistor is connected to the source of the first PMOS transistor, the drain of the second tail transistor is connected to the source of the second PMOS transistor, and the gate of the second tail transistor is connected to the gate of the first tail transistor. The common-mode control circuit includes a first pair of series common-mode pseudo resistors. The two ends of the first pair of series common-mode pseudo resistors are respectively connected to the non-inverting output port and the inverting output port of the second-stage amplifier circuit. The middle node of the first pair of series common-mode pseudo resistors is connected to the gate of the third tail transistor and the gate of the fourth tail transistor. The drain of the third tail transistor is connected to the source of the first NMOS transistor, the drain of the fourth tail transistor is connected to the source of the second NMOS transistor, the source of the third tail transistor and the source of the fourth tail transistor are grounded, and the gate of the third tail transistor is connected to the gate of the fourth tail transistor for receiving common-mode feedback voltage signals.
9. The sensor interface according to claim 7, characterized in that, The sensor interface further includes: a first control switch; The first control switch is a PMOS transistor. The source of the first control switch is connected to the power supply. The gate of the first control switch is connected to the enable signal output terminal of the control circuit to receive the enable control signal. The drain of the first control switch is connected to the connection node between the source of the first tail transistor and the source of the second tail transistor. The first control switch is used to turn on when the enable control signal is valid, so as to enable the second stage amplifier circuit; and to turn off when the enable control signal is invalid, so as to disable the second stage amplifier circuit and reset the output of the second stage amplifier circuit to the common-mode voltage.
10. The sensor interface according to claim 1, characterized in that, The non-inverting input node of the sensor interface is connected to the non-inverting input port of the first-stage amplifier circuit, and the inverting input node of the sensor interface is connected to the inverting input port of the first-stage amplifier circuit. The non-inverting output port of the first-stage amplifier circuit is connected to the non-inverting input port of the second-stage amplifier circuit, and the inverting output port of the first-stage amplifier circuit is connected to the inverting input port of the second-stage amplifier circuit. The non-inverting output port of the second-stage amplifier circuit is connected to the non-inverting input port of the buffer circuit through a set of noise storage capacitors, and the inverting output port of the second-stage amplifier circuit is connected to the inverting input port of the buffer circuit through a set of noise storage capacitors. The non-inverting output port of the buffer circuit is the non-inverting output node of the sensor interface, and the inverting output port of the buffer circuit is the inverting output node of the sensor interface.