A high-gain structure for improving linearity of a millimeter wave power amplifier

Abstract

The application discloses a high-gain structure for improving the linearity of a millimeter wave power amplifier. The structure comprises an input matching network, a driving stage amplifier, an inter-stage matching network, a power stage amplifier and an output matching network connected in sequence; wherein the input matching network and the output matching network respectively comprise a transformer and a parallel capacitor, and the inter-stage matching network comprises a transformer; the driving stage amplifier adopts a multi-gate transistor, the bias combination of which is class A and class C, and has a gain expansion characteristic; the power stage amplifier adopts a common source structure and is biased in class A, and has a gain compression characteristic. The application utilizes the cascade combination of the gain expansion of the driving stage and the gain compression of the power stage, improves the 1dB compression point of the output power of the power amplifier while maintaining high gain, and thus improves the linearity. The application can solve the problem that the 180-nm CMOS process cannot use the cascade method to improve the linearity due to low gain in the millimeter wave frequency band, and is suitable for a millimeter wave wireless communication system.

Description

Technical Field

[0001] This invention relates to a power amplifier in microwave and millimeter-wave integrated circuits, and more particularly to a high-gain structure for improving the linearity of millimeter-wave power amplifiers. Background Technology

[0002] To meet the ever-increasing demands for data transmission and wireless communication, the development of fifth-generation mobile communication technology (5G) is accelerating, and it has already begun to be applied in fields such as people's livelihood and technology. 5G FR2 covers a frequency range of 24-52GHz, featuring ultra-large bandwidth and extremely high speed, ultra-low latency, and abundant and clean spectrum resources. Although the 5G millimeter-wave band offers even richer spectrum resources and numerous benefits for data transmission and communication, the higher frequency and more complex modulation methods also place higher demands on transceivers in wireless communication systems.

[0003] As a key module in wireless systems, the performance of power amplifiers directly impacts transceiver performance, requiring high gain, high output power, high power-added efficiency, and high linearity. Traditional common-source amplifiers typically have a 3dB difference between their 1dB compression point and saturated output power, meaning the efficiency of a power amplifier operating linearly differs significantly from its saturated operating efficiency. In 5G mobile communication, high-order quadrature amplitude modulation (QAM) is widely used to achieve high-speed transmission. This modulation method places high demands on transmitter linearity, and power amplifiers often operate before the 1dB compression point to ensure linearity. The 1dB compression point can be extended by cascading amplifiers with different gain characteristics (e.g., Class C cascading Class A). However, in the millimeter-wave band, limitations imposed by the dielectric loss and low cutoff frequency of 180nm CMOS technology restrict the transistor's performance. MAX The drop in gain causes the gain of Class C power amplifiers to fall below the matching losses, posing a challenge to improving linearity through cascading different gain characteristics. Therefore, improving the gain, efficiency, and linearity of power amplifiers in the millimeter-wave band is a significant challenge. Summary of the Invention

[0004] Purpose of the Invention: This invention addresses the shortcomings of existing technologies by disclosing a high-gain structure for improving the linearity of millimeter-wave power amplifiers. It maintains high gain while improving the linear range of the power amplifier (raising the output compression point by 1dB), and is particularly suitable for 180-nm CMOS processes in the millimeter-wave band.

[0005] Technical solution: The present invention provides a high-gain structure for improving the linearity of millimeter-wave power amplifiers, comprising an input matching network, a driver stage amplifier, an inter-stage matching network, a power stage amplifier, and an output matching network;

[0006] The input matching network consists of a first matching capacitor, a first transformer, and a third resistor. One end of the primary coil of the first transformer is connected to the input terminal of the power amplifier, and the other end is grounded. The first matching capacitor is connected in parallel with the primary coil of the first transformer. The two ends of the secondary coil of the first transformer are respectively connected to the gates of the second transistor and the third transistor of the driver stage amplifier. One end of the third resistor is connected to the center tap of the secondary coil of the first transformer, and the other end is connected to the first bias voltage.

[0007] The driver stage amplifier comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first neutralizing capacitor, a second neutralizing capacitor, a first isolation capacitor, a second isolation capacitor, a first resistor, and a second resistor. The two ends of the first neutralizing capacitor are connected to the drain of the first transistor and the gate of the third transistor, respectively; the two ends of the second neutralizing capacitor are connected to the gate of the second transistor and the drain of the fourth transistor, respectively; the two ends of the first isolation capacitor are connected to the gates of the first transistor and the second transistor, respectively; the two ends of the second isolation capacitor are connected to the gates of the third transistor and the fourth transistor, respectively; the two ends of the first resistor are connected to the gate of the first transistor and a third bias voltage, respectively; the two ends of the second resistor are connected to the gate of the fourth transistor and a fourth bias voltage, respectively; the sources of the first, second, third, and fourth transistors are grounded; wherein, the selection of the third bias voltage causes the first transistor to operate in Class C mode under the corresponding input signal amplitude, and the selection of the fourth bias voltage causes the fourth transistor to operate in Class C mode under the corresponding input signal amplitude; the selection of the first bias voltage causes the second and third transistors to operate in Class A mode under the corresponding input signal amplitude.

[0008] The interstage matching network consists of a second transformer and a fourth resistor; one end of the primary coil of the second transformer is connected to the drain of the first and second transistors, and the other end is connected to the drain of the third and fourth transistors; one end of the secondary coil of the second transformer is connected to the gate of the fifth transistor, and the other end is connected to the gate of the sixth transistor; the center tap of the primary coil of the second transformer is connected to the power supply; one end of the fourth resistor is connected to the center tap of the secondary coil of the second transformer, and the other end is connected to the second bias voltage.

[0009] The power stage amplifier consists of a fifth transistor, a sixth transistor, a third neutralizing capacitor, and a fourth neutralizing capacitor; one end of the third neutralizing capacitor is connected to the drain of the fifth transistor, and the other end is connected to the gate of the sixth transistor; one end of the fourth neutralizing capacitor is connected to the gate of the fifth transistor, and the other end is connected to the gate of the sixth transistor; the sources of the fifth and sixth transistors are connected to ground; wherein, the selection of the second bias voltage causes the fifth and sixth transistors to operate in Class A mode under the amplitude of the corresponding input signal.

[0010] The output matching network consists of a third transformer and a second matching capacitor; one end of the primary coil of the third transformer is connected to the drain of the fifth transistor and the other end is connected to the drain of the sixth transistor; one end of the secondary coil of the third transformer serves as the output terminal of the power amplifier and the other end is grounded; the second matching capacitor is connected in parallel to the secondary coil of the third transformer; the center tap of the primary coil of the third transformer is connected to the power supply.

[0011] Beneficial Effects: The advantages of this invention lie in providing a high-gain structure for improving the linearity of millimeter-wave power amplifiers, comprising an input matching network, a driver stage amplifier, an inter-stage matching network, a power stage amplifier, and an output matching network. The driver stage amplifier uses a combination of Class A and Class C biases, with the first and fourth transistors being Class C biased and the second and third transistors being Class A biased, exhibiting both gain expansion characteristics and high gain. The power amplifier unit uses Class A bias, exhibiting compressed gain characteristics. Through the cascaded combination of gain expansion and compression, the overall linear range of the power amplifier is improved, overcoming the difficulty of improving linearity using cascading methods in 180-nm CMOS processes. Attached Figure Description

[0012] Figure 1 This is a circuit diagram of the power amplifier in this invention.

[0013] Figure 2 This is a graph showing the gain of the driver stage amplifier and the Class C driver stage amplifier in this invention as a function of frequency.

[0014] Figure 3 This refers to the gain characteristics of the driver stage amplifier, power stage amplifier, and cascaded amplifier in this invention.

[0015] Figure 4 This refers to the output power characteristics of the power amplifier in this invention.

[0016] Figure 5 The output power characteristics of a two-stage Class A cascaded power amplifier.

[0017] The diagram includes: first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, sixth transistor M6, first neutralizing capacitor Cg1, second neutralizing capacitor Cg2, third neutralizing capacitor Cg3, fourth neutralizing capacitor Cg4, first isolation capacitor C1, second isolation capacitor C2, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, first transformer XFMR1, second transformer XFMR2, third transformer XFMR3, first matching capacitor Cp1, second matching capacitor Cp2, first bias voltage Vbias1, second bias voltage Vbias2, third bias voltage Vbias3, fourth bias voltage Vbias4, power supply VDD, input In, and output Out. Detailed Implementation

[0018] The present invention will be further explained below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0019] This embodiment provides a millimeter-wave power amplifier employing the structure of the present invention, such as... Figure 1 As shown, it consists of an input matching network, a driver stage amplifier, an interstage matching network, a power stage amplifier, and an output matching network.

[0020] like Figure 1 As shown, the input matching network consists of a first matching capacitor Cp1, a first transformer XFMR1, and a third resistor R3. One end of the primary coil XFMR1 of the first transformer is connected to the input terminal In of the power amplifier, and the other end is grounded. The first matching capacitor Cp1 is connected in parallel with the primary coil of the first transformer. The two ends of the secondary coil of the first transformer XFMR1 are respectively connected to the gates of the second transistor M2 and the third transistor M3 in the driver stage amplifier. One end of the third resistor R3 is connected to the center tap of the secondary coil of the first transformer XFMR1, and the other end is connected to the first bias voltage Vbias1. The center tap of the secondary coil of the first transformer XFMR1 is connected to the first bias voltage Vbias1 via the third resistor R3.

[0021] The driver stage amplifier consists of a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first neutralizing capacitor Cg1, a second neutralizing capacitor Cg2, a first isolation capacitor C1, a second isolation capacitor C2, a first resistor R1, and a second resistor R2. The two ends of the first neutralizing capacitor Cg1 are connected to the drain of the first transistor M1 and the gate of the third transistor M3, respectively. The two ends of the second neutralizing capacitor Cg2 are connected to the gate of the second transistor M2 and the drain of the fourth transistor M4, respectively. The two ends of the first isolation capacitor C1 are connected to the gate of the first transistor M1 and the gate of the second transistor M2, respectively. The two ends of the second isolation capacitor C2 are connected to the gate of the third transistor M4 and the gate of the fourth transistor M4, respectively. The gates of transistor M3 and M4 are connected; the two ends of the first resistor R1 are connected to the gate of the first transistor M1 and the third bias voltage Vbias3, respectively; the two ends of the second resistor R2 are connected to the gate of the fourth transistor M4 and the fourth bias voltage Vbias4, respectively; the sources of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are grounded; wherein, the third bias voltage Vbias3 causes the first transistor M1 to operate in class C state, the fourth bias voltage Vbias4 causes the fourth transistor M4 to operate in class C state, and the first bias voltage Vbias1 causes the second transistor M2 and the third transistor M3 to operate in class A state;

[0022] The interstage matching network consists of a second transformer XFMR2 and a fourth resistor R4. One end of the primary coil of the second transformer XFMR2 is connected to the drain of the first transistor M1 and the second transistor M2, and the other end is connected to the drain of the third transistor M3 and the fourth transistor M4. One end of the secondary coil of the second transformer XFMR2 is connected to the gate of the fifth transistor M5, and the other end is connected to the gate of the sixth transistor M6. The center tap of the primary coil of the second transformer XFMR2 is connected to the power supply VDD. One end of the fourth resistor is connected to the center tap of the secondary coil of the second transformer XFMR2, and the other end is connected to the second bias voltage Vbias2.

[0023] The power stage amplifier consists of a fifth transistor M5, a sixth transistor M6, a third neutralizing capacitor Cg3, and a fourth neutralizing capacitor Cg4. One end of the third neutralizing capacitor Cg3 is connected to the drain of the fifth transistor M5, and the other end is connected to the gate of the sixth transistor M6. One end of the fourth neutralizing capacitor Cg4 is connected to the gate of the fifth transistor M5, and the other end is connected to the gate of the sixth transistor M6. The sources of the fifth transistor M5 and the sixth transistor M6 are connected to ground. The second bias voltage Vbias2 causes the fifth transistor M5 and the sixth transistor M6 to operate in Class A mode.

[0024] The output matching network consists of a third transformer XFMR3 and a second matching capacitor Cp2. One end of the primary coil of the third transformer XFMR3 is connected to the drain of the fifth transistor M5, and the other end is connected to the drain of the sixth transistor M6. One end of the secondary coil of the third transformer XFMR3 serves as the output terminal of the power amplifier, and the other end is grounded. The second matching capacitor Cp2 is connected in parallel with the secondary coil of the third transformer XFMR3. The center tap of the primary coil of the third transformer XFMR3 is connected to the power supply Vdd.

[0025] In terms of working principle, the high-gain structure of this invention for improving the linearity of millimeter-wave power amplifiers utilizes the gain expansion characteristics of the driver stage amplifier and the gain compression characteristics of the power stage amplifier. The cascading of these two components improves the overall linear range of the power amplifier. Since the gain of 180-nm CMOS technology rapidly decreases in the millimeter-wave band, Class C bias is no longer applicable. The driver stage amplifier of this invention employs multi-gate transistors with both Class C and Class A biases, simultaneously possessing high gain and gain expansion characteristics, thus solving the application challenges of 180-nm CMOS technology in the millimeter-wave band.

[0026] Based on the above working principle, this embodiment designs and simulates the above circuit using 180-nm CMOS technology, verifying the practicality of the present invention.

[0027] Figure 2 The gain curves of the driver amplifier of the present invention and the Class C biased driver amplifier are given as a function of frequency. It can be seen that at 24.5 GHz, the gain of the driver amplifier of the present invention is increased by about 1.6 dB compared with the amplifier under Class C bias.

[0028] Figure 3 The principle of this invention, which utilizes multi-gate transistor driver stage gain expansion cascaded with Class A power stage gain compression to improve linearity, is presented. Figure 4 The output power characteristics of the power amplifier structure of the present invention are given. Figure 5 The output power characteristics of a two-stage Class A cascaded power amplifier are presented. It can be seen that the 1dB compression point of the power amplifier of this invention is 13.31dBm, and the saturation output power is 15.31dBm, a difference of 2dB. (Comparison) Figure 5 The common-source structure shown has a significant improvement, which means that the linearity of the power amplifier of the present invention is improved.

[0029] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A high-gain structure for improving the linearity of millimeter-wave power amplifiers, characterized in that, This includes the input matching network, driver stage amplifier, interstage matching network, power stage amplifier, and output matching network. The input matching network consists of a first matching capacitor (Cp1), a first transformer (XFMR1), and a third resistor (R3). One end of the primary coil of the first transformer (XFMR1) is connected to the input terminal (In) of the power amplifier, and the other end is grounded. The first matching capacitor (Cp1) is connected in parallel with the primary coil of the first transformer. The two ends of the secondary coil of the first transformer (XFMR1) are respectively connected to the gates of the second transistor (M2) and the third transistor (M3) in the driver stage amplifier. One end of the third resistor (R3) is connected to the center tap of the secondary coil of the first transformer (XFMR1), and the other end is connected to the first bias voltage (Vbias1). The driver stage amplifier consists of a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4), a first neutralizing capacitor (Cg1), a second neutralizing capacitor (Cg2), a first isolation capacitor (C1), a second isolation capacitor (C2), a first resistor (R1), and a second resistor (R2). The two ends of the first neutralizing capacitor (Cg1) are connected to the drain of the first transistor (M1) and the gate of the third transistor (M3), respectively. The two ends of the second neutralizing capacitor (Cg2) are connected to the gate of the second transistor (M2) and the drain of the fourth transistor (M4), respectively. The first isolation capacitor (Cg1)... 1) The two ends of the first transistor (M1) are connected to the gate of the second transistor (M2) and the gate of the third transistor (M3) and the gate of the fourth transistor (M4) respectively; the two ends of the first resistor (R1) are connected to the gate of the first transistor (M1) and the third bias voltage (Vbias3) respectively; the two ends of the second resistor (R2) are connected to the gate of the fourth transistor (M4) and the fourth bias voltage (Vbias4) respectively; the sources of the first transistor (M1), the second transistor (M2), the third transistor (M3) and the fourth transistor (M4) are grounded; The interstage matching network consists of a second transformer (XFMR2) and a fourth resistor (R4). One end of the primary coil of the second transformer (XFMR2) is connected to the drain of the first transistor (M1) and the second transistor (M2), and the other end is connected to the drain of the third transistor (M3) and the fourth transistor (M4). One end of the secondary coil of the second transformer (XFMR2) is connected to the gate of the fifth transistor (M5), and the other end is connected to the gate of the sixth transistor (M6). The center tap of the primary coil of the second transformer (XFMR2) is connected to the power supply (VDD). One end of the fourth resistor is connected to the center tap of the secondary coil of the second transformer (XFMR2), and the other end is connected to the second bias voltage (Vbias2). The power stage amplifier consists of a fifth transistor (M5), a sixth transistor (M6), a third neutralizing capacitor (Cg3), and a fourth neutralizing capacitor (Cg4). One end of the third neutralizing capacitor (Cg3) is connected to the drain of the fifth transistor (M5), and the other end is connected to the gate of the sixth transistor (M6). One end of the fourth neutralizing capacitor (Cg4) is connected to the gate of the fifth transistor (M5), and the other end is connected to the gate of the sixth transistor (M6). The sources of the fifth transistor (M5) and the sixth transistor (M6) are connected to ground. The output matching network consists of a third transformer (XFMR3) and a second matching capacitor (Cp2); One end of the primary coil of the third transformer (XFMR3) is connected to the drain of the fifth transistor (M5), and the other end is connected to the drain of the sixth transistor (M6). One end of the secondary coil of the third transformer (XFMR3) serves as the output terminal of the power amplifier, and the other end is grounded. The second matching capacitor (Cp2) is connected in parallel with the secondary coil of the third transformer (XFMR3). The center tap of the primary coil of the third transformer (XFMR3) is connected to the power supply (VDD).

2. The high-gain structure for improving the linearity of millimeter-wave power amplifiers according to claim 1, characterized in that, The driver stage amplifier is composed of a first transistor (M1), a second transistor (M2), a third transistor (M3), and a fourth transistor (M4). A first isolation capacitor (C1) is connected between the gates of the first transistor (M1) and the second transistor (M2), a second isolation capacitor (C2) is connected between the gates of the third transistor (M3) and the fourth transistor (M4), a first neutralizing capacitor (Cg1) is connected between the drain of the first transistor (M1) and the gate of the third transistor (M3), and a second neutralizing capacitor (Cg2) is connected between the gate of the second transistor (M2) and the drain of the fourth transistor (M4).

3. A high-gain structure for improving the linearity of millimeter-wave power amplifiers according to claim 1, characterized in that, The gate of the first transistor (M1) in the driver stage amplifier is connected to one end of the first resistor (R1) and the other end is connected to the third bias voltage (Vbias3). The gate of the fourth transistor (M4) is connected to one end of the second resistor (R2) and the other end is connected to the fourth bias voltage (Vbias4). The selection of the third bias voltage (Vbias3) causes the first transistor to operate in Class C mode under the amplitude of the corresponding input signal, and the selection of the fourth bias voltage (Vbias4) causes the fourth transistor to operate in Class C mode under the amplitude of the corresponding input signal.

4. A high-gain structure for improving the linearity of a millimeter-wave power amplifier according to claim 1, characterized in that, The gates of the second transistor (M2) and the third transistor (M3) in the driver stage amplifier are connected to one end of the third resistor (R3) through the secondary coil of the first transformer (XFMR1), and the other end is connected to the first bias voltage (Vbias1). The selection of the first bias voltage (Vbias1) causes the second transistor (M2) and the third transistor (M3) to operate in Class A mode under the amplitude of the corresponding input signal.

5. A high-gain structure for improving the linearity of a millimeter-wave power amplifier according to claim 1, characterized in that, The gates of the fifth transistor (M5) and the sixth transistor (M6) in the core of the power amplifier unit are connected to one end of the fourth resistor (R4) through the secondary coil of the second transformer (XFMR2), and the other end is connected to the second bias voltage (Vbias2). The selection of the second bias voltage (Vbias2) causes the fifth transistor (M5) and the sixth transistor (M6) to operate in Class A mode under the amplitude of the corresponding input signal.

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