Three-dimensional filter stack structure and method of making the same

Abstract

The application provides a three-dimensional filter stack structure and a preparation method thereof. A first chip structure is attached to a substrate to form a first cavity, and a plurality of first chip structures are combined with a plurality of first back wiring layers to form a chip stack body in sequence from the first back wiring layer of the first chip, and a bottom chip structure is arranged on the first back wiring layer of the chip stack body. The substrate and different chip structures are electrically connected through the conductive columns, and the front wiring layer is arranged after the substrate is thinned to connect the metal bumps, so that the three-dimensional stacking of the chip in the packaging process can be realized, the packaging chip area is greatly reduced, the integration and use of the chip are facilitated, the miniaturization and light weight of the chip are realized, and in addition, the plurality of cavities are arranged in a closed structure, the sound energy density of the device is improved, the sound wave is better limited, and the loss of the device is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology and relates to a three-dimensional filter stack structure and its fabrication method. Background Technology

[0002] Electronic devices include radio frequency (RF) chip modules to enable wireless communication. These RF chip modules include components such as filters, low-noise amplifiers, power amplifiers, and RF switches. For filters, a cavity structure is included to provide vibration space for sound waves. Currently, when using chip-scale packaging (CSP) technology to package filters, the filter wafer is soldered to a substrate using solder balls, and an organic thin film is coated on the surface of the filter wafer to form a cavity structure; then, it is encapsulated with epoxy molding compound (EMC) material.

[0003] With the development of semiconductor technology, the requirements for miniaturization and lightweighting in electronic devices are constantly increasing. For example, taking the radio frequency (RF) module of a 5G mobile phone as an example, this RF module generally uses a quadrupler, which combines four BAW filters and shares the same node to achieve simultaneous reception of two frequency bands. However, the quadrupler requires four filters, resulting in a larger chip package area, which is not conducive to integration and use, and remains an important technical problem that urgently needs to be solved by those in the field.

[0004] Therefore, it is essential to provide a three-dimensional filter stack structure and its fabrication method to solve the problem of large chip packaging area hindering integration and use.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a three-dimensional filter stack structure and its fabrication method, so as to solve the problem of large chip packaging area causing difficulties in integration and use.

[0007] To achieve the above and other related objectives, the present invention provides a three-dimensional filter stack structure, the three-dimensional filter stack structure comprising:

[0008] A first chip structure includes a first chip and a first wiring layer; the first chip has a first surface and a second surface disposed opposite to each other, and the first chip includes a first circuit and a first conductive post located on the first surface of the first chip; the first wiring layer is located on the first surface of the first chip, and the first wiring layer is provided with a first groove, the first groove exposing the first circuit, the first wiring layer being electrically connected to the first circuit and electrically connected to the first conductive post.

[0009] A substrate, the substrate being located on the first wiring layer, the substrate including substrate conductive pillars electrically connected to the first wiring layer, and the substrate covering the first groove to form a first cavity;

[0010] A first back wiring layer is located on the second side of the first chip and is electrically connected to the first conductive pillar.

[0011] A bottom chip structure includes a bottom chip and a bottom wiring layer. The bottom chip structure is located on the second side of the first chip, electrically connected to the first back wiring layer, and forms a bottom cavity. The bottom chip has a first side and a second side disposed opposite to each other, and the bottom chip includes a bottom circuit located on the first side of the bottom chip. The bottom wiring layer is formed on the first side of the bottom chip, and the bottom wiring layer has a bottom groove that exposes the bottom circuit. The bottom wiring layer is electrically connected to the bottom circuit.

[0012] A front wiring layer is located on the substrate and is electrically connected to the conductive pillars of the substrate.

[0013] A metal bump, the metal bump being located on the front wiring layer and electrically connected to the front wiring layer.

[0014] Optionally, the first chip includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip; the bottom chip includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip.

[0015] Optionally, the first back wiring layer and the bottom chip structure further include a chip stack and a corresponding second cavity. The chip stack is formed by stacking n first chip structures corresponding to n first back wiring layers in the same orientation, and n≥1.

[0016] Optionally, the thickness of the first cavity ranges from 1 μm to 20 μm; the thickness of the second cavity ranges from 1 μm to 20 μm; and the thickness of the bottom cavity ranges from 1 μm to 20 μm.

[0017] Optionally, the substrate includes one of a wafer, a silicon oxide substrate, or an organic resin substrate, and the thickness of the substrate is 50 μm to 100 μm.

[0018] Optionally, the centerline of the first vertical cavity coincides with the centerline of the bottom cavity.

[0019] This invention also proposes a method for fabricating a three-dimensional filter stack structure, characterized by comprising the following steps:

[0020] S1: A first chip structure is provided, the first chip structure includes a first chip and a first wiring layer; the first chip has a first surface and a second surface disposed opposite to each other, and the first chip includes a first circuit and a first conductive post located on the first surface of the first chip; the first wiring layer is formed on the first surface of the first chip, and the first wiring layer is provided with a first groove, the first groove exposes the first circuit, the first wiring layer is electrically connected to the first circuit, and is electrically connected to the first conductive post.

[0021] S2: A substrate is bonded to the first wiring layer, and the substrate covers the first groove to form a first cavity;

[0022] S3: Thin the second side of the first chip to expose the first conductive pillar;

[0023] S4: A first back-side wiring layer is formed on the second side of the first chip, and the first back-side wiring layer is electrically connected to the first conductive pillar;

[0024] S5: Provide a bottom chip structure, the bottom chip structure including a bottom chip and a bottom wiring layer; the bottom chip has a first surface and a second surface disposed opposite to each other, and the bottom chip includes a second circuit located on the first surface of the bottom chip; the bottom wiring layer is formed on the first surface of the bottom chip, and the bottom wiring layer has a bottom groove, the bottom groove exposing the bottom circuit, and the bottom wiring layer is electrically connected to the bottom circuit;

[0025] S6: The bottom wiring layer is bonded to the first back wiring layer and electrically connected to the first back wiring layer; the first back wiring layer covers the bottom groove to form a bottom cavity;

[0026] S7: Thin the substrate and form substrate conductive pillars in the substrate, wherein the substrate conductive pillars are electrically connected to the first wiring layer;

[0027] S8: A front wiring layer is formed on the substrate, and the front wiring layer is electrically connected to the conductive pillars of the substrate;

[0028] S9: A metal bump is formed on the front wiring layer, and the metal bump is electrically connected to the front wiring layer.

[0029] Optionally, between step S4 and step S5, a step of forming a chip stack is further included. The chip stack is formed by stacking n first chip structures corresponding to n first back-side wiring layers in the same orientation, and correspondingly forming n second cavities. The step of preparing the chip stack includes repeating step S1, step S3 and step S4 n times.

[0030] Optionally, the thickness of the first cavity, the second cavity, and the bottom cavity ranges from 1 μm to 20 μm.

[0031] Optionally, the first wiring layer includes a damascus wiring layer; the bottom wiring layer includes a damascus wiring layer.

[0032] As described above, this invention provides a three-dimensional filter stack structure and its fabrication method. A first chip structure is bonded to a substrate to form a first cavity. Simultaneously, multiple first chip structures, combined with multiple first back-side wiring layers, are sequentially stacked from the first back-side wiring layers of the first chip to form a chip stack. A bottom chip structure is then disposed on the first back-side wiring layer of the chip stack. Electrical connections are achieved between the substrate and different chip structures through conductive pillars. By thinning the substrate and arranging front-side wiring layers with connecting metal bumps, three-dimensional stacking of the chips during the packaging process can be realized, significantly reducing the packaged chip area. This is beneficial for chip integration and use, achieving chip miniaturization and weight reduction. Furthermore, by setting multiple cavities as closed structures, the acoustic energy density of the device is improved, sound waves are better confined, and device losses are reduced. Attached Figure Description

[0033] Figure 1 The diagram shows a cross-sectional view of the three-dimensional filter stack structure in Embodiment 1 and Embodiment 2 of the present invention.

[0034] Figure 2 The diagram shows a flowchart illustrating the fabrication method of the three-dimensional filter stack structure in Embodiment 1 of the present invention.

[0035] Figure 3 The diagram shown is a structural schematic of the first chip provided in Embodiment 1 of the present invention.

[0036] Figure 4 The diagram shown is a schematic diagram of the structure forming the first chip structure in Embodiment 1 of the present invention.

[0037] Figure 5 The image shown is a top view of the first chip structure according to an embodiment of the present invention.

[0038] Figure 6The diagram shown is a schematic representation of the structure of the substrate after bonding in Embodiment 1 of the present invention.

[0039] Figure 7 The diagram shown is a schematic diagram of the structure of the second side of the first chip after thinning in Embodiment 1 of the present invention.

[0040] Figure 8 The diagram shown is a schematic diagram of the structure after the first back-side wiring layer is formed in Embodiment 1 of the present invention.

[0041] Figure 9 The diagram shown is a schematic diagram of the structure after the bottom chip structure is provided in Embodiment 1 of the present invention.

[0042] Figure 10 The diagram shown is a schematic diagram of the structure after the bottom chip structure is bonded in Embodiment 1 of the present invention.

[0043] Figure 11 The diagram shows the structure after the substrate is thinned and conductive pillars are formed in Embodiment 1 of the present invention.

[0044] Figure 12 The diagram shows the structure after the front wiring layer is formed in Embodiment 1 of the present invention.

[0045] Figure 13 The diagram shown is a schematic representation of the structure after the metal bumps are formed in Embodiment 1 of the present invention.

[0046] Figures 14-20 The diagram shown is a structural schematic of the process of forming a chip stack with n=2 in Embodiment 3 of the present invention.

[0047] Figure 21 The diagram shown is a structural schematic of the bottom chip structure provided in Embodiment 3 of the present invention.

[0048] Figure 22 The diagram shown is a schematic diagram of the structure after the bottom chip structure is bonded in Embodiment 3 of the present invention.

[0049] Figure 23 The diagram shown is a schematic diagram of the structure for forming conductive pillars on a substrate in Embodiment 3 of the present invention.

[0050] Figure 24 The diagram shown is a schematic representation of the structure after the front wiring layer is formed in Embodiment 3 of the present invention.

[0051] Figure 25 The diagram shows the final cross-sectional schematic of the three-dimensional filter stack structure in Embodiments 3 and 4 of the present invention.

[0052] Explanation of reference numerals in the attached figures

[0053] 101 First Chip Structure

[0054] 100 First Chip

[0055] 110 First conductive post

[0056] 120 First Circuit

[0057] 130 First Groove

[0058] 131 First cavity

[0059] 140 First wiring layer

[0060] 141 First Metal Layer

[0061] 142 First Dielectric Layer

[0062] 150 First Backside Wiring Layer

[0063] 151 First back metal layer

[0064] 160 substrate

[0065] 161 Substrate conductive pillars

[0066] 170 Front Wiring Layer

[0067] 171 Front metal layer

[0068] 180 metal bumps

[0069] 231 Second cavity

[0070] 300-chip stack

[0071] 401 Bottom Chip Structure

[0072] 400 bottom chip

[0073] 420 Bottom Circuit

[0074] 430 Bottom Groove

[0075] 431 Bottom cavity

[0076] 440 Bottom Wiring Layer

[0077] 441 Bottom Metal Layer

[0078] 442 Bottom Dielectric Layer Detailed Implementation

[0079] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0080] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0081] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for the device in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between. The phrase “between” as used herein includes both endpoint values.

[0082] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0083] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0084] Example 1

[0085] See Figure 1 This is the three-dimensional filter stack structure prepared in this embodiment, wherein... Figures 2 to 13 The diagram illustrates the structural features of each step in fabricating the three-dimensional filter stack structure in this embodiment. The fabrication method of the three-dimensional filter stack structure is described below with reference to the accompanying drawings.

[0086] First, refer to Figures 2-4In step S1, a first chip structure 101 is provided, which includes a first chip 100 and a first wiring layer 140. The first chip 100 has a first surface and a second surface disposed opposite to each other, and the first chip 100 includes a first circuit 120 and a first conductive post 110 located on the first surface of the first chip 100. The first wiring layer 140 is formed on the first surface of the first chip 100, and the first wiring layer 140 is provided with a first groove 130, which exposes the first circuit 120. The first wiring layer 140 is electrically connected to the first circuit 120 and to the first conductive post 110.

[0087] Specifically, the first circuit 120 is exposed on the first side of the first chip 100, and the first circuit 120 is a filter circuit composed of capacitors, inductors and resistors. The filter circuit can effectively filter out a specific frequency point or a frequency other than that frequency point in the power line to obtain a power signal of a specific frequency or eliminate a power signal of a specific frequency.

[0088] Furthermore, the first chip 100 includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip. In this embodiment, the first chip 100 is a bulk acoustic wave filter chip. The bulk acoustic wave filter performs better at high frequencies, such as in the 5 GHz or even higher frequency bands, and is especially widely used in the high-frequency range of 4 GHz and 5 GHz.

[0089] As an example, the first chip 100 can function as either a transmitter or a receiver. In this embodiment, the first chip 100 functions as a receiver to receive signals and reduce or eliminate interference from other signals or devices, ensuring the quality of the received signal. In some other embodiments, the first chip 100 can also function as a transmitter of a filter chip, which will not be detailed here.

[0090] As an example, see Figure 3 The first conductive post 110 is formed by forming a deep hole on the first surface of the first chip 100 and forming the first conductive post 110 that fills the deep hole.

[0091] Specifically, the first conductive post 110 is formed using TSV technology. In this embodiment, the grooving method for the deep hole is not limited to one of mechanical grooving, laser etching, or plasma etching, and can be selected as needed.

[0092] Furthermore, the first conductive post 110 extends inward from the first surface of the first chip 100; the first conductive post 110 is filled with conductive material, such as copper, tungsten, etc., in the deep hole to form a connection channel for vertical electrical connection.

[0093] As an example, see Figure 4 To reduce interconnect resistance, improve device reliability, and achieve a high-density interconnect structure, the first wiring layer 140 is a damascus wiring layer fabricated using a damascus process. The first wiring layer 140 includes a first metal layer 141 and a first dielectric layer 142. To reduce parasitic capacitance between interconnects, the first dielectric layer 142 is typically made of materials with low dielectric constants, such as silicon oxide, silicon fluoride, or silicon dioxide. In this embodiment, the material of the first dielectric layer 142 in the damascus process is silicon oxide. Furthermore, because copper has low resistivity, it can achieve a smaller linewidth at the same current density, increasing interconnect density; therefore, copper is used as the material of the first metal layer 141.

[0094] Furthermore, the first metal layer 141 is formed by depositing a copper seed layer or by electroplating, and is electrically connected to the first conductive pillar 110.

[0095] As an example, the grooving method of the first groove 130 is not limited to one of mechanical grooving, laser etching, plasma etching, or chemical etching; it can be selected according to specific needs. As an example, the first wiring layer 140 is annular, and the first groove 130 is located at the center of the first wiring layer 140.

[0096] Next, refer to Figure 2 and Figure 6 In step S2, a substrate 160 is bonded to the first wiring layer 140, and the substrate 160 covers the first groove 130 to form a first cavity 131.

[0097] Specifically, the substrate 160 includes one of a wafer, a silicon oxide substrate, or an organic resin substrate. In this embodiment, the substrate 160 is a wafer.

[0098] Furthermore, the substrate 160 can be bonded to the first wiring layer 140 using an epoxy resin bonding chip bonding process, or it can be bonded to the first wiring layer 140 using a wafer-on-a-film (DAF) bonding process. In this embodiment, a small amount of epoxy resin is placed on the first wiring layer 140, and the substrate 160 and the first wiring layer 140 are bonded together. The epoxy resin is cured at a temperature of 150°C to 250°C by reflow or curing, thereby achieving bonding between the first chip 100 and the substrate 160.

[0099] Furthermore, see Figure 5To improve sound energy density, better confine sound waves, and reduce losses, the first wiring layer 140 in this embodiment adopts a ring structure to make the first cavity 131 a closed cavity. To ensure the structural stability of the filter structure and avoid affecting the reflection of sound waves and the formation of standing waves, the height of the first cavity 131 is in the range of 1μm to 20μm, such as any value within this range, such as 1μm, 3μm, 5μm, 8μm, 10μm, 15μm, 20μm, etc., which effectively improves the stability of the device and reduces the loss of the device.

[0100] Next, refer to Figure 2 and Figure 7 Step S3 is executed to thin the second side of the first chip 100 to expose the first conductive pillar 110.

[0101] Specifically, in order to make the subsequent chip structure electrically connected to the first chip 100, the second side of the first chip 100 is thinned to expose the first conductive pillar 110; the thinning process includes CMP, plasma dry chemical etching, mechanical masking and other processes to ensure the flatness, quality and performance of the chip surface.

[0102] Next, refer to Figure 2 and Figure 8 Step S4 is executed, forming a first back-side wiring layer 150 on the second side of the first chip 100, and the first back-side wiring layer 150 is electrically connected to the first conductive post 110.

[0103] Specifically, the first back-side wiring layer 150 is a damascus wiring layer fabricated using the damascus process. The first back-side wiring layer 150 includes a first back-side metal layer 151 and a first back-side dielectric layer (not labeled). To reduce parasitic capacitance between interconnects, the materials used for the first back-side dielectric layer typically include low dielectric constants such as silicon oxide, silicon fluoride, or silicon dioxide. In this embodiment, the material of the first back-side dielectric layer in the damascus process is silicon oxide. In addition, since copper has a low resistivity, it can achieve a smaller linewidth at the same current density, thereby increasing the interconnect density. Therefore, copper is used as the material of the first back-side metal layer 151.

[0104] Next, refer to Figure 2 and Figure 9In step S5, a bottom chip structure 401 is provided, which includes a bottom chip 400 and a bottom wiring layer 440. The bottom chip 400 has a first surface and a second surface disposed opposite to each other, and the bottom chip 400 includes a bottom circuit 420 located on the first surface of the bottom chip 400. The bottom wiring layer 440 is formed on the first surface of the bottom chip 400, and the bottom wiring layer 440 is provided with a bottom recess 430, which exposes the bottom circuit 420. The bottom wiring layer 440 is electrically connected to the bottom circuit 420.

[0105] Specifically, the bottom circuit 420 is exposed on the surface of the bottom chip 400, and the bottom circuit 420 is a filter circuit composed of capacitors, inductors and resistors. The filter circuit can effectively filter out a specific frequency point or a frequency other than that frequency point in the power line to obtain a power signal of a specific frequency or eliminate a power signal of a specific frequency.

[0106] Furthermore, similar to the first chip 100, the bottom chip 400 includes one of a bulk acoustic wave (BAW) filter chip and a surface acoustic wave (SAW) filter chip. In this embodiment, the bottom chip 400 is a BAW filter chip. The BAW filter performs better at high frequencies, such as in the 5 GHz and even higher frequency bands, especially in the 4 GHz and 5 GHz high-frequency range.

[0107] As an example, the bottom chip 400 can function as either a transmitter or a receiver. In this embodiment, the first chip 100 serves as a transmitter, ensuring that the transmitted signal meets specific frequency characteristics, reducing unnecessary frequency components to avoid interfering with other communication signals, and improving signal transmission efficiency and quality. In some other embodiments, the bottom chip 400 can also function as a receiver, which will not be detailed here.

[0108] As an example, the bottom wiring layer 440 is a masquerade wiring layer fabricated using the damascus process. The bottom wiring layer 440 also includes a bottom dielectric layer 442 and a bottom metal layer 441. To reduce parasitic capacitance between interconnects, the bottom dielectric layer 442 is typically made of a low dielectric constant material such as silicon oxide, silicon fluoride, or silicon dioxide. In this embodiment, the bottom dielectric layer 442 fabricated using the damascus process is made of silicon oxide. Furthermore, because copper has low resistivity, it can achieve a smaller linewidth at the same current density, increasing interconnect density; therefore, copper is used as the material for the bottom metal layer 441.

[0109] Furthermore, the bottom metal layer 441 is formed by depositing a copper seed layer or by electroplating.

[0110] As an example, the grooving method of the bottom groove 430 is not limited to one of mechanical grooving, laser etching, plasma etching, or chemical etching; the specific method can be selected as needed.

[0111] Specifically, in this embodiment, similar to the first wiring layer 140, the bottom groove 430 is located at the center of the first wiring layer 140 and exposes the bottom circuit 420.

[0112] Next, refer to Figure 2 and Figure 10 In step S6, the bottom wiring layer 440 is bonded to the first back wiring layer 150 and electrically connected to the first back wiring layer 150; the first back wiring layer 150 covers the bottom groove 430 to form a bottom cavity 431.

[0113] As an example, the process of bonding the bottom wiring layer 440 to the first back wiring layer 150 includes using epoxy resin for adhesive bonding and using wafer-on-a-film (DAF) for chip bonding. Of course, other bonding methods can also be used, and there are no limitations here.

[0114] Furthermore, in order to improve the sound energy density, better confine sound waves, and reduce losses, the bottom wiring layer 440 in this embodiment adopts a ring structure to make the bottom cavity 431 a closed cavity. In order to ensure the structural stability of the filter structure and avoid affecting the reflection of sound waves or the formation of standing waves, the height range of the bottom cavity 431 is 1μm to 20μm, such as any value within this range, such as 1μm, 3μm, 5μm, 8μm, 10μm, 15μm, 20μm, etc., which effectively improves the stability of the device and reduces the loss of the device.

[0115] Furthermore, in order to increase the effective sensor area of ​​the filter, improve the performance of the filter, and reduce the transmission path, the center line of the first vertical cavity 131 coincides with the center line of the bottom cavity 431.

[0116] Next, refer to Figure 2 and Figure 11 Step S7 is executed to thin the substrate 160 and form substrate conductive pillars 161 in the substrate 160. The substrate conductive pillars 161 are electrically connected to the first wiring layer 140.

[0117] Specifically, in order to reduce the height of the three-dimensional stack structure, shrink the package size, and enable electrical connection of the substrate 160, the substrate 160 is thinned; the thinning method can be such as chemical mechanical polishing (CMP) or etching, which will not be elaborated on here.

[0118] Furthermore, the substrate conductive pillar 161 is formed by TSV technology. In this embodiment, the grooving method of the deep hole is not limited to one of mechanical grooving, laser etching, and plasma etching, and can be selected according to the specific needs.

[0119] Next, refer to Figure 2 and Figure 12 Step S8 is executed, in which a front wiring layer 170 is formed on the substrate 160, and the front wiring layer 170 is electrically connected to the conductive pillars 161 of the substrate.

[0120] As an example, the front wiring layer 170 is formed using a damascus process. The front wiring layer 170 shown includes a front metal layer 171 and a front dielectric layer (not identified). To maintain the miniaturization of the package structure size, the thickness of the front wiring layer 170 ranges from 10μm to 30μm, for example, any value within this range such as 10μm, 15μm, 20μm, 25μm, 30μm, etc.

[0121] The front dielectric layer may be one or a combination of silicon oxide, silicon nitride, fluorinated glass, PI, PBO, and BCB layers. The front metal layer 171 may be one or a combination of copper, aluminum, nickel, gold, and silver layers. The material, number of wiring layers, and wiring distribution of the front wiring layer 170 are not limited here and can be selected as needed.

[0122] Next, refer to Figure 2 and Figure 13 In step S9, a metal bump 180 is formed on the front wiring layer 170, and the metal bump 180 is electrically connected to the front wiring layer 170.

[0123] The metal bumps may include, for example, solder ball bumps, C4 metal bumps, column bumps, etc. The material of the metal bumps may be one of copper, aluminum, nickel, gold, silver or titanium. The specific type of the metal bumps 180 is not excessively limited here.

[0124] Example 2

[0125] This embodiment provides a three-dimensional filter stack structure. The three-dimensional filter stack structure is obtained using the fabrication method described in Embodiment 1 or other suitable similar methods. Please refer to [link to previous document]. Figure 1 The diagram shows a schematic of the three-dimensional filter stack structure, which includes a first chip structure 101, a substrate 160, a first back wiring layer 150, a bottom chip structure 401, a front wiring layer 170, and metal bumps 180.

[0126] The first chip structure 101 includes a first chip 100 and a first wiring layer 140; the first chip 100 has a first surface and a second surface disposed opposite to each other, and the first chip 100 includes a first circuit 120 and a first conductive post 110 located on the first surface of the first chip 100; the first wiring layer 140 is located on the first surface of the first chip 100, and the first wiring layer 140 is provided with a first groove 130, the first groove 130 exposes the first circuit 120, the first wiring layer 140 is electrically connected to the first circuit 120, and is electrically connected to the first conductive post 110.

[0127] The substrate 160 is located on the first wiring layer 140. The substrate 160 includes substrate conductive pillars 161 that are electrically connected to the first wiring layer 140, and the substrate 160 covers the first groove 130 to form a first cavity 131.

[0128] The first back wiring layer 150 is located on the second side of the first chip 100, and the first back wiring layer 150 is electrically connected to the first conductive post 110.

[0129] The bottom chip structure 401 includes a bottom chip 400 and a bottom wiring layer 440. The bottom chip structure 401 is located on the second side of the first chip 100, electrically connected to the first back wiring layer 150, and forms a bottom cavity 431. The bottom chip 400 has a first side and a second side disposed opposite to each other, and the bottom chip 400 includes a bottom circuit 420 located on the first side of the bottom chip 400. The bottom wiring layer 440 is formed on the first side of the bottom chip 400, and the bottom wiring layer 440 is provided with a bottom groove 430, the bottom groove 430 exposes the bottom circuit 420, and the bottom wiring layer 440 is electrically connected to the bottom circuit 420.

[0130] The front wiring layer 170 is located on the substrate 160, and the front wiring layer 170 is electrically connected to the conductive pillar 161 of the substrate.

[0131] The metal bump 180 is located on the front wiring layer 170 and is electrically connected to the front wiring layer 170.

[0132] As an example, the substrate 160 includes one of a wafer, a silicon oxide substrate 160, or an organic resin substrate 160, and the thickness of the substrate 160 is 50 μm to 100 μm.

[0133] As an example, the first chip 100 includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip; the bottom chip 400 includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip.

[0134] As an example, the thickness of the first cavity 131 ranges from 1 μm to 20 μm; the thickness of the bottom cavity 431 ranges from 1 μm to 20 μm.

[0135] As an example, in order to increase the effective sensor area of ​​the filter, improve the performance of the filter, and reduce the transmission path, the center line of the first cavity 131 along the vertical direction coincides with the center line of the bottom cavity 431.

[0136] As an example, the first wiring layer 140 includes a damascus wiring layer; the bottom wiring layer 440 includes a damascus wiring layer.

[0137] As an example, the front wiring layer 170 is formed using a damascus process. The front wiring layer 170 includes a front metal layer 171 and a front dielectric layer (not labeled). To maintain a miniaturized package structure, the thickness of the front wiring layer 170 ranges from 10μm to 30μm, for example, any value within this range such as 10μm, 15μm, 20μm, 25μm, or 30μm. The front dielectric layer can be one or a combination of materials such as silicon oxide, silicon nitride, fluorinated glass, PI, PBO, and BCB. The front metal layer 171 can include one or a combination of materials such as copper, aluminum, nickel, gold, and silver. The material, number of wiring layers, and wiring distribution of the front wiring layer 170 are not limited here and can be selected as needed. The materials of the first wiring layer 140, the bottom wiring layer 440, and the substrate 160 have been described in Embodiment 1 and will not be repeated here. The first chip structure 101 and the bottom chip structure 401 have been described in Embodiment 1, and will not be repeated here.

[0138] Example 3

[0139] The fabrication method of the three-dimensional filter stack structure prepared in this embodiment is based on the reference. Figure 2 The process is further expanded, including Figures 1 to 8 as well as Figures 14-25 The diagram illustrates the structural features of each step in fabricating the three-dimensional filter stack structure in this embodiment. The fabrication method of the three-dimensional filter stack structure is described below with reference to the accompanying drawings.

[0140] First, refer to Figure 2 and Figure 3In step S1, a first chip structure 101 is provided. The first chip structure 101 includes a first chip 100 and a first wiring layer 140 located on the first chip 100. The first chip 100 has a first surface and a second surface disposed opposite to each other, and the first chip 100 includes a first circuit 120 and a first conductive post 110 located on the first surface of the first chip 100. The first wiring layer 140 is formed on the first surface of the first chip 100, and the first wiring layer 140 is provided with a first groove 130 and a first metal layer 141. The first groove 130 exposes the first circuit 120, and the first metal layer 141 is electrically connected to the first conductive post 110.

[0141] Specifically, the first circuit 120 is exposed on the first side of the first chip 100, and the first circuit 120 is a filter circuit composed of capacitors, inductors and resistors. The filter circuit can effectively filter out a specific frequency point or a frequency other than that frequency point in the power line to obtain a power signal of a specific frequency or eliminate a power signal of a specific frequency.

[0142] Furthermore, the first chip 100 includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip. In this embodiment, the first chip 100 is a bulk acoustic wave filter chip. The bulk acoustic wave filter performs better at high frequencies, such as in the 5 GHz or even higher frequency bands, and is especially widely used in the high-frequency range of 4 GHz and 5 GHz.

[0143] As an example, the first chip 100 can function as either a transmitter or a receiver. In this embodiment, the first chip 100 functions as a receiver to receive signals and reduce or eliminate interference from other signals or devices, ensuring the quality of the received signal. In some other embodiments, the first chip 100 can also function as a transmitter of a filter chip, which will not be detailed here.

[0144] As an example, see Figure 3 The first conductive post 110 is formed by forming a deep hole on the first surface of the first chip 100 and forming the first conductive post 110 that fills the deep hole.

[0145] Specifically, the first conductive post 110 is formed using TSV technology. In this embodiment, the grooving method for the deep hole is not limited to one of mechanical grooving, laser etching, or plasma etching, and can be selected as needed.

[0146] Furthermore, the first conductive post 110 extends inward from the first surface of the first chip 100; the first conductive post 110 is filled with conductive material, such as copper, tungsten, etc., in the deep hole to form a connection channel for vertical electrical connection.

[0147] As an example, see Figure 4 To reduce interconnect resistance, improve device reliability, and achieve a high-density interconnect structure, the first wiring layer 140 is a damascus wiring layer fabricated using a damascus process. The first wiring layer 140 includes a first metal layer 141 and a first dielectric layer 142. To reduce parasitic capacitance between interconnects, the first dielectric layer 142 is typically made of materials with low dielectric constants, such as silicon oxide, silicon fluoride, or silicon dioxide. In this embodiment, the material of the first dielectric layer 142 in the damascus process is silicon oxide. Furthermore, because copper has low resistivity, it can achieve a smaller linewidth at the same current density, increasing interconnect density; therefore, copper is used as the material of the first metal layer 141.

[0148] Furthermore, the first metal layer 141 is formed by depositing a copper seed layer or by electroplating, and is electrically connected to the first conductive pillar 110.

[0149] As an example, the grooving method of the first groove 130 is not limited to one of mechanical grooving, laser etching, plasma etching, or chemical etching; the specific method can be selected as needed. See also [reference needed]. Figure 15 The first wiring layer 140 is annular, and the first groove 130 is located at the center of the first wiring layer 140.

[0150] Next, refer to Figure 2 and Figure 6 In step S2, a substrate 160 is bonded to the first wiring layer 140, and the substrate 160 covers the groove to form a first cavity 131.

[0151] Specifically, the substrate 160 includes one of a wafer, a silicon oxide substrate, or an organic resin substrate. In this embodiment, the substrate 160 is a wafer.

[0152] Furthermore, the substrate 160 can be bonded to the first wiring layer 140 using an epoxy resin bonding chip bonding process, or it can be bonded to the first wiring layer 140 using a wafer-on-a-film (DAF) bonding process. In this embodiment, a small amount of epoxy resin is placed on the first wiring layer 140, and the substrate 160 and the first wiring layer 140 are bonded together. The epoxy resin is cured at a temperature of 150°C to 250°C by reflow or curing, thereby achieving bonding between the first chip 100 and the substrate 160.

[0153] Furthermore, see Figure 5To improve sound energy density, better confine sound waves, and reduce losses, the first wiring layer 140 in this embodiment adopts a ring structure to make the first cavity 131 a closed cavity. To ensure the structural stability of the filter structure and avoid affecting the reflection of sound waves and the formation of standing waves, the height of the first cavity 131 is in the range of 1μm to 20μm, such as any value within this range, such as 1μm, 3μm, 5μm, 8μm, 10μm, 15μm, 20μm, etc., which effectively improves the stability of the device and reduces the loss of the device.

[0154] Next, refer to Figure 2 and Figure 7 Step S3 is executed to thin the second side of the first chip 100 to expose the first conductive pillar 110.

[0155] Specifically, in order to make the subsequent chip structure electrically connected to the first chip 100, the second side of the first chip 100 is thinned to expose the first conductive pillar 110; the thinning process includes CMP, plasma dry chemical etching, mechanical masking and other processes to ensure the flatness, quality and performance of the chip surface.

[0156] Next, refer to Figure 2 and Figure 8 Step S4 is executed, forming a first back-side wiring layer 150 on the second side of the first chip 100, and the first back-side wiring layer 150 is electrically connected to the first conductive post 110.

[0157] Specifically, the first back-side wiring layer 150 is a damascus wiring layer fabricated using the damascus process. The first back-side wiring layer 150 includes a first back-side metal layer 151 and a first back-side dielectric layer (not labeled). To reduce parasitic capacitance between interconnects, the materials used for the first back-side dielectric layer typically include low dielectric constants such as silicon oxide, silicon fluoride, or silicon dioxide. In this embodiment, the material of the first back-side dielectric layer in the damascus process is silicon oxide. In addition, since copper has a low resistivity, it can achieve a smaller linewidth at the same current density, thereby increasing the interconnect density. Therefore, copper is used as the material of the first back-side metal layer 151.

[0158] Next, refer to Figure 14 The system provides n ≥ 1 first chip structures 101, each of which includes either a bulk acoustic wave filter chip or a surface acoustic wave filter chip. The n first chip structures 101 can be of the same type or of different types.

[0159] In this embodiment, n is 2 as an example, but the value of n is not limited to this. Specifically, when n is 2, the first step S1 is executed first, see [link to documentation]. Figure 14 The first chip structure 101 is provided, which includes a first chip 100 and a first wiring layer 140 located on the first chip 100. The first chip 100 has a first surface and a second surface disposed opposite to each other, and the first chip 100 includes a first circuit 120 and a first conductive post 110 located on the first surface of the first chip 100. The first wiring layer 140 is formed on the first surface of the first chip 100, and the first wiring layer 140 is provided with a first groove 130 and a first metal layer 141. The first groove 130 exposes the first circuit 120, and the first metal layer 141 is electrically connected to the first conductive post 110.

[0160] See Figure 15 The first wiring layer 140 in the first chip structure 101 is bonded to the already formed first back wiring layer 150 to form a second cavity 231.

[0161] See Figure 16 Step S3 is executed for the first time to thin the second side of the exposed first chip 100 to expose the first conductive pillar 110.

[0162] See Figure 17 Step S4 is executed for the first time, forming a first back-side wiring layer 150 on the second side of the exposed first chip 100. The first back-side wiring layer 150 is electrically connected to the first conductive post 110. Thus, the n=1 step is completed.

[0163] In this embodiment, n=2, so steps S1, the bonding of the first chip structure 101, S3, and S4 need to be repeated again. (See attached document.) Figure 18 , Figure 19 and Figure 20 Thus, the steps for n=2 are now complete.

[0164] When n is greater than 2, the above steps S1, the bonding step of the first chip structure 101, S3, and S4 are repeated n times until n chip stacks 300, each corresponding to one of the first chip structures 101 and one of the first back-side wiring layers 150, are formed in the same orientation, simultaneously forming n second cavities 231. The height of the second cavity 231 can be in the range of 1μm to 20μm, such as any value within this range, such as 1μm, 3μm, 5μm, 8μm, 10μm, 15μm, 20μm, etc., which effectively improves the stability of the device and reduces the device loss.

[0165] Next, refer to Figure 2 and Figure 21 In step S5, a bottom chip structure 401 is provided, which includes a bottom chip 400 and a bottom wiring layer 440. The bottom chip 400 has a first surface and a second surface disposed opposite to each other, and the bottom chip 400 includes a bottom circuit 420 located on the first surface of the bottom chip 400. The bottom wiring layer 440 is formed on the first surface of the bottom chip 400, and the bottom wiring layer 440 is provided with a bottom groove 430 and a bottom metal layer 441. The bottom groove 430 exposes the bottom circuit 420, and the bottom wiring layer 440 is electrically connected to the bottom circuit 420.

[0166] Specifically, the bottom circuit 420 is exposed on the surface of the bottom chip 400, and the bottom circuit 420 is a filter circuit composed of capacitors, inductors and resistors. The filter circuit can effectively filter out a specific frequency point or a frequency other than that frequency point in the power line to obtain a power signal of a specific frequency or eliminate a power signal of a specific frequency.

[0167] Furthermore, similar to the first chip 100, the bottom chip 400 includes one of a bulk acoustic wave (BAW) filter chip and a surface acoustic wave (SAW) filter chip. In this embodiment, the bottom chip 400 is a BAW filter chip. The BAW filter performs better at high frequencies, such as in the 5 GHz and even higher frequency bands, especially in the 4 GHz and 5 GHz high-frequency range.

[0168] As an example, the bottom chip 400 can function as either a transmitter or a receiver. In this embodiment, the first chip 100 serves as a transmitter, ensuring that the transmitted signal meets specific frequency characteristics, reducing unnecessary frequency components to avoid interfering with other communication signals, and improving signal transmission efficiency and quality. In some other embodiments, the bottom chip 400 can also function as a receiver, which will not be detailed here.

[0169] As an example, the bottom wiring layer 440 is a masquerade wiring layer fabricated using the damascus process. The bottom wiring layer 440 also includes a bottom dielectric layer 442. To reduce parasitic capacitance between interconnects, the bottom dielectric layer 442 is typically made of a low dielectric constant material such as silicon oxide, silicon fluoride, or silicon dioxide. In this embodiment, the bottom dielectric layer 442 fabricated using the damascus process is made of silicon oxide. Furthermore, because copper has low resistivity, it can achieve a smaller linewidth at the same current density, increasing interconnect density; therefore, copper is used as the material for the bottom metal layer 441.

[0170] Furthermore, the bottom metal layer 441 is formed by depositing a copper seed layer or by electroplating.

[0171] As an example, the grooving method of the bottom groove 430 is not limited to one of mechanical grooving, laser etching, plasma etching, or chemical etching; the specific method can be selected as needed.

[0172] Specifically, in this embodiment, similar to the first wiring layer 140, the bottom groove 430 is located at the center of the first wiring layer 140 and exposes the bottom circuit 420.

[0173] Next, refer to Figure 2 and Figure 22 In step S6, the bottom wiring layer 440 is bonded to the first back wiring layer 150 of the chip stack 300 and electrically connected; the chip stack 300 covers the bottom groove 430 to form a bottom cavity 431.

[0174] As an example, the process of bonding the bottom wiring layer 440 to the substrate 160 includes an adhesive bonding process using epoxy resin and a chip bonding process using a wafer bonding film (DAF). In this embodiment, a small amount of epoxy resin is placed on the bottom wiring layer 440, and the substrate 160 and the bottom wiring layer 440 are bonded together. The epoxy resin is cured at a temperature of 150°C to 250°C by reflow or curing, thereby achieving the bonding between the bottom chip 400 and the substrate 160. Of course, other bonding methods can also be used for bonding, and there are no limitations here.

[0175] Furthermore, in order to improve the sound energy density, better confine sound waves, and reduce losses, the bottom wiring layer 440 in this embodiment adopts a ring structure to make the bottom cavity 431 a closed cavity. In order to ensure the structural stability of the filter structure and avoid affecting the reflection of sound waves or the formation of standing waves, the height range of the bottom cavity 431 is 1μm to 20μm, such as any value within this range, such as 1μm, 3μm, 5μm, 8μm, 10μm, 15μm, 20μm, etc., which effectively improves the stability of the device and reduces the loss of the device.

[0176] Furthermore, in order to increase the effective sensor area of ​​the filter, improve the filter performance, and reduce the transmission path, the center line of the first cavity 131 in the vertical direction coincides with the center line of the second cavity 231 and the bottom cavity 431.

[0177] Next, refer to Figure 2 and Figure 23Step S7 is executed to thin the substrate 160 and form substrate conductive pillars 161 in the substrate 160. The substrate conductive pillars 161 are electrically connected to the first wiring layer 140.

[0178] Specifically, in order to reduce the height of the three-dimensional stack structure, shrink the package size, and enable electrical connection of the substrate 160, the substrate 160 is thinned; the thinning method can be such as chemical mechanical polishing (CMP) or etching, which will not be elaborated on here.

[0179] Furthermore, the substrate conductive pillar 161 is formed by TSV technology. In this embodiment, the grooving method of the deep hole is not limited to one of mechanical grooving, laser etching, and plasma etching, and can be selected according to the specific needs.

[0180] Next, refer to Figure 2 and Figure 24 Step S8 is executed, in which a front wiring layer 170 is formed on the substrate 160, and the front wiring layer 170 is electrically connected to the conductive pillars 161 of the substrate.

[0181] As an example, the front wiring layer 170 is formed using a damascus process. The front wiring layer 170 shown includes a front metal layer 171 and a front dielectric layer (not identified). To maintain the miniaturization of the package structure size, the thickness of the front wiring layer 170 ranges from 10μm to 30μm, for example, any value within this range such as 10μm, 15μm, 20μm, 25μm, 30μm, etc.

[0182] The front dielectric layer may be one or a combination of silicon oxide, silicon nitride, fluorinated glass, PI, PBO, and BCB layers. The front metal layer 171 may be one or a combination of copper, aluminum, nickel, gold, and silver layers. The material, number of wiring layers, and wiring distribution of the front wiring layer 170 are not limited here and can be selected as needed.

[0183] Next, refer to Figure 2 and Figure 25 In step S9, a metal bump 180 is formed on the front wiring layer 170, and the metal bump 180 is electrically connected to the front wiring layer 170.

[0184] The metal bump 180 may include, for example, solder ball bumps, C4 metal bumps, column bumps, etc. The material of the metal bump 180 may be one of copper, aluminum, nickel, gold, silver or titanium. The specific type of metal bump is not excessively limited here.

[0185] In this embodiment, the selected value of n is 2. Of course, in some other embodiments, n can take the value of 1, 3, 4, 5, etc., depending on the actual situation, to realize the stack structure of the three-dimensional filter, thereby obtaining a smaller package structure, which is beneficial to chip integration and use, and realizes chip miniaturization and weight reduction.

[0186] Example 4

[0187] This embodiment provides a three-dimensional filter stack structure. The three-dimensional filter stack structure is obtained using the fabrication method described in Embodiment 3 or other suitable similar methods. Please refer to [link to previous document]. Figure 25 The diagram shows a schematic of the three-dimensional filter stack structure, which includes: a first chip structure 101, a substrate 160, a first back wiring layer 150, a chip stack 300, a bottom chip structure 401, a front wiring layer 170, and metal bumps 180.

[0188] The first chip structure 101 includes a first chip 100 and a first wiring layer 140; the first chip 100 has a first surface and a second surface disposed opposite to each other, and the first chip 100 includes a first circuit 120 and a first conductive post 110 located on the first surface of the first chip 100; the first wiring layer 140 is located on the first surface of the first chip 100, and the first wiring layer 140 is provided with a first groove 130, the first groove 130 exposes the first circuit 120, the first wiring layer 140 is electrically connected to the first circuit 120, and is electrically connected to the first conductive post 110.

[0189] The substrate 160 is located on the first wiring layer 140. The substrate 160 includes substrate conductive pillars 161 that are electrically connected to the first wiring layer 140, and the substrate 160 covers the first groove 130 to form a first cavity 131.

[0190] The first back wiring layer 150 is located on the second side of the first chip 100, and the first back wiring layer 150 is electrically connected to the first conductive post 110.

[0191] The chip stack 300 is formed by sequentially stacking n first chip structures 101 corresponding to n first back-side wiring layers 150 in the same orientation, where n ≥ 1. The chip stack 300 includes n second cavities 231. In this embodiment, n = 2, and the chip stack 300 is formed by sequentially stacking two first chip structures 101 corresponding to two first back-side wiring layers 150 in the same orientation. In this embodiment, n = 2 is used as an example, but the value of n is not limited to this.

[0192] The bottom chip structure 401 includes a bottom chip 400 and a bottom wiring layer 440. The bottom chip structure 401 is located on the first back wiring layer 150 of the chip stack 300, and is electrically connected to the first back wiring layer 150 to form a bottom cavity 431. The bottom chip 400 has a first surface and a second surface disposed opposite to each other, and the bottom chip 400 includes a bottom circuit 420 located on the first surface of the bottom chip 400. The bottom wiring layer 440 is formed on the first surface of the bottom chip 400, and the bottom wiring layer 440 is provided with a bottom groove 430, the bottom groove 430 exposes the bottom circuit 420, and the bottom wiring layer 440 is electrically connected to the bottom circuit 420.

[0193] The front wiring layer 170 is located on the substrate 160, and the front wiring layer 170 is electrically connected to the conductive pillar 161 of the substrate.

[0194] The metal bump 180 is located on the front wiring layer 170 and is electrically connected to the front wiring layer 170.

[0195] As an example, the substrate 160 includes one of a wafer, a silicon oxide substrate, or an organic resin substrate, and the thickness of the substrate 160 is 50 μm to 100 μm.

[0196] As an example, the first chip 100 includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip; the bottom chip 400 includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip.

[0197] As an example, the first wiring layer 140 has a ring-shaped structure; the bottom wiring layer 440 has a ring-shaped structure; the thickness of the first cavity 131 ranges from 1μm to 20μm, for example, any value within this range such as 1μm, 3μm, 5μm, 8μm, 10μm, 15μm, 20μm; the thickness of the second cavity 231 ranges from 1μm to 20μm, for example, any value within this range such as 1μm, 3μm, 5μm, 8μm, 10μm, 15μm, 20μm; the thickness of the bottom cavity 431 ranges from 1μm to 20μm, for example, any value within this range such as 1μm, 3μm, 5μm, 8μm, 10μm, 15μm, 20μm.

[0198] As an example, the fabrication method of the first wiring layer 140 and the bottom wiring layer 440 includes fabrication using a damascus process.

[0199] As an example, in order to increase the effective sensor area of ​​the filter, improve the performance of the filter, and reduce the transmission path, the center line of the first cavity 131 along the vertical direction coincides with the center line of the second cavity 231 and the bottom cavity 431.

[0200] As an example, the chip stack 300 contains n first chip structures 101, each of which includes either a bulk acoustic wave filter chip or a surface acoustic wave filter chip. The n first chip structures 101 can be of the same type or different types of filter chip structures.

[0201] The materials of the first wiring layer 140, the bottom wiring layer 440, and the substrate 160 have been described in Embodiment 1 and will not be repeated here. The first chip structure 101 and the bottom chip structure 401 have been described in Embodiment 1 and will not be repeated here.

[0202] In this embodiment, the selected value of n is 2. Of course, in some other embodiments, n can take the value of 1, 3, 4, 5, etc., depending on the actual situation, to realize the stack structure of the three-dimensional filter, thereby obtaining a smaller package structure, which is beneficial to chip integration and use, and realizes chip miniaturization and weight reduction.

[0203] In summary, this invention provides a three-dimensional filter stack structure and its fabrication method. A first chip structure is bonded to a substrate to form a first cavity. Simultaneously, multiple first chip structures, combined with multiple first back-side wiring layers, are sequentially stacked from the first back-side wiring layers of the first chips to form a chip stack. A bottom chip structure is then placed on the first back-side wiring layer of the chip stack. Electrical connections are achieved between the substrate and the different chip structures through conductive pillars. By thinning the substrate and arranging front-side wiring layers with connecting metal bumps, three-dimensional stacking of the chips during the packaging process can be achieved, significantly reducing the packaged chip area. This is beneficial for chip integration and use, enabling chip miniaturization and weight reduction. Furthermore, by setting multiple cavities as a closed structure, the acoustic energy density of the device is improved, sound waves are better confined, and device losses are reduced. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0204] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A three-dimensional filter stack structure, characterized in that, The three-dimensional filter stack structure includes: A first chip structure includes a first chip and a first wiring layer; the first chip has a first surface and a second surface disposed opposite to each other, and the first chip includes a first circuit and a first conductive post located on the first surface of the first chip; the first wiring layer is located on the first surface of the first chip, and the first wiring layer is provided with a first groove, the first groove exposing the first circuit, the first wiring layer being electrically connected to the first circuit and electrically connected to the first conductive post. A substrate, the substrate being located on the first wiring layer, the substrate including substrate conductive pillars electrically connected to the first wiring layer, and the substrate covering the first groove to form a first cavity; A first back wiring layer is located on the second side of the first chip and is electrically connected to the first conductive pillar. A bottom chip structure includes a bottom chip and a bottom wiring layer. The bottom chip structure is located on the second side of the first chip, electrically connected to the first back wiring layer, and forms a bottom cavity. The bottom chip has a first side and a second side disposed opposite to each other, and the bottom chip includes a bottom circuit located on the first side of the bottom chip. The bottom wiring layer is formed on the first side of the bottom chip, and the bottom wiring layer has a bottom groove that exposes the bottom circuit. The bottom wiring layer is electrically connected to the bottom circuit. A front wiring layer is located on the substrate and is electrically connected to the conductive pillars of the substrate. A metal bump, the metal bump being located on the front wiring layer and electrically connected to the front wiring layer.

2. The three-dimensional filter stack structure according to claim 1, characterized in that: The first chip includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip; the bottom chip includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip.

3. The three-dimensional filter stack structure according to claim 1, characterized in that: The first back wiring layer and the bottom chip structure further include a chip stack and a corresponding second cavity. The chip stack is formed by n first chip structures corresponding to n first back wiring layers stacked in the same direction, and n≥1.

4. The three-dimensional filter stack structure according to claim 3, characterized in that: The thickness of the first cavity ranges from 1 μm to 20 μm; the thickness of the second cavity ranges from 1 μm to 20 μm; and the thickness of the bottom cavity ranges from 1 μm to 20 μm.

5. The three-dimensional filter stack structure according to claim 1, characterized in that: The substrate includes one of a wafer, a silicon oxide substrate, or an organic resin substrate, and the thickness of the substrate is 50 μm to 100 μm.

6. The three-dimensional filter stack structure according to claim 1, characterized in that: The centerline of the first vertical cavity coincides with the centerline of the bottom cavity.

7. A method for fabricating a three-dimensional filter stack structure, characterized in that, Includes the following steps: S1: A first chip structure is provided, the first chip structure includes a first chip and a first wiring layer; the first chip has a first surface and a second surface disposed opposite to each other, and the first chip includes a first circuit and a first conductive post located on the first surface of the first chip; the first wiring layer is formed on the first surface of the first chip, and the first wiring layer is provided with a first groove, the first groove exposes the first circuit, the first wiring layer is electrically connected to the first circuit, and is electrically connected to the first conductive post. S2: A substrate is bonded to the first wiring layer, and the substrate covers the first groove to form a first cavity; S3: Thin the second side of the first chip to expose the first conductive pillar; S4: A first back-side wiring layer is formed on the second side of the first chip, and the first back-side wiring layer is electrically connected to the first conductive pillar; S5: Provide a bottom chip structure, the bottom chip structure including a bottom chip and a bottom wiring layer; the bottom chip has a first surface and a second surface disposed opposite to each other, and the bottom chip includes a second circuit located on the first surface of the bottom chip; the bottom wiring layer is formed on the first surface of the bottom chip, and the bottom wiring layer has a bottom groove, the bottom groove exposing the bottom circuit, and the bottom wiring layer is electrically connected to the bottom circuit; S6: The bottom wiring layer is bonded to the first back wiring layer and electrically connected to the first back wiring layer; the first back wiring layer covers the bottom groove to form a bottom cavity; S7: Thin the substrate and form substrate conductive pillars in the substrate, wherein the substrate conductive pillars are electrically connected to the first wiring layer; S8: A front wiring layer is formed on the substrate, and the front wiring layer is electrically connected to the conductive pillars of the substrate; S9: A metal bump is formed on the front wiring layer, and the metal bump is electrically connected to the front wiring layer.

8. The method for fabricating a three-dimensional filter stack structure according to claim 7, characterized in that: Between step S4 and step S5, there is also a step of forming a chip stack, which is formed by stacking n first chip structures corresponding to n first back wiring layers in the same orientation, and forming n second cavities accordingly; wherein, the step of preparing the chip stack includes repeating the corresponding steps S1, S3 and S4 n times.

9. The method for fabricating a three-dimensional filter stack structure according to claim 8, characterized in that: The thickness of the first cavity, the second cavity, and the bottom cavity ranges from 1 μm to 20 μm.

10. The method for fabricating a three-dimensional filter stack structure according to claim 7, characterized in that: The first wiring layer includes a damascus wiring layer; the bottom wiring layer includes a damascus wiring layer.

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