Three-dimensional filter stack structure and method of making the same

Abstract

The application provides a three-dimensional filter stack structure and a preparation method thereof. The first chip and the second chip are stacked through a shared middle substrate. The middle substrate can form a second conductive column through a TSV technology to realize electrical connection between the first chip and the second chip. Meanwhile, after two surfaces of the middle substrate are attached to the first chip and the second chip respectively, a closed first cavity and a closed second cavity are formed to improve the acoustic energy density of the device, better limit the acoustic wave and reduce the loss of the device. In addition, the chips are three-dimensionally stacked in the packaging process, which effectively reduces the packaging chip area, is beneficial to the integration and use of the chips and realizes the miniaturization and light weight of the chips.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology and relates to a three-dimensional filter stack structure and its fabrication method. Background Technology

[0002] Electronic devices include radio frequency (RF) chip modules to enable wireless communication. These RF chip modules include components such as filters, low-noise amplifiers, power amplifiers, and RF switches. For filters, a cavity structure is included to provide vibration space for sound waves. Currently, when using chip-scale packaging (CSP) technology to package filters, the filter wafer is soldered to a substrate using solder balls, and an organic thin film is coated on the surface of the filter wafer to form a cavity structure; then, it is encapsulated with epoxy molding compound (EMC) material.

[0003] With the development of semiconductor technology, the requirements for miniaturization and lightweighting in electronic devices are constantly increasing. For example, taking the radio frequency (RF) module of a 5G mobile phone as an example, this RF module generally uses a quadrupler, which combines four BAW filters and shares the same node to achieve simultaneous reception of two frequency bands. However, the quadrupler requires four filters, resulting in a larger chip package area, which is not conducive to integration and use, and remains an important technical problem that urgently needs to be solved by those in the field.

[0004] Therefore, it is essential to provide a three-dimensional filter stack structure and its fabrication method to solve the problem of large chip packaging area hindering integration and use.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a three-dimensional filter stack structure and its fabrication method, so as to solve the problem of large chip packaging area causing difficulties in integration and use.

[0007] To achieve the above and other related objectives, the present invention provides a three-dimensional filter stack structure, the three-dimensional filter stack structure comprising:

[0008] A first chip has a first side and a second side disposed opposite to each other, and the first chip includes a first circuit located on the first side of the first chip.

[0009] The first conductive post penetrates the first chip;

[0010] A first wiring layer is located on the first side of the first chip. The first wiring layer has a first groove that exposes the first circuit. The first wiring layer is electrically connected to the first circuit and the first conductive pillar.

[0011] A substrate, which is located on the first wiring layer and covers the first groove to form a first cavity;

[0012] The second conductive post penetrates the substrate and is electrically connected to the first wiring layer;

[0013] A second wiring layer is located on the substrate and includes a second groove. The second wiring layer is electrically connected to the first wiring layer.

[0014] The second chip is located on the second wiring layer, includes a second circuit, and covers the second groove to form a second cavity, and the second cavity exposes the second circuit.

[0015] The third wiring layer is located on the second side of the first chip, and the first conductive pillar is electrically connected to the third wiring layer;

[0016] A metal bump, the metal bump being located on the third wiring layer and electrically connected to the third wiring layer.

[0017] Optionally, the substrate includes one of a wafer, a silicon oxide substrate, or an organic resin substrate, and the thickness of the substrate is 50 μm to 100 μm.

[0018] Optionally, the thickness of the first cavity ranges from 1 μm to 20 μm; the thickness of the second cavity ranges from 1 μm to 20 μm.

[0019] Optionally, the first chip includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip, and the second chip includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip.

[0020] Optionally, the first wiring layer includes a damascus wiring layer; the second wiring layer includes a damascus wiring layer.

[0021] Optionally, the centerline of the first cavity along the vertical axis coincides with the centerline of the second cavity.

[0022] This invention also provides a method for fabricating a three-dimensional filter stack structure, comprising the following steps:

[0023] A first chip is provided, the first chip having a first side and a second side disposed opposite to each other, and the first chip including a first circuit located on the first side of the first chip;

[0024] A deep hole is formed on the first surface of the first chip, and a first conductive post is formed to fill the deep hole;

[0025] A first wiring layer is formed on a first surface of the first chip, and the first wiring layer has a first groove, the first groove exposes the first circuit, the first wiring layer is electrically connected to the first circuit and electrically connected to the first conductive post;

[0026] A substrate is bonded to the first wiring layer, and the substrate covers the first groove to form a first cavity;

[0027] The substrate is thinned, and a second conductive pillar is formed in the substrate, the second conductive pillar being electrically connected to the first wiring layer;

[0028] A second chip is provided, the second chip including a second circuit, and the second circuit is located on the surface of the second chip;

[0029] A second wiring layer is formed on the second chip, and the second wiring layer has a second groove, the second groove exposes the second circuit, and the second wiring layer is electrically connected to the second circuit;

[0030] The second wiring layer is bonded to the substrate, and the second wiring layer is electrically connected to the first wiring layer, and the substrate covers the second groove to form a second cavity;

[0031] Thin the first chip from its second side to expose the first conductive pillar;

[0032] A third wiring layer is formed on the second side of the first chip, and the third wiring layer is electrically connected to the first conductive pillar;

[0033] Metal bumps are formed on the third wiring layer, and the metal bumps are electrically connected to the third redistribution layer.

[0034] Optionally, the substrate includes one of a wafer, a silicon oxide substrate, or an organic resin substrate, and the thickness of the thinned substrate ranges from 50 μm to 100 μm.

[0035] Optionally, the first conductive post is formed using TSV technology, and the second conductive post is formed using TSV technology.

[0036] Optionally, the method for fabricating the first wiring layer includes fabricating it using a damascus process; the method for fabricating the second wiring layer includes fabricating it using a damascus process.

[0037] As described above, this invention provides a three-dimensional filter stack structure and its fabrication method. A first chip and a second chip are stacked by sharing a substrate located in the middle. The middle substrate can form a second conductive pillar through TSV technology to realize the electrical connection between the first chip and the second chip. At the same time, after the two sides of the middle substrate are respectively attached to the first chip and the second chip, a closed first cavity and a second cavity are formed, which improves the acoustic energy density of the device, better confines the sound waves, and reduces the device loss. In addition, the chips form a three-dimensional stack during the packaging process, which effectively reduces the packaged chip area, which is beneficial to the integration and use of the chip, and realizes the miniaturization and weight reduction of the chip. Attached Figure Description

[0038] Figure 1 The diagram shows a cross-sectional schematic of the three-dimensional filter stack structure in Embodiments 1 and 2 of the present invention.

[0039] Figure 2 The diagram shows a flowchart illustrating the fabrication method of the three-dimensional filter stack structure in Embodiment 1 of the present invention.

[0040] Figure 3 The diagram shown is a structural schematic of the first chip provided in Embodiment 1 of the present invention.

[0041] Figure 4 The diagram shown is a schematic diagram of the structure for forming the first conductive pillar in Embodiment 1 of the present invention.

[0042] Figure 5 The diagram shown is a schematic diagram of the structure after the first wiring layer is formed in Embodiment 1 of the present invention.

[0043] Figure 6 The image shown is a top view of the first wiring layer after it has been formed in Embodiment 1 of the present invention.

[0044] Figure 7 The diagram shown is a schematic representation of the structure after the first cavity is formed in Embodiment 1 of the present invention.

[0045] Figure 8 The diagram shown is a schematic representation of the structure after the second conductive pillar is formed in Embodiment 1 of the present invention.

[0046] Figure 9 The diagram shown is a schematic diagram of the structure of the second chip provided in Embodiment 1 of the present invention.

[0047] Figure 10 The diagram shown is a schematic diagram of the structure after the second wiring layer is formed in Embodiment 1 of the present invention.

[0048] Figure 11 The diagram shown is a schematic representation of the structure after the second cavity is formed in Embodiment 1 of the present invention.

[0049] Figure 12 The diagram shown is a schematic representation of the structure of the first chip after thinning in Embodiment 1 of the present invention.

[0050] Figure 13 The diagram shown is a schematic representation of the structure after the third wiring layer is formed in Embodiment 1 of the present invention.

[0051] Figure 14 The diagram shown is a schematic representation of the structure after the metal bumps are formed in Embodiment 1 of the present invention.

[0052] Explanation of reference numerals in the attached figures

[0053] 100 First Chip

[0054] 110 First conductive post

[0055] 120 First Circuit

[0056] 200 First wiring layer

[0057] 210 First Metal Layer

[0058] 220 First Dielectric Layer

[0059] 230 First Groove

[0060] 231 First cavity

[0061] 300 substrates

[0062] 310 Second Conductive Post

[0063] 400 Second wiring layer

[0064] 410 Second metal layer

[0065] 420 Second Dielectric Layer

[0066] 430 Second Groove

[0067] 431 Second cavity

[0068] 500 Second Chip

[0069] 520 Second Circuit

[0070] 600 Third wiring layer

[0071] 610 Third Metal Layer

[0072] 620 Third Dielectric Layer

[0073] 700 metal bumps Detailed Implementation

[0074] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0075] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0076] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for the device in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between. The phrase “between” as used herein includes both endpoint values.

[0077] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0078] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0079] Example 1

[0080] See Figure 1 This is the three-dimensional filter stack structure prepared in this embodiment, wherein... Figures 2 to 14 The diagram illustrates the structural steps involved in fabricating the three-dimensional filter stack structure. The fabrication of the three-dimensional filter stack structure is described below with reference to the accompanying drawings.

[0081] First, refer to Figure 2 and Figure 3 Step S1 is executed, providing a first chip 100, the first chip 100 having a first side and a second side disposed opposite to each other, and the first chip 100 including a first circuit 120, the first circuit 120 being located on the first side of the first chip 100.

[0082] Specifically, the first circuit 120 is exposed on the first side of the first chip 100, and the first circuit 120 is a filter circuit composed of capacitors, inductors and resistors. The filter circuit can effectively filter out a specific frequency point or a frequency other than that frequency point in the power line to obtain a power signal of a specific frequency or eliminate a power signal of a specific frequency.

[0083] Furthermore, the first chip 100 includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip. In this embodiment, the first chip 100 is a bulk acoustic wave filter chip. The bulk acoustic wave filter performs better at high frequencies, such as in the 5 GHz or even higher frequency bands, and is especially widely used in the high-frequency range of 4 GHz and 5 GHz.

[0084] As an example, the first chip 100 can function as either a transmitter or a receiver. In this embodiment, the first chip 100 functions as a receiver to receive signals and reduce or eliminate interference from other signals or devices, ensuring the quality of the received signal. In some other embodiments, the first chip 100 can also function as a transmitter of a filter chip, which will not be detailed here.

[0085] Next, refer to Figure 2 and Figure 4 Step S2 is executed to form a deep hole on the first surface of the first chip 100 and to form a first conductive post 110 that fills the deep hole.

[0086] Specifically, the first conductive post 110 is formed using TSV technology. In this embodiment, the grooving method for the deep hole is not limited to one of mechanical grooving, laser etching, or plasma etching, and can be selected as needed.

[0087] Furthermore, the first conductive post 110 extends inward from the first surface of the first chip 100; the first conductive post 110 is filled with conductive material, such as copper, tungsten, etc., in the deep hole to form a connection channel for vertical electrical connection.

[0088] Next, refer to Figure 2 and Figure 5In step S3, a first wiring layer 200 is formed on the first surface of the first chip 100, and the first wiring layer 200 is provided with a first groove 230. The first groove 230 exposes the first circuit 120. The first wiring layer 200 is electrically connected to the first circuit 120 and to the first conductive post 110.

[0089] Specifically, to reduce interconnect resistance, improve device reliability, and achieve a high-density interconnect structure, the first wiring layer 200 is a damascus wiring layer fabricated using a damascus process. The first wiring layer 200 also includes a first dielectric layer 220. To reduce parasitic capacitance between interconnects, the first dielectric layer 220 is typically made of materials with low dielectric constants, such as silicon oxide, silicon fluoride, or silicon dioxide. In this embodiment, the material of the first dielectric layer 220 in the damascus process is silicon oxide. Furthermore, because copper has low resistivity, it can achieve a smaller linewidth at the same current density, increasing interconnect density; therefore, copper is used as the material of the first metal layer 210.

[0090] Furthermore, the first metal layer 210 is formed by depositing a copper seed layer or by electroplating, and is electrically connected to the first conductive pillar 110.

[0091] As an example, the grooving method of the first groove 230 is not limited to one of mechanical grooving, laser etching, plasma etching, or chemical etching, and can be selected according to the specific needs.

[0092] For details, please refer to Figure 6 The first wiring layer 200 is annular, and the first groove 230 is located at the center of the first wiring layer 200.

[0093] Next, refer to Figure 2 and Figure 7 In step S4, a substrate 300 is bonded to the first wiring layer 200, and the substrate 300 covers the first groove 230 to form a first cavity 231.

[0094] Specifically, the substrate 300 includes one of a wafer, a silicon oxide substrate, or an organic resin substrate. In this embodiment, the substrate 300 is a wafer.

[0095] Furthermore, the substrate can be bonded to the first wiring layer 200 using an epoxy resin bonding chip bonding process, or it can be bonded to the first wiring layer 200 using a wafer-on-film (DAF) bonding process. In this embodiment, a small amount of epoxy resin is placed on the first wiring layer 200, and the substrate 300 and the first wiring layer 200 are bonded together. The epoxy resin is cured at a temperature of 150°C to 250°C by reflow or curing, thereby achieving bonding between the first chip 100 and the substrate 300.

[0096] Furthermore, see Figure 6 and Figure 7 To improve sound energy density, better confine sound waves, and reduce losses, the first wiring layer 200 in this embodiment adopts a ring structure to make the first cavity 231 a closed cavity. To ensure the structural stability of the filter structure and avoid affecting the reflection of sound waves and the formation of standing waves, the height of the first cavity 231 is in the range of 1μm to 20μm, such as any value within this range, such as 1μm, 3μm, 5μm, 8μm, 10μm, 15μm, 20μm, etc., which effectively improves the stability of the device and reduces the loss of the device.

[0097] Next, refer to Figure 2 and Figure 8 Step S5 is executed to thin the substrate 300 and form a second conductive pillar 310 in the substrate 300. The second conductive pillar 310 is electrically connected to the first wiring layer 200.

[0098] Specifically, in order to reduce the height of the three-dimensional filter stack structure, shrink the package size, improve the thermal diffusion efficiency of the chip, and avoid reducing the resonant frequency of the wave and affecting the filter performance, this embodiment proposes to thin the substrate 300. The thickness of the thinned substrate 300 is in the range of 50μm to 100μm, such as any value within this range, such as 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, etc. The thinning method can be such as chemical mechanical polishing (CMP) or etching, which will not be elaborated on here.

[0099] Furthermore, the second conductive post 310 is formed using TSV technology. In this embodiment, the grooving method for the hole in TSV technology is not limited to mechanical grooving, laser etching, or plasma etching; it can be selected according to specific needs. The second conductive post 310 is formed by filling the corresponding hole with conductive material, such as copper or tungsten, to form a vertical electrical connection channel.

[0100] Next, refer to Figure 2 and Figure 9Step S6 is executed, providing a second chip 500, the second chip 500 including a second circuit 520, and the second circuit 520 being located on the surface of the second chip 500.

[0101] Specifically, the second circuit 520 is exposed on the surface of the second chip 500, and the second circuit 520 is a filter circuit composed of capacitors, inductors and resistors. The filter circuit can effectively filter out a specific frequency point or a frequency other than that frequency point in the power line to obtain a power signal of a specific frequency or eliminate a power signal of a specific frequency.

[0102] Furthermore, similar to the first chip 100, the second chip 500 includes one of a bulk acoustic wave (BAW) filter chip and a surface acoustic wave (SAW) filter chip. In this embodiment, the second chip 500 is a BAW filter chip. The BAW filter exhibits better performance at high frequencies, such as in applications at 5 GHz or even higher frequency bands, and is particularly widely used in the high-frequency range of 4 GHz and 5 GHz.

[0103] As an example, the second chip 500 can function as either a transmitter or a receiver. In this embodiment, the first chip 100 serves as a transmitter, ensuring that the transmitted signal meets specific frequency characteristics, reducing unnecessary frequency components to avoid interfering with other communication signals, and improving signal transmission efficiency and quality. In some other embodiments, the second chip 500 can also function as a receiver, which will not be detailed here.

[0104] Next, refer to Figure 2 and Figure 10 In step S7, a second wiring layer 400 is formed on the second chip 500, and the second wiring layer 400 is provided with a second groove 430, the second groove 430 exposes the second circuit 520, and the second wiring layer 400 is electrically connected to the second circuit 520.

[0105] Specifically, the second wiring layer 400 is a masquerading wiring layer fabricated using the damascus process. The second wiring layer 400 also includes a second dielectric layer 420. To reduce parasitic capacitance between interconnects, the material of the second dielectric layer 420 typically includes low dielectric constants such as silicon oxide, silicon fluoride, or silicon dioxide. In this embodiment, the material of the second dielectric layer 420 fabricated using the damascus process is silicon oxide. In addition, since copper has a low resistivity, it can achieve a smaller linewidth at the same current density, thereby increasing the interconnect density. Therefore, copper is used as the material of the second metal layer 410.

[0106] Furthermore, the second metal layer 410 is formed by depositing a copper seed layer or by electroplating.

[0107] As an example, the grooving method of the second groove 430 is not limited to one of mechanical grooving, laser etching, plasma etching, or chemical etching; the specific method can be selected as needed.

[0108] Specifically, in this embodiment, similar to the first wiring layer 200, the second groove 430 is located at the center of the first wiring layer 200 and exposes the second circuit 520.

[0109] Next, refer to Figure 2 and Figure 11 In step S8, the second chip 500 is bonded to the substrate 300, and the second wiring layer 400 is electrically connected to the first wiring layer 200, and the substrate 300 covers the second groove 430 to form a second cavity 431.

[0110] As an example, the process for bonding the second chip 500 to the substrate 300 includes an adhesive bonding process using epoxy resin and a chip bonding process using a wafer-on-a-flake (DAF) film. In this embodiment, a small amount of epoxy resin is placed on the second wiring layer 400, and the substrate 300 and the second wiring layer 400 are bonded together. The epoxy resin is cured at a temperature of 150°C to 250°C by reflow or curing, thereby achieving the bonding between the second chip 500 and the substrate 300. Of course, other bonding methods can also be used for bonding, and this is not limited here.

[0111] Furthermore, in order to improve the acoustic energy density, better confine the sound waves, and reduce losses, the second wiring layer 400 in this embodiment adopts a ring structure to make the second cavity 431 a closed cavity. In order to ensure the structural stability of the filter structure and avoid affecting the reflection of sound waves or the formation of standing waves, the height range of the second cavity 431 is 1μm to 20μm, such as any value within this range, such as 1μm, 3μm, 5μm, 8μm, 10μm, 15μm, 20μm, etc., which effectively improves the stability of the device and reduces the loss of the device.

[0112] Furthermore, in order to increase the effective sensor area of ​​the filter, improve the filter performance, and reduce the transmission path, the center line of the first cavity in the vertical direction coincides with the center line of the second cavity.

[0113] Next, refer to Figure 2 and Figure 12 Step S9 is executed, thinning the first chip from the second side of the first chip 100 to expose the first conductive pillar 110.

[0114] Specifically, in order to reduce the height of the three-dimensional stack structure, shrink the package size, and enable the first chip 100 to achieve electrical connection, the second side of the first chip 100 is thinned; the thinning method can be such as chemical mechanical polishing (CMP) or etching, which will not be elaborated on here.

[0115] Next, refer to Figure 2 and Figure 13 In step S10, a third wiring layer 600 is formed on the second side of the first chip 100, and the third wiring layer 600 is electrically connected to the first conductive post 110.

[0116] As an example, the third wiring layer 600 is formed using a damascus process. The third wiring layer 600 includes a third metal layer 610 and a third dielectric layer 620. To maintain a miniaturized package structure, the thickness of the third wiring layer 600 ranges from 10μm to 30μm, for example, any value within this range such as 10μm, 15μm, 20μm, 25μm, or 30μm.

[0117] The third dielectric layer 620 may be one or a combination of silicon oxide, silicon nitride, fluorinated glass, PI, PBO, and BCB layers, and the third metal layer 610 may be one or a combination of copper, aluminum, nickel, gold, and silver layers. The material, number of wiring layers, and wiring distribution of the third wiring layer 600 are not limited here and can be selected as needed.

[0118] Next, refer to Figure 2 and Figure 14 In step S11, a metal bump 700 is formed on the third wiring layer 600, and the metal bump 700 is electrically connected to the third wiring layer 600.

[0119] The metal bump 700 may include, for example, solder ball bumps, C4 metal bumps, column bumps, etc. The material of the metal bump 700 may be one of copper, aluminum, nickel, gold, silver or titanium. The specific type of the metal bump 700 is not excessively limited here.

[0120] Example 2

[0121] This embodiment also provides a three-dimensional filter stack structure. The three-dimensional filter stack structure is obtained using the fabrication method described in Embodiment 1 or other suitable similar methods. For details regarding the fabrication method, materials, and structure of the three-dimensional filter stack structure, please refer to Embodiment 1. Figure 1 The diagram shows a cross-sectional view of the packaging structure, wherein the three-dimensional filter stack structure includes:

[0122] A first chip 100 has a first side and a second side disposed opposite to each other, and the first chip 100 includes a first circuit 120 located on the first side of the first chip 100.

[0123] The first conductive post 110 passes through the first chip 100.

[0124] A first wiring layer 200 is located on the first surface of the first chip 100; the first wiring layer 200 is provided with a first groove 230, the first groove 230 exposes the first circuit 120, and the first wiring layer 200 is electrically connected to the first circuit 120 and the first conductive post 110.

[0125] The substrate 300 is located on the first wiring layer 200 and covers the first groove 230 to form a first cavity 231.

[0126] The second conductive post 310 penetrates the substrate 300 and is electrically connected to the first wiring layer 200.

[0127] A second wiring layer 400 is located on the substrate 300 and includes a second groove 430. The second wiring layer 400 is electrically connected to the first wiring layer 200.

[0128] The second chip 500 is located on the second wiring layer 400 and includes a second circuit 520. The second chip 500 covers the second groove 430 to form a second cavity 431, and the second cavity 431 exposes the second circuit 520.

[0129] A third wiring layer 600 is located on the second side of the first chip 100, and the first conductive post 110 is electrically connected to the third wiring layer 600.

[0130] A metal bump 700 is located on the third wiring layer 600 and is electrically connected to the third wiring layer 600.

[0131] As an example, the substrate 300 includes one of a wafer, a silicon oxide substrate, or an organic resin substrate. In order to reduce the height of the three-dimensional filter stack structure, while shrinking the package size and improving the thermal diffusion efficiency of the chip, and at the same time avoiding the reduction of the resonant frequency of the wave and affecting the filter performance, the thickness of the substrate 300 is 50μm to 100μm, for example, any value within this range such as 50μm, 60μm, 70μm, 80μm, 90μm, 100μm.

[0132] As an example, the first chip 100 includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip, and the second chip 500 includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip.

[0133] As an example, to improve sound energy density, better confine sound waves, and reduce losses, the first wiring layer 200 and the second wiring layer 400 are both annular structures, thus making both the first cavity 231 and the second cavity 431 closed structures. Furthermore, to ensure the structural stability of the filter structure and avoid affecting sound wave reflection or standing wave formation, the thickness of the first cavity 231 ranges from 1μm to 20μm, such as any value within this range (1μm, 3μm, 5μm, 8μm, 10μm, 15μm, 20μm, etc.), effectively improving device stability and reducing device losses. Similarly, the thickness of the second cavity 431 ranges from 1μm to 20μm, such as any value within this range (1μm, 3μm, 5μm, 8μm, 10μm, 15μm, 20μm, etc.), effectively improving device stability and reducing device losses.

[0134] Furthermore, in order to increase the effective sensor area of ​​the filter, improve the filter performance, and reduce the transmission path, the center line of the first cavity in the vertical direction coincides with the center line of the second cavity.

[0135] As an example, the dielectric material used in the first wiring layer 200 includes low dielectric constant materials such as silicon oxycarbonate, silicon fluoride, or silicon dioxide. The first wiring layer 200 also includes a first dielectric layer 220. In this embodiment, the material of the first dielectric layer 220 in the damascus process is silicon oxide; in addition, since copper has a low resistivity, it can achieve a smaller linewidth and increase the interconnect density at the same current density, so copper is used as the material of the first metal layer 210.

[0136] As an example, the second wiring layer 400 also includes a second dielectric layer 420. The materials of the second dielectric layer 420 and the second metal layer 410 are similar to those of the first wiring layer 200, and will not be described in detail here.

[0137] As an example, the third dielectric layer 620 may be one or a combination of silicon oxide, silicon nitride, fluorinated glass, PI, PBO, and BCB layers, and the third metal layer 610 may be one or a combination of copper, aluminum, nickel, gold, and silver layers. The material, number of wiring layers, and wiring distribution of the third wiring layer 600 are not limited here and can be selected as needed.

[0138] As an example, the metal bump 700 may include, for example, solder ball bumps, C4 metal bumps, column bumps, etc. The material of the metal bump 700 may be one of copper, aluminum, nickel, gold, silver or titanium. The specific type of the metal bump 700 is not excessively limited here.

[0139] In summary, this invention provides a three-dimensional filter stack structure and its fabrication method. A first chip and a second chip are stacked together by sharing a central substrate. The central substrate can form a second conductive pillar using TSV technology to achieve electrical connection between the first and second chips. Simultaneously, after the two sides of the central substrate are respectively bonded to the first and second chips, closed first and second cavities are formed, increasing the acoustic energy density of the device, better confining sound waves, and reducing device losses. Furthermore, the three-dimensional stacking of the chips during packaging effectively reduces the packaged chip area, facilitating chip integration and use, and achieving chip miniaturization and weight reduction. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0140] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A three-dimensional filter stack structure, characterized in that, The three-dimensional filter stack structure includes: A first chip has a first side and a second side disposed opposite to each other, and the first chip includes a first circuit located on the first side of the first chip. The first conductive post penetrates the first chip; A first wiring layer is located on the first side of the first chip. The first wiring layer has a first groove that exposes the first circuit. The first wiring layer is electrically connected to the first circuit and the first conductive pillar. A substrate, which is located on the first wiring layer and covers the first groove to form a first cavity; The second conductive post penetrates the substrate and is electrically connected to the first wiring layer; A second wiring layer is located on the substrate and includes a second groove. The second wiring layer is electrically connected to the first wiring layer. The second chip is located on the second wiring layer, includes a second circuit, and covers the second groove to form a second cavity, and the second cavity exposes the second circuit. The third wiring layer is located on the second side of the first chip, and the first conductive pillar is electrically connected to the third wiring layer; A metal bump, the metal bump being located on the third wiring layer and electrically connected to the third wiring layer.

2. The three-dimensional filter stack structure according to claim 1, characterized in that: The substrate includes one of a wafer, a silicon oxide substrate, or an organic resin substrate, and the thickness of the substrate is 50 μm to 100 μm.

3. The three-dimensional filter stack structure according to claim 1, characterized in that: The thickness of the first cavity ranges from 1 μm to 20 μm; the thickness of the second cavity ranges from 1 μm to 20 μm.

4. The three-dimensional filter stack structure according to claim 1, characterized in that: The first chip includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip, and the second chip includes one of a bulk acoustic wave filter chip and a surface acoustic wave filter chip.

5. The three-dimensional filter stack structure according to claim 1, characterized in that: The first wiring layer includes a damascus wiring layer; the second wiring layer includes a damascus wiring layer.

6. The three-dimensional filter stack structure according to claim 1, characterized in that: The centerline of the first cavity coincides with the centerline of the second cavity along the vertical direction.

7. A method for fabricating a three-dimensional filter stack structure, characterized in that, Includes the following steps: A first chip is provided, the first chip having a first side and a second side disposed opposite to each other, and the first chip including a first circuit located on the first side of the first chip; A deep hole is formed on the first surface of the first chip, and a first conductive post is formed to fill the deep hole; A first wiring layer is formed on a first surface of the first chip, and the first wiring layer has a first groove, the first groove exposes the first circuit, the first wiring layer is electrically connected to the first circuit and electrically connected to the first conductive post; A substrate is bonded to the first wiring layer, and the substrate covers the first groove to form a first cavity; The substrate is thinned, and a second conductive pillar is formed in the substrate, the second conductive pillar being electrically connected to the first wiring layer; A second chip is provided, the second chip including a second circuit, and the second circuit is located on the surface of the second chip; A second wiring layer is formed on the second chip, and the second wiring layer has a second groove, the second groove exposes the second circuit, and the second wiring layer is electrically connected to the second circuit; The second wiring layer is bonded to the substrate, and the second wiring layer is electrically connected to the first wiring layer, and the substrate covers the second groove to form a second cavity; Thin the first chip from its second side to expose the first conductive pillar; A third wiring layer is formed on the second side of the first chip, and the third wiring layer is electrically connected to the first conductive pillar; a metal bump is formed on the third wiring layer, and the metal bump is electrically connected to the third redistribution layer.

8. The method for fabricating a three-dimensional filter stack structure according to claim 7, characterized in that: The substrate includes one of a wafer, a silicon oxide substrate, or an organic resin substrate, and the thickness of the thinned substrate ranges from 50 μm to 100 μm.

9. The method for fabricating a three-dimensional filter stack structure according to claim 7, characterized in that: The first conductive post is formed using TSV technology, and the second conductive post is formed using TSV technology.

10. The method for fabricating a three-dimensional filter stack structure according to claim 7, characterized in that: The method for fabricating the first wiring layer includes using a damascus process; the method for fabricating the second wiring layer includes using a damascus process.

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