High integration low loss hybrid FBAR chip based on glass via process

Abstract

The present disclosure relates to a hybrid FBAR chip and electronic device, the hybrid FBAR chip comprising: a glass substrate, a film bulk acoustic resonator chip, an electrical interconnection structure and an integrated passive device structure; the integrated passive device at least comprising a first spiral inductor formed in the substrate, the first spiral inductor being spirally wound perpendicular to the surface of the substrate, and a magnetic field generated during operation being a magnetic field parallel to the surface of the substrate; the film bulk acoustic resonator chip being vertically stacked on the upper surface of the substrate, the film bulk acoustic resonator chip and the integrated passive device structure being electrically connected by the electrical interconnection structure.

Description

Technical Field

[0001] This disclosure relates to a chip. More specifically, it relates to a highly integrated, low-loss hybrid FBAR chip based on a glass through-hole process. Background Technology

[0002] In the field of 5G communication technology, high-speed and clean signal transmission is one of the core requirements, which places stringent demands on filters, a key component of communication systems. With increasingly scarce spectrum resources and ever-increasing data transmission volumes, filters that simultaneously possess wide passband characteristics and high selectivity are becoming increasingly important.

[0003] The existing structure of hybrid thin-film bulk acoustic wave filters (hybrid FBAR filters) typically includes a thin-film bulk acoustic wave resonator (FBAR resonator) and other types of lumped element resonators (such as LC resonators or microstrip lines). See also... Figure 1 , Figure 1 This diagram illustrates the performance distribution of components in a hybrid thin-film bulk acoustic filter in the prior art. (Example:) Figure 1 As shown, the existing hybrid thin-film bulk acoustic filter structure can combine the high selectivity of FBAR filters and the large bandwidth matching advantage of lumped element resonators to meet the performance requirements of hybrid thin-film bulk acoustic filters in terms of both wide passband characteristics and high selectivity.

[0004] Please see Figure 2 , Figure 2 This diagram illustrates a package structure of a hybrid FBAR filter in the prior art. Because... Figure 2 The lumped element resonator 2000 in the hybrid FBAR filter is implemented using a conventional integrated passive device (IPD) process. Therefore, the integrated passive device chip (IPD chip) can be directly used as the substrate 1000, and then the FBAR chip 3000 is flip-chip mounted on it, with the two connected via an interconnect structure 4000. However, Figure 2 The packaging method used in this process can easily lead to strong coupling between the metal on the IPD chip and the metal on the FBAR chip, resulting in uncontrollable parasitic responses. Meanwhile... Figure 2 Whether the grounding in the IPD chip is implemented through a back-gold process or by setting a metal layer on the top layer of the IPD chip as grounding, it is easy to cause technical problems that reduce the performance of the IPD, and thus affect the performance of the hybrid FBAR filter.

[0005] Please see Figure 3 , Figure 3 This diagram illustrates another packaging structure for hybrid FBAR filters in the prior art. (Example:) Figure 3 As shown, in order to overcome Figure 2The performance degradation of hybrid FBAR filters caused by the in-package structure has been addressed in existing technologies by placing the IPD chip and FBAR chip side-by-side and then packaging them on an additional substrate. However... Figure 3 In the packaging structure of the hybrid FBAR filter shown, the FBAR chip is responsible for the high selectivity of the device, the integrated passive device (IPD) chip is responsible for the broadband impedance matching of the device, and the substrate is responsible for the packaging of the device. Therefore, this allocation of responsibilities leads to the excessive size of the hybrid FBAR chip after packaging, and also results in excessively long interconnects between chips.

[0006] Please see Figure 4 , Figure 4 Show Figure 3 A schematic diagram of an interconnection in a mid-package structure. (By...) Figure 4 It can be known Figure 3 The relatively long interconnects on the substrate of the medium-sized package structure mean that the equivalent inductance of the substrate traces cannot be ignored. On the one hand, this will cause a shift in the resonant frequency of the lumped element resonator or generate an additional resonant point NP2. On the other hand, in order to ensure that the final total inductance remains constant, the inductance value of the IPD chip must be appropriately reduced to compensate for the equivalent inductance of the substrate traces. This requires allocating a portion of the high-Q inductance to the low-Q equivalent inductance, which will inevitably increase the overall loss of the filter. Therefore, the industry desires a hybrid FBAR filter packaging structure that reduces parasitic coupling, reduces size and overall loss, and improves yield. Summary of the Invention

[0007] This disclosure addresses the aforementioned technical problems by proposing a hybrid FBAR filter packaging structure to reduce parasitic coupling, decrease size and overall loss, and improve yield. A brief overview of this disclosure will be given below to provide a basic understanding of certain aspects of it. It should be understood that this overview is not an exhaustive summary of this disclosure. It is not intended to identify key or essential parts of this disclosure, nor is it intended to limit the scope of this disclosure. Its purpose is merely to present certain concepts in a simplified form as a prelude to the more detailed description that follows.

[0008] One aspect of this disclosure provides a hybrid FBAR chip, comprising: a substrate, a thin-film bulk acoustic wave resonator chip, an electrical interconnect structure, and an integrated passive device structure; the integrated passive device includes at least a first helical inductor formed in the substrate, the first helical inductor being helically wound perpendicular to the surface of the substrate, and the magnetic field generated during operation being a magnetic field parallel to the surface of the substrate; the thin-film bulk acoustic wave resonator chip is vertically stacked on the upper surface of the substrate, and the thin-film bulk acoustic wave resonator chip and the integrated passive device structure are electrically connected through the electrical interconnect structure.

[0009] Furthermore, the structure of the first spiral inductor includes a through-hole filled with metal material penetrating the substrate, a metal interconnect structure on the upper surface of the substrate at the first end of the through-hole, and a metal interconnect structure on the lower surface of the substrate at the second end of the through-hole.

[0010] Furthermore, the inductors in the hybrid FBAR chip are all composed of first spiral inductors.

[0011] Furthermore, the upper and lower surfaces of the substrate have a metal interconnect structure that serves as a movable tap for the first helical inductor.

[0012] Furthermore, the integrated passive device also includes a second spiral inductor, which is horizontally spirally wound parallel to the substrate surface and generates a magnetic field perpendicular to the substrate surface during operation.

[0013] Furthermore, the second spiral inductor is primarily used to provide an inductance value between 0 and 9 nH.

[0014] Furthermore, the integrated passive device also includes a MIM capacitor.

[0015] Furthermore, the MIM capacitor is integrated on a thin-film bulk acoustic resonator chip.

[0016] Furthermore, the MIM capacitor is integrated on the substrate.

[0017] Another aspect of this disclosure provides an electronic device including the aforementioned hybrid FBAR chip. Attached Figure Description

[0018] The specific details of this disclosure are described below with reference to the accompanying drawings, which will facilitate a more readily understanding of the above and other objects, features, and advantages of this disclosure. The drawings are merely for illustrating the principles of this disclosure. The dimensions and relative positions of the elements are not necessarily drawn to scale in the drawings.

[0019] Figure 1 This diagram illustrates the performance distribution of components in a hybrid thin-film bulk acoustic filter in the prior art. Figure 2 This diagram illustrates a package structure of a hybrid FBAR circuit in the prior art. Figure 3 A schematic diagram of another package structure for hybrid FBAR circuits in the prior art is shown; Figure 4 Show Figure 3 A schematic diagram of an interconnection in a mid-package structure; Figure 5 This illustration shows a specific circuit structure of the hybrid FBAR filter provided in this disclosure; Figure 6 This disclosure provides Figure 5 A three-dimensional schematic diagram of the package structure of a hybrid FBAR filter circuit; Figure 7 This disclosure provides Figure 5 A cross-sectional schematic diagram of the package structure of a hybrid FBAR filter circuit; Figure 8 This is a schematic diagram of the structure of the first spiral inductor 201; Figure 9 The Q-value comparison of the first spiral inductor and the second spiral inductor is shown; Figure 10 This diagram illustrates the structure of the thin-film bulk acoustic resonator in the FBAR chip. Figure 11 The packaging structure of the hybrid FBAR filter chip provided in this disclosure is similar to Figure 3 The performance comparison chart of the hybrid FBAR filter chip package provided in the figure; Figure 12 The diagram shows a cross-sectional view of the IPD chip with a metal ground on the back side of the substrate in a hybrid FBAR chip with stacked packaging. Figure 13 This diagram shows a cross-sectional view of the IPD chip with a metal ground on the front side of the substrate in a stacked hybrid FBAR chip. Figure 14 A schematic diagram of the structure of MIM capacitors integrated into an FBAR chip is given. Detailed Implementation

[0020] Exemplary disclosures of this disclosure will be described below with reference to the accompanying drawings. For clarity and brevity, not all features implementing this disclosure are described in the specification. However, it should be understood that many disclosure-specific decisions can be made in developing any such implementation of this disclosure to achieve the developer’s specific goals, and these decisions may vary depending on the specific disclosure.

[0021] It should also be noted that, in order to avoid obscuring this disclosure with unnecessary details, only the device structure closely related to the scheme according to this disclosure is shown in the accompanying drawings, while other details that are not closely related to this disclosure are omitted.

[0022] It should be understood that this disclosure is not limited to the described embodiments by virtue of the following description with reference to the accompanying drawings. In this disclosure, features may be substituted or borrowed between different embodiments where feasible, and one or more features may be omitted in one embodiment.

[0023] Please see Figure 5 , Figure 5 This illustration shows a specific circuit structure of the hybrid FBAR filter provided in this disclosure. Regarding... Figure 5 For an explanation of the circuit structure principle of the hybrid FBAR filter, please refer to the description in the applicant's patent application CN202411206345.2, and the relevant information is incorporated into the content of this disclosure.

[0024] like Figure 5 As shown, the filter includes a signal input terminal 100, a signal output terminal 200, and a filter network. The filter network is disposed between the signal input terminal 100 and the signal output terminal 200. The filter network includes a series branch NS1, a series branch NS2, a series branch NS3, and a series branch NS4 connected in sequence. A parallel branch NP1 is disposed between the node of the series branches NS1 and NS2 and ground. A parallel branch NP2 is disposed between the node of the series branches NS2 and NS3 and ground. A parallel branch NP3 is disposed between the node of the series branches NS3 and NS4 and ground.

[0025] Series branches NS1 and NS4 include resonant units composed of capacitors and inductors; series branches NS2 and NS3 include resonator networks composed of FBARs; parallel branches NP1 and NP3 include resonant units composed of FBARs and inductors; and parallel branch NP2 includes resonant units composed of capacitors and inductors.

[0026] The resonant unit in the series branch NS1 consists of capacitor C. 3_1 and inductor L 3_1 The series connection is used to construct the resonator network in the series branch NS2, which consists of a thin-film bulk acoustic resonator S. 1_1 Thin-film bulk acoustic resonator S 1_2 and thin-film bulk acoustic resonator S 1_3 The series connection is used to construct the resonator network in the series branch NS3, which consists of a thin-film bulk acoustic resonator S. 2_1 Thin-film bulk acoustic resonator S 2_2 Thin-film bulk acoustic resonator S 2_3 The series connection is used, and the resonant unit in the series branch NS4 is composed of inductor L. 3_2 and capacitor C 3_2 It is connected in series.

[0027] The resonant unit in the parallel branch NP1 consists of a thin-film bulk acoustic resonator P. 1_1 Thin-film bulk acoustic resonator P 1_2 Thin-film bulk acoustic resonator P 1_3 and capacitive inductor L 1_1 It is connected in series. The resonant unit of the parallel branch NP2 consists of capacitor C. 2_1 and inductor L 2_1Then connected in series with capacitor C 2_2 Parallel configuration. The resonant unit of the parallel branch NP3 consists of a thin-film bulk acoustic resonator P. 2_1 Thin-film bulk acoustic resonator P 2_2 Thin-film bulk acoustic resonator P 2_3 and capacitive inductor L 1_2 It is connected in series.

[0028] Figure 5 In the filter circuit structure, the inductor L in the series branch NS4 3_2 and capacitor C 3_2 Capacitor C in parallel branch NP2 is used to adjust the matching assignment of the upper and lower halves of the filter passband. 2_1 and inductor L 2_1 The series connection to ground is used to provide a low-frequency zero, and an additional capacitor C is connected in the parallel branch NP2. 2_2 Grounding can provide a pole at zero-frequency, adjusting the capacitor C in the second parallel branch. 2_1 and inductor L 2_1 Changing the zero-point resonance can affect the pole frequency. In other words, Figure 5 The filter circuit structure can provide in-band poles to support bandwidth and zeros to deepen out-of-band rejection by designing a high degree of freedom LC resonator, thus realizing a "hybrid FBAR circuit".

[0029] Please see Figure 6-8 ,in Figure 6 This disclosure provides Figure 5 A three-dimensional schematic diagram of the package structure of a hybrid FBAR filter circuit; Figure 7 This disclosure provides Figure 5 A cross-sectional schematic diagram of the package structure of a hybrid FBAR filter circuit. Figure 6-7 As can be seen, the packaging structure of the hybrid FBAR filter circuit provided in this disclosure mainly includes a glass substrate 100, an integrated passive device (IPD) structure 200, a thin-film bulk acoustic resonator (FBAR) chip 300, an electrical interconnection structure 400, and a packaging layer 500.

[0030] The integrated passive device (IPD) structure 200 can be fabricated inside or on the surface of the glass substrate using thin-film deposition, photolithography, and etching processes. A thin-film bulk acoustic resonator (FBAR) chip 300 is vertically stacked on the upper surface of the glass substrate 100. Electrical interconnect structures 400 can be formed on both the upper and lower surfaces of the glass substrate 100. The electrical interconnect structure on the upper surface is used to realize the electrical connection between the FBAR chip and the IPD device. The electrical interconnect structure on the lower surface is used to realize the electrical connection between the IPD device and other functional modules.

[0031] The glass substrate can be made of a high-resistivity, low-dielectric-loss glass material. For example, the resistivity can be greater than 1 kΩ·cm, the dielectric constant can be 3.0-5.0, the dielectric loss tangent can be less than or equal to 0.001, the thickness can be 200-300 micrometers, and the flatness error of the glass substrate can be less than or equal to 5 micrometers to ensure low loss in high-frequency signal transmission and stability of chip stacking. Multiple vias (TGVs) are formed in the glass substrate through a glass via process. The vias penetrate the upper and lower surfaces of the glass and are filled with metal, such as copper. It should be understood that some of the vias in the glass substrate are used to form the first helical inductor 201 in the integrated passive device (IPD) structure 200, and other vias are used as electrical interconnects for electrical conduction.

[0032] The integrated passive device (IPD) structure 200 includes a first spiral inductor 201, a second spiral inductor 202, a MIM capacitor, and interconnect wiring.

[0033] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of the first spiral inductor 201. Figure 8 As can be seen from the diagram, the first helical inductor has a vertically wound helical structure. During operation, it generates a magnetic field parallel to the surface of the glass substrate, i.e., a horizontally arranged magnetic field, forming a structure as shown in the diagram. Figure 8 The diagram shows a top trace-TGV-bottom trace structure. Specifically, the first spiral inductor 201 includes metal interconnect structures on the upper and lower surfaces of the glass substrate and a glass via filled with metal material penetrating the glass substrate. Its winding direction is perpendicular to the surface of the glass substrate. The metal material can fill the glass via (TGV) completely, or it can be formed on the sidewalls of the glass via (TGV).

[0034] The second spiral inductor has a horizontally spiral wound structure, and the magnetic field it generates during operation is vertically arranged. Its windings are laid horizontally in a spiral shape on or within the glass substrate, with the winding direction parallel to the glass substrate surface. The second spiral inductor is mainly used to provide inductance values ​​between 0 and 9 nH.

[0035] Please see Figure 9 , Figure 9 The Q-value comparison of the first spiral inductor and the second spiral inductor is shown. Figure 9 Curve 1 represents the frequency-Q value curve of the first spiral inductor, and curve 2 represents the frequency-Q value curve of the second spiral inductor. Figure 9 It can be clearly observed that the first spiral inductor has a higher Q value than the second spiral inductor. For example, the Q value of the first spiral inductor at 4.7 GHz is 68, while the Q value of the second spiral inductor at 4.7 GHz is 34.

[0036] Furthermore, it can be understood that the second spiral inductor 202 is not necessarily included in the integrated passive device structure 200. That is, the inductor form in all integrated passive devices can be set as the first spiral inductor 201. A metal interconnect structure can be further formed between the upper and lower surfaces of the glass substrate as a movable tap to flexibly adjust the inductance design value. In this case, lower insertion loss can be obtained in the same circuit as shown in the figure.

[0037] Furthermore, it can be understood that when Figure 5 When the inductor design values ​​in each branch of the hybrid FBAR filter circuit structure cannot form a complete single first spiral inductor 201, for example, when the glass substrate is 230 micrometers thick, the inductance size of one turn of the first spiral inductor 201 can be 230 micrometers × 200 nanometers, corresponding to an inductance value of approximately 0.374H. When the inductor design values ​​in each branch cannot form an integer number of turns of the first spiral inductor 201, a second spiral inductor 202 can be introduced as an auxiliary inductor to accurately realize the design values ​​of each inductor. In addition, the second spiral inductor 202, placed on the upper and lower surfaces of the glass substrate, also helps to further reduce the size. Together with the first spiral inductor, the hybrid FBAR chip can simultaneously achieve both low loss and high integration.

[0038] A micromolecular-weighted inductively coupled (MIM) capacitor is formed on the surface of a glass substrate and includes an upper electrode, a central dielectric layer, and a lower electrode. The central dielectric layer is made of a material with a high dielectric constant; for example, the central dielectric layer of the MIM capacitor uses a material with a dielectric constant greater than or equal to 6.78. The central dielectric layer can be made of silicon nitride (SiN). Furthermore, in the fabrication of the MIM capacitor, both the upper and lower electrodes can employ multilayer metal structures. The resistivity of each metal structure in the multilayer metal structure can be lower than 50 μΩ·cm to ensure low electrode loss. The thickness of each metal structure should not be less than the skin depth, which would result in excessive resistance of the metal layer. The skin depth refers to the effective thickness of the transmission path in the skin effect. In addition, the surface roughness of the metal structures in the upper and lower electrodes can be lower than 1 nm to ensure the uniformity of the central dielectric layer of the MIM capacitor and prevent localized electric field concentration breakdown. More preferably, the surface roughness of each metal structure should be lower than 0.5 nm to ensure the uniformity of the ultrathin dielectric layer. The materials for the metal structures can be selected from titanium (Ti), aluminum (Al), etc.

[0039] join Figure 10 , Figure 10This diagram illustrates the structure of a thin-film bulk acoustic wave resonator (FBAR) in an FBAR chip. The FBAR chip includes an FBAR chip substrate 3100 and a thin-film bulk acoustic wave resonator structure formed thereon. The FBAR chip substrate 3100 can be made of semiconductor-compatible materials such as silicon, gallium arsenide, indium phosphide, glass, sapphire, alumina, or SiC. The FBAR chip substrate primarily serves a supporting function.

[0040] The thin-film bulk acoustic resonator structure includes an acoustic wave reflecting structure 3101, an FBAR resonator lower electrode 3201 stacked on the acoustic wave reflecting structure 3101, a piezoelectric layer 3202 formed on the resonator lower electrode 3201, a resonator upper electrode 3203 formed on the piezoelectric layer 3202, and a passivation layer, etc.

[0041] Furthermore, the acoustic wave reflecting structure 3101 may be constituted by a first air cavity. Alternatively, the acoustic wave reflecting structure 3101 may be constituted by filling the first air cavity with, for example, a stack of thin films of different acoustic impedances with a thickness of 1 / 4 wavelength. The shape of the lower electrode 3201 of the resonator can be arbitrary, such as a regular polygon like a triangle, rectangle, pentagon, hexagon, or octagon. Those skilled in the art should also understand that a seed layer may be further provided between the lower electrode 3201 and the substrate. The thickness of the lower electrode 3201 can be set according to specific device requirements; for example, the thickness of the lower electrode layer can be set to 300 nm.

[0042] The piezoelectric layer 3202 can be formed from any piezoelectric material compatible with semiconductor processes, such as aluminum nitride, doped aluminum nitride, or zirconate titanate. Its thickness can be set according to specific device requirements; for example, the thickness of the piezoelectric layer 3202 can be set to 300 nm.

[0043] The materials of the upper electrode 3203 and the lower electrode 3201 of the resonator can be the same or different. The shape of the upper electrode 3203 can be arbitrary; it can be an irregular or regular shape, such as a triangle, rectangle, pentagon, hexagon, octagon, or other regular polygon. The thickness of the upper electrode 3203 is set according to the specific device requirements; for example, its thickness can be set between 119-235 nm.

[0044] The passivation layer can be made of insulating materials such as silicon nitride, and its thickness can be, for example, 100 nm.

[0045] The hybrid FBAR chip disclosed in this invention features FBAR chips stacked on a glass substrate, with IPD devices formed within the glass substrate. This solves the problem of excessively large size of the packaged hybrid FBAR chip, avoids excessively long interconnects between chips, and reduces the overall filter loss. For example, the hybrid FBAR chip disclosed in this invention can have a height of 668 micrometers, a width of 1168 micrometers, and a length of 1590 micrometers. Figure 3-4 A comparison of the packaging method in the present invention with the packaging method in the present invention shows that, compared to the packaging method in the present invention, the packaging method in the present invention is superior. Figure 3-4 The total length of the connecting lines in the chip is measured by testing. It is known that the hybrid FBAR chip disclosed in this invention can reduce the total length of the connecting lines from about 800 micrometers to less than 150 micrometers by vertical stacking.

[0046] Please see Figure 11 , Figure 11 The packaging structure of the hybrid FBAR filter chip provided in this disclosure is similar to Figure 3 The performance comparison chart of the hybrid FBAR filter chip package provided in the image is shown. Figure 11 Curve 1 is Figure 3 Curve 2 shows the return loss S11 of the hybrid FBAR filter chip package structure; curve 2 is... Figure 3 Curve 3 is the insertion loss S21 curve of the hybrid FBAR filter chip package structure provided in this disclosure; Curve 4 is the return loss S11 curve of the hybrid FBAR filter chip package structure provided in this disclosure. Figure 11 It can be clearly seen that the hybrid FBAR filter chip provided in this disclosure has a minimum insertion loss of 1.35 dB and a passband return loss of less than 13 dB, which is far superior to the performance of the hybrid FBAR filter chip provided in Figure 3. Furthermore, the hybrid FBAR filter chip provided in this disclosure requires no additional inductor layout and has almost no parasitic response; its performance does not degrade even with a significant reduction in chip size.

[0047] Please see Figure 12-13 , Figure 12 The diagram shows a cross-sectional view of the IPD chip in the stacked hybrid FBAR chip, with a metal ground on the back of the substrate. Figure 13 This diagram shows a cross-sectional view of the IPD chip in a stacked hybrid FBAR chip, with a metal ground plane on the front side of the substrate. Figure 12-13 A comparative test was conducted between the package form in the comparative example and the package form of this disclosure. It was found that the inductor in the IPD chip of the hybrid FBAR chip in the comparative example did not use a vertically wound helical inductor. Figure 12-13It can be seen that the connection method of the hybrid FBAR chip is "interconnection structure - horizontal spiral trace - interconnection structure".

[0048] and Figure 3-4 Compared to the packaging structure of the hybrid FBAR filter chip in this disclosure, the present disclosure and Figure 12-13 The stacked packaging methods in the comparative examples can all reduce Figure 3 The total length of the connection lines when the FBAR chip and IPD chip are placed side by side is reduced, overcoming the problem of excessive size. However, Figure 12 The stacked packaging method in the IPD chip involves grounding the chip via a via to the back metal. Since the inductor in the IPD chip is wound in a horizontal spiral pattern, strong coupling occurs between the back metal and the horizontal coil of the inductor in the IPD chip. This causes some energy to be directly coupled to GND, resulting in a decrease in the inductor's Q value. Figure 13 The stacked packaging method in the IPD chip involves grounding the chip via a via connected to a ring of metal on the front side of the chip. Furthermore, the inductor in the IPD chip is wound in a horizontal spiral configuration. Testing revealed that this grounding method, combined with the horizontal spiral inductor, negatively impacts the performance of the hybrid FBAR filter chip. Figure 13 The packaging method used in this design can easily generate parasitic capacitance between the metal layers of the two chips. Therefore, if the inductor in the IPD chip of a hybrid FBAR filter chip is implemented using only a horizontal spiral winding method, it is prone to interacting with other metal layers, leading to significant and difficult-to-control parasitic coupling in the hybrid FBAR filter chip.

[0049] Because a first helical inductor is introduced into the IPD device in this disclosure, the magnetic field it generates is mainly horizontally distributed, which reduces the coupling with the metal interconnect structure on the glass substrate used as a ground plane, improves the Q value of the inductor, and reduces the parasitic coupling between the FBAR chip and the IPD device.

[0050] In a modified embodiment provided in this disclosure, it is possible to Figure 7 The MIM capacitors in this chip are integrated onto the substrate of the FBAR chip, rather than being disposed on the upper or lower surface of the glass substrate. See also... Figure 14 , Figure 14 A schematic diagram of the structure of MIM capacitors integrated into an FBAR chip is given. Figure 14As shown, the FBAR chip includes a substrate 3100, in which an acoustic wave reflecting structure 3101, such as a cavity, is formed. A lower electrode 3201, a piezoelectric layer 3202, and an upper electrode 3203 of a thin-film bulk acoustic wave resonator are stacked on the substrate 3100. The MIM capacitor 3300 includes a lower electrode layer, a dielectric layer 3302, and an upper electrode layer. The lower electrode layer can be formed by stacking multiple metal layers. For example, the lower electrode layer includes a first lower electrode metal layer 3301-1, a second lower electrode metal layer 3301-2, and a third lower electrode metal layer 3301-3. The upper electrode layer includes a first upper electrode metal layer 3303-1, a second upper electrode metal layer 3303-2, and a third upper electrode metal layer 3303-3. The MIM capacitor 3300 and the thin-film bulk acoustic wave resonator 3200 are arranged side by side on the FBAR chip. The specific materials and parameter settings of the thin-film bulk acoustic wave resonator 3200 and the MIM capacitor 3300 are the same as those described in the previous embodiments, and will not be repeated here.

[0051] The highly integrated, low-loss hybrid FBAR chip disclosed herein can be widely used in electronic devices, with communication devices exemplified as mobile phones, personal digital assistants, video game devices, wearable terminals, etc.

[0052] The present disclosure has been described above with reference to specific implementation schemes. However, those skilled in the art should understand that these descriptions are exemplary and not intended to limit the scope of protection of the present disclosure. Those skilled in the art can make various modifications and variations to the present disclosure based on its spirit and principles, and such modifications and variations are also within the scope of the present disclosure.

Claims

1. A hybrid FBAR chip, characterized in that, include: Glass substrate, thin-film bulk acoustic resonator chip, electrical interconnect structure and integrated passive device structure; The integrated passive device includes at least a first helical inductor formed in the substrate, the first helical inductor being helically wound perpendicular to the surface of the substrate, and the magnetic field generated during operation being a magnetic field parallel to the surface of the substrate; The thin-film bulk acoustic wave resonator chip is vertically stacked on the upper surface of the substrate, and the thin-film bulk acoustic wave resonator chip and the integrated passive device structure are electrically connected through the electrical interconnection structure.

2. The hybrid FBAR chip as described in claim 1, characterized in that: The structure of the first spiral inductor includes a through-hole filled with metal material penetrating the substrate, a metal interconnect structure on the upper surface of the substrate at the first end of the through-hole, and a metal interconnect structure on the lower surface of the substrate at the second end of the through-hole.

3. The hybrid FBAR chip as described in claim 2, characterized in that: The inductors in the hybrid FBAR chip are all composed of first spiral inductors.

4. The hybrid FBAR chip as described in claim 3, characterized in that: The substrate further has a metal interconnect structure between its upper and lower surfaces, which serves as a movable tap for the first helical inductor.

5. The hybrid FBAR chip as described in claim 1 or 2, characterized in that: The integrated passive device also includes a second spiral inductor, which is horizontally spirally wound parallel to the substrate surface and generates a magnetic field perpendicular to the substrate surface during operation.

6. The hybrid FBAR chip as described in claim 5, characterized in that: The second spiral inductor is mainly used to provide an inductance value between 0 and 9 nH.

7. The hybrid FBAR chip as described in any one of claims 1-6, characterized in that: The integrated passive device also includes a MIM capacitor.

8. The hybrid FBAR chip as described in claim 7, characterized in that: The MIM capacitor is integrated on a thin-film bulk acoustic resonator chip.

9. The hybrid FBAR chip as described in claim 7, characterized in that: The MIM capacitor is integrated on the substrate.

10. An electronic device, characterized in that: Includes the hybrid FBAR chip according to any one of claims 1-9.

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