A high-speed down-sampling FIR filter and a control method thereof

Abstract

The application provides a high-speed downsampling FIR filter and a control method thereof. The high-speed downsampling FIR filter comprises a clock generation module and a data processing module. The clock generation module generates a multiphase sampling clock, a synchronization clock and an output clock by using an input clock. The data processing module converts input data into a serial-parallel form, aligns the data, delays the data by different degrees according to different orders of sub-filters, distributes the delayed data to M parallel sub-filters, and integrates output downsampling filter results by the M sub-filters. The high-speed downsampling FIR filter provided by the application improves the working speed of the downsampling FIR filter when the downsampling FIR filter is implemented in an integrated circuit by combining a multipath parallel mode with a multiphase data processing mode. The filter rate is high when the filter integrates and filters by multiple sub-filters simultaneously.

Description

Technical Field

[0001] This invention relates to the field of digital integrated circuit design technology, and in particular to a high-speed downsampling FIR filter and its control method. Background Technology

[0002] As integrated circuit technology enters the submicron stage, data channels are widely used in various digital and mixed-signal circuits. The continuous increase in the speed of electronic devices necessitates ever-increasing operating frequencies of these data channels, while semiconductor processes themselves have speed limits. Under this constraint, the design of downsampling digital filters, especially the widely used downsampling FIR (Finite Impulse Response) filters, faces significant challenges. How to further increase the operating frequency of downsampling FIR filters under existing process conditions, bringing them close to or even exceeding the limits of traditional processes, has become a pressing technical problem in this field.

[0003] Common implementations of downsampling FIR filters include direct, polyphase decomposition, and pipelined types, but each has certain limitations. In the direct type, all multiply-accumulate operations are performed at the highest input rate. The critical path lengthens with the number of taps, limiting the operating frequency and failing to utilize the rate advantage brought by downsampling, resulting in poor performance in ultra-high-speed scenarios. While the polyphase decomposition type can reduce the operation rate of a single branch, the number of parallel branches increases with the decimation ratio, significantly increasing hardware size and wiring complexity. Designing high-order cross-branch pipelines is difficult, limiting the actual operating frequency. The pipelined type improves timing by inserting registers, but does not reduce the full-rate operation pressure, while increasing circuit delay and control complexity, lacking targeted speed optimization for downsampling. Summary of the Invention

[0004] This invention provides a high-speed downsampling FIR filter and its control method to solve the technical problems of complex hardware design, limited operating frequency, and low sampling rate in the above-mentioned downsampling FIR filters.

[0005] In a first aspect, the present invention provides a high-speed downsampling FIR filter, comprising: A clock generation module is used to generate an L-phase sampling clock, a synchronization clock, and an output clock based on an input clock, wherein the frequency of the sampling clock is 1 / L of the frequency of the input clock; The data processing module, connected to the clock generation module, is used to perform parallel sampling of the input data using the L-phase sampling clock to obtain L-phase parallel sampled data; under the trigger of the synchronization clock, the L-phase parallel sampled data is aligned to obtain L-phase intermediate synchronization data; and under the trigger of the output clock, different delay processing is applied to the L-phase intermediate synchronization data respectively, and the delayed data after delay processing is distributed to M parallel sub-filters to integrate the output downsampling filtering results through the M sub-filters. Where M and L are positive integers, M≥2, L≥2.

[0006] In one embodiment of the present invention, the clock generation module includes a frequency division unit, a gating signal generation unit, and a multi-phase clock generation unit. The frequency division unit performs frequency division processing on the input clock to obtain the output clock. The gating signal generation unit, triggered by the input clock, performs logical processing on the output clock to obtain multiple gating signals. The multi-phase clock generation unit, triggered by the input clock, performs output control on the multiple gating signals to generate the L-phase sampling clock. The synchronization clock is one phase of the L-phase sampling clock, or the synchronization clock is generated by the multi-phase clock generation unit based on the gating signals and the input clock.

[0007] In one embodiment of the present invention, the gated signal generation unit includes a frequency divider, a first D flip-flop, a first NOT gate, a first AND gate, a buffer, L second D flip-flops, L first OR gates, and L-1 second NOT gates. The output of the frequency divider is connected to the data input of the first D flip-flops. The output of the frequency divider is also connected to the first input of the first AND gate. The data output of the first D flip-flops is connected to the second input of the first AND gate after passing through the first NOT gate. The output of the first AND gate is connected to the input of the buffer. The output of the buffer is connected to the first input of the first first OR gate. The second input of the first first OR gate is connected to the data output of the Lth second D flip-flop. The output of the first first OR gate is connected to the data output of the first second D flip-flop. The data input terminals are as follows: the input terminals of L-1 second NOT gates are all connected to the output terminal of the first AND gate; the first input terminal of the (i+1)th first OR gate is connected to the output terminal of the ith second NOT gate; the second input terminal of the (i+1)th first OR gate is connected to the data output terminal of the ith second D flip-flop; and the output terminal of the (i+1)th first OR gate is connected to the data input terminal of the (i+1)th second D flip-flop. The input terminal of the frequency divider is the input terminal of the gate signal generation unit; the clock input terminals of the first D flip-flop and the second D flip-flop are the clock trigger terminals of the gate signal generation unit; and the data output terminals of L second D flip-flops are the output terminals of the gate signal generation unit. Here, i is a positive integer, 1 ≤ i ≤ L.

[0008] In one embodiment of the present invention, the multiphase clock generation unit includes L third D flip-flops and L second AND gates. The data output terminal of the i-th third D flip-flop is connected to the first input terminal of the i-th second AND gate, and the clock input terminal of the i-th third D flip-flop is connected to the second input terminal of the i-th second AND gate. The data input terminal of the third D flip-flop is the data input terminal of the multiphase clock generation unit, the clock input terminal of the third D flip-flop is the clock trigger terminal of the multiphase clock generation unit, and the output terminal of the second AND gate is the output terminal of the multiphase clock generation unit.

[0009] In one embodiment of the present invention, the data processing module includes a multi-phase data generation unit, a data synchronization unit, a data delay unit, a switching matrix unit, and M sub-filters. The multi-phase data generation unit is connected to the multi-phase clock generation unit and, triggered by the L-phase sampling clock, performs serial-to-parallel conversion on the input data to obtain the L-phase parallel sampling data. The data synchronization unit is connected to the multi-phase data generation unit and the multi-phase clock generation unit and, triggered by the synchronization clock, aligns the L-phase parallel sampling data to obtain the L-phase intermediate synchronization data. The data delay unit is connected to the data synchronization unit and the frequency division unit and, triggered by the output clock signal, applies different delay amounts to the L-phase intermediate synchronization data to obtain multiple delayed data. The input terminal of the switching matrix is ​​connected to the data delay unit, and the output terminal of the switching matrix is ​​connected to the M sub-filters. Different delayed data are transmitted to the corresponding sub-filters according to the coefficient characteristics of each sub-filter.

[0010] In one embodiment of the present invention, the multi-phase data generation unit includes L fourth D flip-flops, the data input terminals of the L fourth D flip-flops are connected to the input data, the clock input terminals of the L fourth D flip-flops are respectively connected to the L phase sampling clock, and the data output terminals of the L fourth D flip-flops jointly output the L phase parallel sampling data.

[0011] In one embodiment of the present invention, the data synchronization unit includes L fifth D flip-flops, the data input terminals of the L fifth D flip-flops are respectively connected to the L phases of parallel sampling data, the clock input terminals of the L fifth D flip-flops are connected to the synchronization clock, and the data output terminals of the L fifth D flip-flops jointly output the L phases of intermediate synchronization data.

[0012] In one embodiment of the present invention, the data delay unit is composed of L D flip-flop groups, each D flip-flop group includes R cascaded sixth D flip-flops, the clock input terminal of the sixth D flip-flop is connected to the output clock, the data output terminal of each sixth D flip-flop outputs the delayed data, and the first sixth D flip-flop in each D flip-flop group is connected to the corresponding intermediate synchronization data, where R is a positive integer and R≥2.

[0013] In one embodiment of the present invention, the sub-filter includes N multipliers and a first adder. The first input terminal of the multiplier is connected to the delayed data, the second input terminal of the multiplier is connected to the corresponding multiplication coefficient, the N input terminals of the first adder are connected to the output terminals of the N multipliers, and the output terminal of the first adder is the output terminal of the sub-filter, where N is a positive integer and N≥2.

[0014] Secondly, the present invention also provides a control method for a high-speed downsampling FIR filter, comprising: An L-phase sampling clock, a synchronization clock, and an output clock are generated based on the input clock, wherein the frequency of the sampling clock is 1 / L of the frequency of the input clock; The input data is sampled in parallel using the sampling clock described in phase L to obtain phase L parallel sampling data; Under the trigger of the synchronization clock, the parallel sampling data of phase L is synchronized to obtain intermediate synchronization data of phase L; Under the trigger of the output clock, different delay processing is applied to the intermediate synchronization data of phase L to obtain multiple delay data; The delayed data is distributed to M parallel sub-filters, and the downsampling filtering result is output by integrating the M sub-filters. Where M and L are positive integers, M≥2, L≥2.

[0015] The beneficial effects of this invention are as follows: This invention provides a high-speed downsampling FIR filter and its control method. The high-speed downsampling FIR filter includes a clock generation module and a data processing module. The clock generation module uses an input clock to generate a multi-phase sampling clock, a synchronization clock, and an output clock. The data processing module, triggered by the multi-phase sampling clock, the synchronization clock, and the output clock, performs serial-to-parallel conversion and data alignment on the input data. It also applies different degrees of delay based on the different orders of the sub-filters, distributing the delayed data to M parallel sub-filters, thereby integrating the downsampling filtering result through the M sub-filters. The high-speed downsampling FIR filter provided by this invention improves the operating speed of the downsampling FIR filter in integrated circuit implementation by combining multi-path parallel processing and multi-phase data processing. During filtering, it integrates filtering through multiple sub-filters simultaneously, resulting in a high filtering rate. For different integrated circuit processes, a trade-off between speed and area can be achieved by adjusting the number of channels M during implementation. The downsampling FIR filter provided by this invention has a simple hardware structure, the number of sub-filters can be adjusted according to actual conditions, the operating frequency is not limited, and the sampling rate is high. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] In the attached diagram: Figure 1 This is a block diagram of a high-speed downsampling FIR filter provided in an embodiment of the present invention; Figure 2 This is a block diagram of the clock generation module provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the specific structure of the gate signal generation unit provided in this embodiment of the invention; Figure 4 This is a schematic diagram of the specific structure of the multiphase clock generation unit provided in the embodiment of the present invention; Figure 5 This is a block diagram of the data processing module provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the specific structure of the multiphase data generation unit provided in the embodiment of the present invention; Figure 7 This is a schematic diagram of the specific structure of the data synchronization unit provided in this embodiment of the invention; Figure 8This is a schematic diagram of the specific structure of the data delay unit provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the specific structure of the sub-filter provided in the embodiment of the present invention; Figure 10 This is a schematic timing diagram of a high-speed downsampling FIR filter provided in an embodiment of the present invention.

[0018] Reference numerals: 110 - Clock generation module; 111 - Frequency division unit; 112 - Gating signal generation unit; 113 - Multiphase clock generation unit; 120 - Data processing module; 121 - Multiphase data generation unit; 122 - Data synchronization unit; 123 - Data delay unit; 124 - Switch matrix unit; 1251 - First sub-filter; 1252 - Second sub-filter; 125M - Mth sub-filter. Detailed Implementation

[0019] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0020] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0021] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0022] As integrated circuit technology enters the submicron stage, data channels are widely used in various digital and mixed-signal circuits. The continuous increase in the speed of electronic devices necessitates ever-increasing operating frequencies of these data channels, while semiconductor processes themselves have speed limits. Under this constraint, the design of downsampling digital filters, especially the widely used downsampling FIR (Finite Impulse Response) filters, faces significant challenges. How to further increase the operating frequency of downsampling FIR filters under existing process conditions, bringing them close to or even exceeding the limits of traditional processes, has become a pressing technical problem in this field.

[0023] Common implementations of downsampling FIR filters include direct, polyphase decomposition, and pipelined types, but each has certain limitations. In the direct type, all multiply-accumulate operations are performed at the highest input rate. The critical path lengthens with the number of taps, limiting the operating frequency and failing to utilize the rate advantage brought by downsampling, resulting in poor performance in ultra-high-speed scenarios. While the polyphase decomposition type can reduce the operation rate of a single branch, the number of parallel branches increases with the decimation ratio, significantly increasing hardware size and wiring complexity. Designing high-order cross-branch pipelines is difficult, limiting the actual operating frequency. The pipelined type improves timing by inserting registers, but does not reduce the full-rate operation pressure, while increasing circuit delay and control complexity, lacking targeted speed optimization for downsampling.

[0024] To solve the above problems, such as Figure 1 As shown, the present invention provides a high-speed downsampling FIR filter, comprising: Clock generation module 110 is used to generate L-phase sampling clocks (clk_ph0~clk_ph) based on the input clock clkin. L-1 ), synchronization clock clk_sync, and output clock clk_out, where each sampling clock (clk_ph0~clk_ph) L-1 The frequency of ) is 1 / L of the frequency of the input clock clkin; Data processing module 120, connected to clock generation module 110, is used to utilize the L-phase sampling clock (clk_ph0~clk_ph) L-1 The input data din is sampled in parallel to obtain L-phase parallel sampled data; under the trigger of the synchronization clock clk_sync, the L-phase parallel sampled data is aligned to obtain L-phase intermediate synchronization data; and under the trigger of the output clock clk_out, different delay processing is applied to the L-phase intermediate synchronization data, and the delayed data after delay processing is distributed to M parallel sub-filters to integrate the output downsampling filtering result Yout through the M sub-filters; where M and L are positive integers, M≥2, L≥2.

[0025] It is important to emphasize that, for different integrated circuit processes, a trade-off between speed and area can be achieved by adjusting the number of channels M during implementation. When the process speed is low, but the high-speed downsampling FIR filter operates at a high speed, the number of channels M can be increased to achieve high-speed operation; when the process speed is high, the number of channels M can be decreased to achieve a smaller chip area.

[0026] More in detail, such as Figure 2 As shown, the clock generation module 110 includes a frequency divider unit 111, a gate signal generation unit 112, and a multiphase clock generation unit 113. The frequency divider unit 111 divides the input clock clkin to obtain the output clock clk_out. The gate signal generation unit 112, triggered by the input clock clkin, performs logical processing on the output clock clk_out to obtain multiple gate signals ctrl0~ctrl0. L-1 The multiphase clock generation unit 113, triggered by the input clock clkin, controls multiple gate signals ctrl0~ctrl. L-1 Perform output control to generate the L-phase sampling clock (clk_ph0~clk_ph) L-1 The synchronization clock clk_sync is the L-phase sampling clock (clk_ph0~clk_ph). L-1 One phase of the clock, or the synchronous clock clk_sync, is generated by the multi-phase clock generation unit 113 based on the gate signals ctrl0~ctrl. L-1 The input clock clkin is generated. The synchronous clock clk_sync is generated in the same way as the L-phase sampling clock (clk_ph0~clk_ph). L-1 The generation method is the same, and you can also choose the L-phase sampling clock (clk_ph0~clk_ph). L-1 One phase of the clock is used as the synchronization clock clk_sync.

[0027] More in detail, such as Figure 3As shown, the gated signal generation unit 112 includes a frequency divider DIV, a first D flip-flop D11, a first NOT gate NOT11, a first AND gate AND11, a buffer buff, L second D flip-flops (D21~D2L), L first OR gates (OR11~OR1L), and L-1 second NOT gates (NOT21~NOT2(L-1)). The output of the frequency divider DIV is connected to the data input of the first D flip-flop D11, and the output of the frequency divider DIV is also connected to the first input of the first AND gate AND11. The first D flip-flop D11... The data output of gate 1 is connected to the second input of the first AND gate 11 after passing through the first NOT gate (NOT11). The output of the first AND gate 11 is connected to the input of the buffer (buff). The output of the buffer (buff) is connected to the first input of the first OR gate (OR11). The second input of the first OR gate (OR11) is connected to the data output of the Lth second D flip-flop (D2L). The output of the first OR gate (OR11) is connected to the data input of the first second D flip-flop (D21). L-1 second NOT gates (NOT21~NOT2(L-1)) are used. The input terminals of each of the following are connected to the output terminals of the first AND gate AND11. The first input terminal of the (i+1)th first OR gate OR1(i+1) is connected to the output terminal of the ith second NOT gate NOT2i. The second input terminal of the (i+1)th first OR gate OR1(i+1) is connected to the data output terminal of the ith second D flip-flop D2i. The output terminal of the (i+1)th first OR gate OR1(i+1) is connected to the data input terminal of the (i+1)th second D flip-flop D2(i+1). The input terminal of the frequency divider DIV is the input terminal of the gate signal generation unit 112. The input terminal of the gate signal generation unit 112 is connected to the output clock clk_out. The clock input terminal of the first D flip-flop D11 and the clock input terminals of the L second D flip-flops (D21~D2L) are the clock trigger terminals of the gate signal generation unit 112. The clock trigger terminals of the gate signal generation unit 112 are connected to the input clock clkin. The data output terminals of the L second D flip-flops (D21~D2L) are the output terminals of the gate signal generation unit 112. The output terminals of the gate signal generation unit 112 output multiple gate signals ctrl0~ctrl. L-1 Where i is a positive integer, 1≤i≤L, and the division coefficient of the frequency divider DIV is K, which can be adjusted according to the actual situation.

[0028] For example, such as Figure 3As shown, the first input of the second OR gate OR12 is connected to the output of the first NOT gate NOT21. The second input of the second OR gate OR12 is connected to the data output of the first D flip-flop D21. The output of the second OR gate OR12 is connected to the data input of the second D flip-flop D22. The data output of the first D flip-flop D21 outputs the first gating signal ctrl0. The first input of the third OR gate OR13 is connected to the output of the second NOT gate NOT22. The second input of the third OR gate OR13 is connected to the data output of the second D flip-flop D22. The output of the third OR gate OR13 is connected to the data input of the third D flip-flop D23. The data output of the second D flip-flop D22 outputs the second gating signal ctrl1. The connection principle of the (i+1)th first OR gate OR(i+1) to the Lth first OR gate ORL with the L-1 second NOT gates (NOT21~NOT2(L-1)) and the L second D flip-flops (D21~D2L) is the same as above and will not be described again here.

[0029] More in detail, such as Figure 4 As shown, the multiphase clock generation unit 113 includes L third D flip-flops (D31~D3L) and L second AND gates (AND21~AND2L). The data output terminal of the i-th third D flip-flop is connected to the first input terminal of the i-th second AND gate, and the clock input terminal of the i-th third D flip-flop is connected to the second input terminal of the i-th second AND gate. The data input terminals of the L third D flip-flops (D31~D3L) are the data input terminals of the multiphase clock generation unit 113, and the data input terminals of the multiphase clock generation unit 113 are connected to multiple gate control signals ctrl0~ctrl0. L-1 The clock inputs of L third D flip-flops (D31~D3L) serve as the clock triggers for the multi-phase clock generation unit 113, which is connected to the input clock clkin. The outputs of L second AND gates (AND21~AND2L) are the outputs of the multi-phase clock generation unit 113, which outputs L phase sampling clocks (clk_ph0~clk_ph) to the outside. L-1 ).

[0030] For example, such as Figure 4As shown, the data output of the first third D flip-flop D31 is connected to the first input of the first second AND gate AND21, the clock input of the first third D flip-flop D31 is connected to the second input of the first second AND gate AND21, the data input of the first third D flip-flop D31 is connected to the first gate signal ctrl0, and the clock input of the first third D flip-flop D31 is connected to the input clock clkin. The first second AND gate AND21 outputs the first phase sampling clock clk_ph0. The data output of the second third D flip-flop D32 is connected to the first input of the second second AND gate AND22, and the clock input of the second third D flip-flop D32 is connected to the first input of the second second AND gate AND22. The second input of the second AND gate AND22 is connected to the second input terminal of the second third D flip-flop D32. The data input of the second third D flip-flop D32 is connected to the second gate signal ctrl1. The clock input of the second third D flip-flop D32 is connected to the input clock clkin. The second AND gate AND22 outputs the second phase sampling clock clk_ph1. ... The data output of the Lth third D flip-flop D3L is connected to the first input terminal of the Lth second AND gate AND2L. The clock input of the Lth third D flip-flop D3L is connected to the second input terminal of the Lth second AND gate AND2L. The data input of the Lth third D flip-flop D3L is connected to the Lth gate signal ctrl1. L-1 The clock input of the Lth third D flip-flop D3L is connected to the input clock clkin, and the Lth second AND gate AND2L outputs the Lth phase sampling clock clk_ph. L-1 .

[0031] More in detail, such as Figure 5 As shown, the data processing module 120 includes a multi-phase data generation unit 121, a data synchronization unit 122, a data delay unit 123, a switching matrix unit 124, and M sub-filters (1251~125M). The multi-phase data generation unit 121 is connected to the multi-phase clock generation unit 113 in the clock generation module 110, sampling the L-phase clock (clk_ph0~clk_ph). L-1 Triggered by ), the input data din is converted from serial to parallel to obtain L-phase parallel sampling data (d0~d). L-1 The data synchronization unit 122 is connected to the multi-phase data generation unit 121 and the multi-phase clock generation unit 113 in the clock generation module 110. Under the trigger of the synchronization clock clk_sync, it samples the L-phase parallel data (d0~d...). L-1 Alignment is performed to obtain the intermediate synchronization data of phase L (d_sync0[n]~d_sync). L-1[n]); The data delay unit 123 is connected to the data synchronization unit 122 and the frequency divider unit 111 in the clock generation module 110. Under the trigger of the output clock clk_out signal, it synchronizes the intermediate data (d_sync0[n]~d_sync) of the L phase. L-1 [n]) Apply different delay amounts to obtain multiple delayed data; the input of the switch matrix 124 is connected to the data delay unit 123, and the output of the switch matrix 124 is connected to M sub-filters (1251~125M). Different delayed data are transmitted to the corresponding sub-filters according to the coefficient characteristics of each sub-filter. Among them, the number of parallel paths L, the number of sub-filters M, and the downsampling rate D of the downsampling FIR filter in the polyphase data generation unit 121 satisfy the following relationship: L=D×M.

[0032] More in detail, such as Figure 6 As shown, the multiphase data generation unit 121 includes L fourth D flip-flops (D41~D4L). The data input terminals of the L fourth D flip-flops (D41~D4L) are connected to the input data din, and the clock input terminals of the L fourth D flip-flops (D41~D4L) are respectively connected to the L phase sampling clocks (clk_ph0~clk_ph). L-1 The data outputs of L fourth D flip-flops (D41~D4L) jointly output L phase parallel sampled data (d0~d...). L-1 ).

[0033] For example, such as Figure 6 As shown, the data input of the first fourth D flip-flop D41 is connected to the input data din, the clock input of the first fourth D flip-flop D41 is connected to the first phase sampling clock clk_ph0, and the data output of the first fourth D flip-flop D41 outputs the first phase parallel sampling data d0; the data input of the second fourth D flip-flop D42 is connected to the input data din, the clock input of the second fourth D flip-flop D42 is connected to the second phase sampling clock clk_ph1, and the data output of the second fourth D flip-flop D42 outputs the second phase parallel sampling data d1; ...; the data input of the Lth fourth D flip-flop D4L is connected to the input data din, and the clock input of the Lth fourth D flip-flop D4L is connected to the Lth phase sampling clock clk_ph0. L-1 The data output terminal of the Lth fourth D flip-flop D4L outputs the parallel sampled data d of the Lth phase. L-1 .

[0034] More in detail, such as Figure 7 As shown, the data synchronization unit 122 includes L fifth D flip-flops (D51~D5L), and the data input terminals of the L fifth D flip-flops (D51~D5L) are respectively connected to L phases of parallel sampling data (d0~d1). L-1The clock inputs of L fifth D flip-flops (D51~D5L) are connected to a synchronous clock clk_sync, and the data outputs of the L fifth D flip-flops (D51~D5L) jointly output L phase intermediate synchronous data (d_sync0[n]~d_sync). L-1 [n]).

[0035] For example, such as Figure 7 As shown, the data input of the first fifth D flip-flop D51 is connected to the first phase parallel sampling data d0, the clock input of the first fifth D flip-flop D51 is connected to the synchronous clock clk_sync, and the data output of the first fifth D flip-flop D51 outputs the first phase intermediate synchronous data d_sync0[n]; the data input of the second fifth D flip-flop D52 is connected to the second phase parallel sampling data d1, the clock input of the second fifth D flip-flop D52 is connected to the synchronous clock clk_sync, and the data output of the second fifth D flip-flop D52 outputs the second phase intermediate synchronous data d_sync1[n]; ...; the data input of the Lth fifth D flip-flop D5L is connected to the Lth phase parallel sampling data d L-1 The clock input of the Lth fifth D flip-flop D5L is connected to the synchronous clock clk_sync, and the data output of the Lth fifth D flip-flop D5L outputs the intermediate synchronous data d_sync of the Lth phase. L-1 [n].

[0036] More in detail, such as Figure 8 As shown, the data delay unit 123 consists of L D flip-flop groups. Each D flip-flop group includes R cascaded sixth D flip-flops. The clock input of the sixth D flip-flop is connected to the output clock clk_out. The data output of each sixth D flip-flop outputs delayed data. The first sixth D flip-flop in each D flip-flop group is connected to the corresponding intermediate synchronization data. R is a positive integer, and R≥2.

[0037] For example, such as Figure 8As shown, the data delay unit 123 consists of L D flip-flop groups. Each D flip-flop group includes R cascaded sixth D flip-flops. The first D flip-flop group includes sixth D flip-flops D611, D612, ..., D61R. The data input of sixth D flip-flop D611 is connected to the first phase intermediate synchronization data d_sync0[n]. The clock input of sixth D flip-flop D611 is connected to the output clock clk_out. The data output of sixth D flip-flop D611 is connected to the data input of sixth D flip-flop D612, and the data output of sixth D flip-flop D611 outputs delayed data d_sync0[n-1]. The clock input of sixth D flip-flop D612 is connected to the output clock clk_out. The data output of sixth D flip-flop D612 is connected to the data input of sixth D flip-flop D613, and the data output of sixth D flip-flop D612... The data output terminal of the 612 flip-flop outputs delayed data d_sync0[n-2]; ...; The clock input terminal of the sixth D flip-flop D61R is connected to the output clock clk_out, and the data output terminal of the sixth D flip-flop D61R outputs delayed data d_sync0[n-R+1]; The other (R-1) D flip-flop groups each include R cascaded sixth D flip-flops. The difference is that the input data of the first sixth D flip-flop in each D flip-flop group is different. In the first D flip-flop group, the data input terminal of the sixth D flip-flop D611 is connected to the first phase intermediate synchronization data d_sync0[n], in the second D flip-flop group, the data input terminal of the sixth D flip-flop D621 is connected to the second phase intermediate synchronization data d_sync1[n], ..., in the Lth D flip-flop group, the data input terminal of the sixth D flip-flop D6L1 is connected to the Lth phase intermediate synchronization data d_sync L-1 [n].

[0038] More in detail, such as Figure 9 As shown, the sub-filter includes N multipliers (M1~Mn) and a first adder ADD1. The first input of each multiplier is connected to the delayed data, and the second input is connected to the corresponding multiplication coefficients. The N inputs of the first adder ADD1 are connected to the outputs of the N multipliers (M1~Mn), and the output of the first adder ADD1 is the output of the sub-filter. Here, N is a positive integer, N≥2. For example, as... Figure 9 As shown, the first input of the first multiplier M1 is connected to the delayed data d_sync0[n-1], and the second input of the first multiplier M1 is connected to the corresponding multiplication coefficient h0. The first input of the second multiplier M2 is connected to the delayed data d_sync1[n-2], and the second input of the second multiplier M2 is connected to the corresponding multiplication coefficient h1, ..., the first input of the Nth multiplier Mn is connected to the delayed data d_sync0[n-1]. L-1[n-2], the second input of the Nth multiplier Mn is connected to the corresponding multiplication coefficient h. N The N input terminals of the first adder ADD1 are connected to the output terminals of N multipliers (M1~Mn), and the output terminal of the first adder ADD1 outputs the calculation result out.

[0039] Please refer to Figures 1 to 10 As shown, the working principle of the high-speed downsampling FIR filter provided by this invention is as follows: like Figure 1 and Figure 2 As shown, the clock generation module 110 performs logic conversion on the input clock clkin to provide the L-phase sampling clock (clk_ph0~clk_ph). L-1 ), synchronous clock clk_sync and output clock clk_out, such as Figure 10 As shown, the L-phase sampling clock (clk_ph0~clk_ph) L-1 The input frequency is L-division of the input clock clkin; each phase sampling clock (clk_ph0~clk_ph) L-1 The high-level time of the output clock clk_out is the same as the high-level time of the input clock clk. The frequency of the output clock clk_out is L divided by the frequency of the input clock clk, and the duty cycle is 50%.

[0040] like Figures 5 to 10 As shown, the multiphase data generation unit 121 in the data processing module 120 utilizes the L-phase sampling clock (clk_ph0~clk_ph) L-1 The input data din is converted from serial to parallel to obtain L-phase parallel sampling data (d0~d1). L-1 );like Figure 10 As shown, the first phase parallel sampling data d0 corresponds to din[nL], din[n-L+1], ... in the input data din; the second phase parallel sampling data d1 corresponds to din[n-L+1], din[n-L+2], ... in the input data din; the Lth phase parallel sampling data d L-1 Corresponding to din[n-1], din[n]... in the input data din, the serial data is distributed to L parallel paths by triggering, and the data rate of each channel is reduced to 1 / L of the original rate. If the synchronization clock clk_sync is the parallel sampling clock of the Lth phase, the data synchronization unit 122 will sample the L phases of parallel data (d0~d...) based on the synchronization clock clk_sync. L-1 Alignment is performed to obtain the intermediate synchronization data of phase L (d_sync0[n]~d_sync). L-1 [n]), L-phase intermediate synchronization data (d_sync0[n]~d_sync)L-1 The change edge of [n] is consistent with the synchronous clock clk_sync. Therefore, the intermediate synchronous data d_sync0[n], d_sync1[n], ..., d_sync after passing through the multiphase data generation unit 121 and the data synchronization unit 122 are synchronized. L-1 [n] contains L data points between the input data din[n] and din[n+L-1]. Triggered by the output clock clk_out, data delay unit 123 synchronizes the L-phase intermediate data (d_sync0[n]~d_sync) L-1 [n]) Delay by one beat to obtain L delayed data d_sync0[n-1], d_sync1[n-1], ..., d_sync L-1 [n-1]; L delayed data d_sync0[n-1], d_sync1[n-1], ..., d_sync L-1 [n-1] contains L data points between the input data din[nL] and din[n-1]. Triggered by the output clock clk_out, data delay unit 123 synchronizes the L-phase intermediate data (d_sync0[n]~d_sync) L-1 [n]) Delay by two clock cycles to obtain L delayed data points d_sync0[n-2], d_sync1[n-2], ..., d_sync L-1 [n-2]; and L delayed data d_sync0[n-2], d_sync1[n-2], ..., d_sync L-1 [n-2] contains the L data points between the input data din[n-2L] and din[nL-1]. Similarly, for the intermediate synchronization data d_sync0[n], d_sync1[n], ..., d_sync... L-1 [n] By delaying the output clock clk_out field by different numbers of clock cycles, different delayed data can be output.

[0041] In this invention, it is assumed that the FIR filter is of order N, with coefficients h0, h1, ..., h2. N The output of the FIR filter after D-fold downsampling is:

[0042]

[0043]

[0044] Among them, y[ The symbols ] represent the output results in the sub-filters, h0, h1, ..., h2. N din represents the multiplication coefficients of the corresponding multiplier; [] indicates the corresponding data in the input data.

[0045] To calculate one output data point, N+1 input data points din are needed. When M outputs simultaneously, there are D-1 data points between every two outputs. Considering that there are N data points shared between adjacent data points, a total of D×(M-1)+N+1=L+N-D+1 data points are needed. And d_sync0[n], d_sync1[n], ..., d_sync L-1 [n] contains L input data din. Therefore, the intermediate synchronization data d_sync0[n], d_sync1[n], ..., d_sync0[n] need to be synchronized through the output clock clk_out. L-1 [n] delays R beats, where ,in This indicates rounding up to the nearest integer.

[0046] In an exemplary embodiment, the following example is used: sampling rate D=2, number of parallel channels M=2. In this case, L=D×M=4. The output y[n] of the FIR filter without downsampling is:

[0047]

[0048] When the extraction is multiplied by 2, the output is:

[0049]

[0050] When implemented in parallel using two paths, y[n], y[n-4], ... are output by one path; the other path outputs y[n-2], y[n-6], ... . The required data are din[n], din[n-1], ..., din[nN-2].

[0051] The present invention also provides a control method for a high-speed downsampling FIR filter, comprising: L-phase sampling clocks (clk_ph0~clk_ph) are generated based on the input clock clkin. L-1 The sampling clock includes a synchronous clock clk_sync and an output clock clk_out, where the frequency of the sampling clock is 1 / L of the frequency of the input clock clk_kin. Using the L-phase sampling clock (clk_ph0~clk_ph) L-1The input data din is sampled in parallel to obtain L-phase parallel sampling data (d0~d1). L-1 ); triggered by the synchronous clock clk_sync, parallel sampling of L-phase data (d0~d) is performed. L-1 Synchronization processing is performed to obtain the intermediate synchronization data of phase L (d_sync0[n]~d_sync). L-1 [n]); Triggered by the output clock clk_out, the intermediate synchronization data of phase L (d_sync0[n]~d_sync) is synchronized. L-1 [n]) Apply different delay processing to each data point to obtain multiple delay data; The delayed data is distributed to M parallel sub-filters, and the output downsampling filtering result is integrated through the M sub-filters; where M and L are positive integers, M≥2, L≥2.

[0052] This invention provides a high-speed downsampling FIR filter and its control method. The high-speed downsampling FIR filter includes a clock generation module and a data processing module. The clock generation module uses an input clock to generate a multi-phase sampling clock, a synchronization clock, and an output clock. The data processing module, triggered by the multi-phase sampling clock, synchronization clock, and output clock, performs serial-to-parallel conversion and data alignment on the input data. It also applies different degrees of delay based on the different orders of the sub-filters, distributing the delayed data to M parallel sub-filters. The downsampling filter result is then integrated and output through these M sub-filters. The high-speed downsampling FIR filter provided by this invention improves the operating speed of the downsampling FIR filter in integrated circuit implementation by combining multi-path parallel processing and multi-phase data processing. During filtering, multiple sub-filters are used simultaneously for integrated filtering, resulting in a high filtering rate. For different integrated circuit processes, a trade-off between speed and area can be achieved by adjusting the number of channels M during implementation. When the process speed is low but the high-speed downsampling FIR filter operates at a high speed, the number of channels M can be increased to achieve high-speed operation; conversely, when the process speed is high, the number of channels M can be decreased to achieve a smaller chip area. The downsampling FIR filter provided by this invention has a simple hardware structure, the number of sub-filters can be adjusted according to actual conditions, the operating frequency is not limited, and the sampling rate is high.

[0053] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high-speed downsampling FIR filter, characterized in that, include: A clock generation module is used to generate an L-phase sampling clock, a synchronization clock, and an output clock based on an input clock, wherein the frequency of the sampling clock is 1 / L of the frequency of the input clock; The data processing module, connected to the clock generation module, is used to perform parallel sampling of the input data using the L-phase sampling clock to obtain L-phase parallel sampled data; under the trigger of the synchronization clock, the L-phase parallel sampled data is aligned to obtain L-phase intermediate synchronization data; and under the trigger of the output clock, different delay processing is applied to the L-phase intermediate synchronization data respectively, and the delayed data after delay processing is distributed to M parallel sub-filters to integrate the output downsampling filtering results through the M sub-filters. Where M and L are positive integers, M≥2, L≥2.

2. The high-speed downsampling FIR filter according to claim 1, characterized in that, The clock generation module includes a frequency division unit, a gating signal generation unit, and a multi-phase clock generation unit. The frequency division unit divides the input clock to obtain the output clock. The gating signal generation unit, triggered by the input clock, performs logical processing on the output clock to obtain multiple gating signals. The multi-phase clock generation unit, triggered by the input clock, outputs control on the multiple gating signals to generate an L-phase sampling clock. The synchronization clock is one phase of the L-phase sampling clock, or the synchronization clock is generated by the multi-phase clock generation unit based on the gating signals and the input clock.

3. The high-speed downsampling FIR filter according to claim 2, characterized in that, The gated signal generation unit includes a frequency divider, a first D flip-flop, a first NOT gate, a first AND gate, a buffer, L second D flip-flops, L first OR gates, and L-1 second NOT gates. The output of the frequency divider is connected to the data input of the first D flip-flops. The output of the frequency divider is also connected to the first input of the first AND gate. The data output of the first D flip-flops is connected to the second input of the first AND gate after passing through the first NOT gate. The output of the first AND gate is connected to the input of the buffer. The output of the buffer is connected to the first input of the first first OR gate. The second input of the first first OR gate is connected to the data output of the Lth second D flip-flop. The output of the first first OR gate is connected to the data input of the first second D flip-flop. The inputs of L-1 second NOT gates are all connected to the output of the first AND gate. The first input of the (i+1)th first OR gate is connected to the output of the ith second NOT gate. The second input of the (i+1)th first OR gate is connected to the data output of the ith second D flip-flop. The output of the (i+1)th first OR gate is connected to the data input of the (i+1)th second D flip-flop. The input of the frequency divider is the input of the gate signal generation unit. The clock inputs of the first D flip-flop and the second D flip-flop are the clock triggers of the gate signal generation unit. The data outputs of L second D flip-flops are the outputs of the gate signal generation unit. Here, i is a positive integer, 1 ≤ i ≤ L.

4. The high-speed downsampling FIR filter according to claim 3, characterized in that, The multiphase clock generation unit includes L third D flip-flops and L second AND gates. The data output terminal of the i-th third D flip-flop is connected to the first input terminal of the i-th second AND gate, and the clock input terminal of the i-th third D flip-flop is connected to the second input terminal of the i-th second AND gate. The data input terminal of the third D flip-flop is the data input terminal of the multiphase clock generation unit, the clock input terminal of the third D flip-flop is the clock trigger terminal of the multiphase clock generation unit, and the output terminal of the second AND gate is the output terminal of the multiphase clock generation unit.

5. The high-speed downsampling FIR filter according to claim 2, characterized in that, The data processing module includes a multi-phase data generation unit, a data synchronization unit, a data delay unit, a switching matrix unit, and M sub-filters. The multi-phase data generation unit is connected to the multi-phase clock generation unit. Under the trigger of the L-phase sampling clock, it performs serial-to-parallel conversion on the input data to obtain the L-phase parallel sampling data. The data synchronization unit is connected to the multi-phase data generation unit and the multi-phase clock generation unit. Under the trigger of the synchronization clock, it aligns the L-phase parallel sampling data to obtain the L-phase intermediate synchronization data. The data delay unit is connected to the data synchronization unit and the frequency division unit. Under the trigger of the output clock signal, it applies different delay amounts to the L-phase intermediate synchronization data to obtain multiple delayed data. The input terminal of the switching matrix is ​​connected to the data delay unit, and the output terminal of the switching matrix is ​​connected to the M sub-filters. Different delayed data are transmitted to the corresponding sub-filters according to the coefficient characteristics of each sub-filter.

6. The high-speed downsampling FIR filter according to claim 5, characterized in that, The multiphase data generation unit includes L fourth D flip-flops. The data input terminals of the L fourth D flip-flops are connected to the input data, the clock input terminals of the L fourth D flip-flops are respectively connected to the L phase sampling clock, and the data output terminals of the L fourth D flip-flops jointly output the L phase parallel sampling data.

7. The high-speed downsampling FIR filter according to claim 5, characterized in that, The data synchronization unit includes L fifth D flip-flops. The data input terminals of the L fifth D flip-flops are respectively connected to the L phases of parallel sampling data. The clock input terminals of the L fifth D flip-flops are connected to the synchronization clock. The data output terminals of the L fifth D flip-flops jointly output the L phases of intermediate synchronization data.

8. The high-speed downsampling FIR filter according to claim 5, characterized in that, The data delay unit consists of L D flip-flop groups, each of which includes R cascaded sixth D flip-flops. The clock input of each sixth D flip-flop is connected to the output clock, and the data output of each sixth D flip-flop outputs the delayed data. The first sixth D flip-flop in each D flip-flop group is connected to the corresponding intermediate synchronization data. R is a positive integer, and R≥2.

9. The high-speed downsampling FIR filter according to claim 5, characterized in that, The sub-filter includes N multipliers and a first adder. The first input of each multiplier is connected to the delayed data, and the second input of each multiplier is connected to the corresponding multiplication coefficient. The N inputs of the first adder are connected to the outputs of the N multipliers, and the output of the first adder is the output of the sub-filter. Here, N is a positive integer, and N≥2.

10. A control method for a high-speed downsampling FIR filter, characterized in that, include: An L-phase sampling clock, a synchronization clock, and an output clock are generated based on the input clock, wherein the frequency of the sampling clock is 1 / L of the frequency of the input clock; The input data is sampled in parallel using the sampling clock described in phase L to obtain phase L parallel sampling data; Under the trigger of the synchronization clock, the parallel sampling data of phase L is synchronized to obtain intermediate synchronization data of phase L; Under the trigger of the output clock, different delay processing is applied to the intermediate synchronization data of phase L to obtain multiple delay data; The delayed data is distributed to M parallel sub-filters, and the downsampling filtering result is output by integrating the M sub-filters. Where M and L are positive integers, M≥2, L≥2.

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