A method for IIR filter computation based on pipelined-parallel and distributed coefficient prefetching

Abstract

The application discloses a kind of IIR filter calculation methods based on pipeline-parallel and distributed coefficient prefetching, comprising: (1) determining the number of basic second-order nodes and coefficient;(2) store the coefficient in independent ROM;(3) each second-order node is divided into input buffer IF, coefficient multiplication MUL, accumulation operation ACC and output buffer OF stage;(4) read the coefficient;(5) coefficient buffer to register group;(6) multiplication operation;(7) accumulation operation and output buffer;(8) to the remaining second-order node, repeat (4) to (7) operation, complete the whole filter calculation.The application compared with prior art serial structure calculation, total operation delay will not increase with the number of accumulation, FPGA resource is fully utilized at the same time, on the basis of not changing filter structure form and quantization bit width, improve the real-time processing capability of filter module.

Description

Technical Field

[0001] This invention relates to the field of signal filtering and processing, which requires filtering out interference components and retaining effective signals. In particular, when the acquired signal is subject to various types of noise interference, IIR filters are used to filter the signal and optimize the calculation. Background Technology

[0002] In controlled nuclear fusion experiments, lasers operating under complex conditions in tokamak devices are susceptible to factors such as temperature variations, mechanical vibrations, and magnetic field interference, resulting in interference components in the output analog signal and causing errors in frequency measurements and other calculations. Therefore, digital filtering is necessary to remove various interference components mixed in during signal acquisition and retain the effective intermediate frequency signal. Among numerous digital filters, IIR filters are the preferred solution for FPGA platform implementation due to their low order and low hardware resource consumption. They typically employ a structure of N cascaded second-order basic sections to meet passband and stopband performance requirements.

[0003] However, the FPGA implementation of traditional IIR filters has the following shortcomings: On the one hand, when using a serial execution architecture, the next stage can only start operation after the previous stage's second-order section has completed all multiplication and addition operations and output the results, resulting in obvious inter-stage waiting phenomena. The total operation delay accumulates as the number of second-order sections increases, which seriously affects the real-time processing capability of the filtering module. On the other hand, under the serial structure, the hardware resources inside the FPGA, such as DSP48, LUT and registers, are difficult to be fully utilized at the same time, and the advantages of hardware parallel computing are not effectively brought into play, resulting in low resource utilization.

[0004] Meanwhile, traditional IIR filters often employ a centralized coefficient storage method, where the coefficients of all second-order sections are stored in a single ROM. This storage method requires different second-order sections to share a storage port when accessing coefficients, accompanied by complex address decoding and read control logic, which easily leads to access conflicts and increases timing path length. Especially when multiple second-order sections are processed in parallel, the access bottleneck of centralized storage is further exacerbated, weakening the parallel advantages of the computing architecture and causing a decrease in filtering efficiency.

[0005] Therefore, optimizing the FPGA hardware implementation structure of IIR filters while keeping the filter transfer function and fixed bit width constraints unchanged, solving problems such as inter-stage waiting, low resource utilization and coefficient access conflicts, and improving the real-time processing capability of the filtering module have become important technical problems that urgently need to be solved. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of existing technologies by proposing a pipelined-parallel and distributed coefficient prefetching-based IIR filter calculation method. Within a single second-order section, a single filtering calculation is divided into four relatively independent processing stages, shortening the combinational logic path through timing segmentation. Between multiple second-order sections, the hardware parallel execution characteristics of the FPGA are fully utilized, allowing different second-order sections to operate in different processing stages within the same clock interval, achieving efficient overlap of inter-stage operations. Simultaneously, a distributed coefficient storage and prefetching mechanism is designed, allowing the coefficient reading process and data computation process to proceed in parallel, effectively reducing the latency impact of coefficient access on the critical path. This method not only eliminates the inter-stage waiting phenomenon of traditional serial structures, preventing the total computational delay from accumulating with the number of second-order sections, but also fully unleashes the parallel potential of the FPGA's internal DSP48, LUTs, and registers, achieving efficient resource utilization simultaneously. Furthermore, without changing the core filter structure and fixed-point quantization bit width, and without compromising filtering accuracy, it significantly improves the real-time processing capability and data throughput of the filtering module, while reducing the risk of coefficient access conflicts and enhancing the reliability of filtering operations.

[0007] The specific technical solution for achieving the objective of this invention is: a method for calculating IIR filters based on pipelined-parallel and distributed coefficient prefetching, characterized in that it includes:

[0008] S1: Based on the preset passband and stopband performance specifications of the filter, the target order of the filter is determined through filtering algorithm calculation, thereby clarifying the number N of basic second-order sections that need to be cascaded, and solving for the filter coefficient b0 corresponding to each second-order section. i b1 i b2 i a1 i a2 i where i = 1, 2, ..., N;

[0009] S2: Configure an independent ROM storage unit for each basic second-order section, and store the corresponding coefficients b0 of each second-order section. i b1 i b2 i a1 i a2 i Write to ROM storage cells, and set the storage depth of each ROM storage cell to 5;

[0010] S3: The complete filtering operation process of a single second-order section is broken down into four relatively independent pipelined processing stages: input buffering, coefficient multiplication, accumulation operation and output buffering.

[0011] S4: Start filter calculation. For the current input data to be filtered, while performing the input buffer operation in the first second-order section, read all the filter coefficients stored in the ROM storage unit corresponding to the second-order section.

[0012] S5: Latch the read filter coefficients into the register group to complete the coefficient prefetching operation of the second-order section of this stage, ensuring that the coefficient reading process and the subsequent data operation process can proceed in parallel;

[0013] S6: Based on the preset 4-stage pipeline architecture, the first second-order section starts the coefficient multiplication operation, and performs parallel multiplication operations on the filter coefficients latched in the register group and the data to be filtered buffered in the input buffer stage to generate multiple sets of product results.

[0014] S7: Perform an accumulation operation on the obtained multiple product results to obtain the filtered output result of the first second-order section. This result is latched by the output buffer stage and used as the input data of the next second-order section.

[0015] S8: For the remaining N-1 second-order sections, the operation steps from S4 to S7 are executed sequentially in a loop. By utilizing the hardware parallel characteristics of the FPGA, different second-order sections are in different pipeline processing stages within the same clock cycle, realizing overlapping execution of inter-stage operations, and finally completing the calculation of the entire IIR filter.

[0016] The four-stage pipeline processing phase of step S3 is specifically defined as follows: The input buffer stage receives the current input sample to be processed and updates and latches the historical input samples and historical output samples; the coefficient multiplication stage calls the DSP48 computing resources inside the FPGA to perform parallel calculations on the forward term required for filtering, i.e., the product of the input sample and the corresponding coefficient, and the feedback term, i.e., the product of the historical output sample and the corresponding coefficient, generating multiple sets of intermediate multiplication results; the accumulation stage uses an addition tree architecture to sum the multiple sets of multiplication results output by the coefficient multiplication stage to obtain the filtered output value of the current second-order section; the output buffer stage latches the filtered output result obtained by the accumulation stage and passes the result to the next second-order section.

[0017] The coefficients of the first second-order section in step S4 are b01, b11, b21, a11, a21.

[0018] The multiple product terms of the first second-order section in step S6 are b01x(n), b11x(n-1), b21x(n-2), a11y1(n-1), and a21y1(n-2).

[0019] Step S7 involves accumulating the product terms of the first second-order section, resulting in b01x(n) + b11x(n-1) + b21x(n-2) - a11y1(n-1) - a21y1(n-2), which is then latched through the output buffer stage as input data for the next second-order section.

[0020] The specific implementation process of the inter-level operation overlap in step S8 is as follows: In time period T1, the first-level second-order section performs an input buffering operation to complete the latching of the current input data x(n) and the historical input data x(n-1) and x(n-2), while the other second-order sections maintain their current states; In time period T2, the first-level second-order section enters the coefficient multiplication stage and calculates the product terms b01x(n), b11x(n-1), b21x(n-2), a11y1(n-1), and a21y1(n-2) in parallel; At the same time, the second-level second-order section starts the input buffering operation to cache and latch the first-level second-order section in the previous period T1. The historical output results y1(n-1), y1(n-2), and y1(n-3) are output, while the remaining unaffected second-order sections maintain their original states. During time period T3, the first-order second-order section performs an accumulation operation, calculating the output result y1(n) according to the expression b01x(n) + b11x(n-1) + b21x(n-2) - a11y1(n-1) - a21y1(n-2). The second-order second-order section enters the coefficient multiplication stage, calculating b02y1(n-1), b12y1(n-2), b22y1(n-3), a12y2(n-2), and a22y2(n-3) for n-1 frames of data. The product term; the third-order second section initiates the input buffer operation, buffering and latching the historical results y2(n-2), y2(n-3), and y2(n-4) of the previous cycle T2 of the second-order second section, while the remaining second-order sections remain unchanged; in the timing cycle T4, the first-order second section enters the output buffer stage, latching the result y1(n) obtained from the accumulation operation; the second-order second section performs the accumulation operation, calculating the output result according to the formula y2(n-1)=b02y1(n-1)+b12y1(n-2)+b22y1(n-3)-a12y2(n-2)-a22y2(n-3); the third-order second section Entering the coefficient multiplication stage, the product terms b03y2(n-2), b13y2(n-3), b23y2(n-4), a13y3(n-3), and a23y3(n-4) are calculated for n-2 frames of data. The fourth-level second-order section initiates an input buffer operation, caching and latching the historical results y3(n-3), y3(n-4), and y3(n-5) of the previous cycle T3 of the third-level second-order section. Subsequent time-series cycles and the remaining second-order sections proceed sequentially according to the above logic. Through the pipeline scheduling mechanism, the second-order sections of different levels synchronously process data from different times in the same data sequence, ultimately achieving efficient overlap of inter-level operations.

[0021] Compared with existing technologies, this invention significantly improves the real-time processing capability of the filtering module without changing the filter function and quantization accuracy. By employing a hybrid architecture of splitting a single second-order section into four stages and overlapping inter-stage operations across multiple second-order sections, it eliminates inter-stage waiting in traditional serial structures, preventing the total computational latency from accumulating with each stage and greatly improving throughput. A distributed coefficient storage and prefetching mechanism is used, configuring an independent ROM for each second-order section to avoid access conflicts and decoding overhead. Coefficient reading and data computation are performed in parallel, shortening the critical path and optimizing hardware resource utilization. This method ensures that filtering accuracy is not compromised while enhancing the reliability of filtering operations, making it suitable for signal processing requirements under complex conditions such as tokamak nuclear fusion devices. It solves the technical pain point of existing technologies that struggle to balance filtering performance, computational speed, and hardware resource consumption. Attached Figure Description

[0022] Figure 1 This is a framework diagram of the laser frequency stabilization control system of the present invention;

[0023] Figure 2 This is the pipeline parallel timing diagram for Example 1. Detailed Implementation

[0024] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These modifications and improvements all fall within the scope of protection of the present invention.

[0025] Example 1

[0026] See Figure 1 The present invention includes the following steps:

[0027] Step 1: After the system is powered on, the host computer sends a command containing a trigger signal to the FPGA;

[0028] Step 2: After triggering, the data acquisition module starts working, acquiring the analog signal output by the laser detector and performing analog-to-digital conversion. The acquisition work is mainly completed by the ADC chip.

[0029] Step 3: The FPGA filters the acquired signal using a cascaded IIR filter;

[0030] Step 4: The filtered result is transmitted to the data storage module for storage on one side and to the data frequency measurement module on the other side for frequency calculation. The result is compared with the reference frequency transmitted by the host computer through the data transmission module to obtain the error signal. The error signal is then transmitted to the data control output module and converted into an analog voltage signal by the DAC, which in turn changes the voltage of the piezoelectric ceramic to achieve frequency stabilization.

[0031] See Figure 2 The data filtering in step 3 includes the following steps:

[0032] 3-1: Based on the passband and stopband specifications of the filter, calculate the target order of the filter, determine the number N of the cascaded basic second-order sections, and the coefficient b0 of each second-order section. i b1 i b2 i a1 i a2 i where i = 1, 2, ..., N;

[0033] 3-2: Configure an independent ROM storage unit for each second-order section, and store the coefficient b0 i b1 i b2 i a1 i a2 i Write the data to the corresponding ROM storage units respectively, with each ROM storage unit configured with a storage depth of 5;

[0034] 3-3: The operation process of each second-order section is divided into four pipelined stages: input buffer, coefficient multiplication, accumulation operation, and output buffer.

[0035] 3-4: Start filter operation. For the current input data to be filtered, while performing the input buffer operation in the first second-order section, read all the filter coefficients b01, b11, b21, a11, a21 stored in the ROM storage unit corresponding to the second-order section.

[0036] 3-5: Latch the read filter coefficients into the dedicated register group to complete the coefficient prefetching operation of the second-order section of this stage;

[0037] 3-6: Perform coefficient multiplication on the first second-order section, and perform parallel multiplication on the filter coefficients latched in the register group and the data to be filtered buffered in the input buffer stage to generate multiple sets of product results b01x(n), b11x(n-1), b21x(n-2), a11y1(n-1), a21y1(n-2);

[0038] 3-7: Perform an accumulation operation on the obtained multiple product results to obtain the filtered output result of the first second-order section as b01x(n)+b11x(n-1)+b21x(n-2)-a11y1(n-1)-a21y1(n-2). This result is latched in the output buffer stage and used as the input data of the next second-order section.

[0039] 3-8: For the remaining N-1 second-order sections, the operation steps 3-4 to 3-7 are executed sequentially. Utilizing the parallel characteristics of FPGA hardware, different second-order sections are placed in different pipeline processing stages within the same clock cycle, achieving overlapping execution of inter-stage operations. In timing cycle T1, the first-stage second-order section performs an input buffer operation, completing the buffering and latching of the current input data x(n) and historical input data x(n-1) and x(n-2). The remaining second-order sections maintain their current states. In timing cycle T2, the first-stage second-order section enters the coefficient multiplication stage, calculating the product terms b01x(n), b11x(n-1), b21x(n-2), a11y1(n-1), and a21y1(n-2) in parallel. Simultaneously, the second-stage second-order section initiates an input buffer operation, buffering and latching the data from the first-stage second-order section in the previous cycle T. 1. Output historical results y1(n-1), y1(n-2), y1(n-3); During time period T3, the first-level second-order section accumulation operation b01x(n)+b11x(n-1)+b21x(n-2)-a11y1(n-1)-a21y1(n-2) calculates the output result y1(n); The second-level second-order section enters the coefficient multiplication stage, calculating the product terms b02y1(n-1), b12y1(n-2), b22y1(n-3), a12y2(n-2), a22y2(n-3) for n-1 frames of data. The third-order second-stage section initiates an input buffer operation, caching and latching the historical results y2(n-2), y2(n-3), and y2(n-4) output from the previous cycle T2 of the second-order second-stage section, while the remaining second-order sections remain unchanged. In cycle T4, the first-order second-stage section enters the output buffer stage, latching the result y1(n) obtained from the accumulation operation. The second-order second-stage section performs the accumulation operation according to the formula y2(n-1)=b02y1(n-1)+b12y1(n-2)+b22y1(n-3)-a12y2(n-2)-a22y2(n-3) 3) Calculate the output results; the third-order second-order section enters the coefficient multiplication stage, calculating the product terms b03y2(n-2), b13y2(n-3), b23y2(n-4), a13y3(n-3), and a23y3(n-4) for n-2 frames of data; the fourth-order second-order section starts the input buffer operation, buffering and latching the historical results y3(n-3), y3(n-4), and y3(n-5) of the previous cycle T3 of the third-order second-order section; subsequent timing cycles and the remaining second-order sections proceed in sequence according to the above logic, finally completing the calculation of the entire IIR filter.

[0040] This invention discloses a filter computation method based on pipelined-parallel and distributed coefficient prefetching. By employing a hybrid architecture of splitting a single second-order section into four pipeline stages and overlapping inter-stage operations across multiple second-order sections, it eliminates inter-stage waiting in traditional serial structures, preventing the total computational latency from accumulating with each stage and significantly improving throughput. A distributed coefficient storage and prefetching mechanism is used, configuring an independent ROM for each second-order section to avoid access conflicts and decoding overhead. Coefficient reading and data computation are performed in parallel, shortening the critical path and optimizing hardware resource utilization. This method ensures that filtering accuracy is not compromised while enhancing the reliability of the filtering operation.

[0041] The above description is merely a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for calculating IIR filters based on pipelined-parallel and distributed coefficient prefetching, characterized in that, The method specifically includes the following steps: S1: Based on the passband and stopband specifications of the filter, calculate the target order of the filter, determine the number N of the cascaded basic second-order sections, and the coefficient b0 of each second-order section. i b1 i b2 i a1 i a2 i where i = 1, 2, ..., N; S2: Configure an independent ROM storage unit for each second-order section, storing the coefficient b0 i b1 i b2 i a1 i a2 i Write the data to the corresponding ROM storage units respectively, with each ROM storage unit configured with a storage depth of 5; S3: The operation process of each second-order section is divided into four pipelined stages: input buffer, coefficient multiplication, accumulation operation and output buffer. S4: Start filter operation. For the current input data to be filtered, in the input buffer stage of the first second-order section, read all the filter coefficients in the ROM storage unit corresponding to the second-order section. S5: Latch the read filter coefficients into the register group to complete the coefficient prefetching of the second-order section of this stage, so that the coefficient reading process and the subsequent data operation process can be carried out in parallel; S6: Based on a 4-stage pipeline architecture, it performs coefficient multiplication on the first second-order section, and performs parallel multiplication on the latched filter coefficients and the data to be filtered in the input buffer to obtain multiple product terms; S7: Perform an accumulation operation on the obtained multiple product terms to obtain the filtering result of the first second-order section, and then latch the filtering result through the output buffer stage and use it as the input data of the next second-order section; S8: For the remaining N-1 second-order sections, repeat the operations of S4-S7 in sequence. Utilize the parallel characteristics of the FPGA to make different second-order sections be in different pipeline processing stages within the same clock interval, realize inter-stage operation overlap, and complete the filtering calculation of the entire IIR filter.

2. The IIR filter calculation method based on pipelined-parallel and distributed coefficient prefetching according to claim 1, characterized in that, The four-stage pipeline processing in step S3 is as follows: the input buffer stage updates and latches the current input sample and historical samples; the coefficient multiplication stage calls DSP48 resources to perform forward and feedback multiplication in parallel; the accumulation stage uses an addition tree to sum the multiplication results to obtain the current second-order section output; and the output buffer stage is responsible for latching the output results and passing them to the next stage.

3. The IIR filter calculation method based on pipelined-parallel and distributed coefficient prefetching according to claim 1, characterized in that, The coefficients of the first second-order section in step S4 are b01, b11, b21, a11, a21.

4. The IIR filter calculation method based on pipelined-parallel and distributed coefficient prefetching according to claim 1, characterized in that, The multiple product terms of the first second-order section in step S6 are b01x(n), b11x(n-1), b21x(n-2), a11y1(n-1), and a21y1(n-2).

5. The IIR filter calculation method based on pipelined-parallel and distributed coefficient prefetching according to claim 1, characterized in that, Step S7 involves accumulating the product terms of the first second-order section, resulting in b01x(n) + b11x(n-1) + b21x(n-2) - a11y1(n-1) - a21y1(n-2), which is then latched through the output buffer stage as input data for the next second-order section.

6. The IIR filter calculation method based on pipelined-parallel and distributed coefficient prefetching according to claim 1, characterized in that, The specific implementation of the inter-level overlap operation in step S8 is as follows: during time period T1, the input buffer data of the first-level second-order section is x(n), x(n-1), and x(n-2), while the other second-order sections remain unchanged. During time period T2, the first-level second-order section performs coefficient multiplication to calculate b01x(n), b11x(n-1), b21x(n-2), a11y1(n-1), and a21y1(n-2); the input buffer of the second-level second-order section is the historical output results y1(n-1), y1(n-2), and y1(n-3) of the previous period from the previous cycle, while the other second-order sections remain unchanged. At time T3, the first-order second-order section performs an accumulation operation to calculate y1(n), with the expression b01x(n)+b11x(n-1)+b21x(n-2)-a11y1(n-1)-a21y1(n-2); the second-order second-order section performs coefficient multiplication on the data of n-1 frames to calculate b02y1(n-1), b12y1(n-2), b22y1(n-3), a12y2(n-2), and a22y2(n-3); the third-order second-order section outputs the historical results y2(n-2), y2(n-3), and y2(n-4) from the previous cycle in the input buffer S2. At time T4, the first-level second-order section outputs the calculation result y1(n) from the buffer; the second-level second-order section performs an accumulation operation, calculating y2(n-1) = b02y1(n-1) + b12y1(n-2) + b22y1(n-3) - a12y2(n-2) - a22y2(n-3); the third-level second-order section performs coefficient multiplication on the data of n-2 frames, calculating b03y2(n-2), b13y2(n-3), b23y2(n-4), a13y3(n-3), and a23y3(n-4); the fourth-level second-order section inputs the historical results y3(n-3), y3(n-4), and y3(n-5) from the previous cycle from the buffer S3. Subsequent second-order sections and timing cycles follow the same pattern, using a pipeline to process data from different times in the same sequence at different stages.

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