Sawtooth circuit and shielding system

Abstract

The application relates to a sawtooth wave circuit and a shielding system, the sawtooth wave circuit comprising a timer chip and a charging and discharging circuit; the timer chip is used for generating a periodic charging and discharging control signal and transmitting the charging and discharging control signal to the charging and discharging circuit; the charging and discharging circuit is used for charging an energy storage capacitor of the charging and discharging circuit at a preset charging rate based on an accessed external direct-current voltage under the driving of the charging and discharging control signal; in the case that the voltage of the energy storage capacitor rises to a first voltage, the energy storage capacitor is discharged at a preset discharging rate so that the voltage of the energy storage capacitor falls to a second voltage, and a first sawtooth wave is output; the preset discharging rate is greater than the preset charging rate; the second voltage is lower than a preset discharging cut-off voltage threshold; based on this, the problem of discharging end fluctuation caused by temperature drift, chip time delay and the like can be effectively avoided, the stability of a sawtooth wave valley is improved, and therefore the stability and anti-interference capability of the sawtooth wave are effectively improved.

Description

Technical Field

[0001] This application relates to the field of sawtooth wave generation circuit technology, and in particular to a sawtooth wave circuit and a shielding system. Background Technology

[0002] In traditional electronic design, standard 555 timer chips, such as the NE555, are often used to generate basic waveforms like triangular and square waves due to their low cost. The trigger thresholds of the internal comparators in this chip are set to 1 / 3VCC and 2 / 3VCC, theoretically allowing the output waveform to switch stably between these two voltage levels. However, in practical applications, when the operating frequency increases to 200kHz and above, it becomes difficult to strictly lock the waveform level between 1 / 3VCC and 2 / 3VCC, resulting in instability and unpredictability in the output waveform.

[0003] There is currently no effective solution to the problem that traditional techniques struggle to generate stable and reliable sawtooth waves. Summary of the Invention

[0004] Therefore, it is necessary to provide a sawtooth wave circuit and a shielding system to address the aforementioned technical problems.

[0005] In a first aspect, this application provides a sawtooth wave circuit, which includes a timer chip and a charging / discharging circuit; the charging / discharging circuit is connected to the timer chip.

[0006] The timer chip is used to generate periodic charge and discharge control signals and transmit the charge and discharge control signals to the charge and discharge circuit.

[0007] The charging and discharging circuit is used to charge the energy storage capacitor of the charging and discharging circuit according to a preset charging rate based on the external DC voltage, driven by the charging and discharging control signal; and to discharge the energy storage capacitor according to a preset discharging rate when the voltage of the energy storage capacitor rises to a first voltage, so that the voltage of the energy storage capacitor drops to a second voltage and outputs a first sawtooth wave.

[0008] The preset discharge rate is greater than the preset charging rate; the second voltage is lower than the preset discharge cutoff voltage threshold.

[0009] In one embodiment, the sawtooth wave circuit further includes a waveform adjustment circuit; the waveform adjustment circuit is connected to the output terminal of the charging and discharging circuit.

[0010] The waveform adjustment circuit is used to modulate the first sawtooth wave to generate a second sawtooth wave that meets the preset waveform characteristics.

[0011] The peak-to-peak value of the second sawtooth wave is less than or equal to the peak-to-peak value of the first sawtooth wave.

[0012] In one embodiment, the charging and discharging circuit includes a first resistor, a second resistor, and an energy storage capacitor;

[0013] One end of the first resistor is used to connect to the external DC voltage, and the other end of the first resistor is connected to one end of the energy storage capacitor via the second resistor. The other end of the energy storage capacitor is grounded.

[0014] The connection point of the first resistor and the second resistor is connected to the discharge terminal of the timer chip;

[0015] The connection point of the energy storage capacitor and the second resistor is connected to the input terminal of the waveform adjustment circuit.

[0016] In one embodiment, the resistance value of the first resistor is greater than the resistance value of the second resistor;

[0017] The resistance value of the second resistor ranges from 0Ω to 30Ω;

[0018] The capacitance value of the energy storage capacitor ranges from 0.8nF to 1.05nF.

[0019] In one embodiment, the waveform adjustment circuit includes a voltage modulation circuit and a current modulation circuit; the input terminal of the voltage modulation circuit is connected to the output terminal of the charging and discharging circuit; the output terminal of the voltage modulation circuit is connected to the input terminal of the current modulation circuit; the output terminal of the current modulation circuit is used to output a second sawtooth wave that satisfies the preset waveform characteristics.

[0020] The voltage modulation circuit is used to digitally control the peak-to-peak value of the first sawtooth wave according to a preset peak-to-peak value, and output a third sawtooth wave.

[0021] The current modulation circuit is used to digitally control the DC component of the third sawtooth wave according to a preset DC quantity, and output the second sawtooth wave that satisfies the preset waveform characteristics.

[0022] In one embodiment, the voltage modulation circuit includes a first isolation circuit and a voltage divider circuit;

[0023] The first terminal of the first isolation circuit is connected to the output terminal of the charging and discharging circuit, the second terminal of the first isolation circuit is used to connect to the external DC voltage, the third terminal of the first isolation circuit is grounded, and the fourth terminal of the first isolation circuit is connected to the input terminal of the voltage divider circuit.

[0024] The output terminal of the voltage divider circuit is connected to the input terminal of the current modulation circuit.

[0025] In one embodiment, the first isolation circuit includes a transistor and a third resistor; the voltage divider circuit includes a fourth resistor and a first digitally controlled potentiometer.

[0026] The base of the transistor is connected to the output terminal of the charging and discharging circuit, the emitter of the transistor is connected to the external DC voltage through the third resistor, and the collector of the transistor is grounded.

[0027] One end of the fourth resistor is connected to the junction of the collector of the transistor and the third resistor, and the other end of the fourth resistor is connected to the input terminal of the first digitally controlled potentiometer.

[0028] The output terminal of the first digitally controlled potentiometer is connected to the input terminal of the current modulation circuit.

[0029] In one embodiment, the current modulation circuit includes a second isolation circuit, a DC isolation capacitor, a fifth resistor, and a bias adjustment circuit.

[0030] The input terminal of the second isolation circuit is connected to the output terminal of the voltage modulation circuit, and the output terminal of the second isolation circuit is connected to the bias adjustment circuit via the DC isolation capacitor and the fifth resistor.

[0031] The connection point between the DC isolation capacitor and the fifth resistor is used to output the second sawtooth wave that satisfies the preset waveform characteristics.

[0032] In one embodiment, the bias adjustment circuit includes a second digitally controlled potentiometer or a digital-to-analog converter.

[0033] Secondly, this application also provides a shielding system, which includes a voltage-controlled oscillator and a sawtooth wave circuit as described above; the sawtooth wave circuit is connected to the voltage-controlled oscillator.

[0034] The sawtooth wave circuit is used to generate a first sawtooth wave or a second sawtooth wave;

[0035] The voltage-controlled oscillator is used to generate a sweep frequency signal under the drive of the first sawtooth wave or the second sawtooth wave.

[0036] Thirdly, this application also provides a communication device, which includes the shielding system described above.

[0037] The aforementioned sawtooth wave circuit and shielding system include a timer chip and a charging / discharging circuit. The charging / discharging circuit is connected to the timer chip. The timer chip generates periodic charging / discharging control signals and transmits these signals to the charging / discharging circuit. Driven by the charging / discharging control signals, the charging / discharging circuit charges the energy storage capacitor of the charging / discharging circuit according to a preset charging rate based on the external DC voltage. When the voltage of the energy storage capacitor rises to a first voltage, it discharges at a preset discharging rate greater than the preset charging rate, causing the voltage of the energy storage capacitor to drop to a second voltage lower than a preset discharge cutoff voltage threshold, thereby outputting a first sawtooth wave with a slowly rising edge and a steep falling edge. For each cycle, by forcibly discharging the energy storage capacitor to below the preset discharge cutoff voltage threshold, the problem of discharge endpoint fluctuations caused by temperature drift, chip delay, etc., can be effectively avoided, improving the stability of the sawtooth wave valley and thus effectively improving the stability and anti-interference capability of the sawtooth wave. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a block diagram of a sawtooth wave circuit in one embodiment;

[0040] Figure 2 This is a schematic diagram of the capacitor discharge curve in one embodiment;

[0041] Figure 3 The waveform of the first sawtooth wave in one embodiment is shown.

[0042] Figure 4 Here is a block diagram of the sawtooth wave circuit in another embodiment;

[0043] Figure 5 This is a circuit diagram of a sawtooth wave circuit in one embodiment;

[0044] Figure 6 This is a block diagram of the sawtooth wave circuit in other embodiments. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0046] Currently, common frequency sweep signal generation schemes mostly use 555 architecture timer chips to generate square wave signals, and then use these square waves to drive subsequent NMOS switches to charge and discharge energy storage capacitors, thereby generating triangular wave signals. These triangular waves are further used to drive voltage-controlled oscillators (VCOs) to achieve frequency scanning (frequency sweep) functions. However, such schemes have several significant drawbacks: (1) Inconsistent frequency sweep timing: Using triangular wave signals for driving cannot guarantee that the sweep signals take the same amount of time when passing through the same frequency point, thus failing to guarantee the consistency of the sweep period at the same frequency point, affecting the shielding effect. (2) Mismatch between operating frequency and shielding efficiency: Only triangular wave signals with a fixed frequency (such as 100kHz) can be output, but in actual tests, it was found that the optimal sweep period for shielding efficiency is concentrated at 4.5μs. Within the 0.5μs range, the corresponding waveform frequency is 200kHz~250kHz; using a 100kHz signal to drive the VCO cannot cover this high-efficiency range, resulting in poor overall shielding performance. Although related technologies have attempted to directly generate triangular waves with frequencies higher than 200kHz, their waveform stability is poor. Under environmental changes such as high and low temperatures, the output frequency and peak-to-peak value are prone to drift, requiring the introduction of additional temperature compensation circuits, which increases system complexity and cost. (3) The waveform parameters are not adjustable, making it difficult to adapt to mass production and multi-scenario requirements: Most circuits currently use fixed resistor and capacitor parameters, resulting in the inability to dynamically adjust the peak-to-peak value and frequency range of the triangular wave. If adjustment is required, it usually relies on manually replacing resistors or adjusting voltages, which is cumbersome and inconsistent, and cannot meet the needs of automated production and large-scale deployment. (4) Using fixed electrical parameters makes it impossible to dynamically adjust the sweep bandwidth, which makes it difficult to accurately control the actual frequency range of the sweep signal output by the VCO: if the sweep range is too narrow, the shielding will be ineffective, and if it is too wide, it may interfere with adjacent channel communication or the normal operation of the base station.

[0047] In summary, the existing technologies have significant shortcomings in terms of waveform stability, frequency adaptability, environmental adaptability, and parameter adjustability, making it difficult to meet the core requirements of high-performance shielding systems for high-precision, high-stability, and configurable swept-frequency signals. To address these technical issues, a sawtooth wave circuit is proposed below.

[0048] In one embodiment, such as Figure 1 As shown, Figure 1 This is a block diagram of a sawtooth wave circuit in one embodiment; the sawtooth wave circuit includes a timer chip and a charging / discharging circuit; the charging / discharging circuit is connected to the timer chip.

[0049] The timer chip uses a standard 555 architecture. This timer chip can be, but is not limited to, NE555, SA555, or LM555, or other timer integrated circuits compatible with the 555 architecture. The timer chip generates periodic charge / discharge control signals and transmits these signals to the charge / discharge circuit. These control signals are used to control the charging and discharging state of the energy storage capacitor in the charge / discharge circuit.

[0050] It should be noted that a timer chip is a timer integrated circuit. The working principle of a timer chip can be understood by referring to existing technologies, and will not be elaborated upon here.

[0051] In an exemplary embodiment, taking the NE555 timer chip as an example, the discharge terminal (DISCH pin) of the NE555 chip is connected to the control terminal of the charging and discharging circuit, and is used to control the charging and discharging state of the energy storage capacitor in the charging and discharging circuit through the discharge terminal. Exemplarily, when the discharge terminal of the NE555 chip is turned on, the energy storage capacitor in the charging and discharging circuit is controlled to enter the discharging stage; when the discharge terminal of the NE555 chip is turned off, the energy storage capacitor in the charging and discharging circuit is controlled to enter the charging stage.

[0052] The charging and discharging circuit is used to charge the energy storage capacitor of the charging and discharging circuit according to a preset charging rate based on the external DC voltage under the drive of the charging and discharging control signal; when the voltage of the energy storage capacitor rises to a first voltage, the energy storage capacitor is discharged according to a preset discharging rate so that the voltage of the energy storage capacitor drops to a second voltage and a first sawtooth wave is output.

[0053] The frequency of the first sawtooth wave is greater than or equal to 200kHz.

[0054] The preset discharge rate is greater than the preset charging rate (i.e., the discharge time constant is less than the charging time constant). It should be noted that the preset charging rate during the charging phase and the preset discharge rate during the discharging phase are jointly determined by the capacitance value of the energy storage capacitor and the resistance value of the resistive elements in the charging and discharging circuit. When designing the preset discharge rate, it is necessary to ensure that the voltage of the energy storage capacitor rapidly decays to near zero during the discharge phase, thereby guaranteeing the stability of the first sawtooth wave trough level.

[0055] The first voltage is equal to 2 / 3 times the external DC voltage. The external DC voltage needs to be set according to actual needs and is not specifically limited here. For example, the external DC voltage can be 5V, and the first voltage is equal to 2 / 3 × 5V.

[0056] The second voltage is lower than the preset discharge cutoff voltage threshold. It should be noted that the preset discharge cutoff voltage threshold needs to be set based on the discharge characteristics of the energy storage capacitor and system tolerances; no specific limit is given here. The discharge process of the energy storage capacitor follows an exponential decay law (see...). Figure 2 This application discharges the voltage of the energy storage capacitor to below a preset discharge cutoff voltage threshold (e.g., the voltage value corresponding to time 3τ), aiming to reduce the sensitivity of the energy storage capacitor voltage to the discharge duration, even if the discharge time fluctuates in the nanosecond to microsecond range due to factors such as temperature drift and chip delay (e.g., in...). The voltage changes caused by fluctuations within the range are still within the system tolerance, thus effectively ensuring the stability of the first sawtooth wave trough level.

[0057] It should be noted that for the rising edge of the first sawtooth wave, based on the standard operating characteristics of the timer chip (such as the NE555 chip), natural clamping is achieved through the inherent threshold of its internal comparator (i.e., 2 / 3VCC), stabilizing the rising edge at this voltage level (i.e., the first voltage). For the falling edge of the first sawtooth wave, no active clamping is required. Instead, the discharge time constant is designed to be extremely small, allowing the energy storage capacitor to release approximately 95%–97% of its initial voltage within a very short time (i.e., an extreme discharge time constant), thus naturally decaying to near 0V (i.e., below the preset discharge cutoff voltage threshold). This design is because the response time required for the timer chip to detect a change in the energy storage capacitor voltage and trigger the internal discharge transistor to turn off and start the next charging cycle is on the same order of magnitude as the aforementioned discharge time constant. Therefore, when the voltage of the energy storage capacitor rapidly drops to near 0V, the state switch can be completed quickly, and the next charging cycle can begin promptly. Furthermore, the performance differences introduced by the timer chip due to process variations or temperature changes are mainly reflected in the slight fluctuations in its response time to voltage changes. Since the voltage of the energy storage capacitor has entered the exponential decay plateau region (close to 0V) at the end of its discharge, the voltage sensitivity to timing jitter is significantly reduced. Even if there is a nanosecond to microsecond deviation in the response time, the resulting trough voltage change is still within the system tolerance and can be ignored. In summary, discharging the energy storage capacitor to near 0V can effectively suppress the influence of chip individual differences and ambient temperature on the trough level, thereby ensuring the high stability of the first sawtooth wave trough level. At the same time, it can ensure that the frequency of the first sawtooth wave reaches above 200kHz, accurately covering the operating frequency band required for efficient shielding.

[0058] In one exemplary embodiment, the external DC voltage is denoted as VCC; the NE555 timer chip is used as an example for illustration, see [link to documentation]. Figure 3During each cycle, in the energy storage capacitor charging phase, the energy storage capacitor is charged through VCC according to a preset charging rate. Using the clamping function of the NE555 chip, the voltage of the energy storage capacitor (i.e., the high level of the first sawtooth wave) is clamped at the first voltage (i.e., 2 / 3VCC) to form a slowly rising edge. After the voltage of the energy storage capacitor reaches the first voltage, the NE555 chip triggers the energy storage capacitor to enter the discharge phase. The energy storage capacitor is discharged according to a preset discharge rate so that the voltage of the energy storage capacitor is discharged quickly (e.g., after 5 time constants, i.e., 5τ) to below the preset discharge cutoff voltage threshold (i.e., close to 0V), forming a steep falling edge, thereby obtaining a stable first sawtooth wave.

[0059] In this embodiment, a periodic charge / discharge control signal is generated by a timer chip and transmitted to the charge / discharge circuit. Driven by the charge / discharge control signal, the charge / discharge circuit charges the energy storage capacitor of the charge / discharge circuit according to a preset charging rate based on the external DC voltage. When the voltage of the energy storage capacitor rises to a first voltage, the energy storage capacitor is discharged at a preset discharge rate greater than the preset charging rate, so that the voltage of the energy storage capacitor drops to a second voltage lower than a preset discharge cutoff voltage threshold, thereby outputting a first sawtooth wave with a slowly rising edge and a steep falling edge. For each cycle, by forcibly discharging the energy storage capacitor to below the preset discharge cutoff voltage threshold, the problem of discharge endpoint fluctuation caused by temperature drift, chip delay, etc. can be effectively avoided, improving the stability of the sawtooth wave trough, thereby effectively improving the stability and anti-interference capability of the sawtooth wave.

[0060] To address the issue that traditional sawtooth wave generation circuits have fixed and difficult-to-adjust waveform parameters (such as peak-to-peak value and DC component), making them unsuitable for diverse applications and large-scale mass production, this paper proposes a sawtooth wave circuit that enables automated adjustment of waveform parameters. This aims to improve the adaptability and flexibility of the sawtooth wave circuit, avoiding the inconsistencies and low debugging efficiency caused by the cumbersome manual operation of replacing resistors and adjusting potentiometers in traditional solutions. This will better meet the actual needs of automated production, batch deployment, and diverse application scenarios.

[0061] In one embodiment, such as Figure 4 As shown, Figure 4 This is a block diagram of a sawtooth wave circuit in another embodiment; the sawtooth wave circuit also includes a waveform adjustment circuit; the waveform adjustment circuit is connected to the output terminal of the charging and discharging circuit;

[0062] A waveform adjustment circuit is used to modulate the first sawtooth wave to generate a second sawtooth wave that meets the preset waveform characteristics.

[0063] The peak-to-peak value of the second sawtooth wave is less than or equal to the peak-to-peak value of the first sawtooth wave.

[0064] The preset waveform characteristics need to be set according to the actual waveform requirements, and no specific limitations are made here.

[0065] In an exemplary embodiment, the waveform adjustment circuit is further configured to digitally control the peak-to-peak value of the first sawtooth wave according to a preset peak-to-peak value, and output a third sawtooth wave; and to digitally control the DC component of the third sawtooth wave according to a preset DC component, and output a second sawtooth wave that satisfies the preset waveform characteristics.

[0066] Among them, the preset peak-to-peak value and preset DC flow rate are related to the preset waveform characteristics and need to be set according to the actual waveform requirements. No specific limitations are made here.

[0067] It should be noted that the peak-to-peak value of the first sawtooth wave is equal to the voltage difference between the first voltage and the second voltage. The first voltage is equal to 2 / 3 VCC, and the second voltage is lower than the preset discharge cutoff voltage threshold (i.e., the second voltage is close to 0V). Therefore, the peak-to-peak value of the first sawtooth wave is close to 2 / 3 VCC, which is about twice the peak-to-peak value of the waveform generated by traditional timer chips (such as the NE555 chip) (theoretically 1 / 3 VCC). For example, in a 5V system, the peak-to-peak value of the first sawtooth wave can reach 3.3V, which can meet the needs of various applications without the need for additional amplification circuits for secondary amplification, effectively simplifying the circuit complexity.

[0068] In this embodiment, by introducing a waveform adjustment circuit into the sawtooth wave circuit, the waveform of the first sawtooth wave can be automatically modulated to generate a second sawtooth wave that meets the preset waveform characteristics. This effectively improves the adaptability and flexibility of the sawtooth wave circuit and avoids the defects of poor consistency and low debugging efficiency caused by the cumbersome operation of manually replacing resistors and adjusting potentiometers in traditional solutions. This better meets the actual needs of automated production, batch deployment and diverse application scenarios.

[0069] In one embodiment, such as Figure 5 As shown, Figure 5 This is a circuit diagram of a sawtooth wave circuit in one embodiment; the charging and discharging circuit includes a first resistor R1, a second resistor R2, and an energy storage capacitor C1;

[0070] One end of the first resistor R1 is used to connect to the external DC voltage VCC, and the other end of the first resistor R1 is connected to one end of the energy storage capacitor C1 through the second resistor R2. The other end of the energy storage capacitor C1 is grounded.

[0071] The connection point of the first resistor R1 and the second resistor R2 is connected to the discharge terminal DISCH of the timer chip.

[0072] The connection point of the energy storage capacitor C1 and the second resistor R2 is connected to the input terminal of the waveform adjustment circuit.

[0073] In this embodiment, the resistance of the first resistor R1 is greater than the resistance of the second resistor R2; the resistance of the second resistor R2 ranges from 0Ω to 30Ω; and the capacitance of the energy storage capacitor C1 ranges from 0.8nF to 1.05nF. In an exemplary embodiment, the resistance of the second resistor R2 can be 0Ω, 18Ω, or 30Ω; and the capacitance of the energy storage capacitor C1 can be 0.8nF, 1nF, or 1.05nF.

[0074] The resistance value of the first resistor R1 needs to be determined based on the preset waveform frequency, the resistance value of the second resistor R2, and the capacitance value of the energy storage capacitor C1. In an exemplary embodiment, the preset waveform frequency F = 1 / T, R1 >> R2, and the oscillation period T = (R1 + R2) × C1 × ln(3), which can be approximated as T = 1.1 × R1 × C1. With a preset waveform frequency of 200kHz... Taking a 5% value, a second resistor R2 of 18Ω, and an energy storage capacitor C1 of 1nF as an example, based on T = 1.1 × R1 × C1, the theoretical value of the first resistor R1 is approximately 4.55KΩ. However, since there is no precise 4.55KΩ value in standard resistors, actual measurements have verified that at a preset waveform frequency of 200kHz... With a 5% ohm requirement, a second resistor R2 of 18Ω, and an energy storage capacitor C1 of 1nF, a first resistor R1 of 3.6KΩ can output a stable first sawtooth wave. Actual testing has verified this. Figure 3 As shown.

[0075] In one specific embodiment, taking the NE555 timer chip as an example, the discharge process of the energy storage capacitor C1 follows an exponential decay law: Where: τ = R_total × C; R_total = R2 (i.e., the second resistor) + R_ds(on) (i.e., the on-resistance of the internal discharge transistor of the NE555 chip); (i.e., the initial voltage) ≈ 2 / 3 VCC; Assuming VCC = 5.0V, and the second resistor R2 is taken as 18Ω, the following relationship can be obtained: VCC = 5.0V; ≈2 / 3VCC≈3.333V; V_th_low (i.e., the toggle threshold of the lower comparator inside the NE555 chip) = 1 / 3VCC≈1.667V; C1=1nF; R2=18Ω; R_ds(on)≈30Ω; R_total=48Ω; τ=R_total×C=48ns; V_sat (i.e., the saturation voltage drop of the discharge tube)≈0.12V; In the test experiment, taking the range of t_delay (i.e., the detection and state switching delay of the internal circuit of the NE555 chip) as 70ns (-40℃) to 130ns (85℃) as an example, the following test results were obtained, as shown in Table 1.

[0076] Table 1

[0077]

[0078] Based on Table 1, the peak-to-peak deviation of the first sawtooth wave trough level over a wide temperature range does not exceed 0.032V. Compared with the peak-to-peak value of approximately 2 / 3VCC≈3.333V, the relative error is less than 1%. Therefore, the first sawtooth wave trough level has good stability over a wide temperature range and can be stabilized at around 0V.

[0079] In this embodiment, the resistance value of the first resistor R1 is set to be greater than that of the second resistor R2 (where the value of R2 ranges from 1 to 2). The capacitance of the energy storage capacitor C1 is set to 0.8 nF. Within the range of 1.05 nF, the discharge time constant of the charging and discharging circuit is much smaller than the charging time constant, which effectively accelerates the discharge process and ensures that the voltage of the energy storage capacitor decays rapidly to near 0V in the discharge phase of each cycle, thereby generating a steep falling edge. At the same time, it reduces the impact of temperature drift on the trough level and achieves high stability over a wide temperature range.

[0080] In one embodiment, such as Figure 6 As shown, Figure 6 The diagram shows the structural block diagram of the sawtooth wave circuit in other embodiments; the waveform adjustment circuit includes a voltage modulation circuit and a current modulation circuit; the input terminal of the voltage modulation circuit is connected to the output terminal of the charging and discharging circuit; the output terminal of the voltage modulation circuit is connected to the input terminal of the current modulation circuit; the output terminal of the current modulation circuit is used to output a second sawtooth wave that meets the preset waveform characteristics.

[0081] A voltage modulation circuit is used to digitally control the peak-to-peak value of the first sawtooth wave according to a preset peak-to-peak value, and output a third sawtooth wave.

[0082] The current modulation circuit is used to digitally control the DC component of the third sawtooth wave according to the preset DC quantity, and output a second sawtooth wave that meets the preset waveform characteristics.

[0083] Among them, the preset peak-to-peak value and preset DC flow rate are related to the preset waveform characteristics and need to be set according to the actual waveform requirements. No specific limitations are made here.

[0084] For example, the peak-to-peak value of the first sawtooth wave output by the charging and discharging circuit is digitally controlled (e.g., reduced or maintained) according to a preset peak-to-peak value by a voltage modulation circuit, so as to output a third sawtooth wave; then, the DC component of the third sawtooth wave is digitally controlled according to a preset DC component by a current modulation circuit, so as to output a second sawtooth wave that meets the preset waveform characteristics.

[0085] It should be noted that this application uses digital control to achieve waveform adjustment, which not only effectively avoids the problems of cumbersome operation, poor consistency and difficulty in mass production caused by relying on manual adjustment of resistors or potentiometers in traditional solutions, but also supports digital temperature compensation function, which can monitor the ambient temperature in real time and dynamically adjust waveform parameters (such as peak-to-peak value and DC bias) during system operation, thereby ensuring the high stability and accuracy of the second sawtooth wave over a wide temperature range.

[0086] In one embodiment, see Figure 5 The voltage modulation circuit includes a first isolation circuit and a voltage divider circuit. The first terminal of the first isolation circuit is connected to the output terminal of the charging / discharging circuit, the second terminal of the first isolation circuit is used to connect to an external DC voltage, the third terminal of the first isolation circuit is grounded, and the fourth terminal of the first isolation circuit is connected to the input terminal of the voltage divider circuit.

[0087] The output of the voltage divider circuit is connected to the input of the current modulation circuit.

[0088] The first isolation circuit provides electrical isolation, preventing subsequent circuits from interfering with the operation of the preceding circuits (timer chip and charging / discharging circuit), thus ensuring the stability and independence of the first sawtooth wave generation. The voltage divider circuit adjusts the amplitude of the first sawtooth wave, thereby achieving precise control over its peak-to-peak value.

[0089] In one exemplary embodiment, the first isolation circuit includes a transistor Q1 and a third resistor R3; wherein the transistor Q1 is a PNP transistor. The voltage divider circuit includes a fourth resistor R4 and a first digitally controlled potentiometer.

[0090] The base of transistor Q1 is connected to the output terminal of the charging and discharging circuit, the emitter of transistor Q1 is connected to the external DC voltage VCC through the third resistor R3, and the collector of transistor Q1 is grounded.

[0091] One end of the fourth resistor R4 is connected to the junction of the collector of transistor Q1 and the third resistor R3, and the other end of the fourth resistor R4 is connected to the input terminal (H pin) of the first digitally controlled potentiometer.

[0092] The output terminal (W pin) of the first digitally controlled potentiometer is connected to the input terminal of the current modulation circuit.

[0093] It should be noted that the SCL and SDA pins of the first digitally controlled potentiometer are used to connect to an external controller. This controller receives control commands via a preset communication protocol to achieve digital adjustment of the first digitally controlled potentiometer, thereby dynamically adjusting the output waveform parameters. The specific model of the first digitally controlled potentiometer can be selected according to actual needs and is not specifically limited here. By using the first digitally controlled potentiometer, not only is digital control of the sawtooth wave peak-to-peak value achieved, but digital temperature compensation is also realized, avoiding the additional hardware costs and design complexity introduced by relying on analog temperature compensation circuits in traditional solutions.

[0094] In one embodiment, to ensure reliable conduction of transistor Q1 (taking a silicon transistor as an example, its emitter-junction voltage drop VEB≈0.7V), the emitter voltage V of transistor Q1 must satisfy the following condition: V=VCC×R3 / (R3+R4+R 第一数控电位器 ≥ (2 / 3VCC + 0.7V); Based on actual testing, in a VCC = 5 V system, the resistance values ​​are: third resistor R3 = 1 KΩ, fourth resistor R4 = 5.1 KΩ, and the resistance of the first digitally controlled potentiometer R... 第一数控电位器 =10KΩ, which can meet the above voltage requirements.

[0095] In other embodiments, the resistance values ​​of the third resistor R3, the fourth resistor R4, and the first digitally controlled potentiometer need to be set according to different application requirements, and are not specifically limited here. It should be noted that if the value of the third resistor R3 is too small, it will have a certain impact on the charging and discharging circuit. During the design, it is necessary to ensure that the third resistor R3 is not less than 1KΩ.

[0096] It should be noted that since the peak-to-peak value of the first sawtooth wave output by the charging and discharging circuit can reach 2 / 3VCC, there is no need to configure an additional operational amplifier for preamplification in the voltage modulation circuit design process. Only the first digitally controlled potentiometer needs to be introduced to directly realize the digital adjustment of the amplitude, which greatly simplifies the structure of the waveform adjustment circuit and reduces the system complexity and cost.

[0097] In this embodiment, the first isolation circuit is formed by transistor Q1 and third resistor R3, which realizes electrical isolation between the front-end circuit and the back-end circuit. Furthermore, the voltage divider circuit is formed by fourth resistor R4 and first digitally controlled potentiometer. By digitally adjusting the resistance value of the first digitally controlled potentiometer, the voltage division ratio can be dynamically adjusted, thereby realizing precise control of the peak-to-peak value of the output sawtooth wave and temperature compensation.

[0098] In one embodiment, the current modulation circuit includes a second isolation circuit, a DC isolation capacitor C2, a fifth resistor R5, and a bias adjustment circuit.

[0099] The input terminal of the second isolation circuit is connected to the output terminal of the voltage modulation circuit, and the output terminal of the second isolation circuit is connected to the bias adjustment circuit through the DC isolation capacitor C2 and the fifth resistor R5.

[0100] The connection point of DC isolation capacitor C2 and fifth resistor R5 is used to output a second sawtooth wave that meets the preset waveform characteristics.

[0101] The second isolation circuit is used to increase the stability and driving capability of the third sawtooth wave, while also isolating the preceding and following circuits. The second isolation circuit may include, but is not limited to, integrated operational amplifier circuits, such as voltage followers. A DC isolation capacitor C2 is used to isolate the DC component in the third sawtooth wave. A bias adjustment circuit is used to provide a DC bias voltage that meets a preset DC quantity for the third sawtooth wave after the DC component is isolated.

[0102] The bias adjustment circuit includes a second digitally controlled potentiometer or a digital-to-analog converter. In some embodiments, the second digitally controlled potentiometer modulates the DC component, and the preset DC quantity is obtained by dividing the external DC voltage VCC through the second digitally controlled potentiometer; in other embodiments, a digital-to-analog converter (DAC) is used to directly output a DC bias voltage that meets the preset DC quantity.

[0103] In this embodiment, the bias adjustment circuit can be configured by an external main control chip through a digital interface without any manual intervention. This not only improves the efficiency and consistency of the adjustment and testing, but also completely avoids the problems of cumbersome operation, poor repeatability and difficulty in mass production caused by manual adjustment in traditional solutions, and supports a fully automated production and calibration process.

[0104] It should be noted that the sawtooth wave circuit of this application is constructed using general-purpose discrete components (such as resistors, capacitors, transistors, and timer chips), without relying on high-cost application-specific integrated circuits or complex analog modules (such as analog temperature compensation circuits). This effectively reduces circuit complexity and material costs, while simplifying circuit layout, reducing manufacturing difficulty and debugging cycle. It can be applied to different application scenarios, including but not limited to electromagnetic compatibility testing systems, radar frequency sweep sources, sensor excitation circuits, analog shielding circuits, and frequency sweep electromagnetic shielding systems.

[0105] In one embodiment, a shielding system is provided, the shielding system including a voltage-controlled oscillator and a sawtooth wave circuit described in any of the above embodiments; the sawtooth wave circuit is connected to the voltage-controlled oscillator;

[0106] A sawtooth wave circuit is used to generate a first sawtooth wave or a second sawtooth wave.

[0107] A voltage-controlled oscillator is used to generate a sweep frequency signal driven by a first sawtooth wave or a second sawtooth wave.

[0108] It should be noted that, under conventional design, the threshold voltages of the comparators inside 555 timer chips (such as the NE555 chip) are fixed at 1 / 3VCC and 2 / 3VCC, with a maximum output waveform frequency of 100kHz. However, actual shielding tests show that the optimal sweep cycle for shielding efficiency corresponds to a drive signal frequency of 200kHz to 250kHz. Conventional 555 solutions cannot stably output high-quality waveforms in this high-frequency range, making it difficult to cover the operating frequency band required for efficient shielding, thus limiting the overall system performance.

[0109] The sawtooth wave or second sawtooth wave output by the sawtooth wave circuit of this application can operate stably within the frequency range of 200kHz to 250kHz, accurately covering the operating frequency band required for efficient shielding. Simultaneously, it ensures that the voltage-controlled oscillator driven by it takes the same amount of time to pass the same frequency point during each frequency sweep, i.e., the dwell time at each frequency point is constant. This effectively avoids the problem of inconsistent frequency sweep cycles in traditional solutions, improving the repeatability, controllability, and interference suppression efficiency of the frequency sweep signal within the target frequency band. Furthermore, it operates over a wide temperature range (such as...). Within +50°C, the frequency deviation and peak-to-peak fluctuation of the first and second sawtooth waves can be stably controlled within the design tolerance range, thus effectively ensuring the timing reliability and performance consistency of the sweep signal output by the voltage-controlled oscillator.

[0110] It should be noted that the specific limitations of the sawtooth wave circuit in this embodiment can be referred to the limitations mentioned above, and will not be repeated here.

[0111] In this embodiment, the shielding system uses a sawtooth wave circuit to generate a high-frequency, highly stable, and highly anti-interference first or second sawtooth wave. The first or second sawtooth wave then drives a voltage-controlled oscillator to generate a sweep frequency signal, which effectively improves the shielding effect of the sweep frequency signal. This avoids the problems of sweep frequency cycle jitter and inconsistent frequency dwell time in traditional technologies, and enhances the stability and reliability of the sweep frequency signal.

[0112] In one embodiment, a communication device is also provided, which includes the shielding system described in the above embodiments. It should be noted that the specific limitations of the shielding system in this embodiment can be found in the limitations described above, and will not be repeated here.

[0113] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0114] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0115] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0116] It is understood that "at least one" means one or more, and "multiple" means two or more. "At least a part of an element" means part or all of an element. When used herein, the singular forms "a," "an," and "the" may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising / including" or "having," etc., specify the presence of the stated features, integrals, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integrals, steps, operations, components, parts, or combinations thereof. Meanwhile, the term "and / or" as used in this specification includes any and all combinations of the associated listed items.

[0117] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0118] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A sawtooth wave circuit, characterized in that, The sawtooth wave circuit includes a timer chip and a charging / discharging circuit; the charging / discharging circuit is connected to the timer chip. The timer chip is used to generate periodic charge and discharge control signals and transmit the charge and discharge control signals to the charge and discharge circuit. The charging and discharging circuit is used to charge the energy storage capacitor of the charging and discharging circuit according to a preset charging rate based on the external DC voltage, driven by the charging and discharging control signal; and to discharge the energy storage capacitor according to a preset discharging rate when the voltage of the energy storage capacitor rises to a first voltage, so that the voltage of the energy storage capacitor drops to a second voltage and outputs a first sawtooth wave. The preset discharge rate is greater than the preset charging rate; the second voltage is lower than the preset discharge cutoff voltage threshold.

2. The sawtooth wave circuit according to claim 1, characterized in that, The sawtooth wave circuit further includes a waveform adjustment circuit; the waveform adjustment circuit is connected to the output terminal of the charging and discharging circuit. The waveform adjustment circuit is used to modulate the first sawtooth wave to generate a second sawtooth wave that meets the preset waveform characteristics. The peak-to-peak value of the second sawtooth wave is less than or equal to the peak-to-peak value of the first sawtooth wave.

3. The sawtooth wave circuit according to claim 2, characterized in that, The charging and discharging circuit includes a first resistor, a second resistor, and an energy storage capacitor; One end of the first resistor is used to connect to the external DC voltage, and the other end of the first resistor is connected to one end of the energy storage capacitor via the second resistor. The other end of the energy storage capacitor is grounded. The connection point of the first resistor and the second resistor is connected to the discharge terminal of the timer chip; The connection point of the energy storage capacitor and the second resistor is connected to the input terminal of the waveform adjustment circuit.

4. The sawtooth wave circuit according to claim 3, characterized in that, The resistance of the first resistor is greater than the resistance of the second resistor; The resistance value of the second resistor ranges from 0Ω to 30Ω; The capacitance value of the energy storage capacitor ranges from 0.8nF to 1.05nF.

5. The sawtooth wave circuit according to claim 2, characterized in that, The waveform adjustment circuit includes a voltage modulation circuit and a current modulation circuit; the input terminal of the voltage modulation circuit is connected to the output terminal of the charging and discharging circuit; the output terminal of the voltage modulation circuit is connected to the input terminal of the current modulation circuit; the output terminal of the current modulation circuit is used to output a second sawtooth wave that satisfies the preset waveform characteristics. The voltage modulation circuit is used to digitally control the peak-to-peak value of the first sawtooth wave according to a preset peak-to-peak value, and output a third sawtooth wave. The current modulation circuit is used to digitally control the DC component of the third sawtooth wave according to a preset DC quantity, and output the second sawtooth wave that satisfies the preset waveform characteristics.

6. The sawtooth wave circuit according to claim 5, characterized in that, The voltage modulation circuit includes a first isolation circuit and a voltage divider circuit; The first terminal of the first isolation circuit is connected to the output terminal of the charging and discharging circuit, the second terminal of the first isolation circuit is used to connect to the external DC voltage, the third terminal of the first isolation circuit is grounded, and the fourth terminal of the first isolation circuit is connected to the input terminal of the voltage divider circuit. The output terminal of the voltage divider circuit is connected to the input terminal of the current modulation circuit.

7. The sawtooth wave circuit according to claim 6, characterized in that, The first isolation circuit includes a transistor and a third resistor; the voltage divider circuit includes a fourth resistor and a first digitally controlled potentiometer. The base of the transistor is connected to the output terminal of the charging and discharging circuit, the emitter of the transistor is connected to the external DC voltage through the third resistor, and the collector of the transistor is grounded. One end of the fourth resistor is connected to the junction of the collector of the transistor and the third resistor, and the other end of the fourth resistor is connected to the input terminal of the first digitally controlled potentiometer. The output terminal of the first digitally controlled potentiometer is connected to the input terminal of the current modulation circuit.

8. The sawtooth wave circuit according to claim 6, characterized in that, The current modulation circuit includes a second isolation circuit, a DC isolation capacitor, a fifth resistor, and a bias adjustment circuit. The input terminal of the second isolation circuit is connected to the output terminal of the voltage modulation circuit, and the output terminal of the second isolation circuit is connected to the bias adjustment circuit via the DC isolation capacitor and the fifth resistor. The connection point between the DC isolation capacitor and the fifth resistor is used to output the second sawtooth wave that satisfies the preset waveform characteristics.

9. The sawtooth wave circuit according to claim 8, characterized in that, The bias adjustment circuit includes a second digitally controlled potentiometer or a digital-to-analog converter.

10. A shielding system, characterized in that, The shielding system includes a voltage-controlled oscillator and a sawtooth wave circuit according to any one of claims 1 to 9; the sawtooth wave circuit is connected to the voltage-controlled oscillator. The sawtooth wave circuit is used to generate a first sawtooth wave or a second sawtooth wave; The voltage-controlled oscillator is used to generate a sweep frequency signal under the drive of the first sawtooth wave or the second sawtooth wave.

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