A PWM modulation method that balances computational efficiency and control precision

Abstract

The application discloses a PWM modulation method considering calculation efficiency and control accuracy, comprising: configuring a first clock and a second clock, the frequency of the first clock being higher than the frequency of the second clock; setting a target cumulative value; in each feedback cycle, performing the following operation: in a sampling cycle contained in the feedback cycle, using the first clock to accumulate a sampling signal, and when the cumulative sum reaches or exceeds the target cumulative value, recording the cumulative number; determining a duty cycle according to the ratio of the cumulative number to a cycle count value and latching; in at least one output cycle contained in the feedback cycle, using the second clock to output a PWM waveform according to the latched duty cycle; wherein the feedback cycle comprises one sampling cycle and at least one output cycle after the sampling cycle. The application decouples the sampling calculation process and the pulse output process in the time dimension by constructing two clock systems with different frequencies, so as to realize high-frequency and high-precision closed-loop power control under the condition of limited hardware resources.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit control technology, and in particular to a PWM modulation method that balances computational efficiency and control accuracy. Background Technology

[0002] Pulse Width Modulation (PWM) technology achieves precise control of the average power of the load by adjusting the ratio of the on and off time of switching devices. It is widely used in motor drives, power management, atomizer power regulation and other fields.

[0003] In atomizer applications, to achieve a fine and uniform atomization effect and avoid audible whistling noise, it is usually necessary to drive the atomizing plate or heating wire at a high frequency (e.g., above 20kHz). High-frequency PWM output places stringent demands on the real-time performance and computing power of the control system.

[0004] Traditional closed-loop PWM control methods typically follow this process: the analog-to-digital converter (ADC) periodically samples the load's operating parameters (such as voltage and current); the processor calculates the current power or RMS value based on the sampled values; the calculation result is compared with a preset target value, and a new duty cycle is calculated through a control algorithm; finally, the new duty cycle is updated to the PWM output module.

[0005] However, when the above traditional solution is applied to high-frequency PWM control scenarios, there are two prominent problems: First, there is an inherent contradiction between the sampling calculation speed and the PWM output frequency.

[0006] To achieve high-frequency PWM output, the PWM period is compressed to the microsecond level. Within this brief time window, a series of operations must be completed sequentially, including ADC sampling and conversion, processor data reading, power calculation, and duty cycle update. However, ADC conversion itself requires a certain settling and conversion time, and processor operations also consume instruction cycles. When the PWM frequency increases to a certain level, the duration of a single PWM cycle will be insufficient to complete a complete "sampling-calculation-update" closed-loop operation. If high-frequency output is forcibly maintained, the control loop will be unable to effectively adjust each PWM cycle, leading to output power deviations, response lag, or even oscillations, severely restricting the improvement of control accuracy. Secondly, the power calculation process consumes significant processor resources, making it difficult to meet the real-time requirements of high-frequency control.

[0007] Traditional methods for calculating average power or RMS value typically rely on multiplication and division operations. For resource-constrained microcontrollers, a single division operation can consume tens or even hundreds of clock cycles. In high-frequency control scenarios, repeatedly performing such complex operations within each PWM cycle or shorter cycles significantly consumes processor resources, preventing the system from completing the calculation task within the specified time limit. This not only limits further increases in PWM frequency but also makes it difficult for the processor to simultaneously respond to other real-time tasks, impacting the overall system performance and reliability.

[0008] In summary, how to overcome the contradiction between sampling calculation speed and PWM output frequency under the conditions of limited processor computing power and ADC conversion rate, and significantly reduce the processor resource occupation of the calculation process, so as to achieve accurate and stable closed-loop control of high-frequency PWM output, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0009] This invention proposes a PWM modulation method that balances computational efficiency and control accuracy, comprising: Configure a first clock and a second clock, wherein the frequency of the first clock is higher than the frequency of the second clock; Set a target cumulative value, which is proportional to the cycle count value of one output cycle; Within each feedback cycle, perform the following operations: Within the sampling period included in the feedback period, the sampled signal is accumulated using the first clock. When the accumulated sum reaches or exceeds the target accumulated value, the number of accumulations is recorded. The duty cycle is determined and latched based on the ratio of the accumulated number to the periodic count value; During at least one output cycle included in the feedback cycle, a PWM waveform is output using the second clock according to the latched duty cycle; The feedback period includes one sampling period and at least one output period following the sampling period.

[0010] Optionally, determining the duty cycle based on the ratio of the accumulated number to the period count value includes: If the number of accumulations is less than or equal to the period count value, then the ratio of the number of accumulations to the period count value is used as the duty cycle; If the number of accumulations is greater than the period count value, the duty cycle is 100%.

[0011] Optionally, configuring the first clock and the second clock includes: The minimum clock period of the second clock is determined based on the number of bits in the counter and the duration of the output period. The frequency division ratio is determined based on the minimum clock period of the second clock and the first clock. The first clock is divided according to the frequency division ratio to obtain the second clock.

[0012] Optionally, the sampling signal is determined according to the target operating mode: In average value mode, the sampled signal is a voltage sample value; In root mean square mode, the sampled signal is the square of the voltage sample value; In constant power mode, the sampling signal is the product of the voltage sample value and the current sample value.

[0013] Optionally, the target cumulative value is the product of the period count value and the single sampling target value; The single sampling target value Calculated using the following formulas respectively: Average value mode: ,in, The target average voltage is given by Ratio, where Ratio is the voltage sampling ratio and VREF is the ADC reference voltage. The number of bits in the ADC; Root mean square mode: ,in, The target average voltage is given by Ratio, where Ratio is the voltage sampling ratio and VREF is the ADC reference voltage. The number of bits in the ADC; Constant power mode: Where Pat is the target constant power value. Here, Ratio is the current scaling factor for the chip's internal circuitry, Ratio is the voltage sampling ratio, ref is the reference resistor for the current-to-voltage conversion, and VREF is the ADC reference voltage. The number of bits in the ADC.

[0014] Optionally, the cycle count value is determined by the product of the output cycle duration and the frequency of the second clock.

[0015] Optionally, the duty cycle, after being latched, remains unchanged in subsequent output cycles within the same feedback cycle until it is updated when the sampling cycle of the next feedback cycle is completed.

[0016] Optionally, the duration of the sampling period is not less than the duration of the output period.

[0017] Optionally, adjacent feedback cycles are independent of each other, and sampling, calculation, and duty cycle updates are re-executed in each feedback cycle. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram illustrating the steps of an embodiment of the PWM modulation method of the present invention, which balances computational efficiency and control precision. Figure 2 This is a schematic diagram of the steps of another embodiment of the PWM modulation method of the present invention that balances computational efficiency and control precision. Figure 3 A schematic diagram illustrating the steps of another embodiment of the PWM modulation method of the present invention, which balances computational efficiency and control precision; Figure 4 This is a timing diagram of an embodiment of the PWM modulation method of the present invention that balances computational efficiency and control precision.

[0020] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0023] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0024] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0025] This invention provides a PWM modulation method that balances computational efficiency and control precision. This method constructs two clock systems with different frequencies and decouples the sampling calculation process and the pulse output process in the time dimension, thereby achieving high-frequency, high-precision closed-loop power control under limited hardware resources.

[0026] In the first embodiment, as Figure 1 As shown, the PWM modulation method that balances computational efficiency and control accuracy includes: Configure a first clock and a second clock, wherein the frequency of the first clock is higher than the frequency of the second clock; Set a target cumulative value, which is proportional to the cycle count value of one output cycle; Within each feedback cycle, perform the following operations: Within the sampling period included in the feedback period, the sampled signal is accumulated using the first clock. When the accumulated sum reaches or exceeds the target accumulated value, the number of accumulations is recorded. The duty cycle is determined and latched based on the ratio of the accumulated number to the periodic count value; During at least one output cycle included in the feedback cycle, a PWM waveform is output using the second clock according to the latched duty cycle; The feedback period includes one sampling period and at least one output period following the sampling period.

[0027] It should be explained that this method involves two clock signals, referred to as the first clock and the second clock. The first clock has a higher frequency and a shorter clock period, primarily used to drive the accumulation and comparison operations of sampled values ​​to complete duty cycle related calculations in a short time. The second clock has a lower frequency and a relatively longer clock period, primarily used for timing division and counting of the pulse width modulation output waveform. The first and second clocks can be generated from the same system clock source using different frequency division coefficients, or they can be provided by independent clock sources, as long as there is a clear frequency relationship between them. The specific frequency values ​​of the first and second clocks are determined according to the actual output requirements.

[0028] A pulse width modulation (PWM) waveform consists of a series of repeating output cycles. Each output cycle corresponds to a complete switching cycle, and its duration is determined by the desired PWM frequency. For example, when a 20 kHz PWM signal is desired, each output cycle lasts 50 microseconds. Within an output cycle, the cycle is divided using the clock cycle of a second clock as the basic time unit; the number of divisions is called the cycle count. If the frequency of the second clock is 8 MHz, its clock cycle is 125 nanoseconds, and the aforementioned 50 microsecond output cycle is divided into 400 basic time units, resulting in a cycle count of 400. The cycle count represents the maximum resolution that allows for fine-grained pulse width adjustment within an output cycle. The larger the cycle count, the finer the duty cycle adjustment granularity. More specifically... Cycle count value: refers to the total number of segments into which the output cycle is divided, using the second clock cycle as the basic unit, within one output cycle. The cycle count value determines the resolution of PWM duty cycle adjustment, and its value is equal to the product of the output cycle duration and the second clock frequency.

[0029] High-level count count: This refers to the value latched into the PWM comparator register after the duty cycle is determined. Within one output cycle, when the PWM counter count is less than this high-level count count, the PWM output pin outputs a high level; otherwise, it outputs a low level. The ratio of the high-level count count to the cycle count value is the current duty cycle.

[0030] Single-sample value: refers to the digital quantity obtained from each sample within the sampling period, after undergoing mode-related calculations (such as voltage value in average mode, voltage square value in root mean square mode, and voltage-current product value in constant power mode). This value characterizes the relative amount of energy consumed by the load at the instant of a single sample.

[0031] Target total count: also known as the target cumulative value, is the digital threshold corresponding to the total energy expected to be output to the load within one output cycle. The target total count is equal to the product of the cycle count value and the single-sample target value.

[0032] This method introduces a "feedback cycle" as the basic working unit of the control loop. A feedback cycle consists of a sampling period and at least one output period following that sampling period. In other words, the feedback cycle comprises consecutive "sampling phases" and "output phases".

[0033] The sampling period is a dedicated time window for signal acquisition, accumulation calculation, and duty cycle determination. During the sampling period, the system does not immediately reflect the calculation results in the pulse width modulation output; instead, it focuses on completing the calculation task. The output period is the time window for actually generating and outputting the pulse width modulation waveform. During the output period, the system continuously generates the pulse waveform based on the previously determined and latched duty cycle parameters, without performing complex sampling and calculations. A feedback period can contain multiple output periods. For example, within a feedback period, a calculation is first completed using one sampling period, and then the duty cycle obtained from this calculation is used for output in the following ten output periods. When the next feedback period arrives, sampling and calculation are re-executed, and the duty cycle is updated.

[0034] This time-separation method separates "computation" and "output" in time, so that the computation process is no longer limited by the short duration of a single output cycle, and the output process is no longer interrupted by waiting for the computation result.

[0035] Before performing any calculations, a target cumulative value needs to be preset. The target cumulative value is a digital threshold corresponding to the physical quantity to be output (such as average voltage, RMS voltage, or constant power). The target cumulative value is proportional to the cycle count value of one output cycle.

[0036] Specifically, the target cumulative value is equal to the product of the cycle count value and a preset single-sample target value. The single-sample target value is obtained by quantizing the target physical quantity, and its determination method will be explained in detail later in conjunction with the specific working mode. The physical meaning of the target cumulative value is: the total number of "energy particles" that the system expects to output to the load within the time length of one output cycle.

[0037] During the sampling period, the system operates at high speed for the first clock cycle. For each sampled signal value, the system treats it as an addend and continuously accumulates it into an accumulator. The sampled signal value mentioned here, depending on the actual operating mode, can be a directly acquired voltage value, the square of the voltage value, or the product of the voltage and current values. Regardless of the signal form, its essence represents the relative magnitude of the power or energy gained or consumed by the load at that instant.

[0038] The accumulation operation is repeated at the frequency of the first clock cycle. After each accumulation of a sampled signal value, the system compares the current accumulated sum with a pre-set target accumulated value. When the accumulated sum first reaches or exceeds the target accumulated value, accumulation stops, and the total number of accumulations performed from the start to this point is recorded. It is important to note that the above accumulation and comparison process only involves addition and numerical comparison operations, and does not involve complex multiplication or division operations. The high frequency of the first clock cycle ensures that the accumulation process can be completed in a very short time, and the bit width of the accumulator can be reasonably set according to the maximum value of the target accumulated value to avoid the risk of overflow.

[0039] The recorded number of accumulations physically represents the "energy share" contributed by the number of sampling cycles required under the current sampling conditions to accumulate the target total energy needed to reach one output cycle. The number of accumulations is inversely related to the real-time operating state of the load. When the actual power consumed by the load is large, the single sampled signal value is large, and fewer accumulations are required; when the actual power consumed by the load is small, the single sampled signal value is small, and more accumulations are required.

[0040] After obtaining the accumulated count, the accumulated count is compared with the cycle count value of one output cycle to determine the duty cycle.

[0041] If the accumulated count is less than or equal to the period count, the duty cycle is determined by the ratio of the accumulated count to the period count. In practical digital pulse width modulation implementations, this means that within one output cycle, the number of clock cycles in which the second clock signal continuously outputs a high level is the accumulated count, and the remaining clock cycles output a low level. If the accumulated count is greater than the period count, it means that under the current load conditions, even if the output level is high for the entire output cycle (i.e., the duty cycle is 100%), the output energy is still insufficient to reach the desired energy represented by the target accumulated value. In this case, the duty cycle is determined to be 100%, meaning that the entire output cycle outputs a high level.

[0042] It should be noted that the ratio of the accumulated count to the period count is the logical basis for determining the duty cycle, but in actual execution, it is not necessary to actually perform a division once in each feedback cycle. The accumulated count itself directly corresponds to the number of clock cycles of the second clock with the high-level output, so it can be directly used as the comparison threshold of the pulse width modulation counter. The calculated duty cycle parameter (specifically, the number of high-level counts) is latched into a register. The latching operation means that this value is held for a period of time and does not change with the instantaneous fluctuations of the sampled signal.

[0043] After the sampling period ends, the feedback period enters the output phase. This phase contains at least one output cycle. Within each output cycle, the system uses a second clock as the counting clock to drive a counter to increment from zero. In each second clock cycle, the current count value is compared to the number of times the latched high-level count has occurred. When the count value is less than the latched value, the pulse width modulation output pin outputs a high level; when the count value reaches or exceeds the latched value, the output pin toggles low. When the count value reaches the cycle count value, the current output cycle ends, the counter is reset to zero, and the next output cycle begins, continuing to use the same latched value for waveform generation. The same latch duty cycle parameter is reused throughout all output cycles contained in the entire feedback cycle. This duty cycle remains unchanged until the sampling period of the next feedback cycle completes the new calculation and updates the latched value.

[0044] As can be seen from the above process, sampling, accumulation, and comparison calculations are all completed within the sampling period using a high-frequency first clock. Since the duration of the sampling period can encompass the length of multiple output periods, the calculation process gains ample time, completely eliminating the limitation of a single output period. Simultaneously, the output of the pulse width modulation waveform is driven by a lower-frequency second clock, and its output frequency is determined by both the second clock and the period count value, reaching tens of kilohertz or even higher, and the output process is completely unaffected by the sampling calculation time.

[0045] In terms of computing resources, the duty cycle is determined through accumulation and comparison, replacing the division operation frequently used in traditional schemes. For resource-constrained microcontrollers, the clock cycles consumed by addition and comparison operations are far less than those of division operations. Therefore, this method significantly reduces the requirements for processor computing power, enabling even low-computing-power chips to support high-frequency, high-precision closed-loop pulse width modulation control.

[0046] In terms of output stability, since the duty cycle is latched during the feedback period, instantaneous disturbances and noise of the sampled signal will not cause frequent fine-tuning of the duty cycle. The pulse width modulation waveform remains stable within one feedback period, effectively reducing switching losses and suppressing electromagnetic interference and mechanical noise caused by waveform jitter.

[0047] In summary, this method, through timing decoupling and accumulation comparison mechanism, achieves high-frequency output, high-precision control, and low computational resource consumption under limited hardware resource constraints. It is particularly suitable for applications such as atomizers that have high requirements for pulse width modulation frequency and control stability.

[0048] In the second embodiment, as Figure 2 As shown, determining the duty cycle based on the ratio of the accumulated count to the period count value includes: If the number of accumulations is less than or equal to the period count value, then the ratio of the number of accumulations to the period count value is used as the duty cycle; If the number of accumulations is greater than the period count value, the duty cycle is 100%.

[0049] It needs to be explained that within the sampling period, the sampled signal value is accumulated by the first clock drive. When the accumulated sum first reaches or exceeds the target accumulated value, the total number of accumulations is recorded as n. As mentioned earlier, the period count value N is the number of parts into which one output period is divided by the clock period of the second clock, representing the full-scale range of the duty cycle adjustment. The determination of the duty cycle needs to be handled according to the relative magnitude of n and N.

[0050] When the calculated cumulative count n is less than or equal to the cycle count N, it indicates that under the current load condition, by outputting a high level for n second clock cycles within one output cycle, the accumulated output energy can reach the desired energy represented by the target cumulative value. In this case, the duty cycle is the ratio of n to N. In the specific implementation of digital pulse width modulation (PWM), the duty cycle is not necessarily calculated and stored as a percentage, but is directly expressed as the number of continuous high-level clock cycles n. The PWM counter starts counting from zero in each output cycle. When the count value is less than n, it outputs a high level; when the count value is greater than or equal to n, it outputs a low level, until the count value reaches N, at which point it resets, completing one output cycle.

[0051] Since n is a dynamic value obtained by accumulating actual samples within the sampling period, its magnitude is inversely related to the actual power consumption of the load. When the load power is large, the value of a single sampled signal is large, and the number of accumulations n required to reach the target cumulative value is small, corresponding to a lower duty cycle; conversely, when the load power is small, n increases, and the duty cycle increases. This relationship ensures the negative feedback characteristic of the closed-loop control, making the output power approach the preset target value.

[0052] Under certain operating conditions, the calculated number of accumulations, n, may be greater than the cycle count value, N. The physical reason for this is that the actual power consumed by the load is too low, or the target cumulative value is set relatively high. Specifically, if the value of a single sampled signal is small, even if each sampled signal value is accumulated N times (equivalent to all outputs being high-level within one output cycle), the accumulated sum still fails to reach or exceed the target cumulative value. In this case, if the duty cycle is calculated according to the ratio of n to N, a value greater than 100% will be obtained, which is physically meaningless because the maximum duty cycle of pulse width modulation (PWM) is 100%. Therefore, when it is determined that the number of accumulations, n, is greater than the cycle count value, N, the duty cycle is directly determined to be 100%. This means that in subsequent output cycles, the PWM output pin will continuously output a high level without any high-low level switching, and the load will operate at maximum available power. Although the actual output energy is still lower than the expected energy corresponding to the target cumulative value, it cannot be further increased due to the system's maximum output capability.

[0053] In practical circuit implementation, the comparison between the accumulation count n and the period count N can be accomplished by a hardware comparator or a software conditional judgment. Once it is confirmed that n is greater than N, the high-level count latched in the duty cycle register is set to N, thus outputting a high level throughout the output cycle. This processing method also does not involve complex division operations, only adding one numerical comparison operation, and its impact on system resources is negligible.

[0054] By handling the two scenarios described above separately, the duty cycle determination process can achieve precise adjustment within the normal operating range, and provide reasonable saturated output behavior when the load or target value exceeds the system's adjustment capability, thus ensuring the stability and predictability of the closed-loop control system across the entire operating range.

[0055] In one example, such as Figure 3 As shown, configuring the first clock and the second clock includes: The minimum clock period of the second clock is determined based on the number of bits in the counter and the duration of the output period. The frequency division ratio is determined based on the minimum clock period of the second clock and the first clock. The first clock is divided according to the frequency division ratio to obtain the second clock.

[0056] It should be explained that, as mentioned earlier, this method involves two clock signals of different frequencies, where the first clock has a higher frequency and the second clock has a lower frequency. In practical system implementation, the first clock is usually directly taken from the system's master clock or its multiplier, while the second clock is obtained by dividing the first clock. The choice of the division factor directly affects the frequency accuracy of the second clock, and thus affects the accuracy of the pulse width modulation output frequency and the utilization efficiency of the counter resources.

[0057] This example provides a method for determining the division ratio, which can select a suitable division ratio for the second clock under a given counter bit width constraint, so as to balance frequency control accuracy and hardware resource consumption.

[0058] Specifically, in the pulse width modulation (PWM) output stage, a counter is used to count the clock cycles of the second clock to generate the timing within one output cycle. The bit width of the counter determines its maximum count value, i.e., the upper limit of the number of second clock cycles that can be accommodated within one output cycle. Let the duration of the output cycle be T, which is determined by the target PWM frequency; for example, for a 20 kHz output frequency, T is 50 microseconds. If the counter's bit width is x bits, its maximum count value is 2 to the power of x minus 1. To be able to count a complete output cycle, the duration of a single second clock cycle cannot be less than the quotient of T divided by the counter's maximum count value. This yields the minimum clock cycle of the second clock, i.e., the minimum allowed value for the second clock cycle. Based on this minimum clock cycle of the second clock and the known period of the first clock, an upper limit for the division ratio can be calculated. The division ratio must be chosen as an integer value greater than or equal to this upper limit; otherwise, the counter will overflow within a single output cycle, resulting in an abnormal output waveform.

[0059] After satisfying the basic constraint of preventing counter overflow, the optimal selection of the division ratio is further considered. For a given output cycle length T and a first clock cycle, the ideal division ratio should ensure that the second clock cycle is an integer multiple of T, meaning T is exactly equal to the second clock cycle multiplied by a certain integer. This integer is the aforementioned cycle count value N. However, in practical systems, the first clock frequency and the desired output cycle length often cannot directly form a strict integer multiple relationship. In this case, it is necessary to select the division ratio from the available division configuration options that minimizes the deviation between the actual cycle count value and the ideal cycle count value. This process can be achieved by iterating through several division levels supported by the system, calculating the corresponding actual output frequency or actual output cycle length, and comparing it with the target value. For example, assuming the system clock is 16 MHz and the desired output is a 20 kHz pulse width modulation signal, i.e., an output cycle of 50 microseconds, the available division levels supported by the system include divide-by-two, divide-by-four, divide-by-eight, and divide-by-sixteen. Calculate the second clock cycle and the corresponding cycle count value for each frequency division level, compare the actual output cycle with fifty microseconds, and select the one with the smallest deviation as the final frequency division configuration.

[0060] In summary, the configuration process for the first and second clocks can be summarized as follows: First, based on the counter's bit width and the target output period's duration, determine the minimum allowable value for the second clock period, i.e., the minimum clock period of the second clock; second, based on the minimum clock period of the second clock and the period of the first clock, calculate the range of values ​​for the division ratio; third, among the available division ratios supported by the system, select the division ratio that minimizes the deviation between the actual output period and the target output period; finally, divide the first clock according to the selected division ratio to generate the second clock signal.

[0061] The above configuration process can be completed in one go during system initialization, without the need for dynamic adjustments during operation. The resulting second clock signal remains stable throughout the entire operation, providing an accurate time base reference for the pulse width modulation output.

[0062] In the second embodiment, the sampling signal is determined according to the target operating mode: In average value mode, the sampled signal is a voltage sample value; In root mean square mode, the sampled signal is the square of the voltage sample value; In constant power mode, the sampling signal is the product of the voltage sample value and the current sample value.

[0063] It should be noted that this embodiment supports flexible selection of average value mode, root mean square mode, or constant power mode as the target mode for power control, depending on actual application requirements. In different operating modes, the sampled signals used for accumulation calculation have different physical meanings and calculation methods.

[0064] In average value mode, the control objective is for the average voltage across the load to reach a preset value. In this mode, the sampling signal is directly taken from the voltage sample value acquired by the analog-to-digital converter (ADC). This voltage sample value is a digital quantity quantized by the ADC, representing the instantaneous voltage amplitude across the load. Within the sampling period, the system continuously reads the voltage sample value at the first clock cycle and accumulates it in the accumulator.

[0065] In RMS mode, the control objective is for the effective value (RMS value) of the voltage across the load to reach a preset value. According to electrical engineering principles, the effective voltage value is proportional to the square root of the average of the squares of the voltages. Since the square root calculation is relatively complex, and within the cumulative comparison framework of this method, only the consistency of the energy equivalence relationship needs to be ensured, the sampled signal is the square of the voltage sample value. The square of the voltage sample value can be obtained through a hardware multiplier or software multiplication. Accumulating the squared value as the sampled signal essentially accumulates energy; when the accumulated sum reaches the target cumulative value, the corresponding effective voltage value reaches the preset target.

[0066] In constant power mode, the control objective is to keep the actual power consumed by the load constant. According to the definition of electrical power, power equals the product of voltage and current. Therefore, the sampling signal is the product of the voltage sample value and the current sample value. The voltage sample value is obtained by an analog-to-digital converter (ADC) acquiring and quantizing the voltage across the load terminals, while the current sample value is obtained by an ADC acquiring and quantizing a sampled voltage proportional to the load current; this sampled voltage is typically provided by a current sampling resistor or a current-sensing amplifier. The product of the voltage and current sample values ​​can be obtained using a hardware multiplier. This product is accumulated as a sample signal; the sum represents the cumulative amount of energy actually consumed by the load. When the sum reaches the target cumulative value, the corresponding average power reaches the preset target constant power value.

[0067] In this way, the three operating modes are unified into the same accumulation and comparison framework. Regardless of the mode used, the operation within the sampling period is the same: acquire the sampled signal value of the corresponding mode, accumulate it to the accumulator over the first clock cycle, and compare it with the target accumulated value. This uniformity simplifies the hardware implementation and maintains a high degree of consistency in the software logic; only different signal paths and multiplier enablements need to be configured according to the selected mode during the initialization phase.

[0068] As mentioned earlier, the target cumulative value is proportional to the cycle count value of one output cycle, specifically the product of the cycle count value and the single-sample target value. The cycle count value N is determined by the output cycle duration and the second clock frequency, as explained previously and will not be repeated here. The following focuses on the method for determining the single-sample target value under different operating modes. The single-sample target value is a quantified representation of the "energy reference" that can be contributed by a single sample after converting the target physical quantity value of the desired output (such as the target average voltage, target RMS voltage, target constant power value) to the digital domain. Its calculation involves parameters such as the reference voltage of the analog-to-digital converter, the resolution bit depth, and the scaling factor of the sampling circuit.

[0069] For ease of explanation, the following symbol definitions are introduced: VREF represents the reference voltage of the analog-to-digital converter (ADC). When the ADC quantizes the input analog voltage into a digital value, the full-scale input voltage corresponds to the maximum digital output value. For an ADC with N_adc bits, its maximum digital output value is 2 to the power of N_adc. Ratio represents the voltage sampling ratio. In practical circuits, the voltage across the load is typically attenuated by a resistor divider network before being fed into the ADC's input channel.

[0070] Ratio is defined as the attenuation ratio of the voltage divider network, that is, the ratio between the actual load voltage and the sampling voltage sent to the analog-to-digital converter.

[0071] M_IL represents the scaling factor of the current sampling channel. In constant power mode, the load current is converted into a voltage signal through the sampling resistor, and may be processed by amplification or attenuation circuits before being sent to the analog-to-digital converter. M_IL comprehensively reflects the current-to-voltage conversion factor and the gain or attenuation of subsequent signal conditioning circuits, and its dimension is the ratio of voltage to current.

[0072] ref represents the reference resistor value for the current-to-voltage conversion. In the current sampling loop, the load current flows through this reference resistor, generating a voltage drop, which is then sampled by the analog-to-digital converter.

[0073] In average value mode, the control objective is for the load average voltage to reach the target average voltage. Single sample target value. The calculation formula is: ,in, The target average voltage is given by Ratio, where Ratio is the voltage sampling ratio and VREF is the ADC reference voltage. The number of bits in the ADC.

[0074] The physical meaning of this formula is as follows: The target average voltage is converted to the equivalent voltage at the input of the analog-to-digital converter (ADC), and then divided by the ADC's minimum resolution voltage (i.e., VREF divided by 2 to the power of N_adc). This yields the expected digital output value of the ADC corresponding to the target voltage. This expected value is the single-sample target value. Furthermore, multiplying the single-sample target value by the period count value yields the target cumulative value in average mode.

[0075] In RMS mode, the control objective is for the effective value of the load voltage to reach the target average voltage. (Target value for a single sample) The calculation formula is: ,in, The target average voltage is given by Ratio, where Ratio is the voltage sampling ratio and VREF is the ADC reference voltage. The number of bits in the ADC; The physical meaning of this formula is as follows: First, the target root-mean-square voltage is squared, and then converted into the expected square value in the digital domain of the analog-to-digital converter using the same conversion logic as the average value mode. Since the sampled signal is the square of the voltage sample value, the target value for a single sample also corresponds to the expected square value. Furthermore, multiplying the target value for a single sample by the period count value yields the target cumulative value in the root-mean-square mode.

[0076] In constant power mode, the control objective is for the load power consumption to reach a target constant power value. (Single sample target value) The calculation formula is: Where Pat is the target constant power value. Here, Ratio is the current scaling factor for the chip's internal circuitry, Ratio is the voltage sampling ratio, ref is the reference resistor for the current-to-voltage conversion, and VREF is the ADC reference voltage. The number of bits in the ADC.

[0077] The physical meaning of this formula is as follows: The target constant power value, combined with the scaling factor M_IL of the current sampling channel, the voltage sampling ratio Ratio, the current sampling reference resistor ref, and the analog-to-digital converter reference voltage VREF, is uniformly converted into the expected digital value of the product of the voltage sample value and the current sample value. Since the sampled signal is the product of the voltage sample value and the current sample value, the single-sample target value corresponds to the expected value of the product. Furthermore, multiplying the single-sample target value by the period count value yields the target cumulative value in constant power mode.

[0078] The parameters involved in the above formulas, including Ratio, VREF, N_adc, M_IL, and ref, are all known constants determined by the system hardware circuit design, or non-volatile stored parameters that can be written through factory calibration. The target average voltage and target constant power values ​​are set by the user or the upper-level control program according to specific application requirements. In actual implementation, the multiplication, division, and exponentiation operations in the formulas can be completed once during system initialization. After calculating the single-sample target value, it is stored in a register and used directly during operation without repeated calculations. This approach of pre-processing complex calculations during the initialization phase further reduces the processor load during operation.

[0079] By defining corresponding sampling signal formats and single-sample target values ​​for different operating modes, this embodiment incorporates average value control, root mean square (RMS) control, and constant power control into a unified accumulation and comparison framework. Regardless of the mode used, the core control logic remains unchanged; only the mode selection parameters and corresponding target values ​​need to be configured during the initialization phase. This uniformity significantly reduces the complexity of software development and hardware design. Simultaneously, the pre-calculation mechanism of the single-sample target value allows complex dimensional conversions and scaling to be completed during the initialization phase. During operation, only simple accumulation and comparison operations are required, ensuring the real-time performance of high-frequency closed-loop control. Especially in constant power mode, the real-time calculation of the voltage-current product is performed by a hardware multiplier, and the accumulation and comparison are driven by a fast clock. The entire control loop can complete a complete feedback calculation in a very short time, resulting in fast response and high control accuracy.

[0080] In one example, the cycle count value is determined by the product of the output cycle duration and the frequency of the second clock.

[0081] It's important to explain that the cycle count directly determines the precision of the duty cycle adjustment, i.e., the resolution of the pulse width modulation (PWM). Let the duration of the output cycle be T, in seconds. T is determined by the desired PWM output frequency f_PWM, and the two are reciprocals of each other; that is, T equals 1 divided by f_PWM. For example, when a 20 kHz PWM signal needs to be output, f_PWM is 20 kHz, and the corresponding output cycle duration T is 50 microseconds.

[0082] Let the frequency of the second clock be f_pwmclk, in Hertz (Hz). The clock period t_pwmclk of the second clock is the reciprocal of f_pwmclk, that is, t_pwmclk equals 1 divided by f_pwmclk. For example, when the frequency of the second clock is eight MHz, its clock period is one hundred and twenty-five nanoseconds.

[0083] The cycle count value N is the ratio of the output cycle duration T to the second clock cycle t_pwmclk, which is also the product of T and f_pwmclk. This can be expressed as: N equals T multiplied by f_pwmclk.

[0084] Ideally, the output cycle duration T and the second clock cycle t_pwmclk are exactly integer multiples of each other, meaning T is divisible by t_pwmclk. At this point, the cycle count N is an integer value, and the pulse width modulation counter counts from zero to N minus 1. The boundary of each output cycle is strictly aligned with the clock cycle of the second clock, resulting in a stable and jitter-free output waveform.

[0085] In practical systems, due to limitations in the available clock source frequency and division configuration options, the output cycle duration T and the second clock cycle t_pwmclk may not form a strictly integer multiple relationship. In this case, the calculated result of T multiplied by f_pwmclk is not an integer, but a value with a decimal part.

[0086] Since pulse width modulation counters can only count integers, the calculation results need to be rounded. This is typically done by rounding to the nearest integer or rounding down, converting the theoretical non-integer count into a usable integer period count value N. The rounding operation introduces a small frequency deviation, but as long as the second clock frequency is sufficiently high relative to the output frequency (i.e., the period count value N is large enough), the impact of this deviation on the actual output frequency can be controlled within acceptable limits.

[0087] As described in the previous embodiments, the target cumulative value is equal to the product of the cycle count value N and the single-sample target value. Therefore, the cycle count value N acts as a scaling factor, amplifying the target expected value at the single-sample level to the target cumulative value at the entire output cycle level. When the cycle count value N changes due to adjustments in the output frequency or the second clock frequency, the target cumulative value also changes proportionally, thereby maintaining the consistency of the control target.

[0088] This example establishes a clear mapping between clock parameters and control parameters by directly associating the cycle count value with the output cycle duration and the second clock frequency. This allows system designers to quickly determine the required frequency division configuration and counter parameters based on the desired output frequency and available clock resources.

[0089] In the third embodiment, recording the number of accumulations when the sum reaches or exceeds the target cumulative value includes: During the sampling period, the cumulative count counter increments by 1 each time the quantized value of the sampled signal is acquired. The quantized value of the sampled signal is accumulated into the accumulation register; Compare the value in the accumulator register with the target accumulated value; When the value in the accumulator register is greater than or equal to the target cumulative value for the first time, the accumulator stops accumulating, and the value of the accumulator counter at this time is taken as the accumulator count.

[0090] It should be explained that within the sampling period, the system needs to determine whether the current accumulated sum has reached or exceeded the target accumulated value, and record the required number of accumulations. To facilitate numerical comparison and counting, both the target accumulated value and the value of each sampled signal are uniformly quantized into the digital domain of the analog-to-digital converter and expressed in the form of "counts".

[0091] The target total count, also known as the aforementioned target cumulative value, is the equivalent count value in the digital domain of the analog-to-digital converter (ADC) of the total energy expected to be output to the load within one output cycle. The target total count is obtained based on hardware parameters such as the voltage sampling ratio, the ADC reference voltage, and the ADC bit depth, calculated in conjunction with preset physical quantity target values. The specific determination method has been detailed in the preceding embodiments and will not be repeated here.

[0092] A single sampling value is the equivalent count value of the sampled signal value obtained at each sampling moment in the digital domain of the analog-to-digital converter. Depending on the operating mode, the single sampling value may correspond to a single voltage sample value, the square of the voltage sample value, or the product of the voltage sample value and the current sample value. Regardless of the mode, the single sampling value characterizes the relative magnitude of the energy absorbed or consumed by the load at the instant of sampling, and its dimensions are consistent with the target total count, allowing for direct numerical comparison between the two.

[0093] To achieve unified quantization of the target total count and the single sample value, both are calculated based on the same set of analog-to-digital converter parameters, which include the voltage sampling ratio Ratio, the analog-to-digital converter reference voltage VREF, and the number of bits N_adc of the analog-to-digital converter.

[0094] The voltage sampling ratio (Ratio) defines the attenuation factor between the actual load voltage and the sampled voltage fed into the analog-to-digital converter (ADC) input. The ADC reference voltage (VREF) defines the analog voltage value corresponding to the full-scale input of the ADC. The ADC bit depth (N_adc) defines the resolution of the digital output; the full-scale digital value is 2 raised to the power of N_adc.

[0095] During system initialization, the target physical quantity is converted into the target total count using the aforementioned parameters and stored in a register. During operation, each original digital quantity output by the analog-to-digital converter undergoes mode-dependent operations (such as squaring or multiplication) to obtain a single sample value with dimensions consistent with the target total count. Since both are based on the same reference standard, the process of the accumulator accumulating the single sample value and comparing it with the target total count has clear physical meaning: comparing whether the actual accumulated energy has reached the desired total output energy.

[0096] Within the sampling period, the system repeatedly performs the following operations at the first clock cycle: acquire the current sample value, accumulate it to the accumulator, and compare the accumulated sum with the target total count. When the accumulated sum first reaches or exceeds the target total count, accumulation stops, and the current accumulation count n is recorded. Mathematically, the accumulation count n satisfies the following conditions: the sum of n minus one accumulation is less than the target total count, while the sum of n accumulations is greater than or equal to the target total count. Specifically, the accumulator increments by one sample value each time, and the accumulation count increments by one simultaneously. When the accumulated sum crosses the threshold of the target total count, the current accumulation count is the desired result.

[0097] Furthermore, since the accumulated count n will eventually be latched into the pulse width modulation output module as the high-level count count, and the maximum value of n is limited by the period count value N, when n exceeds N, it will be limited to N. Therefore, the small energy overshoot caused by the rounding operation will be naturally cut off when the output is saturated, and will not cause the output to run out of control.

[0098] This embodiment quantizes the target cumulative value and the sampled signal value into a count value based on the same set of analog-to-digital converter parameters, and implicitly implements a rounding operation during the accumulation and comparison process. This method achieves accurate determination of the accumulation count with extremely low hardware overhead. The process requires only an adder, an accumulation register, and a comparator, without the need for a divider, making it particularly suitable for resource-constrained microcontrollers or application-specific integrated circuits. Simultaneously, the rounding operation ensures that the control energy is not lower than the target expected value, guaranteeing the steady-state accuracy of the closed-loop control.

[0099] In the fourth embodiment, after the duty cycle is latched, it remains unchanged in subsequent output cycles within the same feedback cycle until it is updated when the sampling cycle of the next feedback cycle is completed.

[0100] It's easy to understand that the purpose of latching is to fix the result calculated within the sampling period, making it unaffected by fluctuations in the external sampling signal for a subsequent period. Since the sampling signal originates from the analog quantity acquired by the analog-to-digital converter, thermal noise, power supply ripple, and electromagnetic interference are unavoidable in analog circuits. These interferences cause slight jitter in the sampled signal value near the true value. If the instantaneous result of each sampling calculation were directly updated to the pulse width modulation output module in real time, the duty cycle would fluctuate frequently, causing instability in the output energy and potentially exciting parasitic oscillations in the circuit, generating audible noise and additional electromagnetic radiation. Through the latching mechanism, the duty cycle is updated only once in each feedback cycle, effectively filtering out the influence of sampling noise on the output.

[0101] Within a feedback cycle, one or more output cycles follow the sampling cycle. In all these output cycles, the pulse width modulation output module reads the same duty cycle parameter from the latch register and generates the pulse waveform accordingly.

[0102] Duty cycle updates occur only at the boundaries of feedback cycles. A new sampling cycle begins when one feedback cycle ends and the next begins. Within this new sampling cycle, the system re-executes sampling, accumulation, and comparison operations to calculate a new accumulation count adapted to the current load state, thereby determining the new duty cycle parameter. The new duty cycle parameter is written to the latch register at the end of the current sampling cycle, overwriting the old value.

[0103] From a timing perspective, the duty cycle update frequency is equal to the feedback cycle frequency. The length of the feedback cycle can be flexibly configured according to application requirements, and is usually set as the sum of the sampling period and the duration of several output cycles. In scenarios such as atomizers where high power stability is required, the feedback cycle can be set to the millisecond level, corresponding to a duty cycle update frequency of hundreds of hertz to thousands of hertz, while the pulse width modulation output frequency can reach tens of kilohertz.

[0104] It is important to note that during the first feedback cycle immediately after system startup, before the sampling cycle begins, the latch register may not yet contain a valid duty cycle value. In this case, a default safe duty cycle value, such as zero or a small initial value, can be preset during the initialization phase to ensure that unexpected overdrive does not occur in the output stage before the first sampling cycle is completed. Once the first sampling cycle is completed and the valid duty cycle is calculated, this default value is overwritten, and the system enters normal closed-loop control. Similarly, when the system receives a stop command, the duty cycle value in the latch register can be cleared after the last feedback cycle ends, or the output can be forcibly set to a low level to ensure safe load shutdown.

[0105] In one example, such as Figure 4 As shown, the duration of the sampling period is not less than the duration of the output period.

[0106] It should be noted that, as mentioned earlier, one feedback cycle includes one sampling cycle. Figure 4 S and at least one output period following that sampling period, such as Figure 4 In this context, N1 and N2 represent the output period within adjacent feedback periods. The sampling period is a dedicated time window used for signal acquisition, accumulation calculation, and duty cycle determination, while the output period is the basic periodic unit that actually generates and outputs the pulse width modulation waveform. The relative relationship between the two in terms of duration directly affects the performance and feasibility of the control system.

[0107] During the sampling period, the system needs to perform the following operations sequentially or cyclically: First, the analog-to-digital converter (ADC) needs to sample and convert the input analog signal. The ADC process itself includes multiple stages such as sample-and-hold, successive approximation, or integral conversion, each of which consumes a certain number of clock cycles. Second, the converted digital quantity needs to be processed according to the current operating mode. For example, in the root mean square mode, a squaring operation is required, and in the constant power mode, a voltage-current multiplication operation is required. Third, the processed sampled signal value needs to be accumulated to the accumulator, and the accumulated sum is compared with the target accumulated value. Finally, when the accumulation condition is met, the number of accumulations needs to be recorded, the duty cycle calculated, and the result written to the latch register.

[0108] In the series of operations described above, the time consumed by analog-to-digital conversion (ADC) is usually the main bottleneck. Taking a typical successive approximation ADC as an example, the time required to complete one full conversion is its conversion clock cycle multiplied by its resolution bits. For example, a 10-bit resolution ADC with a conversion clock of 2 MHz will take approximately five microseconds for a single conversion. Furthermore, if the system has only one ADC module and needs to acquire multiple signals within the sampling period (such as acquiring voltage and current signals in constant power mode), the total ADC time will increase exponentially. Considering that multiple sampling and accumulation may be required within the sampling period to reach the target cumulative value, and that a comparison and judgment must be made after each accumulation, the sampling period must allow sufficient time margin to ensure that all these operations can be completed within the specified time window.

[0109] In contrast, the operation within the output cycle is extremely simple. During the output cycle, the system only needs to drive the counter to increment by the second clock cycle and compare the count value with the number of latched high-level counts to determine the high or low level state of the output pin. This process is purely hardware-based and does not involve analog-to-digital conversion, multiplication operations, or complex software judgments.

[0110] Because the tasks performed during the sampling period are far more demanding than those during the output period, forcing the sampling period to be shorter than the output period—meaning all sampling and calculation operations must be completed within a shorter time window than the output period—may lead to the following problems: the analog-to-digital conversion may not be complete before the accumulation calculation is interrupted; or the accumulation count may not reach the target cumulative value before the sampling period ends, resulting in the current feedback period failing to generate a valid duty cycle update value. This will prevent the closed-loop control from functioning properly.

[0111] Therefore, setting the sampling period to be no less than the output period is a necessary condition to ensure that the system can reliably complete closed-loop control. When the sampling period is equal to the output period, the system performs a complete sampling and calculation before each output period, and the duty cycle is updated synchronously with the output frequency. This is suitable for scenarios with extremely high requirements for dynamic response speed. When the sampling period is longer than the output period, the system performs sampling and calculation only every few output periods, and the duty cycle update frequency is lower than the output frequency. This is suitable for scenarios with high requirements for output stability and moderate requirements for dynamic response speed, such as the power control of atomizers.

[0112] This example, by explicitly constraining the sampling period to be no less than the output period, ensures at the architectural level that both the sampling calculation process and the pulse width modulation output process have time resources commensurate with their task complexity. The sampling period is given ample time to complete accurate signal acquisition and energy accumulation, guaranteeing the accuracy and reliability of the duty cycle calculation results; while the output period remains extremely short, achieving high-frequency pulse width modulation output, balancing control precision and output frequency.

[0113] In another example, adjacent feedback cycles are independent of each other, and sampling, calculation, and duty cycle updates are re-executed in each feedback cycle.

[0114] It should be noted that the independence between adjacent feedback cycles does not contradict the latching of the duty cycle within the same feedback cycle in the aforementioned embodiments. The two describe the behavioral characteristics at different time dimensions.

[0115] Within the same feedback cycle, the duty cycle is latched at the end of the sampling cycle and remains constant throughout all subsequent output cycles. This is a short-timescale stability design aimed at filtering out sampling noise and ensuring the smoothness of the output waveform.

[0116] Between adjacent feedback cycles, the entire sampling and calculation process is re-executed in each feedback cycle, and the duty cycle is updated cycle by cycle as the load condition changes. This is a long-term responsive design designed to enable the system to track changes in load condition and environmental conditions and adjust the output accordingly.

[0117] The combined effect of these two factors enables the control system to maintain stable output in the short term and to respond to changes in operating conditions in the long term.

[0118] Designing adjacent feedback cycles to be independent of each other, rather than continuously adjusting based on the calculation results of the previous cycle, has the following technical significance.

[0119] First, it avoids error accumulation. If continuous adjustment is used, the duty cycle of the current cycle is fine-tuned based on the previous cycle's duty cycle. This causes quantization errors from the analog-to-digital converter and calculation deviations introduced by sampling noise to gradually accumulate over time, potentially leading to the duty cycle deviating from the correct value and causing long-term drift in output power. However, with each feedback cycle, the accumulation calculation restarts. Errors from a single calculation do not propagate to the next cycle. The system makes independent judgments based on real-time sampled data within each feedback cycle, eliminating the error accumulation path.

[0120] Secondly, it enhances the robustness of the system. In real-world working environments, load conditions may change abruptly for various reasons, such as temperature variations in the atomizing plate causing resistance drift, or a gradual decrease in power supply voltage due to battery discharge. If a continuous adjustment method relying on historical conditions is used, the system needs several adjustment cycles to adapt to new operating conditions, and the response speed is limited by the convergence rate of the adjustment algorithm. However, by using an independent cycle-by-cycle recalculation method, the duty cycle of each feedback cycle is directly determined by the real-time sampled data within that cycle. The response to sudden changes in operating conditions lags only by one feedback cycle, resulting in a much faster response speed.

[0121] Third, it simplifies the control logic. Since each feedback cycle starts from zero and performs accumulation and comparison, there is no need to maintain cross-cycle state variables or design complex integral or derivative adjustment algorithms, making the control logic simple and clear. This not only reduces the complexity of software implementation but also reduces the risk of control instability due to program errors.

[0122] The above description is merely an optional embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A PWM modulation method that balances computational efficiency and control accuracy, characterized in that, include: Configure a first clock and a second clock, wherein the frequency of the first clock is higher than the frequency of the second clock; Set a target cumulative value, which is proportional to the cycle count value of one output cycle; Within each feedback cycle, perform the following operations: Within the sampling period included in the feedback period, the sampled signal is accumulated using the first clock. When the accumulated sum reaches or exceeds the target accumulated value, the number of accumulations is recorded. The duty cycle is determined and latched based on the ratio of the accumulated number to the periodic count value; During at least one output cycle included in the feedback cycle, a PWM waveform is output using the second clock according to the latched duty cycle; The feedback period includes one sampling period and at least one output period following the sampling period.

2. The PWM modulation method that balances computational efficiency and control accuracy as described in claim 1, characterized in that, Determining the duty cycle based on the ratio of the accumulated count to the period count value includes: If the number of accumulations is less than or equal to the period count value, then the ratio of the number of accumulations to the period count value is used as the duty cycle; If the number of accumulations is greater than the period count value, the duty cycle is 100%.

3. The PWM modulation method that balances computational efficiency and control accuracy as described in claim 2, characterized in that, The configuration of the first clock and the second clock includes: The minimum clock period of the second clock is determined based on the number of bits in the counter and the duration of the output period. The frequency division ratio is determined based on the minimum clock period of the second clock and the first clock. The first clock is divided according to the frequency division ratio to obtain the second clock.

4. The PWM modulation method that balances computational efficiency and control accuracy as described in any one of claims 1 to 3, characterized in that, The sampling signal is determined according to the target operating mode: In average value mode, the sampled signal is a voltage sample value; In root mean square mode, the sampled signal is the square of the voltage sample value; In constant power mode, the sampling signal is the product of the voltage sample value and the current sample value.

5. The PWM modulation method that balances computational efficiency and control accuracy as described in claim 4, characterized in that, The target cumulative value is the product of the period count value and the single sampling target value; The single sampling target value Calculated using the following formulas respectively: Average value mode: ,in, The target average voltage is given by Ratio, where Ratio is the voltage sampling ratio and VREF is the ADC reference voltage. The number of bits in the ADC; Root mean square mode: ,in, The target average voltage is given by Ratio, where Ratio is the voltage sampling ratio and VREF is the ADC reference voltage. The number of bits in the ADC; Constant power mode: Where Pat is the target constant power value. Here, Ratio is the current scaling factor for the chip's internal circuitry, Ratio is the voltage sampling ratio, ref is the reference resistor for the current-to-voltage conversion, and VREF is the ADC reference voltage. The number of bits in the ADC.

6. The PWM modulation method that balances computational efficiency and control accuracy as described in claim 4, characterized in that, The cycle count value is determined by the product of the output cycle duration and the frequency of the second clock.

7. The PWM modulation method balancing computational efficiency and control accuracy as described in any one of claims 1 to 3, characterized in that, Once the duty cycle is latched, it remains unchanged in subsequent output cycles within the same feedback cycle until it is updated when the sampling cycle of the next feedback cycle is completed.

8. The PWM modulation method that balances computational efficiency and control accuracy as described in claim 7, characterized in that, The duration of the sampling period is not less than the duration of the output period.

9. The PWM modulation method that balances computational efficiency and control accuracy as described in claim 7, characterized in that, Adjacent feedback cycles are independent of each other, and sampling, calculation and duty cycle update are re-executed in each feedback cycle.

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