Control circuit for programmable soft start and multiplexing of a synchronous external reference source function
By designing an internal bandgap reference circuit and a buffer control circuit, and utilizing the TRK pin to achieve programmable soft-start and synchronous external reference source functions, the problem of high pin packaging cost in traditional designs is solved, realizing function reuse and cost reduction.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI BEILING
- Filing Date
- 2026-04-01
- Publication Date
- 2026-07-14
AI Technical Summary
In the traditional ACOT architecture, programmable soft-start and synchronous external reference source functions need to be implemented through two separate pins, resulting in high pin packaging costs.
Through the design of the internal bandgap reference circuit, buffer control circuit and comparator, the TRK pin is used to realize the multiplexing of programmable soft start and synchronous external reference source functions. After receiving the internal reference voltage, the buffer control circuit realizes the function multiplexing through the TRK pin and voltage buffer circuit. The comparator is used to control the duty cycle of the switching transistor.
It achieves programmable soft-start and synchronous external reference source functions through a single external pin, reducing packaging costs and offering a simple and easy-to-implement structure.
Smart Images
Figure CN122394540A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design, and in particular to a control circuit for programmable soft-start and synchronous external reference source function multiplexing. Background Technology
[0002] The design circuit that multiplexes the functions of programmable soft-start and synchronous external reference source under the traditional ACOT (Adaptive On-Time) architecture BUCK, such as... Figure 1 As shown, the soft-start function uses the internal constant current source Iss to charge the capacitor at the SS soft-start pin, generating a slowly rising ramp voltage that replaces the internal reference source VREF. This ramp voltage is then compared with the FB voltage to generate a PWM_SHOT signal to control the duty cycle of the switching transistor, thereby controlling the inductor current and the output voltage VO to rise slowly. Synchronization with the external reference source relies on the internal reference source output VREF being connected to an external reference voltage source via an external pin. The external reference voltage is directly used to replace VREF and sent to the COMP comparator, where it is compared with the FB voltage to control the duty cycle of the switching transistor, thus achieving synchronization with the external reference source.
[0003] The internal soft-start time expression for the circuit design is: tss = Css_int * VREF / Is s The externally programmable soft-start uses a large external capacitor connected to the external SS soft-start pin. By changing the charging slope of the capacitor at the SS pin, the voltage rise rate at the SS pin is controlled, thus achieving the purpose of externally programmable soft-start. The external soft-start time expression is: tss = (Css_int + Css_ext) * VREF / Iss, where Css_int represents the internal soft-start capacitor, Css_ext represents the external soft-start capacitor, and Iss represents the soft-start charging current.
[0004] However, traditional circuit designs have limitations; the two functions of programmable soft-start and synchronous external reference source require two separate pins ( Figure 1 The SS and VREF pins shown in the diagram are required to achieve this, and it is impossible to achieve both functions with just one pin, resulting in high pin packaging costs. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to overcome the defect that the two functions of programmable soft start and synchronous external reference source cannot be implemented through a single pin, resulting in high pin packaging cost, and to provide a control circuit that multiplexes programmable soft start and synchronous external reference source functions.
[0006] The present invention solves the above-mentioned technical problems through the following technical solution:
[0007] In a first aspect, the present invention provides a control circuit for programmable soft-start and synchronous external reference source function multiplexing, the control circuit comprising: an internal bandgap reference circuit, a buffer control circuit, a comparator and a Buck loop, the buffer control circuit comprising a TRK pin and a voltage buffer circuit;
[0008] The input terminal of the buffer control circuit is electrically connected to the output terminal of the internal bandgap reference circuit, the output terminal of the buffer control circuit is electrically connected to the positive input terminal of the comparator, and the output terminal of the Buck loop is electrically connected to the negative input terminal of the comparator.
[0009] The internal bandgap reference circuit is used to input an internal reference voltage into the buffer control circuit;
[0010] The buffer control circuit is used to receive the internal reference voltage and then, through the TRK pin and the voltage buffer circuit, multiplex the programmable soft-start function and the function of synchronizing the external reference source.
[0011] The comparator is used to compare the voltage value of the TRK pin with the feedback voltage of the Buck loop and output a control signal to control the duty cycle of the switching transistor.
[0012] Preferably, the buffer control circuit further includes a programmable soft-start circuit;
[0013] The output terminal of the voltage buffer circuit, the input terminal of the programmable soft-start circuit, and the TRK pin are electrically connected; the output terminal of the programmable soft-start circuit is electrically connected to the positive input terminal of the comparator.
[0014] The voltage buffer circuit is used to clamp the voltage value of the TRK pin to be the same as the internal reference voltage when using the internal reference source function.
[0015] Under the programmable soft-start function, when the voltage value of the TRK pin is less than the threshold voltage, the external soft-start capacitor in the programmable soft-start circuit is charged with constant current to generate a new linear soft-start voltage to replace the internal reference voltage; when the voltage value of the TRK pin is between the threshold voltage and the internal reference voltage, the external soft-start capacitor in the programmable soft-start circuit is charged with transconductance converter current to control the voltage value of the TRK pin to slowly rise until it is the same as the internal reference voltage;
[0016] The voltage buffer circuit is also used to control the voltage value of the TRK pin to be the same as that of the external reference source under the function of synchronizing the external reference source.
[0017] Preferably, the voltage buffer circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a third PMOS transistor, a second NMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fifth PMOS transistor, a fourth NMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a seventh PMOS transistor;
[0018] The source of the second PMOS transistor and the source of the third PMOS transistor are electrically connected to the drain of the first PMOS transistor. The gate of the second PMOS transistor is electrically connected to the output terminal of the internal bandgap reference circuit. The drain of the second PMOS transistor is electrically connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is grounded.
[0019] The drain of the third PMOS transistor is electrically connected to the drain of the second NMOS transistor, and the gate of the third PMOS transistor is electrically connected to the drain of the fifth PMOS transistor; the source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is electrically connected to the gate of the third NMOS transistor.
[0020] The source of the fourth PMOS transistor is electrically connected to the source of the first PMOS transistor, the source of the fifth PMOS transistor, and the source of the sixth PMOS transistor; the gate of the fourth PMOS transistor and the gate of the sixth PMOS transistor are electrically connected to the gate of the fifth PMOS transistor; the drain of the fourth PMOS transistor is electrically connected to the drain of the third NMOS transistor; and the source of the third NMOS transistor is grounded.
[0021] The drain of the fifth PMOS transistor is electrically connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is grounded.
[0022] The drain of the sixth PMOS transistor is electrically connected to the drain of the fifth NMOS transistor and the drain of the sixth NMOS transistor, and the source of the sixth PMOS transistor is grounded; the gate of the sixth NMOS transistor and the gate of the eighth NMOS transistor are electrically connected to the gate of the seventh NMOS transistor, the source of the sixth NMOS transistor is electrically connected to the drain of the seventh NMOS transistor, the source of the seventh NMOS transistor is electrically connected to the drain of the eighth NMOS transistor, and the source of the eighth NMOS transistor is grounded;
[0023] The drain of the seventh PMOS transistor is electrically connected to the drain of the fourth NMOS transistor, the gate of the seventh PMOS transistor is electrically connected to the inverter, the drain of the seventh PMOS transistor is electrically connected to the drain of the fifth PMOS transistor, and the source of the seventh PMOS transistor is electrically connected to the internal constant current source.
[0024] Preferably, the programmable soft-start circuit further includes an internal soft-start capacitor;
[0025] One end of the internal soft-start capacitor is electrically connected to the positive input terminal of the comparator and the TRK pin, one end of the external soft-start capacitor is electrically connected to the TRK pin, and the other ends of both the external soft-start capacitor and the internal soft-start capacitor are grounded.
[0026] Preferably, the TRK pin is floating when using the internal reference source function.
[0027] Preferably, the TRK pin is electrically connected to the external soft-start capacitor in the programmable soft-start function.
[0028] Preferably, the TRK pin is electrically connected to an external reference source when the external reference source synchronization function is enabled.
[0029] Preferably, the threshold voltage is 0.9 times the internal reference voltage.
[0030] Preferably, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the first NMOS transistor, the fourth NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor together constitute a standard voltage buffer of the OTA structure;
[0031] Preferably, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the first NMOS transistor, the fifth NMOS transistor, the eighth NMOS transistor, the seventh NMOS transistor, the sixth NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth PMOS transistor, and the sixth PMOS transistor together constitute a threshold voltage comparator.
[0032] The significant advantages of this invention are as follows: It provides a control circuit that multiplexes programmable soft-start and synchronous external reference source functions. An internal bandgap reference circuit inputs an internal reference voltage to a buffer control circuit. Upon receiving the internal reference voltage, the buffer control circuit uses the TRK pin and a voltage buffer circuit to multiplex the programmable soft-start and synchronous external reference source functions. A comparator compares the voltage value at the TRK pin with the feedback voltage of the Buck loop and outputs a control signal to control the duty cycle of the switching transistor. This invention achieves both programmable soft-start and synchronous external reference source functions simultaneously through a single external pin, reducing packaging costs and offering a simple and easy-to-implement structure. Attached Figure Description
[0033] Figure 1 A control circuit that reuses the programmable soft-start and synchronous external reference source functions in existing technologies.
[0034] Figure 2 This is a schematic diagram of the first circuit of the control circuit for programmable soft start and synchronous external reference source function multiplexing in Embodiment 1 of the present invention.
[0035] Figure 3 This is a schematic diagram of the second circuit of the control circuit for programmable soft start and synchronous external reference source function multiplexing in Embodiment 1 of the present invention.
[0036] Figure 4 This is a schematic diagram of the simulated current curve of the TRK pin of the standard voltage buffer of the OTA structure of the control circuit for programmable soft start and synchronous external reference source function multiplexing in Embodiment 1 of the present invention.
[0037] Figure 5 This is a schematic diagram of the soft-start waveform of the control circuit for programmable soft-start and synchronous external reference source function multiplexing in Embodiment 1 of the present invention. Detailed Implementation
[0038] The present invention will be further illustrated by way of embodiments below, but the present invention is not limited to the scope of the embodiments described herein.
[0039] Example 1
[0040] like Figure 2 As shown, this embodiment provides a control circuit for programmable soft-start and synchronous external reference source function multiplexing. The control circuit includes: an internal bandgap reference circuit 11, a buffer control circuit 12, a comparator 13 and a Buck loop 14. The buffer control circuit 12 includes a TRK pin 121 and a voltage buffer circuit 122.
[0041] The input terminal of the buffer control circuit 12 is electrically connected to the output terminal of the internal bandgap reference circuit 11, the output terminal of the buffer control circuit 12 is electrically connected to the positive input terminal of the comparator 13, and the output terminal of the Buck loop 14 is electrically connected to the negative input terminal of the comparator 13.
[0042] The internal bandgap reference circuit 11 is used to input the internal reference voltage to the buffer control circuit 12;
[0043] The buffer control circuit 12 is used to multiplex the programmable soft-start function and the synchronization of the external reference source function through the TRK pin 121 and the voltage buffer circuit 122 after receiving the internal reference voltage.
[0044] Comparator 13 is used to compare the voltage value of the TRK pin with the feedback voltage of the Buck loop 14 and output a control signal to control the duty cycle of the switching transistor.
[0045] In this embodiment, after receiving the internal reference voltage VREF output by the internal bandgap reference circuit 11, the buffer control circuit 12 sends the voltage value of the output TRK pin to the positive input of the comparator 13 through a TRK pin 121. This is based on the design logic of the internal reference source function, the programmable soft-start function, and the synchronous external reference source function, and multiplexing the programmable soft-start function and the synchronous external reference source function. After the programmable soft-start function ends, the comparator 13 controls the Buck loop according to the comparison result between the voltage value of the TRK pin 121 and the feedback voltage FB. This method completely solves the problem that in traditional structures, the programmable soft-start function requires the introduction of an SS pin, and the synchronous external reference source function requires the introduction of a VREF pin to achieve both functions simultaneously. It is impossible to achieve function multiplexing by introducing only one external pin, reducing packaging costs and simplifying the structure for easy implementation.
[0046] It should be noted that Buck loop 14 is a control loop commonly found in Buck converters in the prior art, as shown in this embodiment. Figure 2 As shown, the Buck loop 14 may include a PWM_SHOT control signal source, a TON_SHOT control signal source, a Logic & Driver circuit, a PMOS transistor, an NMOS transistor, and a C... out The capacitor, L inductor, Rbt1, and Rbt2 are feedback voltage divider resistors. The FB feedback node outputs a feedback voltage to comparator 13. The specific circuit structure of the Buck loop 14 can be adjusted according to the actual situation and is not subject to specific restrictions.
[0047] In one embodiment, such as Figure 2 As shown, the buffer control circuit 12 also includes a programmable soft-start circuit 123;
[0048] The output of the voltage buffer circuit 122 and the input of the programmable soft-start circuit 123 are electrically connected to the TRK pin 121, and the output of the programmable soft-start circuit 123 is electrically connected to the positive input of the comparator 13.
[0049] The voltage buffer circuit 122 is used to clamp the voltage value of the TRK pin 121 to be the same as the internal reference voltage when using the internal reference source function.
[0050] Under the programmable soft-start function, when the voltage value of TRK pin 121 is less than the threshold voltage, the external soft-start capacitor in the programmable soft-start circuit is charged with constant current to generate a new linear soft-start voltage to replace the internal reference voltage; when the voltage value of TRK pin 121 is between the threshold voltage and the internal reference voltage, the external soft-start capacitor in the programmable soft-start circuit is charged with transconductance converter current to control the voltage value of TRK pin 121 to slowly rise until it is the same as the internal reference voltage.
[0051] The voltage buffer circuit 122 is also used to control the voltage value of the TRK pin 121 to be the same as the external reference source in the synchronous external reference source function.
[0052] The programmable soft-start circuit 123 also includes an internal soft-start capacitor;
[0053] One end of the internal soft-start capacitor is electrically connected to the positive input terminal of the comparator 13 and the TRK pin 121. One end of the external soft-start capacitor is electrically connected to the TRK pin 121. The other ends of the external soft-start capacitor and the internal soft-start capacitor are both grounded.
[0054] Among them, the TRK pin 121 floats when using the internal reference source function; the TRK pin 121 is electrically connected to the external soft-start capacitor in the programmable soft-start function; the TRK pin 121 is electrically connected to the external reference source in the synchronous external reference source function; the threshold voltage is 0.9 times the internal reference voltage.
[0055] In this embodiment, when using the internal reference source function, the TRK pin 121 is set to float. The internal reference voltage VREF automatically clamps the voltage value of the TRK pin 121 to be the same as VREF through the voltage buffer circuit 122 and sends it to the positive input terminal of the COMP comparator 13. After the programmable soft-start function ends, it is compared with the FB feedback voltage to control the Buck loop 14.
[0056] In the programmable soft-start function, the internal soft-start capacitor Css_int is electrically connected to the positive input terminal of the comparator 13, and the external soft-start capacitor Ctrk is electrically connected to the TRK pin 121. The TRK pin 121 is set to be externally connected to a large off-chip capacitor Css_ext, and the charging slope of the voltage buffer circuit 122 driven by VREF to the TRK point capacitor is changed, so as to control the rising speed of the voltage value of the TRK pin 121. The design logic of the programmable soft-start function is determined by the comparison result between the voltage value Vtrk of the TRK pin 121 and the internal reference voltage VREF.
[0057] When Vtrk < 90% * VREF, the external capacitor of the TRK PIN is charged with a constant current Idc to generate a new linear soft-start TRK_INT voltage to replace VREF; when 90% * VREF < Vtrk < VREF, the external capacitor of the TRK pin 121 is charged with a variable current gm * (VREF - Vtrk). The voltage value of the TRK pin 121 is finally clamped to the same voltage value as VREF by the buffer control circuit 12.
[0058] The calculation formula for the programmable soft-start time tss_ext is as follows:
[0059] tss_ext=90%*VREF*Ctrk / Idc+10%*VREF*Ctrk / gm / (VREF-Vtrk)
[0060] Where VREF represents the internal reference voltage, Ctrk represents the external programmable soft-start capacitor of TRK pin 121, gm represents the transconductance of the standard voltage buffer of the OTA structure, Vtrk represents the voltage value of TRK pin 121, and Idc represents the constant current source; the final soft-start time is obtained by comparing the internal soft-start and external soft-start times and taking the longer of the two times as the final soft-start time.
[0061] The formula for calculating the minimum soft-start time tss_int (internal fixed soft-start) is as follows:
[0062] tss_int = Css_int * VREF / Iss
[0063] Where Css_int represents the internal soft-start capacitor and Iss represents the soft-start charging current.
[0064] In this embodiment, two independent functions, programmable soft start and synchronous external reference source, are achieved simultaneously through an external pin; only an additional voltage buffer circuit 122 is needed, making the structure simple and easy to implement; the internal reference and external reference source can be made independent of each other and do not interfere with each other.
[0065] In one embodiment, such as Figure 3 As shown, the voltage buffer circuit includes a first PMOS transistor ( Figure 3 The image shows PM1 and the second PMOS transistor ( Figure 3 The image shows PM2 and the first NMOS transistor ( Figure 3 The diagram shows NM1 and the third PMOS transistor ( Figure 3 The image shows PM3 and the second NMOS transistor ( Figure 3 The diagram shows NM2 and the fourth PMOS transistor ( Figure 3 The image shows PM4 and the third NMOS transistor ( Figure 3 The image shows NM3 and the fifth PMOS transistor ( Figure 3 The image shows PM5 and the fourth NMOS transistor ( Figure 3 The image shows NM4 and the sixth PMOS transistor ( Figure 3 The image shows PM6 and the fifth NMOS transistor ( Figure 3 The image shows NM5 and the sixth NMOS transistor ( Figure 3 The image shows NM6 and the seventh NMOS transistor ( Figure 3 The image shows NM7 and the eighth NMOS transistor ( Figure 3 The image shows NM8 and the seventh PMOS transistor ( Figure 4 PM7 is shown in the image.
[0066] The source of the second PMOS transistor and the source of the third PMOS transistor are electrically connected to the drain of the first PMOS transistor. The gate of the second PMOS transistor is electrically connected to the output terminal of the internal bandgap reference circuit. The drain of the second PMOS transistor is electrically connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is grounded.
[0067] The drain of the third PMOS transistor is electrically connected to the drain of the second NMOS transistor, and the gate of the third PMOS transistor is electrically connected to the drain of the fifth PMOS transistor; the source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is electrically connected to the gate of the third NMOS transistor.
[0068] The source of the fourth PMOS transistor is electrically connected to the source of the first PMOS transistor, the source of the fifth PMOS transistor, and the source of the sixth PMOS transistor. The gates of the fourth PMOS transistor and the sixth PMOS transistor are electrically connected to the gate of the fifth PMOS transistor. The drain of the fourth PMOS transistor is electrically connected to the drain of the third NMOS transistor, and the source of the third NMOS transistor is grounded.
[0069] The drain of the fifth PMOS transistor is electrically connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is grounded.
[0070] The drain of the sixth PMOS transistor is electrically connected to the drain of the fifth NMOS transistor and the drain of the sixth NMOS transistor, and the source of the sixth PMOS transistor is grounded; the gate of the sixth NMOS transistor, the gate of the eighth NMOS transistor, and the gate of the seventh NMOS transistor are electrically connected; the source of the sixth NMOS transistor is electrically connected to the drain of the seventh NMOS transistor; the source of the seventh NMOS transistor is electrically connected to the drain of the eighth NMOS transistor; and the source of the eighth NMOS transistor is grounded.
[0071] The drain of the seventh PMOS transistor is electrically connected to the drain of the fourth NMOS transistor, the gate of the seventh PMOS transistor is electrically connected to the inverter, the drain of the seventh PMOS transistor is electrically connected to the drain of the fifth PMOS transistor, and the source of the seventh PMOS transistor is electrically connected to the internal constant current source.
[0072] Among them, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the first NMOS transistor, the fourth NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor together constitute the standard voltage buffer of the OTA structure;
[0073] And / or,
[0074] The first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the first NMOS transistor, the fifth NMOS transistor, the eighth NMOS transistor, the seventh NMOS transistor, the sixth NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth PMOS transistor, and the sixth PMOS transistor together constitute the threshold voltage comparator.
[0075] In this embodiment, PM1, PM2, PM3, NM1, NM4, NM2, NM3, PM4, and PM5 constitute a standard voltage buffer for the OTA structure, ensuring that the voltage value of TRK pin 121 changes with the VREF voltage value when using the internal reference source function. PM1, PM2, PM3, NM1, NM5, NM8, NM7, NM6, NM2, NM3, PM4, and PM6 constitute a 90%*VREF threshold voltage comparator, which controls the opening and closing of the branch current containing the internal Idc current source PM7 via inverter INV1. In other words, when the voltage value of TRK pin 121 is greater than the threshold voltage 90%*VREF, PM7 is closed by inverter INV1; when the voltage value of TRK pin 121 is less than the threshold voltage 90%*VREF, PM7 is opened by inverter INV1.
[0076] In one embodiment, such as Figure 5 As shown, the horizontal axis V_TRK represents the voltage change at pin 121 of TRK, and the vertical axis I_TRK_COMP represents the current change at pin 121 of TRK. Figure 4 As shown, the horizontal axis tss_ext represents the programmable soft-start time, and the vertical axis V represents the voltage value. According to... The voltage change at pin 121 of the TRK pin and the pull-down current curve of the TRK pin show that there are three stages in the process of V_TRK gradually increasing from 0: before V_TRK reaches 90%*VREF, the current value is a fixed positive value; when V_TRK is between 90%*VREF and VREF, the current value gradually decreases to 0; when V_TRK is higher than VREF, the current value gradually becomes negative and gradually clamps to a fixed negative value.
[0077] This invention provides a control circuit that multiplexes programmable soft-start and synchronous external reference source functions. An internal bandgap reference circuit is used to input an internal reference voltage to a buffer control circuit. Upon receiving the internal reference voltage, the buffer control circuit uses the TRK pin and a voltage buffer circuit to multiplex the programmable soft-start and synchronous external reference source functions. A comparator compares the voltage value at the TRK pin with the feedback voltage of the Buck loop and outputs a control signal to control the duty cycle of the switching transistor. This invention achieves both programmable soft-start and synchronous external reference source functions simultaneously using only a single external TRK pin, reducing packaging costs and offering a simple and easy-to-implement structure.
[0078] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of the present invention is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but all such changes and modifications fall within the scope of protection of the present invention.
Claims
1. A control circuit for programmable soft-start and synchronous external reference source function multiplexing, characterized in that, The control circuit includes: an internal bandgap reference circuit, a buffer control circuit, a comparator, and a Buck loop. The buffer control circuit includes a TRK pin and a voltage buffer circuit. The input terminal of the buffer control circuit is electrically connected to the output terminal of the internal bandgap reference circuit, the output terminal of the buffer control circuit is electrically connected to the positive input terminal of the comparator, and the output terminal of the Buck loop is electrically connected to the negative input terminal of the comparator. The internal bandgap reference circuit is used to input an internal reference voltage into the buffer control circuit; The buffer control circuit is used to receive the internal reference voltage and then, through the TRK pin and the voltage buffer circuit, multiplex the programmable soft-start function and the function of synchronizing the external reference source. The comparator is used to compare the voltage value of the TRK pin with the feedback voltage of the Buck loop and output a control signal to control the duty cycle of the switching transistor.
2. The control circuit for programmable soft-start and synchronous external reference source function multiplexing as described in claim 1, characterized in that, The buffer control circuit also includes a programmable soft-start circuit; The output terminal of the voltage buffer circuit, the input terminal of the programmable soft-start circuit, and the TRK pin are electrically connected; the output terminal of the programmable soft-start circuit is electrically connected to the positive input terminal of the comparator. The voltage buffer circuit is used to clamp the voltage value of the TRK pin to be the same as the internal reference voltage when using the internal reference source function. Under the programmable soft-start function, when the voltage value of the TRK pin is less than the threshold voltage, the external soft-start capacitor in the programmable soft-start circuit is charged with constant current to generate a new linear soft-start voltage to replace the internal reference voltage; when the voltage value of the TRK pin is between the threshold voltage and the internal reference voltage, the external soft-start capacitor in the programmable soft-start circuit is charged with transconductance converter current to control the voltage value of the TRK pin to slowly rise until it is the same as the internal reference voltage; Under the function of synchronizing an external reference source, the voltage value of the TRK pin is controlled to be the same as that of the external reference source.
3. The control circuit for programmable soft-start and synchronous external reference source function multiplexing as described in claim 2, characterized in that, The voltage buffer circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a third PMOS transistor, a second NMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fifth PMOS transistor, a fourth NMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a seventh PMOS transistor; The source of the second PMOS transistor and the source of the third PMOS transistor are electrically connected to the drain of the first PMOS transistor. The gate of the second PMOS transistor is electrically connected to the output terminal of the internal bandgap reference circuit. The drain of the second PMOS transistor is electrically connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is grounded. The drain of the third PMOS transistor is electrically connected to the drain of the second NMOS transistor, and the gate of the third PMOS transistor is electrically connected to the drain of the fifth PMOS transistor; the source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is electrically connected to the gate of the third NMOS transistor. The source of the fourth PMOS transistor is electrically connected to the source of the first PMOS transistor, the source of the fifth PMOS transistor, and the source of the sixth PMOS transistor; the gate of the fourth PMOS transistor and the gate of the sixth PMOS transistor are electrically connected to the gate of the fifth PMOS transistor; the drain of the fourth PMOS transistor is electrically connected to the drain of the third NMOS transistor; and the source of the third NMOS transistor is grounded. The drain of the fifth PMOS transistor is electrically connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is grounded. The drain of the sixth PMOS transistor is electrically connected to the drain of the fifth NMOS transistor and the drain of the sixth NMOS transistor, and the source of the sixth PMOS transistor is grounded; the gate of the sixth NMOS transistor and the gate of the eighth NMOS transistor are electrically connected to the gate of the seventh NMOS transistor, the source of the sixth NMOS transistor is electrically connected to the drain of the seventh NMOS transistor, the source of the seventh NMOS transistor is electrically connected to the drain of the eighth NMOS transistor, and the source of the eighth NMOS transistor is grounded; The drain of the seventh PMOS transistor is electrically connected to the drain of the fourth NMOS transistor, the gate of the seventh PMOS transistor is electrically connected to the anti-suppression device, the drain of the seventh PMOS transistor is electrically connected to the drain of the fifth PMOS transistor, and the source of the seventh PMOS transistor is electrically connected to the internal constant current source.
4. The control circuit for programmable soft-start and synchronous external reference source function multiplexing as described in claim 2, characterized in that, The programmable soft-start circuit also includes an internal soft-start capacitor; One end of the internal soft-start capacitor is electrically connected to the positive input terminal of the comparator and the TRK pin, one end of the external soft-start capacitor is electrically connected to the TRK pin, and the other ends of both the external soft-start capacitor and the internal soft-start capacitor are grounded.
5. The control circuit for programmable soft-start and synchronous external reference source function multiplexing as described in claim 2, characterized in that, The TRK pin is floating when using the internal reference source function.
6. The control circuit for the buck converter with programmable soft start and synchronous external reference source as described in claim 2, characterized in that, The TRK pin is electrically connected to the external soft-start capacitor in the programmable soft-start function.
7. The control circuit for programmable soft-start and synchronous external reference source function multiplexing as described in claim 2, characterized in that, The TRK pin is electrically connected to an external reference source when the external reference source is synchronized.
8. The control circuit for the buck converter with programmable soft start and synchronous external reference source as described in claim 2, characterized in that, The threshold voltage is 0.9 times the internal reference voltage.
9. The control circuit for programmable soft-start and synchronous external reference source function multiplexing as described in claim 3, characterized in that, The first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the first NMOS transistor, the fourth NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor together constitute a standard voltage buffer of the OTA structure.
10. The control circuit for programmable soft-start and synchronous external reference source function multiplexing as described in claim 3, characterized in that, The first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the first NMOS transistor, the fifth NMOS transistor, the eighth NMOS transistor, the seventh NMOS transistor, the sixth NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth PMOS transistor, and the sixth PMOS transistor together constitute a threshold voltage comparator.