Wireless communication device, single-pole double-throw radio frequency switch circuit and control method thereof
By using switching devices with different physical conduction characteristics in a single-pole double-throw RF switch circuit, the RF terminal is automatically turned on or isolated in a zero-bias state, which solves the problem of uncertain logic in the RF signal path, ensures that the path remains unobstructed in the event of power failure, and improves system reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN XINMAI MICRO TECH CO LTD
- Filing Date
- 2026-06-11
- Publication Date
- 2026-07-14
Smart Images
Figure CN122394543A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of wireless communication technology, and in particular to a wireless communication device, a single-pole double-throw radio frequency switch circuit and its control method. Background Technology
[0002] In wireless communication devices, radio frequency (RF) switches are one of the core components in the RF signal link. However, existing single-pole double-throw (SPDT) switches have limitations in practical applications: when the first and second control voltages are both at a low level, the transistors inside the switch are in an uncontrolled physical state due to the lack of an effective bias voltage.
[0003] In this power-down state, the logic states of the first path formed between the common RF terminal and the first RF terminal, and the second path formed between the common RF terminal and the second RF terminal, are often uncertain, or both paths may be in a state of high insertion loss isolation. In practical applications, if it is necessary to keep a specific path open to ensure signal continuity when the switch is powered off, this ordinary single-pole double-throw switch cannot meet the requirements. Summary of the Invention
[0004] The main objective of this application is to provide a wireless communication device, a single-pole double-throw radio frequency switch circuit and its control method, which aims to solve the technical problem that the logic state of the radio frequency signal path is uncertain under power failure or zero bias conditions in existing radio frequency switches.
[0005] To achieve the above objectives, this application proposes a single-pole double-throw radio frequency switch circuit, comprising: Common RF terminal, first RF terminal, and second RF terminal; The first switching circuit includes a first switching path connected between the common radio frequency terminal and the first radio frequency terminal, and a first parallel branch electrically connected to the first switching path. The second switching circuit includes a second switching path connected between the common radio frequency terminal and the second radio frequency terminal, and a second parallel branch electrically connected to the second switching path; Both the first switching path and the second parallel branch include a first switching device with a first physical conduction characteristic, and the controlled terminal of the first switching device is electrically connected to a first control voltage; both the second switching path and the first parallel branch include a second switching device with a second physical conduction characteristic, and the controlled terminal of the second switching device is electrically connected to a second control voltage. Each switching circuit utilizes the physical conduction characteristics of each switching device and the corresponding control voltage to switch the conduction or isolation state between the common RF terminal and the corresponding RF terminal, so as to achieve the common RF terminal being connected to one of the RF terminals and isolated from the other RF terminal.
[0006] In one embodiment, the first characteristic is a normally open characteristic, and the second characteristic is a normally closed characteristic; Specifically, when both the first control voltage and the second control voltage are in a zero bias state, the first switching device is turned on and the second switching device is turned off, so that the first switching circuit connects the common RF terminal and the first RF terminal, and the second switching circuit isolates the common RF terminal and the second RF terminal.
[0007] In one embodiment, the logic levels of the first control voltage and the second control voltage are complementary; In the normal power-on working state, the first RF terminal and the second RF terminal are selectively turned on by the logical switching between the first control voltage and the second control voltage.
[0008] In one embodiment, the first switching device is a depletion-type transistor, and the second switching device is an enhancement-type transistor.
[0009] In one embodiment, the first parallel branch is connected between the first radio frequency terminal and the reference ground, and the second parallel branch is connected between the intermediate node of the second switching path and the reference ground.
[0010] In one embodiment, the first switching path includes n first switching devices connected in series, and the first parallel branch includes m second switching devices connected in series; the second switching path includes n second switching devices connected in series, and the second parallel branch includes n-1 branch groups, each of which includes m first switching devices connected in series. Where n≥2, m≥1; In the first switching path, the connection node between two adjacent first switching devices is electrically connected to a DC power supply, and each of the branch groups is electrically connected between the connection node between two adjacent second switching devices in the second switching path and a reference ground.
[0011] In one embodiment, bias resistors are connected in parallel between the source and drain of adjacent first switching devices in the first switching path and between the source and drain of adjacent second switching devices in the second switching path; the controlled terminals of the first and second switching devices are electrically connected to the corresponding control voltages through current-limiting resistors.
[0012] In one embodiment, the single-pole double-throw radio frequency switch circuit is integrated on the same semiconductor substrate based on gallium arsenide pHEMT process.
[0013] Furthermore, to achieve the above objectives, this application also proposes a control method for a single-pole double-throw radio frequency switch circuit, implemented based on the single-pole double-throw radio frequency switch circuit described above, comprising: When both the first control voltage and the second control voltage are in a zero bias state, the common RF terminal is connected to one of the RF terminals and isolated from the other RF terminal by utilizing the physical conduction characteristics of each switching device. In normal power-on operation, the first RF terminal and the second RF terminal are selectively turned on by logically switching between the first control voltage and the second control voltage.
[0014] In addition, to achieve the above objectives, this application also proposes a wireless communication device, including the single-pole double-throw radio frequency switch circuit as described above.
[0015] One or more technical solutions proposed in this application have at least the following technical effects: This application utilizes the different physical conduction characteristics of the first and second switching devices. When the control voltage is simultaneously low, the first switching path automatically conducts and the second parallel branch automatically conducts, ensuring low insertion loss conduction between the common RF terminal and the first RF terminal, while isolating the second RF terminal. This meets the requirement of maintaining critical links uninterrupted under power failure or abnormal conditions. When the control voltage is normal, the circuit switches to a conventional single-pole double-throw switch mode, achieving selective conduction and isolation between the common RF terminal and either RF terminal without affecting normal communication. Furthermore, this application eliminates the need for additional power failure detection modules or complex bias networks, relying solely on the inherent characteristics of the devices and complementary logic of the control voltage. This reduces circuit complexity, chip area, and power consumption, avoids uncontrollable states caused by external bias failures, and improves system reliability under power fluctuations or power failure scenarios. Attached Figure Description
[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 The circuit topology of an existing gallium arsenide single-pole double-throw switch is shown below. Figure 2 This is a structural framework diagram of a single-pole double-throw radio frequency switch circuit according to an embodiment of this application; Figure 3This is a circuit topology diagram provided in Embodiment 4 of a single-pole double-throw radio frequency switch circuit according to this application; Figure 4 This is a simulation result diagram of the power outage state provided in Embodiment 4 of this application; Figure 5 The simulation results of the power-on state when VDD=3V, V1=3V, V2=0V are provided in Embodiment 4 of this application; Figure 6 The simulation results of the power-on state when VDD=3V, V1=0V, and V2=3V are provided in Embodiment 4 of this application.
[0019] Explanation of reference numerals in the attached diagram: First switch circuit 01, First switch path 11, First parallel branch 12, Second switch circuit 02, Second switch path 21, Second parallel branch 22.
[0020] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0021] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.
[0022] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.
[0023] In wireless communication equipment, RF switches, as core components in the RF signal link, are widely used for signal path switching control. Among them, single-pole double-throw (SPDT) switches are one of the most common types. However, existing SPDT switches have an inherent limitation in practical applications: when the first control voltage and the second control voltage are both at a low level, due to the lack of an effective bias voltage, the transistor inside the switch enters an uncontrolled physical state, which is often referred to as the "power-down indeterminate state." In this state, the logic states of the first path formed between the common RF terminal and the first RF terminal, and the second path formed between the common RF terminal and the second RF terminal, are often indeterminate, or both paths are in a high insertion loss isolated state, which cannot meet the system's requirement to keep specific paths open under power-down or abnormal power-down scenarios.
[0024] Traditional single-pole double-throw (SPDT) switches rely on complementary control voltages to bias the gates of internal field-effect transistors (FETs) to either turn them on or off. When the control voltages are both low, all transistor gates lose effective bias, causing both series and parallel transistors to be in a cut-off or weakly conducting state, making it impossible to form a definite signal path. This design can effectively avoid signal crosstalk caused by simultaneous conduction of two paths during normal operation, but it reveals its inability to maintain a specific path open under system power failure or abnormal power outage scenarios.
[0025] refer to Figure 1 Taking a single-pole double-throw switch (SPD double-throw switch) using existing gallium arsenide (GaAs) technology as an example, its common RF terminal is connected in series with the first RF terminal and the second RF terminal, respectively, by n depletion-mode transistors. The gate of the transistor between the common RF terminal and the first RF terminal is connected to a first control voltage, and the gate of the transistor between the common RF terminal and the second RF terminal is connected to a second control voltage. m depletion-mode transistors are connected in series between the first RF terminal, the second RF terminal, and ground, respectively. The gates of the transistors between the first RF terminal and ground are all connected to the second control voltage, and the gates of the transistors between the second RF terminal and ground are all connected to the first control voltage. The first and second control voltages are complementary control voltages, used to control whether the path between the common RF terminal and the first RF terminal and the path between the common RF terminal and the second RF terminal are in an on or isolated state, respectively. During design, appropriate values for n and m can be selected based on performance indicators such as insertion loss, isolation, and power. However, this structure cannot achieve a state where one path is open and the other is isolated when power is off, i.e., when both the first control voltage and the second control voltage are low, thus limiting its application in scenarios where a path needs to be maintained even when power is off.
[0026] To address the aforementioned issues, this application proposes a single-pole double-throw radio frequency switch circuit, comprising: a common radio frequency terminal RFC, a first radio frequency terminal RF1, and a second radio frequency terminal RF2; a first switch circuit 01, comprising a first switch path 11 connected between the common radio frequency terminal RFC and the first radio frequency terminal RF1, and a first parallel branch 12 electrically connected to the first switch path 11; and a second switch circuit 02, comprising a second switch path 21 connected between the common radio frequency terminal RFC and the second radio frequency terminal RF2, and a second parallel branch 22 electrically connected to the second switch path 21. Both the first switching path 11 and the second parallel branch 22 include a first switching device with a first physical conduction characteristic, and the controlled terminal of the first switching device is electrically connected to a first control voltage V1; both the second switching path 21 and the first parallel branch 12 include a second switching device with a second physical conduction characteristic, and the controlled terminal of the second switching device is electrically connected to a second control voltage V2; wherein, each switching circuit switches the conduction or isolation state between the common radio frequency terminal RFC and the corresponding radio frequency terminal by utilizing the physical conduction characteristics of each switching device and the corresponding control voltage, so as to realize that the common radio frequency terminal RFC is connected to one radio frequency terminal and isolated from the other radio frequency terminal.
[0027] This application utilizes the different physical conduction characteristics of the first and second switching devices. When the control voltage is simultaneously low, the first switching path 11 automatically conducts and the second parallel branch 22 automatically conducts, ensuring low insertion loss conduction between the common RF terminal RFC and the first RF terminal RF1, while isolating the second RF terminal RF2. This meets the requirement of maintaining critical links in power-down or abnormal conditions. When the control voltage is normal, the circuit switches to a conventional single-pole double-throw switch mode, achieving selective conduction and isolation between the common RF terminal RFC and any RF terminal without affecting normal communication. Furthermore, this application eliminates the need for additional power-down detection modules or complex bias networks, relying solely on the inherent characteristics of the devices and complementary control voltage logic. This reduces circuit complexity, chip area, and power consumption, avoids uncontrollable states caused by external bias failures, and improves system reliability under power fluctuations or power-down scenarios.
[0028] Example 1 This embodiment discloses a single-pole double-throw radio frequency switch circuit, the overall architecture of which is as follows: Figure 2 As shown, it is composed of a common radio frequency terminal RFC, a first radio frequency terminal RF1, a second radio frequency terminal RF2, a first switching circuit 01, and a second switching circuit 02. The first switching circuit 01 integrates a first switching path 11 connected between the common radio frequency terminal RFC and the first radio frequency terminal RF1, and a first parallel branch 12 electrically connected to the first switching path 11; the second switching circuit 02 integrates a second switching path 21 connected between the common radio frequency terminal RFC and the second radio frequency terminal RF2, and a second parallel branch 22 electrically connected to the second switching path 21.
[0029] Regarding device selection and topology, both the first switching path 11 and the second parallel branch 22 employ first switching devices with first physical conduction characteristics, and the controlled terminals of these first switching devices are electrically connected to the first control voltage V1. Correspondingly, both the second switching path 21 and the first parallel branch 12 employ second switching devices with second physical conduction characteristics, and the controlled terminals of these second switching devices are electrically connected to the second control voltage V2. In this structure, the first and second physical conduction characteristics have preset differentiated configurations in physical parameters such as threshold voltage (Vth), saturation current, or on-resistance.
[0030] During circuit operation, the logic control of the radio frequency signal path is achieved by combining the levels of the first control voltage V1 and the second control voltage V2, in conjunction with the physical conduction characteristics of the first and second switching devices. When the first control voltage V1 is at the first level and the second control voltage V2 is at the second level, the first switching device in the first switching path 11 presents a low impedance state, establishing a signal transmission link between the common radio frequency terminal RFC and the first radio frequency terminal RF1. Simultaneously, the first switching device in the second parallel branch 22 also presents a low impedance state, connecting the second radio frequency terminal RF2 to ground potential to improve isolation. During this period, the second switching path 21 and the second switching device in the first parallel branch 12 present a high impedance cutoff state under the action of the second control voltage V2.
[0031] When the first control voltage V1 and the second control voltage V2 are both at a low level, such as in a system power-down state, the circuit utilizes the differences in the physical characteristics of the devices to achieve a definite logic response. The first switching device with the first physical conduction characteristic maintains a first impedance state under low-level drive, while the second switching device with the second physical conduction characteristic maintains a second impedance state under the same low-level drive. If the first switching device is preset to be a low-impedance conducting device under 0V bias, and the second switching device is a high-impedance isolated device under 0V bias, then in the power-down condition, the first switching path 11 automatically remains on, the second parallel branch 22 discharges the residual signal of the second RF terminal RF2 to ground, while the second switching path 21 and the first parallel branch 12 remain off.
[0032] This embodiment eliminates the absolute dependence on continuous complementary bias voltage through the above configuration. Without requiring additional intervention from external logic circuitry, it utilizes the difference in conduction characteristics at the physical level between the first and second switching devices to create an asymmetrical logic distribution between the common RF terminal RFC and the first and second RF terminals RF1 and RF2 under specific operating conditions. This structure ensures that the common RF terminal RFC is connected to one of the RF terminals while being isolated from the other, while maintaining a definite initial path state in the event of abnormal control voltage or power failure. This avoids the RF link entering a high-loss, uncertain physical state and maintains signal continuity of the RF system on specific branches.
[0033] Example 2 In this embodiment, the physical characteristics of the first switching device and the second switching device are specifically configured. The first switching device is a depletion-type transistor with normally open characteristics, in which the channel is in the conducting state when the gate-source voltage is zero; the second switching device is an enhancement-type transistor with normally closed characteristics, in which the channel is in the cut-off state when the gate-source voltage is zero.
[0034] When both the first control voltage V1 and the second control voltage V2 are in a zero-bias state, i.e., V1=0V and V2=0V, the circuit enters a preset initial determination state. At this time, the depletion-type transistors distributed in the first switching path 11 and the second parallel branch 22 are driven by zero bias and maintain a physically conducting state; the enhancement-type transistors distributed in the second switching path 21 and the first parallel branch 12 are driven by zero bias and maintain a physically cut-off state. In this state, the common RF terminal RFC and the first RF terminal RF1 are electrically connected through the first switching path 11, allowing the signal from the first RF terminal RF1 to be transmitted to the common RF terminal RFC. Simultaneously, the second switching path 21 is in a high-impedance cutoff state, and the second parallel branch 22 connects the second RF terminal RF2 to ground potential, thereby achieving electrical isolation between the common RF terminal RFC and the second RF terminal RF2. This process establishes a specific path selection logic determined by the physical characteristics of the system under conditions of no external power supply or abnormal power failure.
[0035] Under normal power-on operation, the circuit achieves controlled selection of the RF signal path by switching the logic levels of the first control voltage V1 and the second control voltage V2. The first control voltage V1 and the second control voltage V2 are configured as logically complementary signals. When the first RF terminal RF1 needs to be selected, the first control voltage V1 provides a level that keeps the depletion-mode transistor on, and the second control voltage V2 provides a level that keeps the enhancement-mode transistor off. When switching to the second RF terminal RF2, the first control voltage V1 provides a bias level sufficient to turn off the depletion-mode transistor, causing the first switching path 11 and the second parallel branch 22 to switch to a high-impedance isolation state; at the same time, the second control voltage V2 provides a bias level sufficient to turn on the enhancement-mode transistor, causing the second switching path 21 and the first parallel branch 12 to switch to a low-impedance conduction state, thereby establishing a signal link between the common RF terminal RFC and the second RF terminal RF2, and discharging the residual signal of the first RF terminal RF1 to ground through the first parallel branch 12.
[0036] By alternately deploying depletion-mode transistors and enhancement-mode transistors in a single-pole double-throw circuit and combining them with complementary control logic, this solution addresses the technical deficiency of uncertain path logic in traditional architectures under zero bias while maintaining conventional signal switching functionality. Since depletion-mode and enhancement-mode transistors produce drastically different physical responses to signals of equal voltage levels, the circuit utilizes this asymmetrical physical conduction characteristic to ensure that the RF link automatically reverts to the preset default path (RFC-RF1) in the event of system power failure or control failure. This provides hardware-level fault-safe protection for the RF front-end, preventing system performance fluctuations caused by signal reflection or link interruption.
[0037] Example 3 Based on Embodiment 2, this embodiment provides a specific distribution configuration for the topological connection positions of the first parallel branch 12 and the second parallel branch 22. One end of the first parallel branch 12 is electrically connected between the first radio frequency terminal RF1 and the first switching path 11, and the other end is connected to the reference ground. The second switching path 21 includes at least two switches connected in series. One end of the second parallel branch 22 is electrically connected to the intermediate node between adjacent switches within the second switching path 21, and the other end is connected to the reference ground.
[0038] When the circuit is in the first RF terminal RF1 selected state, the first switching path 11 exhibits low impedance characteristics, and the first parallel branch 12 exhibits high impedance characteristics under the drive of the second control voltage V2, thereby preventing the first RF terminal RF1 signal from leaking to the reference ground. Simultaneously, each series switch in the second switching path 21 is in the off state under the drive of the second control voltage V2, and the second parallel branch 22 exhibits low impedance characteristics under the drive of the first control voltage V1, clamping the intermediate node potential of the second switching path 21 to the reference ground potential. By introducing a ground branch at the middle position of the second switching path 21, the coupling penetration of the RF signal through the parasitic capacitance of each series switch is blocked, improving the isolation between the common RF terminal RFC and the second RF terminal RF2.
[0039] When the circuit is in the selected state of the second RF terminal RF2, each series switch in the second switching path 21 exhibits low impedance characteristics under the drive of the second control voltage V2, and the second parallel branch 22 exhibits high impedance characteristics under the drive of the first control voltage V1, to ensure that the RF signal flows from the common RF terminal RFC through the intermediate node to the second RF terminal RF2. At the same time, the first switching path 11 is in the off state under the drive of the first control voltage V1, and the first parallel branch 12 exhibits low impedance characteristics under the drive of the second control voltage V2, directly connecting the first RF terminal RF1 to the reference ground, thereby achieving grounding discharge of the residual signal of the first RF terminal RF1.
[0040] Under power-down conditions where both the first control voltage V1 and the second control voltage V2 are at zero bias, the first parallel branch 12 uses a switching device with a second physical conduction characteristic (normally closed type), which maintains a high impedance state to ensure that the first RF terminal RF1 is isolated from ground, without affecting the signal transmission of the first switching path 11. The second parallel branch 22 uses a switching device with a first physical conduction characteristic (normally open type), which automatically switches to a low impedance conduction state under zero bias, forcibly grounding the intermediate node of the second switching path 21. This arrangement allows the second switching path 21 to form a multi-stage isolation structure consisting of a "cutoff tube - grounding node - cutoff tube" in the power-down state.
[0041] Through the asymmetrical design of the parallel branch connection positions described above, the isolation performance of the circuit under different logic states is enhanced by utilizing the direct discharge effect of the first parallel branch 12 on the first RF terminal RF1 and the potential clamping effect of the second parallel branch 22 on the intermediate node of the second switching path 21. Especially in the zero bias state, this structure utilizes the intermediate node grounding mechanism to compensate for the possible insufficient turn-off capability of the enhancement-mode transistor under no bias pressure, ensuring high rejection characteristics between the common RF terminal RFC and the second RF terminal RF2, while maintaining the integrity of the signal path between the common RF terminal RFC and the first RF terminal RF1.
[0042] Example 4 In this embodiment, the technical features described in Embodiments 1 to 3 above are specifically integrated. This embodiment discloses a single-pole double-throw radio frequency switch circuit integrated based on gallium arsenide enhancement-mode / depletion-mode pseudo-high electron mobility transistor (E / D pHEMT) technology, with all devices integrated on the same semiconductor substrate.
[0043] References to circuit topology Figure 3 The first switching path 11 is connected between the common RF terminal RFC and the first RF terminal RF1, and consists of n first switching devices (DS1 to DSn) connected in series. The first switching devices are depletion-mode (D-mode) transistors. The first parallel branch 12 includes m second switching devices (EP1 to EPm) connected in series, and the second switching devices are enhancement-mode (E-mode) transistors; one end of the first parallel branch 12 is electrically connected to the RF1 port, and the other end is connected to the reference ground through a capacitor.
[0044] The second switching path 21 connects the common RF terminal RFC and the second RF terminal RF2, and consists of n second switching devices (ES1 to ESn) connected in series, wherein enhancement-mode transistors are selected. The second parallel branch 22 is configured as n There is one branch group, and each branch group contains m first switching devices (DP1 to DPm) connected in series, i.e., depletion-type transistors. One end of each branch group is electrically connected to the intermediate connection node between two adjacent second switching devices (ES) in the second switching path 21, and the other end is connected to the reference ground through a capacitor. Where n≥2, m≥1.
[0045] In the DC bias network configuration, bias resistors are connected in parallel between the source and drain of each adjacent transistor in the first switching path 11 (DS1-DSn) and between the source and drain of each adjacent transistor in the second switching path 21 (ES1-ESn) to limit the DC potential distribution of each stage of the transistors. In the first switching path 11, among the internal nodes other than the RFC and RF1 ports, a selected connection node (such as the connection point between the source of DS2 and the drain of DS3) is electrically connected to the DC power supply (VDD). The controlled terminals (gates) of all first switching devices (DS series and DP series) are electrically connected to the first control voltage V1 through current-limiting resistors; the controlled terminals (gates) of all second switching devices (ES series and EP series) are electrically connected to the second control voltage V2 through current-limiting resistors.
[0046] Under normal power-on operation, the DC power supply (VDD) is at a high level, and the first control voltage V1 and the second control voltage V2 maintain complementary level logic. When V1 is high (equivalent to VDD) and V2 is low (0V), the depletion-type transistors (DS1-DSn) in the first switching path 11 are in the on state, and the enhancement-type transistors (EP1-EPm) in the first parallel branch 12 are in the off state, establishing a signal conduction path from RFC to RF1; at the same time, the enhancement-type transistors (ES1-ESn) in the second switching path 21 are in the off state, and the depletion-type transistors (DP1-DPm) in the second parallel branch 22 are in the on state, clamping the potential of each intermediate node in the second switching path 21 to the reference ground, realizing signal isolation between RFC and RF2.
[0047] Conversely, when V1 is low (0V) and V2 is high, the depletion-type transistor in the first switching path 11 enters the off state driven by the negative voltage difference generated between V1 and the internal node VDD, and the enhancement-type transistor in the first parallel branch 12 enters the on state, grounding the RF1 port; simultaneously, the enhancement-type transistor in the second switching path 21 enters the on state driven by the high level of V2, and the depletion-type transistor in the second parallel branch 22 enters the off state, establishing a signal conduction path from RFC to RF2. Through the above logic switching, the selection function of the single-pole double-throw switch is realized under normal power-on conditions.
[0048] In the event of a system power failure or abnormal control conditions (where VDD, V1, and V2 are all at zero level 0V), the circuit utilizes the physical characteristics of the devices to achieve deterministic self-reset. The depletion-type transistors (DS1-DSn) in the first switching path 11 remain on under 0V bias due to their normally open characteristics, while the enhancement-type transistors (EP1-EPm) in the first parallel branch 12 remain off, ensuring that the physical path between RFC and RF1 is connected. Simultaneously, the enhancement-type transistors (ES1-ESn) in the second switching path 21 remain off due to their normally closed characteristics, while the depletion-type transistors (DP1-DPm) in the second parallel branch 22 automatically turn on under 0V bias, forcibly grounding each internal node of the second switching path 21. This layout achieves the preset physical logic that, in the power-off state, the path between RFC and RF1 is connected while the path between RFC and RF2 is isolated.
[0049] Regarding the circuit structure and simulation performance in Embodiment 4 above, the specific parameter configurations and electrical performance are further analyzed as follows: During the circuit design and parameter optimization phase, the number of transistors *n* in series in the first switching path 11 and the second switching path 21, and the number of transistors *m* in series in the first parallel branch 12 and the second parallel branch 22, are adjusted to customize the circuit's insertion loss, isolation, and power capacity. In the typical configuration provided in this embodiment, *n* is 3 and *m* is 2. Its electrical characteristics in the 10MHz to 2GHz frequency band are verified through simulation as follows: Under power failure conditions, i.e., when the DC power supply (VDD), the first control voltage V1, and the second control voltage V2 are all at 0V zero bias, refer to the attached... Figure 4 .in, Figure 4 (a) represents the insertion loss in the power-off state and the RFC-RF1 conduction state. Figure 4 (b) shows the standing wave ratio of RFC-RF1 in the power-off state and the conduction state. Figure 4 (c) represents the isolation level of the RFC-RF2 isolation state under power-off conditions. Figure 4 (d) represents the standing wave ratio (SWR) in the power-off state of the RFC-RF2 isolation state. Simulation results show that the first path formed by the common RF terminal RFC and the first RF terminal RF1 (RFC-RF1) exhibits conduction characteristics, with an insertion loss of less than 1dB across the entire frequency band from 10MHz to 2GHz, and the input / output SWR of this path is within the preset low value range. Meanwhile, the second path formed by the common RF terminal RFC and the second RF terminal RF2 (RFC-RF2) exhibits high isolation characteristics, with isolation values better than -40dB in the same frequency band. This result confirms that the circuit can achieve deterministic single-path selection logic by utilizing the physical differences between depletion-mode and enhancement-mode transistors without external bias voltage.
[0050] Under power-on operating conditions, the circuit maintains the controlled switching function of a standard single-pole double-throw switch. (See attached reference.) Figure 5 ,in, Figure 5 (a) represents the insertion loss when RFC-RF1 is in the on state, with VDD at 3V, V1 at 3V, and V2 at 0V. Figure 5 (b) shows the standing wave ratio (SWR) of RFC-RF1 in the on state when VDD is 3V, V1 is 3V and V2 is 0V. Figure 5 (c) represents the isolation level of the RFC-RF2 isolation state when VDD is 3V, V1 is 3V, and V2 is 0V. Figure 5 (d) represents the standing wave in the RFC-RF2 isolation state when VDD is 3V, V1 is 3V and V2 is 0V. When VDD is 3V, V1 is 3V and V2 is 0V, the RFC-RF1 path remains in a low-loss conducting state, and the RFC-RF2 path maintains a high degree of isolation.
[0051] Reference Appendix Figure 6 ,in, Figure 6(a) represents the insertion loss when RFC-RF1 is in the on state, with VDD at 3V, V1 at 0V, and V2 at 3V. Figure 6 (b) shows the standing wave ratio (SWR) of RFC-RF1 in the on state when VDD is 3V, V1 is 0V, and V2 is 3V. Figure 6 (c) represents the isolation level of the RFC-RF2 isolation state when VDD is 3V, V1 is 0V, and V2 is 3V. Figure 6 (d) represents the standing wave ratio (SWR) of the RFC-RF2 isolation state when VDD is 3V, V1 is 0V, and V2 is 3V. When VDD is 3V, V1 is 0V, and V2 is 3V, the circuit logic state flips, and the RFC-RF1 path becomes isolated, with its isolation performance meeting design requirements across the entire frequency band; simultaneously, the RFC-RF2 path becomes conductive, and its insertion loss performance remains consistent with the default conductive path performance under power-off conditions.
[0052] In summary, this circuit, by configuring transistors with different conduction characteristics in specific topology node combinations, ensures stable impedance matching and signal transmission performance within the 10MHz to 2GHz frequency band, regardless of whether it is in power-on logic switching mode or power-off physical self-reset mode. In the power-off state, the circuit utilizes a parallel branch with m=2 to ground multiple intermediate nodes of the second switching path 21, combined with a series cutoff structure with n=3, effectively suppressing crosstalk and coupling of RF signals, achieving an isolation level below -40dB. These simulation results demonstrate that this single-pole double-throw RF switch fully retains the high-frequency transmission advantages of gallium arsenide RF devices while eliminating power-off uncertainties.
[0053] Example 5 This application also proposes a control method for a single-pole double-throw radio frequency switch circuit, implemented based on the single-pole double-throw radio frequency switch circuit described above, including: When both the first control voltage V1 and the second control voltage V2 are in a zero bias state, the common RF terminal RFC is connected to one of the RF terminals and isolated from the other RF terminal by utilizing the physical conduction characteristics of each switching device. Under normal power-on operation, the first RF terminal RF1 and the second RF terminal RF2 are selectively connected by the logic switching of the first control voltage V1 and the second control voltage V2.
[0054] It can be understood that this application also proposes a control method based on the aforementioned single-pole double-throw radio frequency switch circuit, the execution logic of which is divided into a power-down deterministic logic holding stage and a power-on controlled logic switching stage.
[0055] When both the first control voltage V1 and the second control voltage V2 are at zero bias, a path self-homing step is executed: utilizing the difference in the preset physical conduction characteristics between the first and second switching devices, without external voltage excitation, the depletion-type transistor in the first switching path 11 is automatically kept in a physically conducting state, while the enhancement-type transistor in the second switching path 21 is automatically kept in a physically cut-off state. Simultaneously, utilizing the conduction characteristics of the depletion-type transistor in the second parallel branch 22, the connection nodes of each adjacent transistor in the second switching path 21 are electrically connected to the reference ground. Through the automatic response of the above physical characteristics, the signal link between the common RF terminal RFC and the first RF terminal RF1 is connected, and a multi-level grounding isolation barrier is established between the common RF terminal RFC and the second RF terminal RF2, thereby locking a unique deterministic selection path in the zero bias state.
[0056] Under normal power-on operation, the path-controlled switching step is executed: complementary level signals are applied to the first control voltage V1 and the second control voltage V2 through the external logic control circuit to actively change the channel impedance state of each switching device.
[0057] When the first gating logic is executed, the first control voltage V1 is configured to be high and the second control voltage V2 is configured to be low. At this time, the first switching path 11 remains in a low-impedance state under the drive of the first control voltage V1, and the second parallel branch 22 remains in a grounded state under the drive of the first control voltage V1; at the same time, the second switching path 21 and the first parallel branch 12 remain in a high-impedance cutoff state under the zero bias or reverse bias of the second control voltage V2. This maintains the conduction logic between the common RF terminal RFC and the first RF terminal RF1.
[0058] When the second gating logic is executed, the first control voltage V1 is configured to be low and the second control voltage V2 is configured to be high. At this time, the first switching device in the first switching path 11 changes from a physically on state to a controlled off state under the drive of the potential difference formed by the first control voltage V1 and the DC power supply (VDD); the first parallel branch 12 changes from a physically off state to a controlled on state under the drive of the second control voltage V2, grounding the first RF terminal RF1. Simultaneously, the second switching device in the second switching path 21 changes from a physically off state to a controlled on state under the drive of the second control voltage V2, and the second parallel branch 22 changes to a high-impedance cutoff state under the drive of the first control voltage V1. This cancels the gating of the first RF terminal RF1 and establishes a conduction link between the common RF terminal RFC and the second RF terminal RF2.
[0059] Through the above control method, the circuit can flexibly switch the RF path during normal power-up using complementary logic, and automatically return to the preset default state when the control voltage is removed or abnormal, thanks to the differentiated configuration of the device's physical characteristics. This method ensures that the single-pole double-throw RF switch has a definite logical orientation throughout its entire lifespan, eliminating signal transmission uncertainties caused by logic malfunction in the RF link under specific operating conditions, and improving the overall reliability of the RF front-end system.
[0060] Example 6 In this embodiment, the present application also proposes a wireless communication device that integrates a single-pole double-throw (SPDT) RF switch circuit as described in the foregoing embodiments. The wireless communication device includes an RF front-end module, an antenna unit, and a baseband processing unit. The SPDT RF switch circuit is configured in the RF front-end module to achieve controlled switching of RF signals between different transmission paths. Specifically, the common RF terminal RFC of the SPDT RF switch circuit is electrically connected to the antenna unit, and the first RF terminal RF1 and the second RF terminal RF2 are respectively electrically connected to different signal processing branches, such as the receiving path branch and the transmitting path branch, or filtering branches of different frequency bands.
[0061] During the operation of the wireless communication device, the baseband processing unit or power management unit provides a first control voltage V1, a second control voltage V2, and DC power to the single-pole double-throw (SPDF) RF switch circuit. When the wireless communication device is in normal communication mode, the real-time selection of the link between the antenna unit and a specific signal processing branch is achieved by switching the logic levels of the first control voltage V1 and the second control voltage V2. When the wireless communication device enters low-power sleep mode, standby mode, or encounters an abnormal power outage, the SPDF RF switch circuit utilizes the physical characteristic difference between its internal depletion-type transistor and enhancement-type transistor to automatically keep the signal processing branch where the antenna unit and the first RF terminal RF1 are located in the conducting state, and simultaneously switches the signal processing branch where the second RF terminal RF2 is located to the isolated state.
[0062] By integrating the aforementioned single-pole double-throw RF switch circuit, wireless communication devices achieve hardware-level fault protection for RF links under power-down conditions without adding additional external logic control circuitry. This configuration ensures that the device can maintain physical connectivity of preset specific frequency bands or specific functional links even when the system power supply is unstable, avoiding the risks of impedance mismatch or total reflection caused by the RF switch entering a logic uncertainty state. Since this circuit is integrated using gallium arsenide pHEMT technology, it exhibits low insertion loss and high isolation in high-frequency operating environments, improving the signal transmission quality and system robustness of wireless communication devices in complex electromagnetic environments.
[0063] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.
Claims
1. A single-pole double-throw radio frequency switch circuit, characterized in that, include: Common RF terminal, first RF terminal, and second RF terminal; The first switching circuit includes a first switching path connected between the common radio frequency terminal and the first radio frequency terminal, and a first parallel branch electrically connected to the first switching path. The second switching circuit includes a second switching path connected between the common radio frequency terminal and the second radio frequency terminal, and a second parallel branch electrically connected to the second switching path; Both the first switching path and the second parallel branch include a first switching device with a first physical conduction characteristic, and the controlled terminal of the first switching device is electrically connected to a first control voltage; both the second switching path and the first parallel branch include a second switching device with a second physical conduction characteristic, and the controlled terminal of the second switching device is electrically connected to a second control voltage. Each switching circuit utilizes the physical conduction characteristics of each switching device and the corresponding control voltage to switch the conduction or isolation state between the common RF terminal and the corresponding RF terminal, so as to achieve the common RF terminal being conducted with one of the RF terminals and isolated from the other RF terminal. The first characteristic is normally open, and the second characteristic is normally closed. Specifically, when both the first control voltage and the second control voltage are in a zero bias state, the first switching device is turned on and the second switching device is turned off, so that the first switching circuit connects the common RF terminal and the first RF terminal, and the second switching circuit isolates the common RF terminal and the second RF terminal.
2. The single-pole double-throw radio frequency switch circuit as described in claim 1, characterized in that, The logic levels of the first control voltage and the second control voltage are complementary. In the normal power-on working state, the first RF terminal and the second RF terminal are selectively turned on by the logical switching between the first control voltage and the second control voltage.
3. The single-pole double-throw radio frequency switch circuit as described in claim 1, characterized in that, The first switching device is a depletion-type transistor, and the second switching device is an enhancement-type transistor.
4. The single-pole double-throw radio frequency switch circuit as described in claim 1, characterized in that, The first parallel branch is connected between the first radio frequency terminal and the reference ground, and the second parallel branch is connected between the intermediate node of the second switching path and the reference ground.
5. The single-pole double-throw radio frequency switch circuit as described in claim 4, characterized in that, The first switching path includes n first switching devices connected in series, and the first parallel branch includes m second switching devices connected in series; the second switching path includes n second switching devices connected in series, and the second parallel branch includes n-1 branch groups, each of which includes m first switching devices connected in series. Where n≥2, m≥1; In the first switching path, the connection node between two adjacent first switching devices is electrically connected to a DC power supply, and each of the branch groups is electrically connected between the connection node between two adjacent second switching devices in the second switching path and a reference ground.
6. The single-pole double-throw radio frequency switch circuit as described in claim 5, characterized in that, A bias resistor is connected in parallel between the source and drain of an adjacent first switching device in the first switching path and between the source and drain of an adjacent second switching device in the second switching path; the controlled terminals of the first and second switching devices are electrically connected to the corresponding control voltage through current-limiting resistors.
7. The single-pole double-throw radio frequency switch circuit as described in any one of claims 1-6, characterized in that, The single-pole double-throw radio frequency switch circuit is integrated on the same semiconductor substrate based on gallium arsenide pHEMT technology.
8. A control method for a single-pole double-throw radio frequency switch circuit, implemented based on the single-pole double-throw radio frequency switch circuit as described in any one of claims 1 to 7, characterized in that, include: When both the first control voltage and the second control voltage are in a zero bias state, the common RF terminal is connected to one of the RF terminals and isolated from the other RF terminal by utilizing the physical conduction characteristics of each switching device. In normal power-on operation, the first RF terminal and the second RF terminal are selectively turned on by logically switching between the first control voltage and the second control voltage.
9. A wireless communication device, characterized in that, Includes a single-pole double-throw radio frequency switch circuit as described in any one of claims 1 to 7.