Improved method of PMOS array and control logic applied to double loop control type DLDO

Abstract

The application relates to an improved method of PMOS array and control logic applied to a double-loop control type DLDO, and belongs to the technical field of integrated circuits. In view of the problems of rough loop overshoot, fine loop iteration redundancy and insufficient precision of the MOS array of the existing double-loop DLDO, the application adopts an 8-bit binary weight PMOS array to realize rough loop fast adjustment, and an 8-bit Fibonacci weight PMOS array to realize fine loop accurate calibration. Through the cooperative control of a dynamic reference voltage generation circuit and a finite state machine (FSM), in combination with iteration temporary storage logic and a shift-latch two-stage architecture, the adjustment precision is improved while the transient response speed is ensured. The application does not need a Flash ADC or a complex modulation module, the hardware structure is simplified, the matching performance of the PMOS array is excellent, the steady-state ripple is low, and the application is suitable for low-voltage and low-power chip scenes.

Description

Technical Field

[0001] This invention relates to an improved method for PMOS arrays and control logic applied to dual-loop controlled digital low-dropout linear regulators (DLDOs), and particularly to a method for regulating power PMOS arrays in a dual-loop control architecture and its hardware implementation, belonging to the field of integrated circuit technology. Background Technology

[0002] In common portable and consumer electronics products, as the size of devices shrinks, battery capacity also decreases. Therefore, in order to improve the battery life of products, low dropout regulators (LDOs) on the market are developing towards smaller power consumption and smaller area.

[0003] Because older transistors were current-controlled current source devices, they consumed additional current, leading to increased power consumption. CMOS technology, on the other hand, uses voltage-controlled current source devices, resulting in lower power consumption. Furthermore, with continuous advancements in photolithography, device feature sizes are shrinking, allowing for the integration of more MOS transistors per unit area. Therefore, most LDO designs on the market today utilize CMOS technology. LDOs can be categorized into analog LDOs (ALDOs) and digital LDOs (DLDOs) based on whether the signal is continuous in the time domain. ALDOs are primarily based on operational amplifiers (op-amps) to achieve high-precision output voltage and high power supply rejection ratios. To maintain the op-amp's normal operation, ALDOs typically require a relatively high power supply voltage. Moreover, ALDOs have a narrow output voltage range and poor process scalability. To address the limitation of traditional ALDOs operating in low-voltage environments, DLDOs were developed. DLDOs eliminate all analog circuitry and are controlled by digital logic circuits. Their main structure consists of a synchronous comparator, a bidirectional shift register, and a PMOS power transistor array. Because they are all digital circuits, DLDOs can operate at much lower power supply voltages and offer excellent process scalability.

[0004] However, when the load current changes abruptly, only one PMOS power transistor can operate per clock cycle, making it difficult to respond quickly to changes in load current. The transient response is limited by the clock frequency. Increasing the clock frequency to speed up the transient response will increase power consumption. Therefore, DLDOs need to optimize the design between transient response and power consumption. Furthermore, the ripple when the output voltage reaches steady state is affected by the number of power transistors. Under the same load current, more power transistors result in lower ripple, but more transistors also mean more bidirectional shift registers, leading to a larger layout area and higher dynamic power consumption. Therefore, the design of voltage ripple and the number of registers also needs to be optimized.

[0005] To address the transient response and voltage ripple issues present in the aforementioned DLDOs, researchers proposed a coarse-to-fine dual-loop DLDO. This approach divides the entire voltage range into coarse and fine-tuning intervals. During coarse-tuning, the output voltage is quickly brought back to near the reference voltage by increasing the clock frequency and controlling the operation of a large-size power transistor, improving transient response. During fine-tuning, the steady-state ripple is reduced by decreasing the clock frequency and controlling the operation of a small-size power transistor, resulting in better voltage ripple control. The dual-loop control architecture balances transient response and regulation accuracy through the coordinated action of the coarse loop quickly pulling back the output voltage deviation and the fine loop precisely calibrating. However, existing technologies have the following drawbacks:

[0006] Coarse-ring circuits often employ unit PMOS arrays or simple binary weight designs, relying on ADC quantization deviations, resulting in complex circuits and high-step sizes that are prone to overshoot. Fine-ring circuits often use binary or linear weight arrays, with numerous iterations and redundant step sizes, making it difficult to match the small deviations in the output of coarse-ring circuits. The weights of the PMOS array are indirectly controlled through a weighted resistor network, and the large differences in resistor values ​​lead to low current matching accuracy and affect the linearity of the adjustment. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides an improved method for PMOS arrays and control logic applied to dual-loop controlled DLDOs. It adopts a dual-loop architecture of "coarse-loop 8-bit binary PMOS array + fine-loop 8-bit Fibonacci PMOS array". The coarse-loop step size requirement is determined by a dynamic reference voltage, and the fine-loop is precisely adjusted by iterative temporary storage logic. By optimizing the PMOS array weight sequence and control logic, the problems of coordination and accuracy of dual-loop adjustment are solved.

[0008] The present invention adopts the following technical solution:

[0009] A PMOS array for use in a dual-loop controlled DLDO includes a coarse-loop adjustment module, a fine-loop adjustment module, and a dual-loop switching module;

[0010] The coarse-ring adjustment module consists of an 8-bit coarse-ring PMOS array, a dynamic reference voltage generation circuit, a comparator, and an 8-bit bidirectional shift register. It judges the conduction state bit by bit based on the "high-bit priority" principle.

[0011] The fine-loop adjustment module consists of a fine-loop PMOS array, an error judgment register, an intermediate result register, an error detection unit, and an FSM; the fine-loop PMOS array is an 8-bit Fibonacci PMOS array, which is based on iterative correction of residual deviation;

[0012] Dual-loop switching module: Employs a comparator and hysteresis control circuit to achieve seamless connection between the coarse-loop adjustment module and the fine-loop adjustment module;

[0013] The reference voltage source is connected to the reference input terminals of the dynamic reference voltage generation circuit, the error detection unit, and the dual-loop switching module, respectively; the input voltage V ref Connect the sources of the thick-ring PMOS array and the thin-ring PMOS array; output voltage V out The signals are respectively connected to the non-inverting input of the comparator, the input of the error detection unit, and the signal input of the dual-loop switching module;

[0014] The output of the bidirectional shift register of the coarse-loop adjustment module and the output of the intermediate result register IR of the fine-loop adjustment module are connected to the gate portions of the coarse-loop PMOS array and the fine-loop PMOS array, respectively; the FSM (finite state machine) outputs control signals to the counter of the coarse-loop adjustment module, the error judgment register ER of the fine-loop adjustment module, and the intermediate result register IR, respectively; the output signal FIN of the dual-loop switching module is connected to the latch terminal of the shift register of the coarse-loop adjustment module and the start terminal of the FSM of the fine-loop adjustment module, respectively, to realize dual-loop coordinated control;

[0015] The drains of the binary coarse-loop PMOS array in the coarse-loop regulation module and the Fibonacci PMOS array in the fine-loop regulation module are connected to the output voltage terminal through the load resistor R. L Grounding forms a complete power supply circuit.

[0016] Preferably, the load resistance R L It is the external load equivalent resistance of the DLDO (equivalent to the load chip in the actual application scenario), and the load capacitance C. L Connected in parallel between Vout and ground; load capacitance C L Used to suppress output voltage ripple and improve transient response stability (typical value 1nF~10nF), load resistor R L This determines the quiescent operating current, and the two together form the output load network of the DLDO, ensuring stable output voltage.

[0017] Preferably, the dynamic reference voltage generation circuit consists of multiple precision resistor dividers connected in series with an analog switch array. The total input of the resistor dividers is connected to the reference voltage, and the control terminal of the analog switch array is connected to the counter output. The output of the analog switch array is connected to the input of a subtractor, the other input of the subtractor is connected to the reference voltage, and the output of the subtractor is connected to the inverting input of a comparator. The output of the comparator is connected to the serial input of a bidirectional shift register, the clock terminal of the bidirectional shift register is connected to the synchronous clock clk signal, and the latch terminal is connected to the signal of the dual-loop switching module.

[0018] Preferably, the output of the error detection unit is connected to the data input of the error judgment register (ER); the output of the error judgment register is connected to the input of the FSM; the output of the FSM is connected to the write enable terminal and the data input terminal of the intermediate result register (IR); the output of the intermediate result register is connected to the gate of the Fibonacci PMOS array via an inverter chain; the FSM also outputs an iterative control signal to the error detection unit to realize the deviation update closed loop.

[0019] Preferably, the two input terminals of the comparator are respectively connected to the output voltage V. out With reference voltage V ref The output terminal is connected to the input terminal of the hysteresis control circuit; the output terminal (FIN) of the hysteresis control circuit is connected to the latch enable terminal of the bidirectional shift register of the coarse ring adjustment module, the start enable terminal of the fine ring adjustment module FSM, and the state holding terminal of the fine ring PMOS array.

[0020] Preferably, the coarse-ring PMOS array and the fine-ring PMOS array are connected in parallel, and the sources of all PMOS arrays are connected to the input voltage Vin, and the drains are connected to the output voltage. The width-to-length ratio of the coarse-ring PMOS array is designed according to the binary weight ratio, and the width-to-length ratio of the fine-ring PMOS array is designed according to the Fibonacci weight ratio.

[0021] An improved method for PMOS array control logic applied to a dual-loop controlled DLDO is presented. The control logic uses a synchronous sequential logic structure (FSM) built upon D flip-flops. It achieves iterative buffering and precise adjustment through "state partitioning - signal interaction - closed-loop control." The FSM contains four mutually exclusive states: initialization state, iterative decision state, register update state, and termination judgment state. The implementation process is as follows:

[0022] S0, initialization state: Input signals are the FIN signal (active high) of the dual-loop switching module and the system reset signal RST (active low); output signals are the ER reset signal (RST_ER), the IR reset signal (RST_IR), and the error detection unit start signal (START_ADC); the operation logic is as follows: when FIN=1 and RST=1, FSM enters S0, resets ER and IR, and starts the error detection unit to quantize the remaining deviation of the coarse loop: the error detection unit compares Vout and Vref to obtain ΔVres, and uses the ADC to convert ΔV... res Convert to digital quantity and store in ER. After completion, output ADC_DONE to FSM. After quantization is complete, trigger state jump to S1.

[0023] S1, Iterative Decision State: Input signals are the digital value of the ER deviation and the Fibonacci step size selection signal (STEP_SEL), generated internally by the FSM. A 3-bit binary signal selects the 8-bit Fibonacci step size in "high-bit → low-bit" order. Output signals are the step size comparison signal CMP_STEP and the IR write enable signal WE_IR. The action logic is to read the current Fibonacci step size in "high-bit → low-bit" order and compare it with the built-in hardware comparator (the built-in hardware comparator and...). Figure 4 The comparator is irrelevant; it is only used to compare the digital value of the deviation amplitude in ER with the preset digital value of the Fibonacci step size to determine whether the remaining deviation is greater than or equal to the current step size. The CMP_STEP signal is output, where 1 indicates that the condition is met and 0 indicates that the condition is not met. If the condition is met, WE_IR is set to prepare to update the IR state, and then the process jumps to S2. If the condition is not met, the process jumps directly to S2 without updating the IR.

[0024] S2, Register Update Status: Input signals are the step size comparison signal CMP_STEP and the current bit selection signal; output signals are the ER update signal UPD_ER, the IR bit status signal, and the status count signal; the action logic is as follows: if CMP_STEP=1, the corresponding bit of IR is set to 1, and the new deviation is calculated by the hardware subtractor (when CMP_STEP=1, the hardware subtractor performs the numerical operation "new deviation = current deviation - current Fibonacci step size", and the calculation result is written to ER through the UPD_ER signal to realize the real-time update of the deviation and ensure the accuracy of iterative calibration). The UPD_ER signal is output to update ER; if CMP_STEP=0, the corresponding bit of IR remains 0, and ER retains the original deviation value; then the count signal is incremented by 1 to determine whether all bit iterations have been completed. If not, it jumps to S1 to continue to the next bit judgment; if it has been completed, it jumps to S3;

[0025] S3, Termination Judgment State: The input signal is the final deviation value of ER and the accuracy threshold signal (the accuracy threshold is set according to the scenario: 0.02mV for high-precision scenarios (sensor), and 0.1mV for normal scenarios (MCU), ensuring V out Stable at ±V ref Within the threshold); the output signals are the fine-loop adjustment module completion signal FINE_DONE and the IR latch signal LOCK_IR; the action logic is to compare the final deviation with the accuracy threshold. If the final deviation is less than or equal to the accuracy threshold, output FINE_DONE=1 and LOCK_IR=1, latch the IR state, and maintain the current conduction combination of the PMOS array; if the final deviation is greater than the accuracy threshold, output RST_IR=1, reset the IR, and jump to S1 to iterate again; the FINE_DONE signal is also fed back to the dual-loop switching module to maintain the working state of the fine-loop adjustment module.

[0026] Preferably, a collaborative mechanism of "coarse loop rapid pull-back - dual loop precise switching - fine loop iterative calibration" is adopted. When the load current changes suddenly or the input voltage fluctuates, causing the output voltage V to drop, the mechanism will be activated. out Deviation from reference voltage V ref When a large deviation occurs, the dual-loop switching module quickly identifies that the deviation exceeds the adjustment range of the fine-loop adjustment module through a comparator, and then activates the coarse-loop adjustment module. The coarse-loop adjustment module, based on an 8-bit coarse-loop PMOS array, in conjunction with a dynamic reference voltage generation circuit and a comparator, determines the conduction state of the PMOS transistors bit by bit according to the "highest bit priority" principle, and dynamically generates a reference voltage V that matches the current bit step size. ref_adj =V ref -V stepk V stepk This represents the current iteration step size of the coarse ring; compare with V. out With V ref_adj The size of V out Below V ref_adj Then the corresponding PMOS transistor is turned on to supplement the adjustment amount. If V out Higher than V ref_adj Then, the corresponding PMOS transistor is turned off to compensate for the adjustment. After all bit iterations are completed, the shift register latches the output control signal to achieve rapid pull-back of large deviations, making V our rapidly approaching V ref The remaining deviation is reduced to the adjustment range of the fine-ring adjustment module;

[0027] At this point, the hysteresis control circuit of the dual-loop switching module precisely triggers the switching, latching the conduction state of the coarse-loop PMOS array, and simultaneously initiating the adjustment of the fine-loop adjustment module to eliminate minor residual deviations. The fine-loop adjustment module, relying on an 8-bit Fibonacci PMOS array and an FSM, first uses an error detection unit to quantify the residual deviation ΔV. res And store it in the error judgment register ER. FSM judges the relationship between the Fibonacci step size and the remaining deviation bit by bit in the order from "high to low". If ΔV res If the current step size is greater than or equal to the current step size, the corresponding PMOS transistor is turned on and the deviation is updated. The intermediate result register IR temporarily stores the iteration state to avoid voltage fluctuations until the remaining deviation meets the preset accuracy requirement. The FSM latches the IR state and outputs a completion signal, ultimately causing V to... out Stable at V ref Within the high precision range.

[0028] Preferably, the implementation process is as follows:

[0029] (1) Initial state and deviation generation

[0030] After the system is powered on, the DLDO is in standby mode, the bidirectional shift register and the intermediate result register IR are both reset to all 0, all PMOS transistors are turned off, and the output voltage is maintained at a low level by the load resistor;

[0031] A sudden change in load current causes a large deviation in the output voltage. At this time, the deviation exceeds the adjustment range of the fine-loop adjustment module. The comparator of the dual-loop switching module outputs a high level, the hysteresis control circuit outputs FIN=0, the coarse-loop adjustment module is started, and the fine-loop adjustment module remains disabled.

[0032] (2) Working process of coarse ring adjustment module

[0033] ① Coarse ring initialization: The counter is reset to the initial state (corresponding to the highest bit step size), the analog switch of the dynamic reference voltage generation circuit selects the highest bit resistor voltage divider, and the subtractor calculates the dynamic reference voltage; the shift register is reset to all 0, the latch enable terminal is low, and the output remains all 0.

[0034] ② Iteration bit by bit:

[0035] a. The comparator compares the output voltage with the dynamic reference voltage and outputs the CMP_OUT signal based on the comparison result;

[0036] b. The rising edge of the synchronous clock triggers the shift register, serially shifting the CMP_OUT signal into the corresponding bit and updating the shift register state;

[0037] c. The counter increments automatically, and the analog switch sequentially selects the subsequent resistor divider. The resistor divider is located between Vref and ground. Eight precision resistors (accuracy ≤ ±0.1%) are connected in series in binary. After selection, the voltage divider signal is output. The dynamic reference voltage is updated synchronously, and the comparison and shifting process is repeated.

[0038] ③ Coarse-ring latch and output:

[0039] a. After all bit iterations are completed, the counter overflows and outputs an overflow signal to the FSM;

[0040] b. The dual-loop switching module detects that the output voltage deviation falls into the fine adjustment range of the fine-loop adjustment module, and outputs FIN=1;

[0041] c. When the shift register latch enable terminal receives the FIN signal, it latches the current state and outputs control signals in parallel;

[0042] d. The gate drive circuit converts the control signal into the PMOS gate level, turning on the corresponding PMOS transistor and turning off the other PMOS transistors;

[0043] e. The conducting PMOS transistor provides the total regulation, and the output voltage is quickly pulled back to near the reference voltage, with the deviation falling into the adjustment range of the fine-loop regulation module;

[0044] ④ Dual-loop switching: The FSM confirms "counter overflow" and "deviation falls within the adjustment range of the fine-loop adjustment module", and outputs a latch signal (latch coarse-loop state) and a start signal (start fine-loop);

[0045] (3) Working process of the fine ring adjustment module

[0046] ①Fine-ring initialization:

[0047] a. When the FSM receives the start signal, it enters the S0 state and outputs a reset signal to reset ER and IR;

[0048] b. The FSM outputs a start signal to activate the error detection unit, which quantizes the remaining deviation of the coarse loop and stores the resulting digital value in the ER.

[0049] c. After quantization, the FSM jumps to the S1 state and the counting signal is initialized (corresponding to the highest bit Fibonacci step size).

[0050] ② Iterative calibration of fine loops:

[0051] a. Bit-by-bit judgment: Select the Fibonacci step size in the order of "high bit → low bit", and use the built-in comparator to judge the relationship between the remaining deviation and the current step size;

[0052] b. Status update: If the remaining deviation is greater than or equal to the current step size, update the status of the corresponding bit of IR and the ER deviation value; if it is less than, it remains unchanged and the counting signal continues to increment.

[0053] c. After all bit iterations are completed, the counting signal reaches the set value and jumps to state S3;

[0054] ③ Termination judgment and steady-state maintenance:

[0055] a. The FSM reads the final deviation value of ER, compares it with the accuracy threshold, and if the accuracy requirement is met, it outputs LOCK_IR=1 and latches the IR state;

[0056] b. The Fibonacci PMOS array turns on the corresponding transistor according to the latching state, providing precise adjustment;

[0057] c. The coarse-ring PMOS array and the fine-ring PMOS array work together to stabilize the output voltage within the target value ± accuracy threshold range;

[0058] d. The FSM periodically triggers deviation detection to maintain steady-state output. If load fluctuations cause the deviation to exceed the threshold, it automatically restarts the iterative calibration.

[0059] (4) The collaborative working process of FSM and coarse ring counter

[0060] The connection between the FSM and the coarse-loop counter is a unidirectional signal exchange (counter→FSM). The core implementation achieves dual-loop collaborative control without FSM→counter control intervention. The specific process is as follows:

[0061] ① Iteration progress synchronization: The counter count status of the coarse loop adjustment module is transmitted to the FSM in real time. The FSM uses this signal to confirm the current iteration position of the coarse loop adjustment module, ensuring that the fine loop adjustment module is started only after the coarse loop adjustment module has completed all iterations.

[0062] ② Iteration termination confirmation: The counter overflow signal of the coarse loop adjustment module is connected to the FSM. The FSM will only trigger the dual-loop switching module when the overflow signal is valid and the deviation falls within the adjustment range of the fine loop adjustment module, so as to avoid insufficient adjustment caused by incomplete iteration of the coarse loop adjustment module.

[0063] ③ Timing synchronization control: The synchronization clock of the counter of the coarse-loop adjustment module also serves as the synchronization clock of the FSM, ensuring seamless connection between the latching of the coarse-loop adjustment module and the initialization of the fine-loop adjustment module, and avoiding voltage fluctuations;

[0064] ④ Switching anti-jitter: After receiving the overflow signal, the FSM delays the clock cycle and then latches the state of the fine-loop adjustment module to filter out instantaneous deviations during the iteration process and reduce switching jitter.

[0065] For any details not covered in this invention, please refer to the prior art.

[0066] The beneficial effects of this invention are as follows:

[0067] The coarse-loop adjustment module of the present invention does not require ADC quantization. It achieves step size determination through dynamic reference voltage and comparator, which simplifies the circuit area, increases the adjustment speed, and reduces the overshoot amplitude.

[0068] The Fibonacci step density of the fine-loop adjustment module is higher than that of the same-bit binary module, with small residual deviation and low steady-state ripple.

[0069] The dual-loop switching module uses a hysteresis control circuit in conjunction with an FSM-counter, resulting in fewer switching operations when there are no load changes, making it suitable for a wide load range.

[0070] The unidirectional signal interaction between the FSM and the coarse-loop counter ensures dual-loop timing synchronization and complete iteration, further reducing switching jitter and voltage fluctuations. Attached Figure Description

[0071] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an undue limitation of this application.

[0072] Figure 1 This is a schematic diagram of the basic dual-ring DLDO framework;

[0073] Figure 2 The state transition diagram is for a finite state machine (FSM).

[0074] Figure 3 The diagram shows a fine-ring PMOS array using a Fibonacci PMOS array and a coarse-ring PMOS array using binary weights, where (a) is a fine-ring PMOS array and (b) is a coarse-ring PMOS array.

[0075] Figure 4 This is a schematic diagram of the DLDO framework proposed in this invention;

[0076] Figure 5 This is a schematic diagram of the transient response waveform of the circuit. Detailed Implementation

[0077] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. However, this is not the only description; all aspects not described in detail herein are based on conventional techniques in the art.

[0078] Example 1

[0079] A PMOS array for use in dual-loop controlled DLDOs, the basic framework of a dual-loop DLDO is as follows: Figure 1 As shown, it consists of comparators and control logic circuits, a voltage comparator, a bidirectional shifter, and a coarse-ring PMOS array and a fine-ring PMOS array. C L Indicates the load capacitance, I LOAD This indicates the load current.

[0080] This embodiment applies to a PMOS array of a dual-loop controlled DLDO, such as... Figure 4 As shown, it includes a coarse-loop adjustment module, a fine-loop adjustment module, and a dual-loop switching module. The modules are connected to form a complete system with clear signal flow and no logical conflicts.

[0081] like Figure 3 As shown, the coarse-ring adjustment module consists of an 8-bit coarse-ring PMOS array, a dynamic reference voltage generation circuit, a comparator, and an 8-bit bidirectional shift register, and judges the conduction state bit by bit based on the "high-bit priority" principle.

[0082] The fine-loop adjustment module consists of a fine-loop PMOS array, an error judgment register, an intermediate result register, an error detection unit, and an FSM; the fine-loop PMOS array is an 8-bit Fibonacci PMOS array, which is based on iterative correction of residual deviation;

[0083] Dual-loop switching module: Employs a comparator and hysteresis control circuit to achieve seamless connection between the coarse-loop adjustment module and the fine-loop adjustment module;

[0084] The reference voltage source is connected to the reference input terminals of the dynamic reference voltage generation circuit, the error detection unit, and the dual-loop switching module, respectively; the input voltage V ref Connect the sources of the thick-ring PMOS array and the thin-ring PMOS array; output voltage V out The signals are respectively connected to the non-inverting input of the comparator, the input of the error detection unit, and the signal input of the dual-loop switching module;

[0085] The output of the bidirectional shift register of the coarse-loop adjustment module and the output of the intermediate result register IR of the fine-loop adjustment module are connected to the gate portions of the coarse-loop PMOS array and the fine-loop PMOS array, respectively; the FSM (finite state machine) outputs control signals to the counter of the coarse-loop adjustment module, the error judgment register ER of the fine-loop adjustment module, and the intermediate result register IR, respectively; the output signal FIN of the dual-loop switching module is connected to the latch terminal of the shift register of the coarse-loop adjustment module and the start terminal of the FSM of the fine-loop adjustment module, respectively, to realize dual-loop coordinated control;

[0086] The drains of the binary coarse-loop PMOS array in the coarse-loop regulation module and the Fibonacci PMOS array in the fine-loop regulation module are connected to the output voltage terminal through the load resistor R. L Grounding forms a complete power supply circuit.

[0087] Load resistance R L It is the external load equivalent resistance of the DLDO (equivalent to the load chip in the actual application scenario), and the load capacitance C. L Connected in parallel between Vout and ground; load capacitance C L Used to suppress output voltage ripple and improve transient response stability (typical value 1nF~10nF), load resistor R L This determines the quiescent operating current, and the two together form the output load network of the DLDO, ensuring stable output voltage.

[0088] Example 2

[0089] A PMOS array for a dual-loop controlled DLDO, as shown in Example 1, differs in that the dynamic reference voltage generation circuit in the coarse-loop adjustment module consists of multiple precision resistor dividers connected in series with an analog switch array. The total input of the resistor dividers is connected to a reference voltage, and the control terminal of the analog switch array is connected to the counter output. The output of the analog switch array is connected to the input of a subtractor, the other input of the subtractor is connected to the reference voltage, and the output of the subtractor is connected to the inverting input of a comparator. The dynamic reference voltage is... Figure 4 V in ref_adjIt is generated by the dynamic reference voltage generation circuit, and the calculation formula is V. ref_adj =V ref- V stepk (V) stepk (This is the adjustment step size for the current iteration bit), used to determine whether the PMOS transistor needs to be turned on bit by bit in the coarse loop, so as to achieve rapid pullback when there is a large deviation; the comparator output is connected to the serial input of the bidirectional shift register, the clock end of the bidirectional shift register is connected to the synchronous clock clk signal, and the latch end is connected to the signal of the dual-loop switching module.

[0090] In the fine-loop adjustment module, the output of the error detection unit is connected to the data input of the error judgment register (ER); the output of the error judgment register is connected to the input of the FSM; the output of the FSM is connected to the write enable terminal and the data input terminal of the intermediate result register (IR); the output of the intermediate result register is connected to the gate of the Fibonacci PMOS array via an inverter chain; the FSM also outputs an iterative control signal to the error detection unit to realize the deviation update closed loop.

[0091] In the dual-loop switching module, the two input terminals of the comparator are respectively connected to the output voltage V. out With reference voltage V ref The output terminal is connected to the input terminal of the hysteresis control circuit; the output terminal (FIN) of the hysteresis control circuit is connected to the latch enable terminal of the bidirectional shift register of the coarse ring adjustment module, the start enable terminal of the fine ring adjustment module FSM, and the state holding terminal of the fine ring PMOS array.

[0092] The coarse-ring PMOS array and the fine-ring PMOS array are connected in parallel. The sources of all PMOS arrays are connected to the input voltage Vin, and the drains are connected to the output voltage. The width-to-length ratio of the coarse-ring PMOS array is designed according to the binary weight ratio, and the width-to-length ratio of the fine-ring PMOS array is designed according to the Fibonacci weight ratio.

[0093] The present invention enables the system to react quickly when the load current or input voltage changes, turn on more PMOS transistors more quickly, reduce overshoot / undershoot, and reduce output voltage fluctuation in steady state.

[0094] Example 3

[0095] An improved method for PMOS array control logic applied to a dual-loop controlled DLDO is proposed. In the control logic, the FSM is a synchronous sequential logic structure built upon D flip-flops. The state transition diagram is shown below. Figure 2 As shown, iterative storage and precise adjustment are achieved through "state division - signal interaction - closed-loop control". The FSM contains four mutually exclusive states: initialization state, iterative decision state, register update state, and termination judgment state. Each state is triggered by a clear input signal, with no state conflicts. The state switching logic is as follows: Figure 2As shown. The input, output, and action logic for each state are clear, with no state conflicts. The implementation process is as follows:

[0096] S0, initialization state: Input signals are the FIN signal (active high) of the dual-loop switching module and the system reset signal RST (active low); output signals are the ER reset signal (RST_ER), the IR reset signal (RST_IR), and the error detection unit start signal (START_ADC); the operation logic is as follows: when FIN=1 and RST=1, FSM enters S0, resets ER and IR, and starts the error detection unit to quantize the remaining deviation of the coarse loop: the error detection unit compares Vout and Vref to obtain ΔVres, and uses the ADC to convert ΔV... res Convert to digital quantity and store in ER. After completion, output ADC_DONE to FSM. After quantization is complete, trigger state jump to S1.

[0097] S1, Iterative Decision State: Input signals are the digital value of the ER deviation and the Fibonacci step size selection signal (STEP_SEL), generated internally by the FSM. A 3-bit binary signal selects the 8-bit Fibonacci step size in "high-bit → low-bit" order. Output signals are the step size comparison signal CMP_STEP and the IR write enable signal WE_IR. The action logic is to read the current Fibonacci step size in "high-bit → low-bit" order and compare it with the built-in hardware comparator (the built-in hardware comparator and...). Figure 4 The comparator is irrelevant; it is only used to compare the digital value of the deviation amplitude in ER with the preset digital value of the Fibonacci step size to determine whether the remaining deviation is greater than or equal to the current step size. The CMP_STEP signal is output, where 1 indicates that the condition is met and 0 indicates that the condition is not met. If the condition is met, WE_IR is set to prepare to update the IR state, and then the process jumps to S2. If the condition is not met, the process jumps directly to S2 without updating the IR.

[0098] S2, Register Update Status: Input signals are the step size comparison signal CMP_STEP and the current bit selection signal; output signals are the ER update signal UPD_ER, the IR bit status signal, and the status count signal; the action logic is as follows: if CMP_STEP=1, the corresponding bit of IR is set to 1, and the new deviation is calculated by the hardware subtractor (when CMP_STEP=1, the hardware subtractor performs the numerical operation "new deviation = current deviation - current Fibonacci step size", and the calculation result is written to ER through the UPD_ER signal to realize the real-time update of the deviation and ensure the accuracy of iterative calibration). The UPD_ER signal is output to update ER; if CMP_STEP=0, the corresponding bit of IR remains 0, and ER retains the original deviation value; then the count signal is incremented by 1 to determine whether all bit iterations have been completed. If not, it jumps to S1 to continue to the next bit judgment; if it has been completed, it jumps to S3;

[0099] S3, Termination Judgment State: The input signal is the final deviation value of ER and the accuracy threshold signal (the accuracy threshold is set according to the scenario: 0.02mV for high-precision scenarios (sensor), and 0.1mV for normal scenarios (MCU), ensuring V out Stable at ±V ref Within the threshold); the output signals are the fine-loop adjustment module completion signal FINE_DONE and the IR latch signal LOCK_IR; the action logic is to compare the final deviation with the accuracy threshold. If the final deviation is less than or equal to the accuracy threshold, output FINE_DONE=1 and LOCK_IR=1, latch the IR state, and maintain the current conduction combination of the PMOS array; if the final deviation is greater than the accuracy threshold, output RST_IR=1, reset the IR, and jump to S1 to iterate again; the FINE_DONE signal is also fed back to the dual-loop switching module to maintain the working state of the fine-loop adjustment module.

[0100] The signal interaction between the FSM and other components also includes: with the Error Decision Register (ER): the FSM outputs RST_ER (reset) and UPD_ER (update) signals, and the ER outputs the digital value of the deviation to the FSM, realizing a "read-determine-update" closed loop for the deviation; with the Intermediate Result Register (IR): the FSM outputs RST_IR (reset), WE_IR (write enable), and LOCK_IR (latch) signals, and the IR outputs the current conduction state to the FSM, ensuring that the temporary state is not lost during iteration; with the Error Detection Unit: the FSM outputs START_ADC (start quantization) and STEP_SEL (step size selection) signals, and the Error Detection Unit outputs the quantization completion signal to the FSM, synchronizing the iteration rhythm; with the Dual-Loop Switching Module: the FSM receives the FIN (start signal) and outputs the FINE_DONE (complete signal), realizing dual-loop state coordination.

[0101] Example 4

[0102] An improved method for PMOS array control logic applied to a dual-loop controlled DLDO, as shown in Example 3, differs in that it employs a collaborative mechanism of "coarse loop fast pull-back - dual-loop precise switching - fine loop iterative calibration." When a sudden change in load current or fluctuation in input voltage causes a change in output voltage V... out Deviation from reference voltage V ref When a large deviation occurs, the dual-loop switching module quickly identifies that the deviation exceeds the adjustment range of the fine-loop adjustment module through a comparator. The comparator uses V... ref Preset fine ring range (Vref-Δ, Vref+Δ): V out When it falls outside the range, the coarse ring is activated, V outWhen the voltage falls within the range, the fine ring switches, and the coarse ring adjustment module is then activated. The coarse ring adjustment module, based on an 8-bit coarse ring PMOS array, works in conjunction with a dynamic reference voltage generation circuit and a comparator to determine the conduction state of the PMOS transistors bit by bit according to the "highest bit priority" principle. It then dynamically generates a reference voltage V that matches the current bit step size. ref_adj =V ref -V stepk V stepk The current iteration step size of the coarse ring is 2. k Design (0≤k≤7, e.g., V) step7 =20mV、V step0 =0.15625mV), obtained by a resistor divider + analog switch selection; compared with V out With V ref_adj The size of V out Below V ref_adj Then the corresponding PMOS transistor is turned on to supplement the adjustment amount. If V out Higher than V ref_adj Then, the corresponding PMOS transistor is turned off to compensate for the adjustment. After all bit iterations are completed, the shift register latches the output control signal to achieve rapid pull-back of large deviations, making V our rapidly approaching V ref The remaining deviation is reduced to the adjustment range of the fine-ring adjustment module;

[0103] At this point, the hysteresis control circuit of the dual-loop switching module precisely triggers the switching, latching the conduction state of the coarse-loop PMOS array, and simultaneously initiating the adjustment of the fine-loop adjustment module to eliminate minor residual deviations. The fine-loop adjustment module, relying on an 8-bit Fibonacci PMOS array and an FSM, first uses an error detection unit to quantify the residual deviation ΔV. res And store it in the error judgment register ER. FSM judges the relationship between the Fibonacci step size and the remaining deviation bit by bit in the order from "high to low". If ΔV res If the current step size is greater than or equal to the current step size, the corresponding PMOS transistor is turned on and the deviation is updated. The intermediate result register IR temporarily stores the iteration state to avoid voltage fluctuations until the remaining deviation meets the preset accuracy requirement. The FSM latches the IR state and outputs a completion signal, ultimately causing V to... out Stable at V ref Within the high precision range.

[0104] The implementation process is as follows:

[0105] (1) Initial state and deviation generation

[0106] After the system is powered on, the DLDO is in standby mode, the bidirectional shift register and the intermediate result register IR are both reset to all 0, all PMOS transistors are turned off, and the output voltage is maintained at a low level by the load resistor;

[0107] A sudden change in load current causes a large deviation in the output voltage. At this time, the deviation exceeds the adjustment range of the fine-loop adjustment module. The comparator of the dual-loop switching module outputs a high level, the hysteresis control circuit outputs FIN=0, the coarse-loop adjustment module is started, and the fine-loop adjustment module remains disabled.

[0108] (2) Working process of coarse ring adjustment module

[0109] ① Coarse ring initialization: The counter is reset to the initial state (corresponding to the highest bit step size), the analog switch of the dynamic reference voltage generation circuit selects the highest bit resistor voltage divider, and the subtractor calculates the dynamic reference voltage; the shift register is reset to all 0, the latch enable terminal is low, and the output remains all 0.

[0110] ② Iteration bit by bit:

[0111] a. The comparator compares the output voltage with the dynamic reference voltage and outputs the CMP_OUT signal based on the comparison result;

[0112] b. The rising edge of the synchronous clock triggers the shift register, serially shifting the CMP_OUT signal into the corresponding bit and updating the shift register state;

[0113] c. The counter increments automatically, and the analog switch sequentially selects the subsequent resistor divider. The resistor divider is located between Vref and ground. Eight precision resistors (accuracy ≤ ±0.1%) are connected in series in binary. After selection, the voltage divider signal is output. The dynamic reference voltage is updated synchronously, and the comparison and shifting process is repeated.

[0114] ③ Coarse-ring latch and output:

[0115] a. After all bit iterations are completed, the counter overflows and outputs an overflow signal to the FSM;

[0116] b. The dual-loop switching module detects that the output voltage deviation falls into the fine adjustment range of the fine-loop adjustment module, and outputs FIN=1;

[0117] c. When the shift register latch enable terminal receives the FIN signal, it latches the current state and outputs control signals in parallel;

[0118] d. The gate drive circuit converts the control signal into the PMOS gate level, turning on the corresponding PMOS transistor and turning off the other PMOS transistors;

[0119] e. The conducting PMOS transistor provides the total regulation, and the output voltage is quickly pulled back to near the reference voltage, with the deviation falling into the adjustment range of the fine-loop regulation module;

[0120] ④ Dual-loop switching: The FSM confirms "counter overflow" and "deviation falls within the adjustment range of the fine-loop adjustment module", and outputs a latch signal (latch coarse-loop state) and a start signal (start fine-loop);

[0121] (3) Working process of the fine ring adjustment module

[0122] ①Fine-ring initialization:

[0123] a. When the FSM receives the start signal, it enters the S0 state and outputs a reset signal to reset ER and IR;

[0124] b. The FSM outputs a start signal to activate the error detection unit, which quantizes the remaining deviation of the coarse loop and stores the resulting digital value in the ER.

[0125] c. After quantization, the FSM jumps to the S1 state and the counting signal is initialized (corresponding to the highest bit Fibonacci step size).

[0126] ② Iterative calibration of fine loops:

[0127] a. Bit-by-bit judgment: Select the Fibonacci step size in the order of "high bit → low bit", and use the built-in comparator to judge the relationship between the remaining deviation and the current step size;

[0128] b. Status update: If the remaining deviation is greater than or equal to the current step size, update the status of the corresponding bit of IR and the ER deviation value; if it is less than, it remains unchanged and the counting signal continues to increment.

[0129] c. After all bit iterations are completed, the counting signal reaches the set value and jumps to state S3;

[0130] ③ Termination judgment and steady-state maintenance:

[0131] a. The FSM reads the final deviation value of ER, compares it with the accuracy threshold, and if the accuracy requirement is met, it outputs LOCK_IR=1 and latches the IR state;

[0132] b. The Fibonacci PMOS array turns on the corresponding transistor according to the latching state, providing precise adjustment;

[0133] c. The coarse-ring PMOS array and the fine-ring PMOS array work together to stabilize the output voltage within the target value ± accuracy threshold range;

[0134] d. The FSM periodically triggers deviation detection to maintain steady-state output. If load fluctuations cause the deviation to exceed the threshold, it automatically restarts the iterative calibration.

[0135] (4) The collaborative working process of FSM and coarse ring counter

[0136] The connection between the FSM and the coarse-loop counter is a unidirectional signal exchange (counter→FSM). The core implementation achieves dual-loop collaborative control without FSM→counter control intervention. The specific process is as follows:

[0137] ① Iteration progress synchronization: The counter count status of the coarse loop adjustment module is transmitted to the FSM in real time. The FSM uses this signal to confirm the current iteration position of the coarse loop adjustment module, ensuring that the fine loop adjustment module is started only after the coarse loop adjustment module has completed all iterations.

[0138] ② Iteration termination confirmation: The counter overflow signal of the coarse loop adjustment module is connected to the FSM. The FSM will only trigger the dual-loop switching module when the overflow signal is valid and the deviation falls within the adjustment range of the fine loop adjustment module, so as to avoid insufficient adjustment caused by incomplete iteration of the coarse loop adjustment module.

[0139] ③ Timing synchronization control: The synchronization clock of the counter of the coarse-loop adjustment module also serves as the synchronization clock of the FSM, ensuring seamless connection between the latching of the coarse-loop adjustment module and the initialization of the fine-loop adjustment module, and avoiding voltage fluctuations;

[0140] ④ Switching anti-jitter: After receiving the overflow signal, the FSM delays the clock cycle and then latches the state of the fine-loop adjustment module to filter out instantaneous deviations during the iteration process and reduce switching jitter.

[0141] like Figure 5 The diagram shown illustrates the transient response waveform of the circuit, representing the load current I. load When a step mutation occurs, the V of the basic bicyclic DLDO out1 V of the DLDO designed in this invention out2 Output voltage transient response difference: When the load current suddenly changes (such as switching from a low load to a high load), the output voltage V of the basic dual-loop DLDO... out1 A significant downward fluctuation will occur, with the downward amplitude reaching V. dip1 It then gradually recovers to a steady state with a relatively gentle curve. The recovery time required to return to steady state from the lowest point of the downward surge is t. R1 The output voltage V of the DLDO of this invention... out2 Under the same load change triggering condition, the undershoot amplitude V dip2 Significantly less than V out1 V dip1 And the time t for recovery from the lowest point of the downward surge to steady state R2 Much shorter than t R1 The recovery curve is also steeper. This difference stems from the dual-loop architecture of this invention, which features "coarse-loop binary PMOS array for rapid pull-back of large deviations, fine-loop Fibonacci array for precise calibration of small deviations, and finite state machine and counter coordinated control." This architecture effectively solves the problems of slow pull-back of the coarse loop and iterative redundancy of the fine loop in the basic dual-loop DLDO, and ultimately achieves a lower voltage downsurge and a shorter steady-state recovery time under load change scenarios, demonstrating superior output voltage stability.

[0142] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A PMOS array applied to a dual-loop controlled DLDO, characterized in that, It includes a coarse ring adjustment module, a fine ring adjustment module, and a dual-ring switching module; The coarse-ring adjustment module consists of an 8-bit coarse-ring PMOS array, a dynamic reference voltage generation circuit, a comparator, and an 8-bit bidirectional shift register. The fine-ring adjustment module consists of a fine-ring PMOS array, an error judgment register, an intermediate result register, an error detection unit, and an FSM; the fine-ring PMOS array is an 8-bit Fibonacci PMOS array; Dual-loop switching module: Employs a comparator and hysteresis control circuit to achieve seamless connection between the coarse-loop adjustment module and the fine-loop adjustment module; The reference voltage source is connected to the reference input terminals of the dynamic reference voltage generation circuit, the error detection unit, and the dual-loop switching module, respectively; the input voltage V ref Connect the sources of the thick-ring PMOS array and the thin-ring PMOS array; output voltage V out The signals are respectively connected to the non-inverting input of the comparator, the input of the error detection unit, and the signal input of the dual-loop switching module; The output of the bidirectional shift register of the coarse-loop adjustment module and the output of the intermediate result register IR of the fine-loop adjustment module are connected to the gate portions of the coarse-loop PMOS array and the fine-loop PMOS array, respectively; the FSM outputs control signals to the counter of the coarse-loop adjustment module, the error judgment register ER of the fine-loop adjustment module, and the intermediate result register IR, respectively; the output signal FIN of the dual-loop switching module is connected to the latch terminal of the shift register of the coarse-loop adjustment module and the start terminal of the FSM of the fine-loop adjustment module, respectively, to realize dual-loop coordinated control; The drains of the binary coarse-loop PMOS array in the coarse-loop regulation module and the Fibonacci PMOS array in the fine-loop regulation module are connected to the output voltage terminal through the load resistor R. L Grounding forms a complete power supply circuit.

2. The PMOS array applied to a dual-ring controlled DLDO according to claim 1, characterized in that, Load resistance R L This is the external load equivalent resistance of the DLDO, and the load capacitance C. L Connected in parallel between Vout and ground; load capacitance C L Used to suppress output voltage ripple and improve transient response stability, load resistor R L This determines the quiescent operating current, and the two together form the output load network of the DLDO, ensuring stable output voltage.

3. The PMOS array applied to a dual-ring controlled DLDO according to claim 2, characterized in that, The dynamic reference voltage generation circuit consists of multiple precision resistor dividers connected in series with an analog switch array. The total input of the resistor dividers is connected to the reference voltage, and the control terminal of the analog switch array is connected to the counter output. The output of the analog switch array is connected to the input of a subtractor, the other input of which is connected to the reference voltage, and the output of the subtractor is connected to the inverting input of a comparator. The output of the comparator is connected to the serial input of a bidirectional shift register, the clock terminal of the bidirectional shift register is connected to the synchronous clock clk signal, and the latch terminal is connected to the signal of the dual-loop switching module.

4. The PMOS array applied to a dual-ring controlled DLDO according to claim 3, characterized in that, The output of the error detection unit is connected to the data input of the error judgment register ER; the output of the error judgment register is connected to the input of the FSM; the output of the FSM is connected to the write enable and data input of the intermediate result register IR respectively; the output of the intermediate result register is connected to the gate of the Fibonacci PMOS array via an inverter chain; the FSM also outputs an iterative control signal to the error detection unit to realize the deviation update closed loop.

5. The PMOS array applied to a dual-ring controlled DLDO according to claim 4, characterized in that, The two input terminals of the comparator are respectively connected to the output voltage V. out With reference voltage V ref The output terminal is connected to the input terminal of the hysteresis control circuit; the output terminal FIN of the hysteresis control circuit is connected to the latch enable terminal of the bidirectional shift register of the coarse ring adjustment module, the start enable terminal of the fine ring adjustment module FSM, and the state holding terminal of the fine ring PMOS array.

6. The PMOS array applied to a dual-loop controlled DLDO according to claim 5, characterized in that, The coarse-ring PMOS array and the fine-ring PMOS array are connected in parallel. The sources of all PMOS arrays are connected to the input voltage Vin, and the drains are connected to the output voltage. The width-to-length ratio of the coarse-ring PMOS array is designed according to the binary weight ratio, and the width-to-length ratio of the fine-ring PMOS array is designed according to the Fibonacci weight ratio.

7. An improved method for PMOS array control logic applied to a dual-loop controlled DLDO as described in claim 6, characterized in that, In the control logic, the FSM is a synchronous sequential logic structure. The FSM contains four mutually exclusive states: initialization state, iterative decision state, register update state, and termination judgment state. The implementation process is as follows: S0, initialization state: The input signals are the FIN signal of the dual-loop switching module and the system reset signal RST; the output signals are the ER reset signal, the IR reset signal, and the error detection unit start signal; the action logic is that when FIN=1 and RST=1, FSM enters S0, resets ER and IR, starts the error detection unit to quantize the remaining deviation of the coarse loop, and after quantization is completed, the trigger state jumps to S1; S1, Iterative Decision State: Input signals are the digital value of the ER deviation and the Fibonacci step size selection signal; output signals are the step size comparison signal CMP_STEP and the IR write enable signal WE_IR; the action logic is to read the current Fibonacci step size in the order of "high bit → low bit", determine whether the remaining deviation is greater than or equal to the current step size through the built-in hardware comparator, and output the CMP_STEP signal, 1 indicates success, 0 indicates failure. If success is achieved, WE_IR is set to prepare to update the IR state, and then jump to S2; if failure is achieved, jump directly to S2 without updating the IR. S2, Register Update Status: Input signals are the step size comparison signal CMP_STEP and the current bit selection signal; output signals are the ER update signal UPD_ER, the IR bit status signal, and the status count signal; the action logic is as follows: if CMP_STEP=1, set the corresponding IR bit to 1, and simultaneously calculate the new deviation through the hardware subtractor and output the UPD_ER signal to update ER; if CMP_STEP=0, the corresponding IR bit remains 0, and ER retains its original deviation value; then the count signal increments by 1 to determine whether all bit iterations have been completed. If not, jump to S1 to continue to the next bit; if completed, jump to S3. S3, Termination Judgment State: The input signals are the final deviation value of ER and the accuracy threshold signal; the output signals are the fine-loop adjustment module completion signal FINE_DONE and the IR latch signal LOCK_IR; the action logic is to compare the final deviation with the accuracy threshold. If the final deviation ≤ the accuracy threshold, output FINE_DONE=1 and LOCK_IR=1, latch the IR state, and maintain the current conduction combination of the PMOS array; if the final deviation > the accuracy threshold, output RST_IR=1, reset IR, and jump to S1 to iterate again. The FINE_DONE signal is simultaneously fed back to the dual-loop switching module to maintain the working state of the fine-loop adjustment module.

8. The improved method for PMOS array control logic applied to a dual-loop controlled DLDO according to claim 7, characterized in that, When the load current changes suddenly or the input voltage fluctuates, the output voltage V out Deviation from reference voltage V ref When a large deviation occurs, the dual-loop switching module quickly identifies that the deviation exceeds the adjustment range of the fine-loop adjustment module through a comparator, and then activates the coarse-loop adjustment module. The coarse-loop adjustment module, based on an 8-bit coarse-loop PMOS array, in conjunction with a dynamic reference voltage generation circuit and a comparator, determines the conduction state of the PMOS transistors bit by bit according to the "highest bit priority" principle, and dynamically generates a reference voltage V that matches the current bit step size. ref_adj =V ref -V stepk V stepk This represents the current iteration step size of the coarse ring; compare with V. out With V ref_adj The size of V out Below V ref_adj Then the corresponding PMOS transistor is turned on to supplement the adjustment amount. If V out Higher than V ref_adj Then, the corresponding PMOS transistor is turned off to compensate for the adjustment. After all bit iterations are completed, the shift register latches the output control signal to achieve rapid pull-back of large deviations, making V our rapidly approaching V ref The remaining deviation is reduced to the adjustment range of the fine-ring adjustment module; At this point, the hysteresis control circuit of the dual-loop switching module precisely triggers the switching, latching the conduction state of the coarse-loop PMOS array, and simultaneously initiating the adjustment of the fine-loop adjustment module to eliminate minor residual deviations. The fine-loop adjustment module, relying on an 8-bit Fibonacci PMOS array and an FSM, first uses an error detection unit to quantify the residual deviation ΔV. res And store it in the error judgment register ER. FSM judges the relationship between the Fibonacci step size and the remaining deviation bit by bit in the order from "high to low". If ΔV res If the current step size is greater than or equal to the current step size, the corresponding PMOS transistor is turned on and the deviation is updated. The intermediate result register IR temporarily stores the iteration state to avoid voltage fluctuations until the remaining deviation meets the preset accuracy requirement. The FSM latches the IR state and outputs a completion signal, ultimately causing V to... out Stable at V ref Within the range of high precision.

9. The improved method for PMOS array control logic applied to a dual-loop controlled DLDO according to claim 8, characterized in that, The implementation process is as follows: (1) Initial state and deviation generation After the system is powered on, the DLDO is in standby mode, the bidirectional shift register and the intermediate result register IR are both reset to all 0, all PMOS transistors are turned off, and the output voltage is maintained at a low level by the load resistor; A sudden change in load current causes a large deviation in the output voltage. At this time, the deviation exceeds the adjustment range of the fine-loop adjustment module. The comparator of the dual-loop switching module outputs a high level, the hysteresis control circuit outputs FIN=0, the coarse-loop adjustment module is started, and the fine-loop adjustment module remains disabled. (2) Working process of coarse ring adjustment module ① Coarse ring initialization: The counter is reset to the initial state, the analog switch of the dynamic reference voltage generation circuit selects the highest-order resistor voltage divider, and the subtractor calculates the dynamic reference voltage; the shift register is reset to all 0, the latch enable terminal is low, and the output remains all 0. ② Iteration bit by bit: a. The comparator compares the output voltage with the dynamic reference voltage and outputs the CMP_OUT signal based on the comparison result; b. The rising edge of the synchronous clock triggers the shift register, serially shifting the CMP_OUT signal into the corresponding bit and updating the shift register state; c. The counter increments automatically, the analog switches sequentially select the subsequent resistor dividers, the dynamic reference voltage is updated synchronously, and the comparison and shifting process is repeated; ③ Coarse-ring latch and output: a. After all bit iterations are completed, the counter overflows and outputs an overflow signal to the FSM; b. The dual-loop switching module detects that the output voltage deviation falls into the fine adjustment range of the fine-loop adjustment module, and outputs FIN=1; c. When the shift register latch enable terminal receives the FIN signal, it latches the current state and outputs control signals in parallel; d. The gate drive circuit converts the control signal into the PMOS gate level, turning on the corresponding PMOS transistor and turning off the other PMOS transistors; e. The conducting PMOS transistor provides the total regulation, and the output voltage is quickly pulled back to near the reference voltage, with the deviation falling into the adjustment range of the fine-loop regulation module; ④ Dual-loop switching: The FSM confirms "counter overflow" and "deviation falls within the adjustment range of the fine-loop adjustment module", and outputs latch signal and start signal; (3) Working process of the fine ring adjustment module ①Fine-ring initialization: a. When the FSM receives the start signal, it enters the S0 state and outputs a reset signal to reset ER and IR; b. The FSM outputs a start signal to activate the error detection unit, which quantizes the remaining deviation of the coarse loop and stores the resulting digital value in the ER. c. After quantization, the FSM jumps to state S1 to initialize the counting signal; ② Iterative calibration of fine loops: a. Bit-by-bit judgment: Select the Fibonacci step size in the order of "high bit → low bit", and use the built-in comparator to judge the relationship between the remaining deviation and the current step size; b. Status update: If the remaining deviation is greater than or equal to the current step size, update the status of the corresponding bit of IR and the ER deviation value; if it is less than, it remains unchanged and the counting signal continues to increment. c. After all bit iterations are completed, the counting signal reaches the set value and jumps to state S3; ③ Termination judgment and steady-state maintenance: a. The FSM reads the final deviation value of ER, compares it with the accuracy threshold, and if the accuracy requirement is met, it outputs LOCK_IR=1 and latches the IR state; b. The Fibonacci PMOS array turns on the corresponding transistor according to the latching state, providing precise adjustment; c. The coarse-ring PMOS array and the fine-ring PMOS array work together to stabilize the output voltage within the target value ± accuracy threshold range; d. The FSM periodically triggers deviation detection to maintain steady-state output. If load fluctuations cause the deviation to exceed the threshold, it automatically restarts the iterative calibration. (4) The collaborative working process of FSM and coarse ring counter ① Iteration progress synchronization: The counter count status of the coarse loop adjustment module is transmitted to the FSM in real time. The FSM confirms the current iteration position of the coarse loop adjustment module, ensuring that the fine loop adjustment module is started only after the coarse loop adjustment module has completed all iterations. ② Iteration termination confirmation: The counter overflow signal of the coarse loop adjustment module is connected to the FSM. The FSM will only trigger the dual-loop switching module when the overflow signal is valid and the deviation falls within the adjustment range of the fine loop adjustment module, so as to avoid insufficient adjustment caused by incomplete iteration of the coarse loop adjustment module. ③ Timing synchronization control: The synchronization clock of the counter of the coarse-loop adjustment module also serves as the synchronization clock of the FSM, ensuring seamless connection between the latching of the coarse-loop adjustment module and the initialization of the fine-loop adjustment module, and avoiding voltage fluctuations; ④ Switching anti-jitter: After receiving the overflow signal, the FSM delays the clock cycle and then latches the state of the fine-loop adjustment module to filter out instantaneous deviations during the iteration process and reduce switching jitter.

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