A fuse trimming device

Abstract

The application discloses a fuse trimming device, comprising: N trimming function modules 100 and a trimming enable module, N is the number of required fuse trimming positions in a chip system, wherein each trimming function module comprises: a trimming data signal input end, a trimming enable signal input end, a fuse output mode control signal input end and a trimming output signal output end, the trimming enable module comprises: a fuse fuse signal input end, an enable bit fuse fuse enable signal input end, a function bit fuse fuse enable signal input end and a trimming enable signal output end, the trimming enable signal input end is connected to the trimming enable signal output end; wherein the trimming function module is used for performing fuse trimming when receiving a first trimming enable signal output by the trimming enable signal output end, wherein the trimming enable module is used for controlling the fuse function of the trimming function module to be closed after the trimming function module completes fuse trimming. Thus, the reliability of fuse trimming is greatly improved.

Description

Technical Field

[0001] This invention relates to the field of fuse adjustment technology, and more specifically to a fuse adjustment device. Background Technology

[0002] Semiconductor manufacturing is an extremely complex physical and chemical process involving hundreds of steps. Even in top-tier factories, nanometer-level process variations are inevitable, such as minute differences in transistor size and uneven impurity concentration. These tiny deviations are amplified in analog circuits (such as reference voltage sources and clock oscillators), causing critical chip parameters (such as voltage and frequency) to deviate from their design values. Without adjustments, a power chip designed to output 1.8V might output 1.75V or 1.85V due to process variations. For high-precision equipment, even a tiny 0.05V error can lead to system instability. Adjustment is a method of adjusting chip parameters after manufacturing, using hardware or software. Adjustment can compensate for process variations, improve product yield, meet high-precision requirements, and adapt to complex environments.

[0003] The principle of tuning is essentially to change the electrical connection state or physical parameters of certain key components inside the chip. The most common method is to adjust a network of resistors, precisely fine-tuning voltage, current, or frequency by connecting or disconnecting certain resistors. Fuse tuning is the most widely used tuning method. Fuse tuning involves applying a large current to "burn out" the polysilicon or metal fuse on the chip. Before and after the fuse blows, the connection of the resistor network or other circuit structures changes, thereby achieving parameter adjustment.

[0004] Fuse tuning is simple in principle, widely used, and low in cost. However, its drawback is that once a fuse blows, it cannot be restored; it is a one-time programming process and irreversible. If a fuse blows incorrectly, it will directly lead to a decrease in chip performance or even prevent normal operation. Therefore, ensuring that the fuse blows correctly during tuning and that it does not blow incorrectly in subsequent operations is crucial for improving chip performance.

[0005] Related technologies have also proposed methods for fuse tuning. For example, patent document (application number: CN202211171397.1) discloses a fuse tuning device and method. Addressing the common problem of volatile output at the fuse-MOS switch connection point in previous fuse-MOS switch tuning structures, this patent adds a fuse status reading structure and introduces a non-volatile output port, eliminating the impact of signal volatility at the fuse-MOS switch connection point on the tuning results and improving tuning accuracy. However, the fuse tuning circuit structure proposed in this patent has a low reliability because the gate potential of the MOS switch connected to the fuse is not completely fixed under repeated power-on and power-off conditions. This can lead to a "power supply-fuse-MOS switch-ground" path being generated during repeated power-on and power-off processes, causing the fuse, which should not have blown, to blow accidentally during use. Summary of the Invention

[0006] To solve the above-mentioned technical problems, the present invention provides a fuse adjustment device. The fuse adjustment device introduces a safety mechanism, which can effectively prevent the fuse from accidentally blowing, thereby greatly improving the reliability of fuse adjustment.

[0007] The technical solution adopted in this invention is as follows:

[0008] A fuse trimming device includes: N trimming function modules and a trimming enable module, where N is the number of fuse trimming bits required in the chip system. Each trimming function module includes: a trimming data signal input terminal, a trimming enable signal input terminal, a fuse output mode control signal input terminal, and a trimming output signal output terminal. The trimming enable module includes: a fuse blowing signal input terminal, an enable bit fuse blowing enable signal input terminal, a function bit fuse blowing enable signal input terminal, and a trimming enable signal output terminal. The trimming enable signal input terminal is connected to the trimming enable signal output terminal. The trimming function modules are used for... Upon receiving the first adjustment enable signal output from the adjustment enable signal output terminal, the fuse adjustment is performed based on the externally input fuse adjustment data signal received from the adjustment data signal input terminal and the fuse output mode control signal received from the fuse output mode control signal input terminal. A corresponding fuse adjustment output signal is then output through the adjustment output signal output terminal. The adjustment enable module is used to output a second adjustment enable signal to the adjustment enable signal input terminal through the adjustment enable signal output terminal after the adjustment function module completes the fuse adjustment, so as to control the fuse breaking function of the adjustment function module to be turned off.

[0009] In one embodiment of the present invention, the fuse trimming device further includes: a bias generation module, the bias generation module including a bias current input terminal and a bias voltage output terminal, each trimming function module further including a first bias voltage input terminal, the trimming enable module further including a second bias voltage input terminal, the bias voltage output terminal being respectively connected to the first bias voltage input terminal and the second bias voltage input terminal, wherein the bias generation module is used to convert externally input bias current into bias voltage.

[0010] In one embodiment of the present invention, the trimming function module further includes: a first fuse control circuit, a first fuse status reading circuit, and a fuse output mode selection circuit; wherein, the first fuse control circuit includes: a target fuse, first to fourth PMOS transistors, first to fourth NMOS transistors, and a first resistor, wherein the source of the first PMOS transistor is connected to the chip power supply, the gate of the first PMOS transistor is connected to the trimming data signal input terminal, and the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor; the gate of the first NMOS transistor is connected to the trimming data signal input terminal, and the source of the first NMOS transistor is grounded; The gate of the second PMOS transistor is connected to the drain of the first PMOS transistor and the drain of the first NMOS transistor, respectively. The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the drain of the first PMOS transistor and the drain of the first NMOS transistor, respectively. The source of the second NMOS transistor is connected to the chip ground. The source of the third PMOS transistor is connected to the chip power supply. The gate of the third PMOS transistor is connected to the adjustment enable signal input terminal. The drain of the third PMOS transistor is connected to the source of the second PMOS transistor. The drain of the third NMOS transistor is connected to the drain of the second PMOS transistor and the drain of the second NMOS transistor, respectively. The gate of the third NMOS transistor is connected to the adjustment enable signal input terminal. The source of the third NMOS transistor is grounded. The drain of the fourth NMOS transistor is connected to one end of the first resistor. The gate of the fourth NMOS transistor is connected to the drain of the second PMOS transistor, the drain of the second NMOS transistor, and the drain of the third NMOS transistor, respectively. The source of the fourth NMOS transistor is grounded. The other end of the first resistor is connected to the chip power supply. The source of the fourth PMOS transistor is connected to the chip power supply. The gate of the fourth PMOS transistor... The first fuse status reading circuit includes: a second resistor, a third resistor, a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The drain of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the fifth PMOS transistor, and the gate of the sixth PMOS transistor. The gate of the fifth NMOS transistor is connected to the first bias voltage input terminal. The source of the fifth NMOS transistor is connected to one end of the second resistor; the other end of the second resistor is grounded. The drain of the sixth NMOS transistor is connected to the drain of the sixth PMOS transistor. The gate of the sixth NMOS transistor is connected to the first bias voltage input terminal and the gate of the fifth NMOS transistor. The source of the sixth NMOS transistor is connected to one end of the third resistor. The other end of the third resistor is connected to the drain of the fourth PMOS transistor and one end of the target fuse. The source of the fifth PMOS transistor is connected to the chip power supply. The source of the sixth PMOS transistor is connected to the chip power supply.The fuse output mode selection circuit includes: first to third inverters, a seventh PMOS transistor, an eighth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor. The source and drain of the seventh PMOS transistor are connected to the source and drain of the seventh NMOS transistor to form a first transmission gate. The source and drain of the eighth PMOS transistor are connected to the source and drain of the eighth NMOS transistor to form a second transmission gate. The gates of the seventh PMOS transistor and the eighth NMOS transistor are both connected to the fuse output mode control signal input terminal. The input terminal of the first inverter is connected to the fuse output mode control signal. The control signal input terminal, the output terminal of the first inverter I0 is connected to the gates of the seventh NMOS transistor and the eighth PMOS transistor, respectively; one end of the first transmission gate is connected to the drains of the sixth PMOS transistor and the sixth NMOS transistor, respectively; one end of the second transmission gate is connected to the trimming data signal input terminal; the input terminal of the second inverter is connected to the other ends of the first transmission gate and the second transmission gate, respectively; the input terminal of the third inverter is connected to the output terminal of the second inverter; and the output terminal of the third inverter I2 is connected to the trimming output signal output terminal.

[0011] In one embodiment of the present invention, the fifth NMOS transistor and the sixth NMOS transistor are the same size, and the channel width-to-length ratio of the fifth PMOS transistor is twice that of the channel width-to-length ratio of the sixth PMOS transistor.

[0012] In one embodiment of the present invention, the fifth PMOS transistor and the sixth PMOS transistor constitute a current mirror with an input-output current transfer ratio of 2:1; the fifth NMOS transistor and the sixth NMOS transistor constitute a current mirror with an input-output current transfer ratio of 1:1.

[0013] In one embodiment of the present invention, the adjustment enable module further includes: a second fuse control circuit, a second fuse status reading circuit, and an enable synthesis circuit, wherein the second fuse control circuit has the same circuit structure as the first fuse control circuit; the second fuse status reading circuit has the same circuit structure as the first fuse status reading circuit; the enable synthesis circuit includes: a fourth inverter and a NAND gate, the input terminal of the fourth inverter is connected to the output of the second fuse status reading circuit, one input terminal of the NAND gate is connected to the output terminal of the fourth inverter, the other input terminal of the NAND gate is connected to the function bit fuse fuse enable signal input terminal, and the output terminal of the NAND gate is connected to the adjustment enable signal output terminal.

[0014] In one embodiment of the present invention, the bias generation module further includes a ninth NMOS transistor and a fourth resistor, wherein the drain and gate of the ninth NMOS transistor are connected, the drain of the ninth NMOS transistor is also connected to the bias current input terminal, the gate of the ninth NMOS transistor is also connected to the bias voltage output terminal, the source of the ninth NMOS transistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is grounded.

[0015] In one embodiment of the present invention, the adjustment function module further includes a first working power input terminal, the adjustment enable module further includes a second working power input terminal, and the fuse adjustment device further includes a fuse blowing power module, wherein the fuse blowing power module includes a power supply input terminal and a working power output terminal, the power supply input terminal is connected to the chip reusable pad interface, and the working power output terminal is connected to the first working power input terminal and the second working power input terminal respectively.

[0016] In one embodiment of the present invention, the fuse-based power supply module includes a ninth PMOS transistor, a tenth PMOS transistor, and a tenth NMOS transistor. The source of the tenth PMOS transistor is connected to the chip power supply, the gate and drain of the tenth PMOS transistor are connected and both connected to the gate of the tenth NMOS transistor, the source of the tenth NMOS transistor is grounded, the drain of the tenth NMOS transistor is connected to the gate of the ninth PMOS transistor, the drain of the ninth PMOS transistor is connected to the chip's reusable pad interface, and the source of the ninth PMOS transistor is connected to the operating power supply output terminal.

[0017] The beneficial effects of this invention are: (1) This invention introduces a safety function in fuse adjustment to avoid the fuse from being accidentally blown by the MOS switch being turned on during the power-up and power-down process of the chip, and reduces the risk of subsequent functional bit fuses being accidentally blown under a specific combination of input signals by blowing the safety bit fuse after the adjustment is completed. (2) The present invention connects the fuse power supply through the reusable pad interface of the chip, which can flexibly adjust the voltage value of the fuse power supply without being limited by the voltage withstand of other devices in the chip, thereby improving the success rate of fuse blowing and reducing the risk of accidental fuse blowing after adjustment. Attached Figure Description

[0018] Figure 1 This is a block diagram of the fuse trimming device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the adjustment function module according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the adjustment enable module according to an embodiment of the present invention; Figure 4This is a schematic diagram of the bias generation module according to an embodiment of the present invention; Figure 5 This is a waveform diagram of the fuse trimming signal of a fuse trimming device according to an embodiment of the present invention; Figure 6 This is a block diagram of a fuse trimming device according to another embodiment of the present invention; Figure 7 This is a schematic diagram of the adjustment function module according to another embodiment of the present invention; Figure 8 This is a schematic diagram of the adjustment enable module according to another embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of a fuse-operated power supply module according to another embodiment of the present invention; Figure 10 The diagram shows the fuse adjustment signal waveform of a fuse adjustment device according to another embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Figure 1 This is a block diagram of the fuse adjustment device according to an embodiment of the present invention.

[0021] like Figure 1 As shown, the fuse trimming device of this embodiment may include: N trimming function modules 100 and trimming enable module 200, wherein N is the number of fuse trimming bits required in the chip system.

[0022] Each adjustment function module 100 includes: an adjustment data signal input terminal DATA1_IN, an adjustment enable signal input terminal ENN1, a fuse output mode control signal input terminal MODE, and an adjustment output signal output terminal DATA1_OUT. The adjustment enable module 200 may include: a fuse blow signal input terminal DATA2_IN, an enable bit fuse blow enable signal input terminal ENN2, a function bit fuse blow enable signal input terminal FUSE_EN, and an adjustment enable signal output terminal DATA2_OUT. The adjustment enable signal input terminal ENN1 is connected to the adjustment enable signal output terminal DATA2_OUT.

[0023] The trimming function module 100 is used to, upon receiving the first trimming enable signal output from the trimming enable signal output terminal DATA2_OUT, adjust the fuse trimming data signal (i.e., DATA_IN) received from the external input terminal DATA1_IN based on the externally input fuse trimming data signal (i.e., DATA_IN). <0> DATA_IN <1> ... DATA_IN <n-1>The fuse is adjusted using the fuse output mode control signal received at the fuse output mode control signal input terminal, and the corresponding fuse adjustment output signal (i.e., DATA_OUT) is output through the adjustment output signal output terminal DATA1_OUT. <0> DATA_OUT <1> ... DATA_OUT <n-1>The trimming enable module 200 is also used to output a second trimming enable signal to the trimming enable signal input terminal ENN1 through the trimming enable signal output terminal DATA2_OUT after the trimming function module 100 has completed the fuse trimming, so as to control the fuse function of the trimming function module 100 to be turned off.

[0024] Specifically, in this embodiment of the invention, the adjustment function module 100 is enabled under a first adjustment enable signal and disabled under a second adjustment enable signal. The first adjustment enable signal is a low-level signal, and the second adjustment enable signal is a high-level signal. That is, when the adjustment enable signal input terminal ENN1 receives the first adjustment enable signal, the adjustment function module 100 performs fuse adjustment; after the fuse adjustment is completed, the adjustment enable signal input terminal ENN1 receives the second adjustment enable signal, and the fuse-breaking function of the adjustment function module 100 is turned off. Thus, by introducing a safety mechanism into the fuse adjustment device, the erroneous fuse blowing situation can be effectively prevented, thereby greatly improving the reliability of fuse adjustment.

[0025] In one embodiment of the present invention, such as Figure 1 As shown, the fuse adjustment device also includes a bias generation module 300, which includes a bias current input terminal IBIAS_IN and a bias voltage output terminal VBIAS_OUT. Each adjustment function module 100 also includes a first bias voltage input terminal VBIAS1_IN, and the adjustment enable module 200 also includes a second bias voltage input terminal VBIAS2_IN. The bias voltage output terminal VBIAS_OUT is connected to the first bias voltage input terminal VBIAS1_IN and the second bias voltage input terminal VBIAS2_IN, respectively. The bias generation module 300 is used to convert the externally input bias current into a bias voltage.

[0026] In one embodiment of the present invention, such as Figure 2 As shown, the adjustment function module 100 also includes: a first fuse control circuit 101, a first fuse status reading circuit 102, and a fuse output mode selection circuit 103.

[0027] The first fuse control circuit 101 includes: a target fuse F0, first to fourth PMOS transistors (i.e., first PMOS transistor M0, second PMOS transistor M2, third PMOS transistor M4, and fourth PMOS transistor M7), first to fourth NMOS transistors (i.e., first NMOS transistor M1, second NMOS transistor M3, third NMOS transistor M5, and fourth NMOS transistor M6), and a first resistor R0. The source of the first PMOS transistor M0 is connected to the chip power supply, the gate of the first PMOS transistor M0 is connected to the adjustment data signal input terminal DATA1_IN, and the drain of the first PMOS transistor M0 is connected to the drain of the first NMOS transistor M1. The gate of the first NMOS transistor M1 is connected to the adjustment data signal input terminal DATA1_IN, and the source of the first NMOS transistor M1 is grounded. The first PMOS transistor M0 and the first NMOS transistor M1 form a typical inverter circuit. The gate of the second PMOS transistor M2 is connected to the drains of the first PMOS transistor M0 and the first NMOS transistor M1, respectively. The drain of the second PMOS transistor M2 is connected to the drain of the second NMOS transistor M3. The gate of the second NMOS transistor M3 is connected to the drains of the first PMOS transistor M0 and the first NMOS transistor M1, respectively. The source of the second NMOS transistor M3 is connected to the chip ground. The source of the third PMOS transistor M4 is connected to the chip power supply. The gate of the third PMOS transistor M4 is connected to the trim enable signal input terminal ENN1. The drain of the third PMOS transistor M4 is connected to the source of the second PMOS transistor M2. The drain of the third NMOS transistor M5 is connected to the drains of the second PMOS transistor M2 and the second NMOS transistor M3, respectively. The gate of OS transistor M5 is connected to the adjustment enable signal input terminal ENN1, and the source of the third NMOS transistor M5 is grounded; the drain of the fourth NMOS transistor M6 is connected to one end of the first resistor R0, and the gate of the fourth NMOS transistor M6 is connected to the drains of the second PMOS transistor M2, the second NMOS transistor M3, and the third NMOS transistor M5, respectively, and the source of the fourth NMOS transistor M6 is grounded; the other end of the first resistor R0 is connected to the chip power supply; the source of the fourth PMOS transistor M7 is connected to the chip power supply, and the gate of the fourth PMOS transistor M7 is connected to one end of the first resistor R0 and the drain of the fourth NMOS transistor M6, respectively, and the drain of the fourth PMOS transistor M7 is connected to one end of the target fuse F0; the other end of the target fuse F0 is grounded.

[0028] The first fuse status reading circuit 102 includes: a second resistor R1, a third resistor R2, a fifth PMOS transistor M11 and a sixth PMOS transistor M12, a fifth NMOS transistor M9 and a sixth NMOS transistor M10. The drain of the fifth NMOS transistor M9 is connected to the drain of the fifth PMOS transistor M11, the gate of the fifth PMOS transistor M11, and the gate of the sixth PMOS transistor M12. The gate of the fifth NMOS transistor M9 is connected to the first bias voltage input terminal VBIAS1_IN. The source of the fifth NMOS transistor M9 is connected to one end of the second resistor R1. The other end of resistor R1 is grounded; the drain of the sixth NMOS transistor M10 is connected to the drain of the sixth PMOS transistor M12; the gate of the sixth NMOS transistor M10 is connected to the first bias voltage input terminal VBIAS1_IN and the gate of the fifth NMOS transistor M9, respectively; the source of the sixth NMOS transistor M10 is connected to one end of the third resistor R2; the other end of the third resistor R2 is connected to the drain of the fourth PMOS transistor M7 and one end of the target fuse F0, respectively; the source of the fifth PMOS transistor M11 is connected to the chip power supply; the source of the sixth PMOS transistor M12 is connected to the chip power supply.

[0029] The fuse output mode selection circuit 103 includes: first to third inverters (i.e., first inverter I0, second inverter I1, and third inverter I2), a seventh PMOS transistor M13, an eighth PMOS transistor M15, a seventh NMOS transistor M14, and an eighth NMOS transistor M16. The first inverter I0, second inverter I1, and third inverter I2 are typical inverter structures composed of one PMOS transistor and one NMOS transistor. The source and drain of the seventh PMOS transistor M13 are connected to the source and drain of the seventh NMOS transistor M14 to form a first transmission gate. The source and drain of the eighth PMOS transistor M15 are connected to the source and drain of the eighth NMOS transistor M16 to form a second transmission gate. The seventh PMOS transistor M13 and the eighth NMOS transistor M16... The gates of all 16 are connected to the fuse output mode control signal input terminal MODE. The input terminal of the first inverter I0 is connected to the fuse output mode control signal input terminal MODE. The output terminal of the first inverter I0 is connected to the gates of the seventh NMOS transistor M14 and the eighth PMOS transistor M15, respectively. One end of the first transmission gate is connected to the drain of the sixth PMOS transistor M12 and the sixth NMOS transistor M10, respectively. One end of the second transmission gate is connected to the trimming data signal input terminal DATA1_IN. The input terminal of the second inverter I1 is connected to the other end of the first and second transmission gates, respectively. The input terminal of the third inverter I2 is connected to the output terminal of the second inverter I1. The output terminal of the third inverter I2 is connected to the trimming output signal output terminal DATA1_OUT.

[0030] Specifically, such as Figure 2 As shown, the first fuse control circuit 101 controls the target fuse F0 to blow, and the adjustment enable signal input terminal ENN1 is low-level enabled. Specifically, if the adjustment enable signal input terminal ENN1 is high-level, the third PMOS transistor M4 is turned off, the third NMOS transistor M5 is turned on, the gate potential of the fourth NMOS transistor M6 is pulled close to ground, and the fourth NMOS transistor M6 is turned off. The first resistor R0 is set to a first resistance value (for example, 10KΩ), which is much smaller than the resistance of the fourth NMOS transistor M6 in the off state. Therefore, the gate potential of the fourth PMOS transistor M7 is close to the chip power supply, the fourth PMOS transistor M7 is turned off, and the target fuse F0 will not be blown. When the adjustment enable signal input terminal ENN1 is low-level, the third PMOS transistor M4 is turned on, the third NMOS transistor M5 is turned off, and the first PMOS transistor M0 and the first NMOS transistor M1 form a... The inverter is formed by the second PMOS transistor M2 and the second NMOS transistor M3. If the adjustment data signal input terminal DATA1_IN is low, the fourth NMOS transistor M6 and the fourth PMOS transistor M7 are turned off, and the target fuse F0 will not be blown. When the adjustment enable signal input terminal ENN1 is low and the adjustment data signal input terminal DATA1_IN is high, the fourth NMOS transistor M6 is turned on. The resistance value of the first resistor R0 is much greater than the resistance when the fourth NMOS transistor M6 is turned on. The gate potential of the fourth PMOS transistor M7 is close to ground, and the fourth PMOS transistor M7 is turned on, forming a path from the chip power supply - the fourth PMOS transistor M7 - the target fuse F0 - ground, and the target fuse F0 is blown.

[0031] The first fuse status reading circuit 102 reads and outputs the status of the target fuse F0. Specifically, the third resistor R2 is used to limit the maximum current in the path from the sixth PMOS transistor M12 to the sixth NMOS transistor M10, then to the third resistor R2, and finally to the target fuse F0, ensuring that a large current will not be generated that could cause the fuse to blow accidentally. The resistance values ​​of the second resistor R1 and the third resistor R2 are set to the second resistance value (e.g., 10KΩ). The bias voltage of the first bias voltage input terminal VBIAS1_IN is set so that a small current, such as a few microamps, is generated in the second resistor R1. If the current in R1 is 5 microamps, then the voltage in R1 is 50mV, which will not affect the turn-on of the fifth NMOS transistor M9 and the sixth NMOS transistor M10. If the chip power supply is 5V, then the second resistor R1 limits the current on the fifth PMOS transistor M11 and the fifth NMOS transistor M9 to no more than 0.5 mA, and the third resistor R2 limits the current on the sixth PMOS transistor M12, the sixth NMOS transistor M10 and the target fuse F0 to no more than 0.5 mA. This amount of current will not blow the fuse.

[0032] In the first fuse status reading circuit 102, the fifth NMOS transistor M9 and the sixth NMOS transistor M10 have the same dimensions. The channel width-to-length ratio of the fifth PMOS transistor M11 is twice that of the sixth PMOS transistor M12. The fifth PMOS transistor M11 and the sixth PMOS transistor M12 form a current mirror with an input-output current transfer ratio of 2:1. The first bias voltage input terminal VBIAS1_IN serves as the bias voltage for the fifth NMOS transistor M9 and the sixth NMOS transistor M10, causing a small current, such as a few microamps, to be generated in the path of the fifth PMOS transistor M11-the fifth NMOS transistor M9-the second resistor R1. If the target fuse F0 is not blown, its resistance is very small and negligible compared to the resistances of the second resistor R1 and the third resistor R2. In this case, the fifth NMOS transistor M9 and the sixth NMOS transistor M10 form a current mirror with an input-output current transfer ratio of 1:1, while the fifth PMOS transistor M11 and the sixth PMOS transistor M12 form a current mirror with an input-output current transfer ratio of 2:1. At this time, the current capability of the sixth NMOS transistor M10 is stronger than that of the sixth PMOS transistor M12, and the potential at the drain connection of the sixth NMOS transistor M10 and the sixth PMOS transistor M12 will be close to ground. If the target fuse F0 has blown, the source of the sixth NMOS transistor M10 is essentially floating, and the sixth NMOS transistor M10 has no current capability. The sixth PMOS transistor M12 pulls up the potential at the drain connection of the sixth NMOS transistor M10 and the sixth PMOS transistor M12 to near the chip power supply. In summary, if the target fuse F0 does not blow, the first fuse status reading circuit 102 outputs a low level; if the target fuse F0 blows, the first fuse status reading circuit 102 outputs a high level. Thus, the first fuse status reading circuit 102 has the capability to read fuse status.

[0033] The fuse output mode selection circuit 103 selects one of the two signals, namely the output of the first fuse state reading circuit 102 and the adjustment data signal input at the adjustment data signal input terminal DATA1_IN, based on the fuse output mode control signal input terminal MODE, and outputs it through the adjustment output signal output terminal DATA1_OUT. Specifically, if the fuse output mode control signal input terminal MODE is low, the seventh PMOS transistor M13 and the seventh NMOS transistor M14 are turned on, and the eighth PMOS transistor M15 and the eighth NMOS transistor M16 are turned off. The output of the first fuse status reading circuit 102 passes through the first transmission gate composed of the seventh PMOS transistor M13 and the seventh NMOS transistor M14, and then through the buffer formed by the second inverter I1 and the third inverter I2, and is output to the trimming output signal output terminal DATA1_OUT. If the fuse output mode control signal input terminal MODE is high, the eighth PMOS transistor M15 and the eighth NMOS transistor M16 are turned on, and the seventh PMOS transistor M13 and the seventh NMOS transistor M14 are turned off. The trimming data signal input at the trimming data signal input terminal DATA1_IN passes through the second transmission gate composed of the eighth PMOS transistor M15 and the eighth NMOS transistor M16, and then through the buffer formed by the second inverter I1 and the third inverter I2, and is output to the trimming output signal output terminal DATA1_OUT.

[0034] In one embodiment of the present invention, such as Figure 3 As shown, the adjustment enable module 200 further includes: a second fuse control circuit 201, a second fuse status reading circuit 202, and an enable synthesis circuit 203. The second fuse control circuit 201 has the same circuit structure as the first fuse control circuit 101; the second fuse status reading circuit 202 has the same circuit structure as the first fuse status reading circuit 102; the enable synthesis circuit 203 includes: a fourth inverter I3 and a NAND gate I4. The input terminal of the fourth inverter I3 is connected to the output of the second fuse status reading circuit 202. One input terminal of the NAND gate I4 is connected to the output terminal of the fourth inverter I3, and the other input terminal of the NAND gate I4 is connected to the function bit fuse blow-off enable signal input terminal FUSE_EN. The output terminal of the NAND gate I4 is connected to the adjustment enable signal output terminal DATA2_OUT.

[0035] Specifically, if the adjustment enable signal input terminal ENN1 of the adjustment function module 100 is low-level enabled, and the function bit fuse blow enable signal input terminal FUSE_EN is low-level, the adjustment enable signal output terminal DATA2_OUT of the adjustment enable module 200 will output high-level, the fuse blowing function of each adjustment function module 100 will not be enabled, and the target fuse F0 in the adjustment function module 100 will not be blown; if the function bit fuse blow enable signal input terminal FUSE_EN is high-level, and the adjustment When the fuse F1 in the enable module 200 is intact, the adjustment enable signal output terminal DATA2_OUT outputs a low level, enabling the fuse-breaking function of each adjustment function module 100; after the target fuse F0 in each adjustment function module 100 is correctly blown, the fuse F1 in the adjustment enable module 200 is blown, the adjustment enable signal output terminal DATA2_OUT of the adjustment enable module 200 outputs a high level, and each adjustment function module 100 can no longer blow the target fuse F0, thus realizing the safety function.

[0036] In one embodiment of the present invention, such as Figure 4 As shown, the bias generation module 300 also includes: a ninth NMOS transistor M17 and a fourth resistor R3, wherein the drain and gate of the ninth NMOS transistor M17 are connected, the drain of the ninth NMOS transistor M17 is also connected to the bias current input terminal IBIAS_IN, the gate of the ninth NMOS transistor M17 is also connected to the bias voltage output terminal VBIAS_OUT, the source of the ninth NMOS transistor M17 is connected to one end of the fourth resistor R3, and the other end of the fourth resistor R3 is grounded.

[0037] In one embodiment of the present invention, based on Figures 1-4 The specific structure of the fuse trimming device, and the waveform diagram of the fuse trimming signal of the fuse trimming device are shown below. Figure 5 As shown. For demonstration purposes, the number of adjustment bits N in the waveform diagram can be set to 2. The waveforms represent the function bit fuse enable signal FUSE_ENK input at the FUSE_EN terminal, the fuse output mode control signal MODEK input at the MODE terminal, and the 2-bit fuse adjustment data signals DATA_IN input at the two adjustment data signal input terminals DATA1_IN respectively. <0> and DATA_IN <1> The 2-bit fuse adjustment output signal DATA_OUT is output from the DATA1_OUT terminal. <0> and DATA_OUT <1> The DATA2_IN terminal receives the enable bit fuse-breaking signal DATA_LOCK, and the ENN2 terminal receives the enable bit fuse-breaking enable signal LOCK_ENN. The function bit fuse-breaking enable signal FUSE_ENK is enabled at a high level, and the enable bit fuse-breaking enable signal LOCK_ENN is enabled at a low level.

[0038] Specifically, such as Figure 5 As shown, the entire fuse adjustment process is divided into three parts: pseudo-adjustment process, real adjustment process, and fuse tripping process. During the pseudo-adjustment process, the function bit fuse tripping enable signal FUSE_ENK remains low, so the target fuse F0 of the adjustment function module 100 will not be tripped. The fuse output mode control signal MODEK remains high, and the fuse adjustment output signal DATA_OUT... <0> Follow the fuse adjustment data signal DATA_IN <0> Changes, fuse adjustment output signal DATA_OUT <1> Follow the fuse adjustment data signal DATA_IN <1> The change keeps the fuse-breaking enable signal DATA_LOCK low and the fuse-breaking enable signal LOCK_ENN high. During the pseudo-adjustment process, the two-bit fuse adjustment data signal DATA_IN is traversed. <0> and DATA_IN <1> This allows observation of the changes in the adjustment result corresponding to each fuse adjustment data signal value. The adjustment result that best matches the desired outcome can be selected, and its corresponding fuse adjustment data signal value recorded. For ease of explanation, assume that the optimal result obtained by a certain chip in the pseudo-adjustment corresponds to the fuse adjustment data signal value: fuse adjustment data signal DATA_IN. <0> Set to 0, fuse adjustment data signal DATA_IN <1> Take 1.

[0039] During the actual adjustment process, the function bit fuse blow enable signal FUSE_ENK remains high, the fuse output mode control signal MODEK remains low, and the fuse adjustment data signal DATA_IN remains high. <0> Keep low, DATA_IN <1> The fuse adjustment data signal should be held at a high level for a duration that completely covers the time the function bit fuse blow enable signal FUSE_ENK is high, to avoid erroneous fuse blowing. The enable bit fuse blow enable signal DATA_LOCK should be held low, and the enable bit fuse blow enable signal LOCK_ENN should be held high. Figure 5 The wavy line in the true adjustment process represents a variable duration, which can be set from several milliseconds to tens of milliseconds depending on the specific situation, to ensure that the target fuse F0 in the adjustment function module 100 blows according to the fuse adjustment data signal corresponding to the pseudo-optimal adjustment result. The high level time of the function bit fuse-breaking enable signal FUSE_ENK is the time for the target fuse F0 to blow. After the function bit fuse-breaking enable signal FUSE_ENK changes from high level to low level, the true adjustment process ends, and the fuse adjustment output signal becomes the value of the fuse adjustment data signal set during the true adjustment process. In this example, after the true adjustment process ends, the fuse adjustment output signal DATA_OUT... <0> Keep low level, fuse trimming output signal DATA_OUT <1> It becomes high level.

[0040] like Figure 5 As shown, after the actual adjustment process is completed, the fuse F1 continues to be blown. The function bit fuse blowing enable signal FUSE_ENK remains low, the fuse output mode control signal MODEK remains low, and the fuse adjustment data signal DATA_IN remains low. <0> and fuse adjustment data signal DATA_IN <1> The DATA_LOCK enable signal is kept low, while the LOCK_ENN enable signal is kept high. Figure 5 The wavy line representing the fuse tripping process indicates that the duration is not constant and can be set from several milliseconds to tens of milliseconds depending on the specific situation, to ensure that the fuse F1 in the adjustment enable module 200 blows. After the fuse F1 in the adjustment enable module 200 blows, the adjustment enable signal output terminal DATA2_OUT of the adjustment enable module 200 will output a high level, and the target fuse F0 in the adjustment function module 100 will not be enabled, thereby avoiding the problem of accidental fuse tripping after the adjustment process is completed, and realizing the protection function.

[0041] Therefore, this invention introduces a safety function in fuse adjustment to avoid accidental fuse blowing caused by the MOS switch being turned on during chip power-up and power-down, and reduces the risk of subsequent target fuses blowing under specific input signal combinations by blowing the fuse after adjustment.

[0042] In another embodiment of the invention, such as Figure 6 As shown, the adjustment function module 100 also includes a first working power input terminal VIN_SOURCE1, the adjustment enable module 200 also includes a second working power input terminal VIN_SOURCE2, and the fuse adjustment device also includes a fuse breaking power module 400. The fuse breaking power module 400 includes a power supply input terminal PAD_X and a working power output terminal VOUT_SOURCE. The power supply input terminal PAD_X is connected to the chip reusable pad interface PAD_XP, and the working power output terminal VOUT_SOURCE is connected to the first working power input terminal VIN_SOURCE1 and the second working power input terminal VIN_SOURCE2 respectively.

[0043] Specifically, after setting the first working power input terminal VIN_SOURCE1 on the adjustment function module 100, the connection method of the adjustment function module 100 also needs to be adjusted.

[0044] Specifically, such as Figure 7 As shown, the structure of the first fuse control circuit 101 is approximately the same as... Figure 2 The first fuse control circuit 101 in the middle is different in that, Figure 7 In the first fuse control circuit 101, the first resistor R0 and the source of the fourth PMOS transistor M7 are connected to the first operating power input terminal VIN_SOURCE1, and the power input at the first operating power input terminal VIN_SOURCE1 is used as the power supply when the target fuse F0 blows. The fuse status reading circuit 102 and... Figure 2 The fuse status reading circuit 102 in the circuit has the same structure. The fuse output mode selection circuit 103 and... Figure 2 The fuse output mode selection circuit 103 in the circuit has the same structure. Specifically, Figure 7 In the circuit, the first fuse control circuit 101 controls the target fuse F0 to blow. When the adjustment enable signal input terminal ENN1 is low, the third PMOS transistor M4 is turned off, the third NMOS transistor M5 is turned on, and the gate potential of the fourth NMOS transistor M6 is pulled close to ground, causing M6 to turn off. Even if a high-level power supply is applied to the first operating power input terminal VIN_SOURCE1 at this time, the gate potential of the fourth PMOS transistor M7 will approach the level of VIN_SOURCE1, causing M7 to turn off, and the target fuse F0 will not blow. When it is necessary to blow the target fuse F0, the adjustment enable signal input terminal ENN1 can be set to a low level, and a high level power supply can be applied to the first working power input terminal VIN_SOURCE1. The adjustment data signal input terminal DATA1_IN is also set to a high level. At this time, a path is formed from the first working power input terminal VIN_SOURCE1 to the fourth PMOS transistor M7, the target fuse F0, and ground, and the target fuse F0 is blown.

[0045] like Figure 8 As shown, after setting the second operating power input terminal VIN_SOURCE2 in the adjustment enable module 200, the second fuse control circuit 201 in the adjustment enable module 200 and Figure 7 The circuit structure of the first fuse control circuit 101 is the same as that of the second fuse status reading circuit 202. Figure 7 The circuit structure of the second fuse status reading circuit 102 is the same as that of the enable synthesis circuit 203. Figure 3 The circuit structure of the enable synthesis circuit 203 is the same.

[0046] In one embodiment of the present invention, such as Figure 9 As shown, the fuse-operated power supply module 400 may include: a ninth PMOS transistor M18, a tenth PMOS transistor M19, and a tenth NMOS transistor M20. The source of the tenth PMOS transistor M19 is connected to the chip power supply. The gate and drain of the tenth PMOS transistor M19 are connected and both are connected to the gate of the tenth NMOS transistor M20. The source of the tenth NMOS transistor M20 is grounded. The drain of the tenth NMOS transistor M20 is connected to the gate of the ninth PMOS transistor M18. The drain of the ninth PMOS transistor M18 is connected to the chip's reusable pad interface PAD_XP. The source of the ninth PMOS transistor M18 is connected to the operating power output terminal VOUT_SOURCE.

[0047] Specifically, the gate and drain of the tenth PMOS transistor M19 are connected together, forming a diode connection. The drain potential of the tenth PMOS transistor M19 is pulled up to near the chip power supply, meaning the gate potential of the tenth NMOS transistor M20 is close to the chip power supply, and the tenth NMOS transistor M20 conducts. This pulls down the gate potential of the ninth PMOS transistor M18 to near ground, and the ninth PMOS transistor M18 conducts, forming a power path from the power input terminal PAD_X to the operating power output terminal VOUT_SOURCE. The ninth PMOS transistor M18 is a large-size PMOS transistor to ensure that a large current can pass through when the fuse blows. In implementation, the size of the ninth PMOS transistor M18 can be set according to the specific number of fuses.

[0048] Therefore, the fuse-based power supply module 400 can not only directly use the chip power supply, but also reuse other pins in the chip as power supply terminals. It is necessary to ensure that the reusable pad interface PAD_XP in the chip is not used as a signal input port during the tuning phase. Using a separate fuse-based power supply during the tuning phase, compared to using the chip power supply, offers several advantages. First, a separate fuse-based power supply allows for flexible voltage adjustment, potentially increasing the voltage to improve the fuse's success rate, making it more flexible than a fixed chip power supply. Second, since the fuse and MOS switch are not connected to the chip power supply, if the operating voltage at the power supply input terminal PAD_X is not high under normal operating conditions after tuning, the risk of accidental fuse blowing can be further reduced.

[0049] In another embodiment of the invention, based on Figures 6-9 The specific structure of the fuse trimming device, and the waveform diagram of the fuse trimming signal of the fuse trimming device are shown below. Figure 10 As shown. For ease of demonstration, the adjustment bit N can be set to 2. Figure 10 The waveform diagram shown is compared to Figure 5 The waveform diagram shown is different in that it includes the waveform of the power supply input terminal PAD_X. Figure 10 The remaining signal waveforms and Figure 5 The corresponding signal waveforms are the same. During the pseudo-adjustment process, since it does not involve fuse blowing, the power supply input terminal PAD_X can be kept at a low level; during the true adjustment process, a high level power supply needs to be applied to the power supply input terminal PAD_X to provide power for the target fuse F0 in the multiple adjustment function modules 100 to blow; during the fuse tripping process, a high level power supply needs to be applied to the power supply input terminal PAD_X to provide power for the fuse F1 in the adjustment enable module 200 to blow.

[0050] Therefore, by reusing chip pins as the fuse power supply, the present invention can flexibly adjust the fuse power supply voltage value without being limited by the voltage withstand capability of other components in the chip, thereby improving the fuse blowing success rate and reducing the risk of accidental fuse blowing after adjustment.

[0051] In summary, the fuse trimming device according to an embodiment of the present invention includes: N trimming function modules 100 and a trimming enable module, where N is the number of fuse trimming bits required in the chip system. Each trimming function module includes: a trimming data signal input terminal, a trimming enable signal input terminal, a fuse output mode control signal input terminal, and a trimming output signal output terminal. The trimming enable module includes: a fuse blowing signal input terminal, an enable bit fuse blowing enable signal input terminal, a function bit fuse blowing enable signal input terminal, and a trimming enable signal output terminal. The trimming enable signal input terminal is connected to the trimming enable signal output terminal. In this system, when the adjustment function module receives the first adjustment enable signal from the adjustment enable signal output terminal, it performs fuse adjustment based on the externally input fuse adjustment data signal received from the adjustment data signal input terminal and the fuse output mode control signal received from the fuse output mode control signal input terminal. A corresponding fuse adjustment output signal is then output through the adjustment output signal output terminal. After the adjustment function module completes the fuse adjustment, the adjustment enable module outputs a second adjustment enable signal to the adjustment enable signal input terminal to control the fuse-breaking function of the adjustment function module to shut down. Therefore, this fuse adjustment device incorporates a safety mechanism, effectively preventing accidental fuse blowing and significantly improving the reliability of the fuse adjustment process.

[0052] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. "A plurality of" means two or more, unless otherwise explicitly specified.

[0053] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0054] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that they are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0055] In the description of this specification, the references to "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0056] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0057] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A fuse adjustment device, characterized in that, include: There are N trimming function modules and trimming enable modules, where N is the number of fuse trimming bits required in the chip system. Each trimming function module includes: a trimming data signal input terminal, a trimming enable signal input terminal, a fuse output mode control signal input terminal, and a trimming output signal output terminal. Each trimming enable module includes: a fuse blown signal input terminal, an enable bit fuse blown enable signal input terminal, a function bit fuse blown enable signal input terminal, and a trimming enable signal output terminal. The trimming enable signal input terminal is connected to the trimming enable signal output terminal. The trimming function module is used to perform fuse trimming based on the externally input fuse trimming data signal received at the trimming data signal input terminal and the fuse output mode control signal received at the fuse output mode control signal input terminal when it receives the first trimming enable signal output from the trimming enable signal output terminal, and outputs a corresponding fuse trimming output signal through the trimming output signal output terminal. The adjustment enable module is used to output a second adjustment enable signal to the adjustment enable signal input terminal through the adjustment enable signal output terminal after the adjustment function module completes the fuse adjustment, so as to control the fuse function of the adjustment function module to be turned off.

2. The fuse trimming device according to claim 1, characterized in that, Also includes: A bias generation module includes a bias current input terminal and a bias voltage output terminal. Each adjustment function module further includes a first bias voltage input terminal, and the adjustment enable module further includes a second bias voltage input terminal. The bias voltage output terminal is respectively connected to the first bias voltage input terminal and the second bias voltage input terminal. The bias generation module is used to convert the externally input bias current into a bias voltage.

3. The fuse trimming device according to claim 2, characterized in that, The adjustment function module further includes: a first fuse control circuit, a first fuse status reading circuit, and a fuse output mode selection circuit; wherein... The first fuse control circuit includes: a target fuse, first to fourth PMOS transistors, first to fourth NMOS transistors, and a first resistor. The source of the first PMOS transistor is connected to the chip power supply, the gate of the first PMOS transistor is connected to the adjustment data signal input terminal, and the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to the adjustment data signal input terminal, and the source of the first NMOS transistor is grounded. The gate of the second PMOS transistor is connected to the drains of both the first PMOS transistor and the first NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the drains of both the first PMOS transistor and the first NMOS transistor, and the source of the second NMOS transistor is connected to the chip ground. The source of the third PMOS transistor is connected to the chip power supply, the gate of the third PMOS transistor is connected to the adjustment enable signal input terminal, and the drain of the third PMOS transistor is connected to the source of the second PMOS transistor. The drain of the third NMOS transistor is connected to the drains of both the second PMOS transistor and the second NMOS transistor. The gate of the MOS transistor is connected to the adjustment enable signal input terminal, and the source of the third NMOS transistor is grounded; the drain of the fourth NMOS transistor is connected to one end of the first resistor, the gate of the fourth NMOS transistor is connected to the drains of the second PMOS transistor, the second NMOS transistor, and the third NMOS transistor, and the source of the fourth NMOS transistor is grounded; the other end of the first resistor is connected to the chip power supply; the source of the fourth PMOS transistor is connected to the chip power supply, the gate of the fourth PMOS transistor is connected to one end of the first resistor and the drain of the fourth NMOS transistor, and the drain of the fourth PMOS transistor is connected to one end of the target fuse; the other end of the target fuse is grounded. The first fuse status reading circuit includes: a second resistor, a third resistor, a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The drain of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the fifth PMOS transistor, and the gate of the sixth PMOS transistor. The gate of the fifth NMOS transistor is connected to a first bias voltage input terminal. The source of the fifth NMOS transistor is connected to one end of the second resistor; the other end of the second resistor is grounded. The drain of the sixth NMOS transistor is connected to the drain of the sixth PMOS transistor. The gate of the sixth NMOS transistor is connected to both the first bias voltage input terminal and the gate of the fifth NMOS transistor. The source of the sixth NMOS transistor is connected to one end of the third resistor. The other end of the third resistor is connected to the drain of the fourth PMOS transistor and one end of the target fuse. The source of the fifth PMOS transistor is connected to the chip power supply. The source of the sixth PMOS transistor is also connected to the chip power supply. The fuse output mode selection circuit includes: first to third inverters, a seventh PMOS transistor, an eighth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor. The source and drain of the seventh PMOS transistor are connected to the source and drain of the seventh NMOS transistor to form a first transmission gate. The source and drain of the eighth PMOS transistor are connected to the source and drain of the eighth NMOS transistor to form a second transmission gate. The gates of the seventh PMOS transistor and the eighth NMOS transistor are both connected to the fuse output mode control signal input terminal. The input terminal of the first inverter is connected to the fuse output mode control signal. The control signal input terminal, the output terminal of the first inverter I0 is connected to the gates of the seventh NMOS transistor and the eighth PMOS transistor respectively, one end of the first transmission gate is connected to the drain of the sixth PMOS transistor and the sixth NMOS transistor respectively, one end of the second transmission gate is connected to the trimming data signal input terminal, the input terminal of the second inverter is connected to the other end of the first transmission gate and the second transmission gate respectively, the input terminal of the third inverter is connected to the output terminal of the second inverter, and the output terminal of the third inverter I2 is connected to the trimming output signal output terminal.

4. The fuse trimming device according to claim 3, characterized in that, The fifth NMOS transistor and the sixth NMOS transistor have the same dimensions, and the channel width-to-length ratio of the fifth PMOS transistor is twice that of the sixth PMOS transistor.

5. The fuse trimming device according to claim 4, characterized in that, The fifth PMOS transistor and the sixth PMOS transistor form a current mirror with an input-output current transfer ratio of 2:1; the fifth NMOS transistor and the sixth NMOS transistor form a current mirror with an input-output current transfer ratio of 1:

1.

6. The fuse trimming device according to claim 3, characterized in that, The adjustment enable module further includes: a second fuse control circuit, a second fuse status reading circuit, and an enable synthesis circuit, wherein... The second fuse control circuit has the same circuit structure as the first fuse control circuit; The second fuse status reading circuit has the same circuit structure as the first fuse status reading circuit; The enable synthesis circuit includes a fourth inverter and a NAND gate. The input of the fourth inverter is connected to the output of the second fuse status reading circuit. One input of the NAND gate is connected to the output of the fourth inverter. The other input of the NAND gate is connected to the function bit fuse blow-off enable signal input. The output of the NAND gate is connected to the trim enable signal output.

7. The fuse trimming device according to claim 2, characterized in that, The bias generation module further includes a ninth NMOS transistor and a fourth resistor, wherein the drain and gate of the ninth NMOS transistor are connected, the drain of the ninth NMOS transistor is also connected to the bias current input terminal, the gate of the ninth NMOS transistor is also connected to the bias voltage output terminal, the source of the ninth NMOS transistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is grounded.

8. The fuse trimming device according to claim 1, characterized in that, The adjustment function module further includes a first working power input terminal, the adjustment enable module further includes a second working power input terminal, and the fuse adjustment device further includes a fuse blowing power supply module. The fuse-operated power supply module includes a power supply input terminal and a working power output terminal. The power supply input terminal is connected to the chip's reusable pad interface, and the working power output terminal is connected to the first working power input terminal and the second working power input terminal, respectively.

9. The fuse trimming device according to claim 6, characterized in that, The fuse-operated power supply module includes: a ninth PMOS transistor, a tenth PMOS transistor, and a tenth NMOS transistor, wherein... The source of the tenth PMOS transistor is connected to the chip power supply. The gate and drain of the tenth PMOS transistor are connected and both are connected to the gate of the tenth NMOS transistor. The source of the tenth NMOS transistor is grounded. The drain of the tenth NMOS transistor is connected to the gate of the ninth PMOS transistor. The drain of the ninth PMOS transistor is connected to the chip's reusable pad interface. The source of the ninth PMOS transistor is connected to the operating power supply output terminal.

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