A ternary logic circuit based on RRAM mirror device

Abstract

The application discloses a ternary logic circuit based on a RRAM mirror device and belongs to the field of integrated circuit design. The circuit comprises a basic inverter unit, which comprises one RRAM mirror device and one NMOS tube in series with each other. The source of the NMOS tube is connected to ground, the gate is connected to an input signal as an input end, and the drain is connected to an output signal as an output end. The RRAM mirror device is connected in series between a voltage source and the drain of the NMOS tube to form a voltage division loop. The RRAM mirror device comprises a first main end, a second main end and at least two configuration ends. The first main end is connected to the voltage source, the second main end is connected to the drain of the NMOS tube, and the configuration ends are respectively connected to a first setting voltage signal and a second setting voltage signal, which are used for changing the internal resistance state of the RRAM mirror device. While the circuit function integrity is maintained, the number of devices and the circuit structure are simplified. Through the design, not only the ternary logic function is realized, but also obvious advantages are achieved in the aspects of integration and manufacturing cost.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to a ternary logic circuit based on an RRAM mirror device. Background Technology

[0002] With the explosive growth of data volume in the era of big data, the demand for computing performance in chips is increasing daily. However, traditional methods of improving performance by shrinking transistor size or building large-scale integrated circuits face technical bottlenecks and problems such as high power consumption and high interconnect complexity. Ternary logic, with its higher information density, shows significant advantages in improving computing performance and reducing chip area, and its related circuit design has become an important direction for breaking through existing technological limitations. Current implementation schemes for ternary logic circuits have obvious shortcomings: some schemes require a decoder to convert ternary signals into binary signals before operation, resulting in high interconnect complexity and low computational efficiency; other schemes are based on ternary logic truth table design, which has problems such as complex structure, large number of transistors, and large delay and power consumption. Moreover, existing ternary logic gate circuits are mostly designed directly for operations such as addition and multiplication, lacking basic units that can be flexibly expanded; at the same time, although ternary logic circuits based on new devices such as memristors have potential in terms of integration, they face challenges such as device variability, noise accumulation, and slow switching speed, and are mostly limited to single-level logic gate implementations, lacking mature multi-level combinational logic design schemes.

[0003] Although existing transistor-based logic circuit schemes can implement ternary logic functions and realize the functions of half-adders and full-adders, they still have the following shortcomings in practical applications: 1) Complex circuit structure: Logic units usually require multiple transistors to work together, resulting in a large number of devices and a large area occupied, which is not conducive to achieving high-density integration and low-cost manufacturing.

[0004] 2) Complex process: Existing CMOS production lines are highly optimized for binary, and adapting to ternary requires adjusting process parameters to achieve transistors with multiple threshold voltages.

[0005] 3) High energy consumption: As the scale increases, the complexity of device interconnection and wiring increases significantly, further aggravating energy consumption and reliability issues.

[0006] Although existing transistor-based multi-valued logic circuits, especially ternary logic circuits, have provided new implementation paths for improving computing performance, they still have significant shortcomings in terms of circuit area, power consumption control, stability, and interconnection complexity. There is an urgent need to propose new structures and methods to improve overall performance and application value. Summary of the Invention

[0007] In view of the shortcomings of the prior art, the purpose of this invention is to provide a ternary logic circuit based on RRAM mirror devices, which solves the problems in the prior art.

[0008] The objective of this invention can be achieved through the following technical solutions: A ternary logic circuit based on an RRAM mirror device includes: a basic inverter unit, wherein the basic inverter unit comprises, in series with: an RRAM mirror device and an NMOS transistor connected in series; The source of the NMOS transistor is grounded, the gate is used as the input terminal to receive the input signal, and the drain is used as the output terminal to output the signal. The RRAM mirror device is connected in series between the voltage source and the drain of the NMOS transistor to form a voltage divider circuit. The RRAM mirror device includes a first main terminal, a second main terminal, and at least two configuration terminals. The first main terminal is connected to the voltage source, the second main terminal is connected to the drain of the NMOS transistor, and the configuration terminals are respectively connected to a first setting voltage signal and a second setting voltage signal to control the RRAM mirror device to switch between a low-resistance state, a medium-resistance state, and a high-resistance state.

[0009] Furthermore, the RRAM mirror device internally includes four RRAM units integrated on the same substrate, namely: a first RRAM unit, a second RRAM unit, a third RRAM unit, and a fourth RRAM unit; The first setting voltage signal and the second setting voltage signal are respectively connected to the top electrodes of the four RRAM cells; By combining the high and low resistance states of the four RRAM cells, the RRAM mirror device can macroscopically present a low resistance state, a medium resistance state, or a high resistance state.

[0010] Furthermore, the basic inverter unit is reconstructed into three logic gates under the same physical series topology, based on the different resistive states of the RRAM mirror device: When the RRAM mirror device is in a low-resistance state, the basic inverter unit constitutes a positive ternary inverter; When the RRAM mirror device is in a medium-resistance state, the basic inverter unit constitutes a conventional ternary inverter; When the RRAM mirror device is in a high-impedance state, the basic inverter unit constitutes a negative ternary inverter.

[0011] Furthermore, the ternary logic circuit also includes: a ternary OR gate, and a first negative ternary inverter, a second negative ternary inverter, a positive ternary inverter, and a conventional ternary inverter, each composed of the basic inverter unit; The first negative ternary inverter, the second negative ternary inverter, the positive ternary inverter, the conventional ternary inverter, and the ternary OR gate are cascaded together to form a ternary decoder; The first negative ternary inverter and the positive ternary inverter are connected in parallel to receive the input signal. The input terminal of the second negative ternary inverter is connected to the output terminal of the positive ternary inverter. The output terminals of the first negative ternary inverter and the second negative ternary inverter are connected to the input terminal of the ternary OR gate. The output terminal of the ternary OR gate is connected to the input terminal of the conventional ternary inverter.

[0012] Furthermore, the ternary logic circuit further includes at least one ternary AND gate and at least one second ternary OR gate, wherein the ternary decoder, the ternary AND gate, and the second ternary OR gate are electrically connected to form a ternary arithmetic logic array; In the ternary arithmetic logic array, at least one input of the ternary AND gate is directly electrically connected to a DC bias voltage terminal of a voltage source with an amplitude of half, so as to clamp the highest output level of the ternary AND gate to the corresponding logic 1 level.

[0013] An operation method based on the above-mentioned ternary logic circuit includes the following steps: Using the first and second setting voltage signals, the resistance state of the RRAM mirror device is controlled to switch between low resistance, medium resistance and high resistance states, so as to reconstruct the input-output voltage transfer characteristics of the basic inverter unit. The input signal is provided with three voltage states: a first level, a second level, and a third level, which correspond to logic 0, logic 1, and logic 2, respectively.

[0014] Furthermore, the amplitudes of the three voltage states are 0 volts, half the voltage source amplitude, and the voltage source amplitude, respectively. When the RRAM mirror device is set to a low-impedance state, the basic inverter unit performs a positive ternary inversion operation, and the output logic levels for the input signals of logic 0, logic 1 and logic 2 are 2, 2 and 0 respectively. When the RRAM mirror device is set to medium impedance state, the basic inverter unit performs a conventional ternary inversion operation, and the output logic levels for the input signals of logic 0, logic 1 and logic 2 are 2, 1 and 0 respectively. When the RRAM mirror device is set to a high-impedance state, the basic inverter unit performs a negative ternary inversion operation, and the output logic levels for the input signals of logic 0, logic 1 and logic 2 are 2, 0 and 0 respectively.

[0015] Furthermore, the RRAM mirror device internally includes four RRAM cells integrated on the same substrate; the operation method further includes: The four RRAM cells are divided into a first group and a second group; When all RRAM cells in the first group and the second group are programmed to a high-impedance state by the first setting voltage signal and the second setting voltage signal, the RRAM mirror device as a whole presents the high-impedance state; When one of the first group and the second group is programmed to a high-resistance state and the other group is programmed to a low-resistance state, the RRAM mirror device as a whole presents the medium-resistance state. When all RRAM cells in the first group and the second group are programmed to a low-resistance state, the RRAM mirror device as a whole presents the low-resistance state.

[0016] An electronic device includes at least one ternary logic circuit based on an RRAM mirror device as described above.

[0017] Furthermore, the electronic device is an integrated circuit chip; The integrated circuit chip contains a ternary half-adder, a ternary full adder, a ternary multiplier, or a ternary comparator, which are formed by cascading multiple ternary logic circuits according to the Karnaugh map minterm sum logic rule.

[0018] The beneficial effects of this invention are: 1. This invention utilizes the multi-value characteristics of RRAM mirror devices (RMDs) and combines them with CMOS technology. Using only one RMD structure and one transistor (NMOS transistor) in series, three types of ternary inverters can be designed and reconstructed: conventional ternary inverter (STI), positive ternary inverter (PTI), and negative ternary inverter (NTI). This overcomes the complex problems of traditional schemes where logic units usually require multiple transistors to work together or require adjustment of process parameters to achieve multi-threshold voltage transistors, thereby significantly optimizing the circuit structure and reducing the number of transistors in ternary logic circuits.

[0019] 2. The internal structure of the RMD unit of this invention integrates four RRAM units onto the same substrate. In terms of system architecture, based on a single RMD structure and an inverter composed of a single transistor, a complete ternary decoder, half-adder, full-adder, multiplier, and comparator are designed. The internally multi-cell integrated RMD unit directly reduces the area occupied. Simultaneously, while maintaining the functional integrity of the ternary logic circuit, this design makes the overall circuit structure extremely compact and significantly reduces the number of components, thus exhibiting significant advantages in integration and manufacturing cost, overcoming the shortcomings of existing technologies such as large area occupation, unfavorable for high-density integration, and low-cost manufacturing.

[0020] 3. This invention is based on a ternary logic gate circuit with an extremely simple hardware structure. Utilizing 27 single-variable functions of ternary logic, this ternary logic gate circuit is widely applied to complex ternary logic circuit systems. By simplifying the structure and reducing the number of transistors, the power consumption of the ternary logic circuit is effectively reduced, alleviating the energy consumption and reliability problems caused by the increased complexity of device interconnection and wiring as the scale increases, thereby improving the computational efficiency of the ternary logic circuit. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is the truth table and structural schematic diagram of the ternary inverter of the present invention; Figure 2 This is the truth table and structural diagram of the ternary decoder of the present invention; Figure 3 This is the operation result table and Karnaugh map of the ternary half-adder of the present invention; Figure 4 This is a schematic diagram of the ternary half-adder of the present invention; Figure 5 This invention provides the truth table and Karnaugh map for the ternary full adder. Figure 6 This is a schematic diagram of the ternary full adder of the present invention; Figure 7 This invention provides a table of operation results and a Karnaugh map for the ternary multiplier. Figure 8 This is a schematic diagram of the ternary multiplier of the present invention; Figure 9 This is the truth table and Karnaugh map of the ternary comparator of the present invention; Figure 10 This is a schematic diagram of the ternary comparator of the present invention; Figure 11 This is an internal diagram and simplified diagram of the RMD of this invention; Figure 12 This is a simulation result diagram of the ternary inverter of the present invention; Figure 13 This is a simulation result diagram of the ternary decoder of the present invention; Figure 14 This is a simulation result diagram of the ternary half-adder of the present invention; Figure 15This is a simulation result diagram of the ternary full adder of the present invention; Figure 16 This is a simulation result diagram of the ternary multiplier of the present invention; Figure 17 This is a simulation result diagram of the ternary comparator of the present invention; Figure 18 This is a circuit diagram of the TAND and TOR gates of this invention; Figure 19 This is the I-V characteristic diagram of the RRAM device of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Example 1 This embodiment proposes a ternary logic circuit based on an RRAM mirror device (RMD). Its core idea is to utilize the multi-valued characteristics of the RMD to implement a ternary logic design: an inverter, decoder, half-adder, full-adder, multiplier, and comparator.

[0025] 1. Ternary inverter Due to the multi-valued nature of RMDs, this design combines the RMD structure with CMOS technology, enabling the design of three types of ternary inverters using only one RMD structure and one transistor: a conventional ternary inverter (STI), a positive ternary inverter (PTI), and a negative ternary inverter (NTI), thus significantly optimizing the circuit structure. For example... Figure 1 As shown in (a), the circuit consists of an RMD and an NMOS transistor connected in series. The source of the NMOS transistor is grounded, the input signal is connected to the gate of the NMOS transistor, and the output signal is connected to the drain of the NMOS transistor. The RMD is a four-terminal device, with its bottom electrode connected to the voltage source VDD and the drain of the NMOS transistor, and its top electrode connected to the voltage signal V. in1 and V in2 Used to set the resistance state of RMD.

[0026] The NMOS transistor used in this invention is a 50-nm BSIM4, and the RRAM model parameters used are shown in Table 1 below: Ron, Roff, and Rinit represent the low resistance, high resistance, and initial resistance of the RRAM, respectively; Th and Tl represent the set voltage (Vset) and reset voltage (Vreset) of the device, respectively; and Kh1, Kh2, Kl1, and Kl2 are control parameters that affect the switching rate of the device's resistive state.

[0027] Table 1 RRAM Model Parameters When RMD is set to the low resistance state (LRS), this structure corresponds to Figure 1 The PTI in (a) of the structure corresponds to the medium-resistance state (MRS) when RMD is set. Figure 1 In (a), the STI corresponds to the structure when RMD is set to the high-resistivity state (HRS). Figure 1 The NTI in (a) is shown. The input voltage Vin has three states (0, 1, 2), corresponding to voltages (0, VDD / 2, VDD). The input-output relationships of the three ternary inverters are as follows: Figure 1 As shown in (b) of the diagram.

[0028] 2. Ternary decoder This embodiment proposes a ternary decoder based on an RMD-CMOS ternary inverter. The core idea is to design a ternary decoder using an RMD-CMOS ternary inverter and known MRL technology. The design of the ternary decoder requires: two NTIs, one PTI, one STI, and a ternary OR gate (TOR) structure. For example... Figure 2 As shown in (a), the input signal X has three cases (0, 1, 2). When the input signal X = 0, the output signal (X0, X1, X2) = (2, 0, 0); when the input signal X = 1, the output signal (X0, X1, X2) = (0, 2, 0); when the input signal X = 2, the output signal (X0, X1, X2) = (0, 0, 2).

[0029] Figure 2 (b) is its circuit structure diagram, and the signal V in (X) is connected to the input terminals of PTI and the first-stage NTI. The input terminal of the second-stage NTI is connected to the output terminal of PTI. The output terminals of the first-stage NTI and the second-stage NTI are connected to the input terminal of TOR. The output terminal of TOR is connected to the input terminal of STI. The output terminal signals (X0, X1, X2) correspond to the outputs of the first-stage NTI, STI, and second-stage NTI, respectively.

[0030] 3. Ternary half-adder This embodiment proposes a ternary half-adder design based on an RMD-CMOS ternary decoder. The core idea is to utilize an RMD-CMOS-based ternary decoder and known MRL technology to design a ternary half-adder. The ternary half-adder (THA) has two ternary inputs (A, B) and outputs a sum (S) and a carry (C). Its operation follows standard bitwise addition rules, such as... Figure 3 As shown in (a) above. According to Figure 3The Karnaugh map shown in (b) provides the formulas for the carry C and the summation S: (1) (2) This formula can be used to design a ternary half-adder, such as... Figure 4 As shown, the structure includes: 2 decoders, 11 two-input TANDs, 3 three-input TORs, and 1 two-input TOR. Two input signals A and B are connected to the input terminals of the ternary decoder to generate signals (A0, A1, A2) and (B0, B1, B2) respectively. The connections are made according to the above formula: for a carry C, there are three products to add, requiring TANDs. 1-3 The input terminals are connected to A1B2, A2B1, and A2B2 respectively, and TAND 1-3 The output terminal of TOR1 is connected to the input terminal of TOR1 to realize the addition operation in the carry-in C formula. The output terminal of TOR1 and the voltage source VDD / 2 are connected to the input terminal of TAND0 to realize the coefficient 1 in the carry-in C formula (1). Similarly, the connection method for summing S is also implemented in the same way as described above.

[0031] 4. Ternary full adder This embodiment proposes a ternary full adder based on an RMD-CMOS ternary decoder. The core idea is to design a ternary full adder using an RMD-CMOS ternary decoder and known MRL technology. The ternary full adder (TFA) includes one carry input (Cin), has three input ports (A, B, Cin), and outputs the sum (S) and carry (C). Its truth table is as follows: Figure 5 As shown in (a) above. According to Figure 5 From the Karnaugh map in (b), we can obtain the formulas for the carry C and the summation S: (3) (4) This formula can be used to design a ternary half-adder, such as... Figure 6 As shown, it includes: 3 decoders, 6 two-input TANDs, 14 three-input TORs, 6 three-input TORs, and 4 two-input TORs. The three input signals are A, B, and C. in (Carry input signal) is connected to the input of the ternary decoder to generate signals (A0, A1, A2), (B0, B1, B2), and (C) respectively. in0 C in1 C in2 Connecting according to the above formula: For a carry C, there are 6 products to add, requiring TAND. 1-6 The input terminals are connected to A2B2 and A2C respectively. in1 B2C in1, A1B2, A2B1, and A1B1C in1 . TAND 1-3 's output terminal is connected to the input terminal of TOR1, and TAND 4-6 's output terminal is connected to the input terminal of TOR2, and TOR 1-2 's output terminal is connected to the input terminal of TOR7 to implement the addition operation in the carry C formula. The output terminal of TOR7 and the voltage source VDD / 2 are connected to the input terminal of TAND 19 to implement the coefficient 1 in the carry C formula (3). Similarly, the connection method for the sum S is also implemented in the above manner.

[0032] 5. Ternary Multiplier This embodiment proposes a ternary multiplier based on an RMD-CMOS ternary decoder. Its core idea is to use the RMD-CMOS based ternary decoder and the known MRL technology to design a ternary multiplier. The ternary multiplier (TMUL) performs a multiplication operation on two input signals (A, B), generating a product (P) and a carry (C), and the operation result is as shown in Figure 7 (a). According to the Karnaugh map shown in Figure 7 (b), the formulas for the carry C and the product P can be obtained: (5) (6) Design the ternary multiplier according to this formula, as shown in Figure 8 , including: 2 decoders, 6 two-input TANDs, and 3 two-input TORs. The two input signals A and B are connected to the input terminals of the ternary decoder to generate signals (A0, A1, A2) and (B0, B1, B2) respectively. Connect according to the above formula: for the carry C, there is 1 product, and the input terminal of TAND1 is connected to A2B2. The output terminal of TAND1, the voltage source VDD / 2, and the input terminal of TAND6 are connected to implement the coefficient 1 in the carry C formula (5). Similarly, the connection method for the product P is also implemented in the above manner.

[0033] 6. Ternary Comparator This embodiment proposes a ternary comparator based on an RMD-CMOS ternary decoder. Its core idea is to use the RMD-CMOS based ternary decoder and the known MRL technology to design a ternary comparator. The ternary numerical comparator (TMC) compares two ternary input signals (A, B) and outputs three signals: E (indicating A = B), G (indicating A > B), and L (indicating A < B). Its truth table is as shown in Figure 9 (a), according to Figure 9The Karnaugh map shown in (b) yields formulas for values ​​greater than (G), equal to (E), and less than (L): (7) (8) (9) This formula can be used to design a ternary comparator, such as... Figure 10 As shown, it includes: 2 decoders, 9 two-input TANDs, and 3 three-input TORs. The two input signals A and B are connected to the input terminals of the ternary decoders to generate signals (A0, A1, A2) and (B0, B1, B2) respectively. The connections are made according to the above formula: for G, there are 3 products to add, requiring TANDs. 1-3 The input terminals are connected to A2B2, A2B2, and A2B2, TAND 1-3 The output terminal of TOR1 is connected to the input terminal of TOR1 to realize formula (7). Similarly, the connection methods of formulas (8) and (9) are also implemented in the same way.

[0034] This circuit has a compact structure and a small number of components, providing new possibilities for the implementation of ternary logic circuits. The internal structure of the RMD unit is as follows: Figure 11 As shown in Figure 11(a), the RMD structure consists of a resistive switching layer sandwiched between the top electrode (TE) and the bottom electrode (BE), with all components fabricated on a single substrate. This structure integrates four resistive random access memory (RRAM) cells within a compact region, significantly improving device-level integration density. Its internal equivalent circuit is shown in Figure 11(b), with the four RRAM cells labeled A, B, C, and D. Input terminal V... IN1 and V IN2 Connected to the top electrode, the resistance states of the upper (A, B) and lower (C, D) RRAM pairs can be independently adjusted. When VDD is set to a low logic level, the resistance is adjusted by sending a signal to VDD. IN1 or V IN2 Applying a voltage pulse of appropriate polarity can switch the corresponding RRAM cell to a high-resistance state (HRS) or a low-resistance state (LRS). Specifically, V IN1 When a positive voltage is applied, the upper RRAM pair is programmed as LRS; when a negative voltage is applied, it switches to HRS; V IN2 The control logic for the lower RRAM pair is completely consistent with this. To avoid unexpected writes, when V... IN1 and V IN2 When in a floating state, the voltage of VDD must be lower than the switching threshold. The advantage of this structure is that it allows four RRAM cells to be integrated onto a single substrate, thus reducing the footprint. IN1 and VIN2 The signal input terminal is connected to the top electrode of the internal RRAM. The relationship between the resistance state of the RMD and the four internal RRAMs is shown in Table 2: Table 2 Three resistive states of RMD When all three states (ABCD) are in a high-resistance state, RMD is in a high-resistance state; when one of AB and CD is in a high-resistance state and the other is in a low-resistance state, RMD is in a medium-resistance state; when all three states (ABCD) are in a low-resistance state, RMD is in a low-resistance state. Figure 19 (a) in the figure shows the analog resistance state transition characteristics of the RRAM under positive and negative bias. When the input is positive bias, the device transitions to a low resistance state, and when the input is negative bias, the device transitions to a high resistance state. Figure 19 (b) is the IV relationship curve of the device. When the input voltage exceeds the switching threshold, the device resistance begins to change. The device switches to a low resistance state when the input voltage exceeds 0.8V and to a high resistance state when the input voltage is below -0.8V.

[0035] Furthermore, it should be noted that ternary AND gates (TAND) and ternary OR gates (TOR) are extensions of memristor-ratioed logic (MRL). The ternary implementation requires allowing each input port to have three discrete level states, corresponding to logic values ​​0, 1, and 2 respectively.

[0036] like Figure 18 As shown, both TAND and TOR consist of two RRAM devices with opposite polarities connected in series. The output node of TAND is connected to the top electrode of the RRAM, and the output node of TOR is connected to the bottom electrode of the RRAM. The output node is located at the common connection point of the two memristor devices, and the other end of each memristor device receives the input signal. The corresponding logic function is determined by the voltage division relationship of the input voltage across the memristor pair. The specific simulation results of the ternary AND gate and OR gate are shown below. Figure 18 As shown.

[0037] Example 2 In this embodiment, the specific operation of the above-mentioned ternary circuit is explained and verified by simulation. 1. Ternary inverter Circuit structure as follows Figure 1As shown in (a), during the operation of the STI, the input signal Vin has three voltage values: (0, VDD / 2, VDD), which can be mapped to logic (0, 1, 2). When the input is logic 0, the output is logic 2; when the input is logic 1, the output is logic 1; and when the input is logic 2, the output is logic 2. When the PTI is operating, if the input signal logic is (0, 1, 2), the corresponding output is (2, 2, 0). When the NTI is operating, if the input signal logic is (0, 1, 2), the corresponding output is (2, 0, 0).

[0038] Simulation results are as follows Figure 12 As shown, it can be seen that when the input signal is logic 0, the output results of STI, PTI and NTI are (2, 2, 2); when the input signal is logic 1, the output results of STI, PTI and NTI are (1, 2, 0); and when the input signal is logic 2, the output results of STI, PTI and NTI are (0, 0, 0).

[0039] 2. Ternary decoder Circuit structure as follows Figure 2 As shown in (b) above, the input signal V in (X) has three voltage values: (0, VDD / 2, VDD), which can be mapped to logic (0, 1, 2). When the input is logic 0, the output (X2, X1, X0) is (0, 0, 2); when the input is logic 1, the output (X2, X1, X0) is (0, 2, 0); and when the input is logic 2, the output (X2, X1, X0) is (2, 0, 0).

[0040] Simulation results are as follows Figure 13 As shown, when the input is logic 0, the PTI output ("2") is inverted by the NTI to obtain X2=0; the first NTI output X0=2; TOR and STI form a ternary NOR gate (TNOR), ultimately outputting X1=0. When the input is logic 1, the PTI / NTI link output X2=0; the first NTI output X0=0; the TNOR gate based on X2 and X0 outputs X1=2. When the input is logic 2, the PTI / NTI link output X2=2; other paths output X0=0 and X1=0 respectively. Figure 13 The SPICE simulation results shown verify that the ternary decoder (TDecoder) has the correct logic function in all input states.

[0041] 3. Ternary half-adder Circuit structure as follows Figure 4 As shown, taking inputs A=1 and B=1 as an example, the timing analysis is given: First, the ternary decoder outputs signal A1=B1=2, and all other outputs of the decoder are logic 0.

[0042] Secondly, in carry branch C, the relevant TAND 1-3 The gate outputs logic 0, TOR1 outputs logic 0, and this signal combines with VDD / 2 in TAND0 to obtain carry C=0.

[0043] Finally, in the branch S, only TAND5 outputs logic 2 (corresponding to A1B1), TOR2 and TOR3 process the terms with input logic levels of (0,2,0) and (0,0,0) respectively, and finally output the sum value S=2 through TOR4 gate.

[0044] Simulation results are as follows Figure 14 As shown, the circuit works correctly under all 9 input combinations. It can be seen that, taking input A=1 and B=1 as an example, the timing analysis case is given below: First, after decoding, A1=B1=2 is obtained, and all other outputs of the decoder are "0"; Second, in the carry branch, the relevant TAND output is "0", and the OR gate (TOR1) outputs "0". After the signal and VDD / 2 are logically operated on in the AND gate (TAND0), the carry C="0" is obtained; Finally, in the summation branch, only the AND gate (TAND5) outputs "2" (corresponding to the logical operation result of A1B1), and the OR gates (TOR2) and (TOR3) output "2" and "0" respectively. Finally, the sum S=2 is output through the OR gate (TOR4). Figure 14 The SPICE simulation results shown verify that the circuit can perform correct operations under all nine input combinations.

[0045] 4. Ternary full adder Circuit structure as follows Figure 6 As shown, with inputs A=1, B=1, C in Taking =1 as an example, the timing analysis is given: First, the ternary decoder outputs signals A1=B1=C. in1 =2, all other outputs of the decoder are logic 0.

[0046] Secondly, in carry branch C, TAND 4-6 The outputs are (0,0,2), TOR2 outputs logic 2, and then TOR7 also outputs logic 2. This signal is transmitted through TAND. 19 Perform a bitwise AND operation with logic 1 to obtain a carry output C=1; Finally, in branch S, TAND 7-18 Both TOR8 and TOR9 output logic 0, causing TAND to output 0 as well. 20 Output logic 0; finally, TOR10 Performing an OR operation on the above signals results in a final output sum S=0.

[0047] Simulation results are as follows Figure 15 As shown, taking inputs A=1, B=1, and Cin=1 as an example, the working principle is explained as follows: First, the ternary decoder (TDecoder) expands the output to A1=B1=Cin1=2, and the remaining branches are all logic values ​​"0"; Second, in the carry branch, the output of AND gate (TAND4-6) is (0, 0, 2), and the output of OR gate (TOR2) and subsequent OR gate (TOR7) is logic value "2". This signal is ANDed with logic value "1" by AND gate (TAND19), finally obtaining the carry output C=1; Third, in the sum branch, the outputs of AND gate (TAND7-18) are all logic values ​​"0", causing the outputs of OR gate (TOR8) and OR gate (TOR9) to be "0", so AND gate (TAND20) outputs logic value "0"; Finally, OR gate (TOR10) combines the above signals and outputs the sum S=0.

[0048] Figure 15 The feasibility of the RMD-CMOS circuit scheme was verified, and it was confirmed that after the transient switching process stabilized, the output value was consistent with... Figure 5 The truth table of (a) is completely consistent.

[0049] 5. Ternary multiplier Circuit structure as follows Figure 8 As shown, taking inputs A=1 and B=1 as an example, the timing analysis is given: First, the ternary decoder expands the output to A1=B1=2, and the remaining branches are all logic 0; Secondly, in the carry branch C, the output of TAND1 is 0. This signal is ANDed with logic 1 by TAND5 to obtain the carry output C=0; Finally, in the product branch P, TAND 1-4 The output is (0,2,0,0), which makes the outputs of TOR1 and TOR2 2 and 0 respectively. Therefore, TAND6 outputs logic 1. Finally, TOR3 performs an OR operation on the above signals and finally outputs the product P=0.

[0050] Simulation results are as follows Figure 16As shown, it can be seen that taking the input A = 1 and B = 1 as an example, its working principle is as follows: First, the ternary decoder (TDecoder) expands the output to A1 = B1 = 2, and the remaining branches are all logical values "0"; Second, in the carry branch, the AND gate (TAND1) outputs "0", and this signal is AND-operated with the logical value "1" through the AND gate (TAND5) to obtain the carry output C = 0; Third, in the product branch, the outputs of the AND gates (TAND1–4) are (0, 2, 0, 0), causing the OR gates (TOR1) and (TOR2) to output "2" and "0" respectively. Therefore, the AND gate (TAND6) outputs the logical value "1"; Finally, the OR gate (TOR3) combines the above signals and outputs the product value P = 0.

[0051] Figure 16 The simulation results shown verify the correctness of the function of this module.

[0052] 6. Ternary Comparator The circuit structure is as Figure 10 shown. Taking the input A = 1 and B = 0 as an example, the timing analysis is given as follows: First, the ternary decoder expands the output to A1 = B0 = 2, and the remaining branches are all logical 0; Second, in the G branch, the output of TAND 1-3 is (0, 0, 2); in the E branch, the output of TAND 4-6 is (0, 0, 0); in the L branch, the output of TAND 7-9 is (0, 0, 0); Finally, after the ternary OR operation, the output of TOR 1-3 is (2, 0, 0).

[0053] The simulation results are as Figure 17 shown. It can be seen that taking the input A = 1 and B = 0 as an example, its working principle is as follows: First, the ternary decoder (TDecoder) expands the output to A1 = B0 = 2, and the remaining branches are all logical values "0"; Second, in the "greater than" branch (G branch, corresponding to A > B), the outputs of the AND gates (TAND1 - 3) are (0, 0, 2); in the "equal to" branch (E branch, corresponding to A = B), the outputs of the AND gates (TAND4 - 6) are (0, 0, 0); in the "less than" branch (L branch, corresponding to A < B), the outputs of the AND gates (TAND7 - 9) are (0, 0, 0); Third, after the ternary OR operation, the outputs of the OR gates (TOR1 - 3) are (2, 0, 0).

[0054] Figure 17The simulation results verified the correct operation of the circuit.

[0055] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0056] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A ternary logic circuit based on an RRAM mirror device, characterized in that, include: A basic inverter unit, comprising, in series with, an RRAM mirror device and an NMOS transistor; The source of the NMOS transistor is grounded, the gate is used as the input terminal to receive the input signal, and the drain is used as the output terminal to output the signal. The RRAM mirror device is connected in series between the voltage source and the drain of the NMOS transistor to form a voltage divider circuit. The RRAM mirror device includes a first main terminal, a second main terminal, and at least two configuration terminals. The first main terminal is connected to the voltage source, the second main terminal is connected to the drain of the NMOS transistor, and the configuration terminals are respectively connected to a first setting voltage signal and a second setting voltage signal to control the RRAM mirror device to switch between a low-resistance state, a medium-resistance state, and a high-resistance state.

2. A ternary logic circuit based on an RRAM mirror device according to claim 1, characterized in that, The RRAM mirror device includes four RRAM units integrated on the same substrate, namely: a first RRAM unit, a second RRAM unit, a third RRAM unit, and a fourth RRAM unit; The first setting voltage signal and the second setting voltage signal are respectively connected to the top electrodes of the four RRAM cells; By combining the high and low resistance states of the four RRAM cells, the RRAM mirror device can macroscopically present a low resistance state, a medium resistance state, or a high resistance state.

3. A ternary logic circuit based on an RRAM mirror device according to claim 1, characterized in that, The basic inverter unit is reconstructed into three logic gates under the same physical series topology, based on the different resistive states of the RRAM mirror device: When the RRAM mirror device is in a low-resistance state, the basic inverter unit constitutes a positive ternary inverter; When the RRAM mirror device is in a medium-resistance state, the basic inverter unit constitutes a conventional ternary inverter; When the RRAM mirror device is in a high-impedance state, the basic inverter unit constitutes a negative ternary inverter.

4. A ternary logic circuit based on an RRAM mirror device according to claim 3, characterized in that, The ternary logic circuit further includes: a ternary OR gate, and a first negative ternary inverter, a second negative ternary inverter, a positive ternary inverter, and a conventional ternary inverter, each composed of the basic inverter unit; The first negative ternary inverter, the second negative ternary inverter, the positive ternary inverter, the conventional ternary inverter, and the ternary OR gate are cascaded together to form a ternary decoder; The first negative ternary inverter and the positive ternary inverter are connected in parallel to receive the input signal. The input terminal of the second negative ternary inverter is connected to the output terminal of the positive ternary inverter. The output terminals of the first negative ternary inverter and the second negative ternary inverter are connected to the input terminal of the ternary OR gate. The output terminal of the ternary OR gate is connected to the input terminal of the conventional ternary inverter.

5. A ternary logic circuit based on an RRAM mirror device according to claim 4, characterized in that, The ternary logic circuit further includes at least one ternary AND gate and at least one second ternary OR gate, wherein the ternary decoder, the ternary AND gate and the second ternary OR gate are electrically connected to form a ternary arithmetic logic array; In the ternary arithmetic logic array, at least one input of the ternary AND gate is directly electrically connected to a DC bias voltage terminal of a voltage source with an amplitude of half, so as to clamp the highest output level of the ternary AND gate to the corresponding logic 1 level.

6. An operation method based on the ternary logic circuit of claim 1, characterized in that, Includes the following steps: Using the first and second setting voltage signals, the resistance state of the RRAM mirror device is controlled to switch between low resistance, medium resistance and high resistance states, so as to reconstruct the input-output voltage transfer characteristics of the basic inverter unit. The input signal is provided with three voltage states: a first level, a second level, and a third level, which correspond to logic 0, logic 1, and logic 2, respectively.

7. The operation method of the ternary logic circuit according to claim 6, characterized in that, The amplitudes of the three voltage states are 0 volts, half the voltage source amplitude, and the voltage source amplitude, respectively. When the RRAM mirror device is set to a low-impedance state, the basic inverter unit performs a positive ternary inversion operation, and the output logic levels for the input signals of logic 0, logic 1 and logic 2 are 2, 2 and 0 respectively. When the RRAM mirror device is set to medium impedance state, the basic inverter unit performs a conventional ternary inversion operation, and the output logic levels for the input signals of logic 0, logic 1 and logic 2 are 2, 1 and 0 respectively. When the RRAM mirror device is set to a high-impedance state, the basic inverter unit performs a negative ternary inversion operation, and the output logic levels for the input signals of logic 0, logic 1 and logic 2 are 2, 0 and 0 respectively.

8. The operation method of the ternary logic circuit according to claim 6, characterized in that, The RRAM mirror device internally contains four RRAM cells integrated on the same substrate; the operation method further includes: The four RRAM cells are divided into a first group and a second group; When all RRAM cells in the first group and the second group are programmed to a high-impedance state by the first setting voltage signal and the second setting voltage signal, the RRAM mirror device as a whole presents the high-impedance state; When one of the first group and the second group is programmed to a high-resistance state and the other group is programmed to a low-resistance state, the RRAM mirror device as a whole presents the medium-resistance state. When all RRAM cells in the first group and the second group are programmed to a low-resistance state, the RRAM mirror device as a whole presents the low-resistance state.

9. An electronic device, characterized in that, It includes at least one ternary logic circuit based on an RRAM mirror device as described in any one of claims 1-5.

10. The electronic device according to claim 9, characterized in that, The electronic device is an integrated circuit chip; The integrated circuit chip contains a ternary half-adder, a ternary full adder, a ternary multiplier, or a ternary comparator, which are formed by cascading multiple ternary logic circuits according to the Karnaugh map minterm sum logic rule.

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