Logic gate circuit and logic signal generation method, processor, chip and device

Abstract

The application discloses a logic gate circuit and a logic signal generation method, a processor, a chip and equipment, and relates to the technical field of integrated circuits. The circuit comprises a first inverter, a logic selection circuit and a buffer circuit. The first inverter inverts a first input signal provided by a first signal input line and transmits the first input signal to a first signal transmission node. The logic selection circuit and the buffer circuit are interconnected, and exclusive or logic operation is performed on the first input signal and a second input signal. That is, based on the potential of the first signal transmission node, a corresponding logic signal path is selected, a circuit structure for coupling logic operation and driving output is designed, and accordingly, the number of transistors can be reduced when the logic gate circuit is constituted, so that the power consumption of the logic gate circuit during exclusive or logic operation is reduced. In the case of integrating the logic gate circuit in a chip, the chip area is reduced, and the chip manufacturing cost is reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a logic gate circuit and a method for generating logic signals, a processor, a chip, and a device. Background Technology

[0002] Logic gates are the basic building blocks of digital integrated circuits, used to perform basic Boolean algebra operations and output digital logic levels. Basic Boolean algebra operations include the XOR logic operation.

[0003] In related technologies, logically independent transmission gate networks and buffers are coupled together. Based on the combination of two input signals, the corresponding transmission gate is selected, and digital logic levels are directly transmitted to the buffer, thereby outputting the XOR logic operation result signal.

[0004] However, constructing the above logic gate circuit requires at least 5 pairs of complementary transistors, resulting in a large number of transistors and high power consumption; when the logic gate circuit is integrated into the chip, it occupies a large area. Summary of the Invention

[0005] This application provides a logic gate circuit and a method for generating logic signals, a processor, a chip, and a device. The technical solutions provided by this application include the following aspects.

[0006] According to one aspect of the embodiments of this application, a logic gate circuit is provided, the logic gate circuit comprising: The first inverter includes K1 transistors, which are coupled to a first signal input line, a power supply, and a first signal transmission node. In response to receiving a first input signal provided by the first signal input line and a power supply signal provided by the power supply, the first signal transmission node is controlled to invert the first input signal. A logic selection circuit includes K2 transistors, which are coupled to a first signal input line, a second signal input line, a first signal transmission node, and a second signal transmission node. The K2 transistors are used to control the potential of the second signal transmission node in response to receiving a first input signal from the first signal input line, a second input signal from the second signal input line, and the potential of the first signal transmission node. Specifically, when the first input signal corresponds to a first potential, the second input signal is selected to be transmitted to the second signal transmission node; when the first input signal corresponds to a second potential, the inverted signal of the second input signal is selected to be transmitted to the second signal transmission node. The first potential is higher than the second potential. A buffer circuit includes K3 transistors, which are coupled to the power supply, the second signal transmission node, and the output node. The K3 transistors are used to control the potential of the output node in response to the potential change of the second signal transmission node and the power signal received from the power supply, so that the potential of the second signal transmission node is reversed. K1, K2, and K3 are all positive integers, and the sum of K1, K2, and K3 is less than 10.

[0007] Optionally, the K1 transistors include: The first transistor has its gate coupled to the first signal input line, its first terminal coupled to the power supply, and its second terminal coupled to the first signal transmission node. The second transistor has its gate coupled to the first signal input line, its first terminal grounded, and its second terminal coupled to the first signal transmission node.

[0008] Optionally, the logic selection circuit includes: A transmission gate is used to connect the second signal input line and the second signal transmission node when the first input signal corresponds to the first potential, and to transmit the second input signal to the second signal transmission node; and to disconnect the second signal input line and the second signal transmission node when the first input signal corresponds to the second potential. The second inverter is configured to, when the first input signal corresponds to the second potential, turn on the second signal input line and the second signal transmission node to transmit the inverted signal of the second input signal to the second signal transmission node, and, when the first input signal corresponds to the first potential, turn off the second signal input line and the second signal transmission node.

[0009] Optionally, the logic selection circuit includes: The transmission gate is coupled to the first signal input line, the second signal input line, the first signal transmission node, and the second signal transmission node, and is used to control the on / off state of the second signal input line and the second signal transmission node in response to the first input signal provided by the first signal input line and the potential of the first signal transmission node, and to control the potential of the second signal transmission node in response to the first input signal provided by the first signal input line and the potential of the first signal transmission node.

[0010] Optionally, the transmission gate includes K4 transistors, and the K2 transistors include the K4 transistors; the K4 transistors include: The third transistor has its gate coupled to the first signal transmission node, its first electrode coupled to the second signal input line, and its second electrode coupled to the second signal transmission node. A fourth transistor, wherein the gate of the fourth transistor is coupled to the first signal input line, the first electrode of the fourth transistor is coupled to the second signal input line, and the second electrode of the fourth transistor is coupled to the second signal transmission node.

[0011] Optionally, the logic selection circuit includes: The second inverter is coupled to the first signal input line, the second signal input line, the first signal transmission node, and the second signal transmission node, and is used to control the on / off state of the second signal input line and the second signal transmission node in response to the first input signal provided by the first signal input line and the potential of the first signal transmission node, and to control the potential of the second signal transmission node in response to the first input signal provided by the first signal input line, the second input signal provided by the second signal input line, and the potential of the first signal transmission node.

[0012] Optionally, the second inverter includes K5 transistors, and the K2 transistors include the K5 transistors; the K5 transistors include: The fifth transistor has its gate coupled to the second signal input line, its first terminal coupled to the first signal transmission node, and its second terminal coupled to the second signal transmission node. A sixth transistor, wherein the gate of the sixth transistor is coupled to the second signal input line, the first terminal of the sixth transistor is coupled to the first signal input line, and the second terminal of the sixth transistor is coupled to the second signal transmission node.

[0013] Optionally, the K3 transistors include: A seventh transistor, wherein the gate of the seventh transistor is coupled to the second signal transmission node, the first terminal of the seventh transistor is coupled to the power supply, and the second terminal of the seventh transistor is coupled to the output node; The eighth transistor has its gate coupled to the second signal transmission node, its first terminal grounded, and its second terminal coupled to the output node.

[0014] According to one aspect of the embodiments of this application, a method for generating logic signals is provided, the method being applied to logic gate circuits as provided in the above embodiments of this application; the method includes: The first inverter of the logic gate circuit generates a first inverted signal based on the first input signal provided by the first signal input line and the power signal provided by the power supply, and transmits it to the first signal transmission node of the logic gate circuit. The logic selection circuit of the logic gate circuit generates a first logic signal based on the first input signal provided by the first signal input line, the second input signal provided by the second signal input line, and the first inverted signal provided by the first signal transmission node, and transmits it to the second signal transmission node of the logic gate circuit. The buffer circuit of the logic gate circuit generates a second logic signal based on the first logic signal provided by the second signal transmission node, and drives the output node of the logic gate circuit to output the second logic signal.

[0015] According to one aspect of the embodiments of this application, a processor is provided, the processor including the logic gate circuits as provided in the embodiments of this application above.

[0016] According to one aspect of the embodiments of this application, a chip is provided, the chip including a processor, the processor including logic gate circuits as provided in the embodiments of this application above.

[0017] According to one aspect of the embodiments of this application, a computer device is provided, the computer device including a processor, the processor including logic gate circuits as provided in the embodiments of this application above.

[0018] The technical solution provided in this application can bring the following beneficial effects: The first input signal provided by the first signal input line is inverted by the first inverter and transmitted to the first signal transmission node. Through interconnected logic selection circuits and buffer circuits, an XOR logic operation is performed on the first input signal and the second input signal provided by the first signal input line and the second signal input line, respectively. That is, based on the potential selection of the logic signal path corresponding to the first signal transmission node, the circuit structure of logic operation and drive output is coupled. Accordingly, the number of transistors can be reduced when constructing logic gate circuits, thereby reducing the power consumption of logic gate circuits when performing XOR logic operations. Furthermore, when logic gate circuits are integrated into the chip, the chip area is reduced and the chip manufacturing cost is reduced. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the circuit structure of an XOR gate circuit provided in an exemplary embodiment of this application; Figure 2 This is a schematic diagram of the circuit structure of an XOR gate circuit provided in another exemplary embodiment of this application; Figure 3This is a schematic diagram of the structure of a logic gate circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of another logic gate circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram of the circuit structure of a logic gate circuit provided in an embodiment of this application; Figure 6 This is a schematic diagram of the circuit structure of another logic gate circuit provided in an embodiment of this application; Figure 7 This is a flowchart of a logic signal generation method provided in an embodiment of this application; Figure 8 This is a flowchart of another method for generating logic signals provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of a chip provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of a computer device provided in an exemplary embodiment of this application. Detailed Implementation

[0020] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0021] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0022] It should be understood that although the terms first, second, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0024] The transistors used in the embodiments of this application can be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. Examples of FETs include metal-oxide-semiconductor (MOS) FETs, also known as MOS transistors. Furthermore, depending on their function in the circuit, the transistors used in the embodiments of this application are implemented as complementary metal-oxide-semiconductor (CMOS) structures.

[0025] It should be noted that, in the embodiments of this application, coupling refers to the phenomenon of energy or signal transmission between two or more systems, components, or circuits through physical connection or electromagnetic field interaction. In this application, "coupling" refers to a physical or electrical relationship between two or more electronic components, circuit nodes, or systems, established through a conductive medium (such as wires or metal interconnects) with low impedance, enabling current to flow, potentials to be equal, or signals to be directly transmitted, wherein the electrical connection is established upon physical contact.

[0026] Furthermore, the transistors used in the embodiments of this application may include any one of P-channel transistors and N-channel transistors, wherein the P-channel transistor is turned on when the gate is at a low potential and turned off when the gate is at a high potential; the N-channel transistor is turned on when the gate is at a high potential and turned off when the gate is at a low potential. Optionally, the P-channel transistor may be, for example, a low-temperature polysilicon (LTPS) transistor, and the N-channel transistor may be, for example, an oxide transistor. That is, the P-channel transistor can be fabricated using LTPS material, and the N-channel transistor can be fabricated using oxide material. The P-channel transistor may be a PMOS transistor, and the N-channel transistor may be an NMOS transistor.

[0027] Schematic representation: A PMOS transistor includes a P-channel enhancement-mode field-effect transistor and a P-channel depletion-mode field-effect transistor. On an N-type silicon substrate, there are two P+ regions, the source and drain, respectively. There is no conduction between these two regions. In the case of a P-channel enhancement-mode PMOS transistor, when a sufficient positive voltage is applied to the source and the gate is grounded, a P-type inversion layer forms on the N-type silicon surface under the gate, becoming the channel connecting the source and drain. Changing the gate voltage alters the hole density in the channel, thereby changing the channel resistance. In the case of a P-channel depletion-mode PMOS transistor, a P-type inversion layer channel already exists on the N-type silicon substrate surface without a gate voltage. Applying an appropriate bias voltage to the PMOS transistor changes the channel resistance.

[0028] Since the source and drain of the transistor used here are symmetrical, they are interchangeable. In the embodiments of this application, the source can be referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is designated as the control electrode, also known as the gate; the signal input terminal is the source; and the signal output terminal is the drain.

[0029] Furthermore, in the embodiments of this application, multiple signals correspond to a first potential and a second potential. The first potential can refer to a high level (logic 1), and the second potential can refer to a low level (logic 0). Moreover, the first potential and the second potential only represent that the signal has two potential levels, and do not represent that it has a specific voltage value.

[0030] In this embodiment, logic gate circuits generate output signals according to predetermined logic rules based on combinations of input signals, thus forming the basic operational units of a digital system. Each logic gate circuit comprises multiple logic gate units, which are indivisible digital circuit modules used to implement basic Boolean algebra operations (such as AND, OR, NOT, etc.). These logic gate units are interconnected to form the logic gate circuit. Schematic examples include, but are not limited to, adders, multipliers, signal selectors, and flip-flops. The same or different logic gate circuits can be combined to construct a complete digital system, such as a microprocessor or memory.

[0031] In some embodiments, the logic gate circuit includes an XOR gate circuit that implements the XOR logic operation. The XOR gate circuit is a core sub-circuit used to implement processing modules such as arithmetic operations and data encryption. The implementation methods of the XOR gate circuit include, but are not limited to, at least two of the following: 1. Basic CMOS structure: It uses 10 transistors to form a CMOS XOR gate circuit, which performs an XOR logic operation on two input signals and outputs the corresponding operation result; for example, if input signals A and B are passed through the XOR gate circuit of the basic CMOS structure, the result signal corresponding to A⊕B will be output.

[0032] For illustrative purposes, please refer to the following: Figure 1 This illustrates a schematic diagram of the circuit structure of an XOR gate circuit provided in an exemplary embodiment of this application. Figure 1 As shown, the logic gate circuit includes 10 transistors, where transistors M-P0, M-P1, M-P2, M-P3, and M-P4 are P-channel transistors (e.g., PMOS TFTs); and transistors M-N0, M-N1, M-N2, M-N3, and M-N4 are N-channel transistors (e.g., NMOS TFTs). The logic gate circuit includes at least two input terminals, where the first input terminal receives signal A, and the second input terminal receives signal B.

[0033] like Figure 1 As shown, the NOR gate circuit composed of transistors M-P0, M-P4, M-N0, and M-N4 outputs the inverted signal A+B; the inverter circuit composed of transistors M-P3 and M-N1 inverts the signal corresponding to the intermediate node, thus obtaining the A+B signal; the AND gate structure composed of transistors M-P1, M-P2, M-N3, and M-N2 obtains the AB signal; the complementary network combines the AB signal with the A+B signal to obtain an equivalent A⊕B signal as the output of the XOR gate circuit, that is, a low level is output when the A signal and the B signal are the same, and a high level is output when the A signal and the B signal are opposite.

[0034] Each input terminal of the XOR gate circuit in the aforementioned basic CMOS structure is driven by a complementary transistor group consisting of one PMOS transistor and one NMOS transistor, i.e., fan-in (fin) = 1. Here, fin indicates the maximum number of independent input signals that can be connected to the input terminal of the logic gate circuit. Increasing fin through repeated parallel connections reduces the equivalent resistance of the transmission gate circuit and increases signal transmission speed, thus enhancing driving capability; correspondingly, the circuit structure needs to be adjusted. For example, with fin = 2, the XOR gate circuit of the basic CMOS structure requires 14 transistors.

[0035] 2. Pass-Transistor Logic (PTL) structure: It uses two transmission gates and three inverters to form an XOR gate circuit, which performs an XOR logic operation on two input signals and outputs the corresponding operation result; the XOR gate circuit corresponding to the PTL structure based on transmission gates includes 10 transistors.

[0036] For illustrative purposes, please refer to the following: Figure 2This illustrates a circuit structure diagram of an XOR gate circuit provided in another exemplary embodiment of this application. Figure 2 As shown, this logic gate circuit includes 10 transistors, where transistors M1, M3, M5, M7, and M9 are P-channel transistors (e.g., PMOS TFTs); and transistors M2, M4, M6, M8, and M10 are N-channel transistors (e.g., NMOS TFTs). This logic gate circuit includes two input terminals: the first input terminal receives signal A, and the second input terminal receives signal B.

[0037] like Figure 2 As shown, the inverter composed of transistors M1 and M2 transmits the inverted signal of A, thereby controlling the working states of the transmission gates composed of transistors M5 and M4 and M3 and M6, respectively. The two-stage inverting buffer composed of transistors M7, M8, M9 and M10 shapes and amplifies the output signals of the two transmission gates, obtaining an equivalent signal of A⊕B as the output of the XOR gate circuit. That is, when the signals A and B are the same, the output is low level, and when the signals A and B are opposite, the output is high level.

[0038] like Figure 2 As shown, when the transmission gate composed of transistors M5 and M4 is in the ON state, it outputs a C signal, which is the same as the B signal. When the transmission gate composed of transistors M3 and M6 is in the ON state, it outputs a C signal, which is the opposite of the B signal. Specifically, the transmission gate receives the inverted B signal and outputs the C signal; the inverted B signal is output by an inverter composed of transistors M7 and M8. The output signal corresponding to the transmission gate, such as the C signal, has a high impedance and weak driving capability. Therefore, an inverter composed of transistors M9 and M10 shapes and amplifies the output signal to ensure that the XOR gate circuit corresponding to the PTL structure based on the transmission gate has stable driving capability.

[0039] However, the above-mentioned at least two methods for generating logic gates and logic signals have at least the following problems: 1. A large number of transistors are required, which in turn leads to larger node capacitances in the logic gates and higher dynamic power consumption. Simultaneously, the static leakage path increases with the number of transistors, resulting in a corresponding increase in static power consumption. In chip design based on logic gates, the number of transistors directly determines the layout area; a larger number of transistors results in lower chip integration density and higher manufacturing costs. 2. The logic gates have lower driving capability, resulting in smaller charging and discharging currents to the load capacitors of the logic gate units. This leads to slower signal transitions, increasing transmission delay and reducing circuit operating speed. Furthermore, the slower signal edges are more susceptible to noise interference such as crosstalk and power supply fluctuations, potentially causing logic misjudgments and reducing the stability of the logic gates.

[0040] To address the aforementioned issues, this application provides a logic gate circuit implemented as an XOR gate circuit, wherein the number of transistors included in the logic gate circuit is relatively small. Accordingly, a method for generating logic signals is provided for this logic gate circuit, which performs an XOR logic operation by combining a first inverter with a logic selection circuit, and improves the driving capability of the logic gate circuit by using a buffer circuit.

[0041] The logic gate circuit includes: a first inverter containing K1 transistors, the K1 transistors being coupled to a first signal input line, a power supply, and a first signal transmission node, and being used to control the potential of the first signal transmission node in response to receiving a first input signal provided by the first signal input line and a power supply signal provided by the power supply, thereby inverting the first input signal; A logic selection circuit includes K2 transistors, which are coupled to a first signal input line, a second signal input line, a first signal transmission node, and a second signal transmission node. The circuit is used to control the potential of the second signal transmission node in response to receiving a first input signal from the first signal input line, a second input signal from the second signal input line, and the potential of the first signal transmission node. Specifically, when the first input signal corresponds to a first potential, the circuit selects to transmit the second input signal to the second signal transmission node; when the first input signal corresponds to a second potential, the circuit selects to transmit the inverted signal of the second input signal to the second signal transmission node. The first potential is higher than the second potential. The buffer circuit includes K3 transistors, which are coupled to the power supply, the second signal transmission node, and the output node. In response to the potential change of the second signal transmission node and the power signal received from the power supply, the buffer circuit controls the potential of the output node so that the potential of the second signal transmission node is reversed. K1, K2, and K3 are all positive integers, and the sum of K1, K2, and K3 is less than 10.

[0042] Figure 3 This is a schematic diagram of a logic gate circuit provided in an embodiment of this application, such as... Figure 3 As shown, the logic gate circuit includes: a first inverter 01, a logic selection circuit 02, and a buffer circuit 03.

[0043] The first inverter 01 is coupled to the first signal input line IN1, the power supply, and the first signal transmission node X, and is used to control the potential of the first signal transmission node X in response to the first input signal provided by the first signal input line IN1 and the power supply signal provided by the power supply.

[0044] For example, the first inverter 01 can control the potential of the first signal transmission node X to the second potential when the potential of the first input signal provided by the first signal input line IN1 is the first potential, or control the potential of the first signal transmission node X to the first potential when the potential of the first input signal provided by the first signal input line IN1 is the second potential; optionally, the first inverter 01 has a gain function, amplifying the first input signal and outputting a larger current to the logic selection circuit 02.

[0045] Optionally, as mentioned above, the first potential can refer to a high level (logic 1), i.e., a high potential, and the second potential can refer to a low level (logic 0), i.e., a low potential.

[0046] Optionally, combined Figure 3 In this embodiment, the power supply includes a positive terminal (the node with the highest potential in the circuit) and a negative terminal (the node with the reference ground potential in the circuit), wherein the negative terminal is also the ground terminal; the first inverter 01 is connected to the positive and negative terminals of the power supply. The positive terminal of the power supply can be the drain power supply voltage (VDD), and the negative terminal of the power supply, i.e., the ground terminal, can be the source power supply voltage (VSS); wherein the potential of the power signal provided by the positive terminal VDD corresponds to a high potential, and the reference potential provided by the negative terminal VSS corresponds to a low potential, here high potential and low potential are relative; for example, the positive terminal of the power supply corresponds to the highest potential in the circuit (positive power supply), and the negative terminal of the power supply corresponds to the reference ground potential of the circuit (0V). Accordingly, the positive terminal VDD can also be called a pull-up power supply; the negative terminal VSS can also be called a pull-down power supply.

[0047] Optionally, in a bipolar junction transistor (BJT) circuit or a transistor-transistor logic (TTL) circuit, the positive terminal of the power supply can be the collector power supply voltage (VCC), and the negative terminal of the power supply can be the ground terminal (GND).

[0048] The logic selection circuit 02 is coupled to the first signal input line IN1, the second signal input line IN2, the first signal transmission node X, and the second signal transmission node Y, and is used to control the potential of the second signal transmission node Y in response to the first input signal provided by the first signal input line IN1, the second input signal provided by the second signal input line IN2, and the potential of the first signal transmission node X.

[0049] For example, the logic selection circuit 02 can control the potential of the second signal transmission node Y to be consistent with the potential of the second input signal provided by the second signal input line IN2 when the potential of the first signal transmission node X is the second potential, that is, when the potential of the first input signal provided by the first signal input line IN1 is the first potential; or, when the potential of the first signal transmission node X is the first potential, that is, when the potential of the first input signal provided by the first signal input line IN1 is the second potential, control the potential of the second signal transmission node Y to be opposite to the potential of the second input signal provided by the second signal input line IN2.

[0050] In some embodiments, the logic selection circuit 02 may include the following logic gate units: 1. A transmission gate, used to control the connection and disconnection of the second signal input line IN2 and the second signal transmission node Y in response to the first input signal provided by the first signal input line IN1 and the potential of the first signal transmission node X, and to control the potential of the second signal transmission node Y in response to the first input signal provided by the first signal input line IN1 and the potential of the first signal transmission node X.

[0051] For example, when the potential of the first signal transmission node X is the first potential, the second signal input line IN2 is disconnected from the second signal transmission node Y. The disconnection is used to indicate that the second signal input line IN2 cannot provide the second input signal to the second signal transmission node Y through the transmission gate. When the potential of the first signal transmission node X is the second potential, the second signal input line IN2 is turned on to the second signal transmission node Y, and the potential of the second signal transmission node Y is kept consistent with the potential of the second input signal provided by the second signal input line IN2.

[0052] 2. A second inverter, used to control the on / off state of the second signal input line IN2 and the second signal transmission node Y in response to the first input signal provided by the first signal input line IN1 and the potential of the first signal transmission node X, and to control the potential of the second signal transmission node Y in response to the first input signal provided by the first signal input line IN1, the second input signal provided by the second signal input line IN2 and the potential of the first signal transmission node X.

[0053] For example, when the potential of the first signal transmission node X is the first potential, the second signal input line IN2 is controlled to be connected to the second signal transmission node Y, and the potential of the second signal transmission node Y is controlled to be opposite to the potential of the second input signal provided by the second signal input line IN2; when the potential of the first signal transmission node X is the second potential, the second signal input line IN2 is controlled to be disconnected from the second signal transmission node Y, wherein the disconnection is used to indicate that the second signal input line cannot provide the inverted signal of the second input signal to the second signal transmission node Y through the second inverter.

[0054] The buffer circuit 03 is coupled to the power supply, the second signal transmission node Y, and the output node OUT, and is used to control the potential of the output node OUT in response to the potential of the second signal transmission node Y and the power signal provided by the power supply.

[0055] For example, the buffer circuit 03 can control the output node OUT to a second potential when the potential of the second signal transmission node Y is a first potential, or control the output node OUT to a first potential when the potential of the second signal transmission node Y is a second potential. Using the buffer circuit 03 as a push-pull structure, the output signal of the logic selection circuit 02 is amplified and output to the output node OUT with a larger current.

[0056] Optionally, combined Figure 3 In this embodiment, the power supply includes a positive terminal and a negative terminal, and the buffer circuit 03 is connected to both the positive and negative terminals. The positive terminal can be VDD, and the negative terminal can be VSS, i.e., ground. The power signal provided by the positive terminal VDD corresponds to a high potential, and the reference potential provided by the negative terminal VSS corresponds to a low potential; here, high and low potentials are relative. Accordingly, the positive terminal VDD can also be called a pull-up power supply, and the negative terminal VSS can also be called a pull-down power supply.

[0057] In some embodiments, the method for implementing the XOR logic operation using the above-mentioned logic gate circuits includes the following steps: 1. Signal control is achieved through the first inverter 01, and the corresponding signal path is selected by the control logic selection circuit 02 based on the first input signal provided by the first signal input line IN1. Specifically, when the potential of the first input signal is the first potential, the output control logic selection circuit 02 of the first inverter 01 selects the inverted signal path of the second input signal; when the potential of the first input signal is the second potential, the output control logic selection circuit 02 of the first inverter 01 selects the signal path of the second input signal.

[0058] Schematic example, taking the first input signal as signal A and the second input signal as signal B, when signal A is implemented as logic 0 (A=0), the inverted signal of A output by the first inverter 01 is logic 1, which controls the logic selection circuit 02 to select the B signal path. The B signal path is used to indicate that the logic signal output to the output node OUT of the signal path is consistent with the B signal. When signal A is implemented as logic 0 (A=1), the inverted signal of A output by the first inverter 01 is logic 0, which controls the logic selection circuit 02 to select the B inverted signal path. The B inverted signal path is used to indicate that the logic signal output to the output node OUT of the signal path is opposite to the B signal.

[0059] 2. Path switching is achieved through logic selection circuit 02. Based on the output of the first inverter 01, the corresponding signal path is selected, and the second input signal or its inverted signal is output to the second signal transmission node Y. Specifically, when the signal path of the second input signal is selected, the inverted signal of the second input signal is output to the second signal transmission node Y; when the inverted signal path of the second input signal is selected, the second input signal is output to the second signal transmission node Y.

[0060] 3. Buffered output is achieved through buffer circuit 03. Based on the output of logic selection circuit 02, the logic signal corresponding to the second signal transmission node Y is converted to a standard CMOS level and subjected to shaping and amplification processing. The stable XOR logic operation result is then output to output node OUT. Specifically, when logic selection circuit 02 outputs the inverted signal of the second input signal, that is, when the potential of the second signal transmission node Y is opposite to the potential of the second input signal, the second input signal is output to output node OUT; when logic selection circuit 02 outputs the second input signal, that is, when the potential of the second signal transmission node Y is the same as the potential of the second input signal, the inverted signal of the second input signal is output to output node OUT.

[0061] In CMOS digital circuits, standard CMOS levels indicate the defined voltage ranges for logic 0 and logic 1. These levels are based on the power rail and define distinct low and high level regions. Schematably, the voltage range for logic 0 is typically 0V to the maximum value of the input low level, with the maximum input level close to VSS; the voltage range for logic 1 is typically the minimum value of the input high level to VDD, with the minimum input high level close to VDD. When the logic level corresponding to the output node OUT is close to the power rail, the logic gate does not incur threshold loss. Furthermore, because the logic level corresponding to the output node OUT is close to the power rail, the allowable deviation range for the potential of the second signal transmission node Y is relatively large, meaning that circuit noise has a smaller impact on the output signal corresponding to the output node OUT.

[0062] Schematic example, taking signal A as the first input signal and signal B as the second input signal, when signal A is logic 0 (A=0), the control logic selection circuit 02 selects the path of signal B, outputs the inverted signal of signal B to the second signal transmission node Y, and inputs it to the buffer circuit 03. The buffer circuit 03 then inverts the inverted signal of signal B, outputting signal B to the output node OUT. Similarly, when signal A is logic 0 (A=1), the control logic selection circuit 02 selects the path of the inverted signal of signal B, outputs signal B to the second signal transmission node Y, and inputs it to the buffer circuit 03. The buffer circuit 03 then inverts the signal B, outputting the inverted signal of signal B to the output node OUT.

[0063] In summary, this application provides a logic gate circuit. This logic gate circuit inverts the first input signal provided by the first signal input line using a first inverter and transmits it to the first signal transmission node. Through a logic selection circuit and a buffer circuit, it performs an XOR logic operation on the first and second input signals provided by the first and second signal input lines respectively, thereby increasing the drive current and reducing the power consumption of the logic gate circuit during the XOR logic operation. Furthermore, by integrating the logic gate circuit onto a chip, it reduces the chip's footprint and lowers chip manufacturing costs.

[0064] In some embodiments, this application provides a logic gate circuit, wherein the logic selection circuit in the logic gate circuit includes a transmission gate and a second inverter, for performing logic signal selection in an XOR logic operation, and the logic selection circuit includes: The transmission gate is used to connect the second signal input line and the second signal transmission node when the first input signal corresponds to the first potential, and to transmit the second input signal to the second signal transmission node; and to disconnect the second signal input line and the second signal transmission node when the first input signal corresponds to the second potential. The second inverter is configured to, when the first input signal corresponds to the second potential, turn on the second signal input line and the second signal transmission node to transmit the inverted signal of the second input signal to the second signal transmission node, and, when the first input signal corresponds to the first potential, turn off the second signal input line and the second signal transmission node.

[0065] The transmission gate is coupled to the first signal input line, the second signal input line, the first signal transmission node, and the second signal transmission node, and is used to control the on / off state of the second signal input line and the second signal transmission node in response to the first input signal provided by the first signal input line and the potential of the first signal transmission node, and to control the potential of the second signal transmission node in response to the first input signal provided by the first signal input line and the potential of the first signal transmission node.

[0066] The second inverter is coupled to the first signal input line, the second signal input line, the first signal transmission node, and the second signal transmission node, and is used to control the on / off state of the second signal input line and the second signal transmission node in response to the first input signal provided by the first signal input line and the potential of the first signal transmission node, and to control the potential of the second signal transmission node in response to the first input signal provided by the first signal input line, the second input signal provided by the second signal input line, and the potential of the first signal transmission node.

[0067] Please refer to Figure 4 This is a schematic diagram of another logic gate circuit provided in the embodiments of this application. Based on the above embodiments, as shown below... Figure 4 As shown, the logic selection circuit 02 includes a transmission gate 04 and a second inverter 05. That is, the logic gate circuit includes a first inverter 01, a buffer circuit 03, a transmission gate 04, and a second inverter 05.

[0068] Transmission gate 04 is coupled to the first signal input line IN1, the second signal input line IN2, the first signal transmission node X, and the second signal transmission node Y. It is used to control the on / off state of the second signal input line IN2 and the second signal transmission node Y in response to the first input signal provided by the first signal input line IN1 and the potential of the first signal transmission node X. It also controls the potential of the second signal transmission node Y in response to the first input signal provided by the first signal input line IN1 and the potential of the first signal transmission node X.

[0069] For example, the transmission gate 04 can control the second signal input line IN2 to disconnect from the second signal transmission node Y when the potential of the first input signal provided by the first signal input line IN1 is the second potential, that is, when the potential of the first signal transmission node X is the first potential; wherein, disconnection means that the second signal input line IN2 cannot provide the second input signal to the second signal transmission node Y through the transmission gate 04. Also, when the potential of the first input signal provided by the first signal input line IN1 is the first potential, that is, when the potential of the first signal transmission node X is the second potential, the second signal input line IN2 is controlled to be connected to the second signal transmission node Y, and the potential of the second signal transmission node Y is controlled to be consistent with the potential of the second input signal provided by the second signal input line IN2; optionally, the potential of the second signal transmission node Y is controlled by the second signal input line IN2 providing the second input signal to the second signal transmission node Y through the transmission gate 04.

[0070] Alternatively, as mentioned above, the first potential can refer to a high level (logic 1), and the second potential can refer to a low level (logic 0).

[0071] The second inverter 05 is coupled to the first signal input line IN1, the second signal input line IN2, the first signal transmission node X, and the second signal transmission node Y. It is used to control the on / off state of the second signal input line IN2 and the second signal transmission node Y in response to the first input signal provided by the first signal input line IN1 and the potential of the first signal transmission node X. It also controls the potential of the second signal transmission node Y in response to the first input signal provided by the first signal input line IN1, the second input signal provided by the second signal input line IN2, and the potential of the first signal transmission node X.

[0072] For example, when the potential of the first input signal provided by the first signal input line IN1 is the second potential, that is, when the potential of the first signal transmission node X is the first potential, the second signal input line IN2 is controlled to be connected to the second signal transmission node Y, and the potential of the second signal transmission node Y is controlled to be opposite to the potential of the second input signal provided by the second signal input line IN2; optionally, the potential of the second signal transmission node Y is controlled by the second signal input line IN2 providing an inverted signal of the second input signal to the second signal transmission node Y through the second inverter 05. And, when the potential of the first input signal provided by the first signal input line IN1 is the first potential, that is, when the potential of the first signal transmission node X is the second potential, the second signal input line IN2 is controlled to be disconnected from the second signal transmission node Y; wherein, disconnection means that the second signal input line IN2 cannot provide a signal to the second signal transmission node Y through the second inverter 05.

[0073] In some embodiments, the transmission gate 04 and the second inverter 05 collaboratively process the second input signal provided by the second signal input line IN2 to implement XOR operation logic. Schematably, when the potential of the first input signal provided by the first signal input line IN1 is the second potential, i.e., when the first input signal corresponds to logic 0, the transmission gate 04 is turned off, and the second inverter 05 and the buffer circuit 03 form a buffer. By performing two inversion operations on the second input signal provided by the second signal input line IN2, the logic corresponding to the second input signal remains unchanged. That is, a logic signal consistent with the second input signal is transmitted to the output node OUT, and the overall driving capability of the logic gate circuit is improved.

[0074] Furthermore, when the potential of the first input signal provided by the first signal input line IN1 is the first potential, that is, when the first input signal corresponds to logic 1, the transmission gate 04 is turned on and the second inverter 05 is turned off. The transmission gate 04, as a modular transmission switch, transmits the second input signal provided by the second signal input line IN2 to the second signal transmission node Y and the buffer circuit 03 in the on state. The buffer circuit 03 performs inversion and amplification processing to transmit a logic signal opposite to the second input signal to the output node OUT. At the same time, it enhances the driving capability of the logic gate circuit.

[0075] Schematic, based on the above embodiments, based on Figure 3 The logic gate circuit shown, Figure 5 A schematic diagram of a logic gate circuit is shown; based on Figure 4 The logic gate circuit shown, Figure 6 A schematic diagram of another logic gate circuit is shown. (Reference) Figure 5 and Figure 6 It can be seen that the first inverter 01 may include a first transistor P1 and a second transistor N1. The logic selection circuit 02 may include a third transistor P2, a fourth transistor N2, a fifth transistor P3, and a sixth transistor N3; wherein, the logic selection circuit 02 includes a transmission gate 04 and a second inverter 05, the transmission gate 04 may include the third transistor P2 and the fourth transistor N2, and the second inverter 05 may include the fifth transistor P3 and the sixth transistor N3. The buffer circuit 03 may include a seventh transistor P4 and an eighth transistor N4.

[0076] Optionally, the embodiments of this application do not limit the type of transistor. For example, the first, third, fifth, and seventh transistors are P-channel transistors (e.g., PMOS TFT); the second, fourth, sixth, and eighth transistors are N-channel transistors (e.g., NMOS TFT). Alternatively, the first, third, fifth, and seventh transistors are N-channel transistors (e.g., NMOS TFT); the second, fourth, sixth, and eighth transistors are P-channel transistors (e.g., PMOS TFT).

[0077] like Figure 5 , Figure 6 As shown in the description of the embodiments of this application, the first transistor P1, the third transistor P2, the fifth transistor P3, and the seventh transistor P4 are P-channel transistors (e.g., PMOS TFTs); the second transistor N1, the fourth transistor N2, the sixth transistor N3, and the eighth transistor N4 are N-channel transistors (e.g., NMOS TFTs); and the first signal input line IN1 is implemented as the first input terminal for inputting signal A, and the second signal input line IN2 is implemented as the second input terminal for inputting signal B; and the positive terminal of the power supply is implemented as VDD, and the negative terminal of the power supply, i.e., the ground terminal, is implemented as VSS. Optionally, the first terminal of the above transistors is implemented as the source, and the second terminal is implemented as the drain.

[0078] Among them, K1 transistors include a first transistor P1 and a second transistor N1: the gate of the first transistor P1 is coupled to the first signal input line IN1, the first terminal of the first transistor P1 is coupled to the power supply, that is, coupled to the positive terminal VDD of the power supply, and the second terminal of the first transistor P1 is coupled to the first signal transmission node X.

[0079] The gate of the second transistor N1 is coupled to the first signal input line IN1, the first terminal of the second transistor N1 is grounded, that is, coupled to the negative power supply VSS, and the second terminal of the second transistor N1 is coupled to the first signal transmission node X.

[0080] K2 transistors include a third transistor P2, a fourth transistor N2, a fifth transistor P3, and a sixth transistor N3: the gate of the third transistor P2 is coupled to the first signal transmission node X, the first terminal of the third transistor P2 is coupled to the second signal input line IN2, and the second terminal of the third transistor P2 is coupled to the second signal transmission node Y.

[0081] The gate of the fourth transistor N2 is coupled to the first signal input line IN1, the first terminal of the fourth transistor N2 is coupled to the second signal input line IN2, and the second terminal of the fourth transistor N2 is coupled to the second signal transmission node Y.

[0082] The gate of the fifth transistor P3 is coupled to the second signal input line IN2, the first terminal of the fifth transistor P3 is coupled to the first signal transmission node X, and the second terminal of the fifth transistor P3 is coupled to the second signal transmission node Y.

[0083] The gate of the sixth transistor N3 is coupled to the second signal input line IN2, the first terminal of the sixth transistor N3 is coupled to the first signal input line IN1, and the second terminal of the sixth transistor N3 is coupled to the second signal transmission node Y.

[0084] The K3 transistors include a seventh transistor P4 and an eighth transistor N4: the gate of the seventh transistor P4 is coupled to the second signal transmission node Y, the first terminal of the seventh transistor P4 is coupled to the power supply, that is, to the positive terminal VDD of the power supply, and the second terminal of the seventh transistor P4 is coupled to the output node OUT.

[0085] The gate of the eighth transistor N4 is coupled to the second signal transmission node Y. The first terminal of the eighth transistor N4 is grounded, that is, coupled to the negative power supply VSS. The second terminal of the eighth transistor N4 is coupled to the output node OUT.

[0086] In some embodiments, the first input signal is inverted by the first transistor P1 and the second transistor N1 in the first inverter 01, and the inverted result is output to the first signal transmission node X through the second terminals of the first transistor P1 and the second transistor N1, which serves as the path selection basis for the logic selection circuit 02.

[0087] The inversion of the first input signal via the first transistor P1 and the second transistor N1 in the first inverter 01 includes at least one of the following steps: 1. When the potential of the first output signal provided by the first signal input line IN1 is the first potential, that is, when the first output signal is logic 1, the gate voltage of the first transistor P1 is approximately VDD, the first electrode voltage of the first transistor P1 is VDD, and the gate-source voltage of the first transistor P1 is VGS = VDD - VDD = 0V. That is, the gate-source voltage of the first transistor P1 does not meet the conduction condition corresponding to the PMOS transistor, so the first transistor P1 is turned off. The gate voltage of the second transistor N1 is approximately VDD, the first electrode voltage of the second transistor N1 is VSS, and the gate-source voltage of the second transistor N1 is VGS = VDD - VSS = VDD, which is much greater than the threshold voltage of the NMOS transistor. Therefore, the second transistor N1 is turned on. In summary, the first signal transmission node X is coupled to the second electrode of the first transistor P1 and the second transistor N1. The second transistor N1 is directly connected to the negative power supply VSS, that is, the ground terminal, through the turned-on second transistor N1. That is, the output of the first inverter O1 is strongly pulled down to VSS, corresponding to the standard CMOS level of logic 0.

[0088] 2. When the potential of the first output signal provided by the first signal input line IN1 is the second potential, that is, when the first output signal is logic 0, the gate voltage of the first transistor P1 is approximately VSS, the first electrode voltage of the first transistor P1 is VDD, and the gate-source voltage (VGS) of the first transistor P1 = VSS - VDD = -VDD. In other words, the absolute value of the gate-source voltage of the first transistor P1 is much greater than the threshold voltage of the PMOS transistor, so the first transistor P1 is turned on. The gate voltage of the second transistor N1 is approximately VSS, the first electrode voltage of the second transistor N1 is VSS, and the gate-source voltage VGS of the second transistor N1 = VSS - VSS = 0V, which is less than the threshold voltage of the NMOS transistor, so the second transistor N1 is turned off. In summary, the first signal transmission node X is coupled to the second electrodes of the first transistor P1 and the second transistor N1. The first transistor P1 is directly connected to the positive power supply VDD, meaning that the output of the first inverter O1 is strongly pulled up to VDD, corresponding to the standard CMOS level of logic 1.

[0089] Optionally, the first inverter 01 is used as a gain stage. In the first inverter 01, the first transistor P1 and the second transistor N1 are turned on simultaneously when the input voltage is near VDD / 2, forming a high transconductance amplification region. Small changes in the input voltage will cause significant changes in the current in the first transistor P1 and the second transistor N1, resulting in a rapid jump in the output voltage. This increases the rate of change of the output voltage relative to the input voltage, thereby generating a gain effect to amplify the logic signal output to the first signal transmission node X, thereby improving the driving capability of the first inverter 01.

[0090] In some embodiments, the third transistor P2, the fourth transistor N2, the fifth transistor P3, and the sixth transistor N3 in the logic selection circuit 02 establish a signal path corresponding to the output of the first inverter 01. That is, they perform logic selection processing on the second input signal provided by the second signal input line IN2 and output the logic selection result to the second signal transmission node Y. Specifically, the transmission gate 04, composed of the third transistor P2 and the fourth transistor N2, is used to establish the inverted signal path of the second input signal, and the second inverter 05, composed of the fifth transistor P3 and the sixth transistor N3, is used to establish the signal path of the second input signal.

[0091] That is, the signal path selection corresponding to the logic selection circuit 02 is realized by the coordinated transmission gate 04 and the second inverter 05, thereby realizing the XOR logic operation with fewer transistors.

[0092] Based on the output of the first inverter 01 and the first input signal provided by the first signal input line IN1, the third transistor P2 and the fourth transistor N2 connected in parallel in the transmission gate 04 control the switching state of the transmission gate 04.

[0093] Schematic, when the potential of the first input signal provided by the first signal input line IN1 is the second potential, that is, when the first output signal is logic 0, the logic signal output by the first inverter 01 to the first signal transmission node X is logic 1, that is, the potential of the first signal transmission node X is the first potential. The gate of the third transistor P2 is coupled to the first signal transmission node X, and the gate-source voltage VGS of the third transistor P2 is ≥ 0, which does not meet the conduction condition corresponding to the PMOS transistor. At this time, the third transistor P2 is turned off. The gate of the fourth transistor N2 is coupled to the first signal input line IN1, and the gate-source voltage VGS of the fourth transistor N2 is ≤ 0, which does not meet the conduction condition corresponding to the NMOS transistor. At this time, the fourth transistor N2 is turned off. That is, when the output of the first inverter 01 is logic 1, the transmission gate 04 is in the off state.

[0094] Schematic, when the potential of the first input signal provided by the first signal input line IN1 is the first potential, that is, when the first output signal is logic 1, the logic signal output by the first inverter 01 to the first signal transmission node X is logic 0, that is, the potential of the first signal transmission node X is the second potential. The gate of the third transistor P2 is coupled to the first signal transmission node X. The absolute value of the gate-source voltage VGS of the third transistor P2 is greater than the threshold voltage of the PMOS transistor. At this time, the third transistor P2 is turned on. The gate of the fourth transistor N2 is coupled to the first signal input line IN1. The gate-source voltage VGS of the fourth transistor N2 is greater than the threshold voltage of the NMOS transistor. At this time, the fourth transistor N2 is turned on. That is, when the output of the first inverter 01 is logic 0, the transmission gate 04 is in the on state.

[0095] By connecting the third transistor P2 and the fourth transistor N2 in the parallel transmission gate 04, a pair of complementary transistors is formed. When the potential of the first signal transmission node X is the second potential, regardless of whether the transmission level is high or low, it is guaranteed that one transistor is in the conducting state, thereby ensuring full-scale transmission of the second input signal provided by the second signal input line IN2. Furthermore, the transmission gate structure reduces the logic gate cascading delay and improves the signal transmission speed. When the transmission gate 04 is in the off state, the short-circuit current is eliminated, reducing the overall power consumption of the logic gate unit.

[0096] In some embodiments, the second inverter 05 is a quasi-inverter. A quasi-inverter is used to indicate that even when the logic signal connected to the sources of a set of complementary transistors in the inverter is in a non-ideal state, such as with threshold loss, it can still convert the output to a standard CMOS level. Based on the output of the first inverter 01 and the first input signal provided by the first signal input line IN1, the fifth transistor P3 and the sixth transistor N3 in the second inverter 05 control the switching state of the second inverter 05. When the second inverter 05 is in the ON state, it inverts the second input signal provided by the second signal input line IN2 and outputs the inverted signal of the second input signal to the second signal transmission node Y.

[0097] The switching states of the second inverter 05 controlled by the fifth transistor P3 and the sixth transistor N3 include the following two cases: 1. The potential of the first output signal provided by the first signal input line IN1 is the second potential, that is, the first output signal is logic 0. The potential of the first signal transmission node X is the first potential. The first terminal of the fifth transistor P3 is coupled to the first signal transmission node X, and the first terminal of the sixth transistor N3 is coupled to the first signal input line IN1. The voltage of the first terminal of the fifth transistor P3 is approximately VDD, and the voltage of the first terminal of the sixth transistor N3 is approximately VSS. Therefore, one of the fifth transistor P3 and the sixth transistor N3 is conducting, that is, the second inverter 05 is in the conducting state. Schematic, when the second inverter 05 is in the conducting state, the inversion of the second input signal provided by the second signal input line IN2 includes at least one of the following steps: 1.1 When the potential of the second input signal provided by the second signal input line IN2 is the first potential, that is, when the second output signal is logic 1, the gate voltage of the fifth transistor P3 is approximately VDD, and the gate-source voltage of the fifth transistor P3 is VGS = VDD - VDD = 0V. That is, the gate-source voltage of the fifth transistor P3 does not meet the conduction condition corresponding to the PMOS transistor, so the fifth transistor P3 is turned off. The gate voltage of the sixth transistor N3 is approximately VDD, and the gate-source voltage of the sixth transistor N3 is VGS = VDD - VSS = VDD, which is greater than the threshold voltage of the NMOS transistor, so the sixth transistor N3 is turned on. In summary, the second signal transmission node Y is coupled to the second terminals of the fifth transistor P3 and the sixth transistor N3, and is directly connected to the first signal input line IN1 through the turned-on first transistor P1. That is, the output of the second inverter 05 is strongly pulled down to the low level corresponding to logic 0.

[0098] 1.2 When the potential of the second output signal provided by the second signal input line IN2 is the second potential, that is, when the second output signal is logic 0, the gate voltage of the fifth transistor P3 is approximately VSS, and the gate-source voltage of the fifth transistor P5 is VGS = VSS - VDD = -VDD. That is, the absolute value of the gate-source voltage of the fifth transistor P5 is much greater than the threshold voltage of the PMOS transistor, so the fifth transistor P5 is turned on. The gate voltage of the sixth transistor N3 is approximately VSS, and the gate-source voltage of the sixth transistor N3 is VGS = VSS - VSS = 0, which is less than the threshold voltage of the NMOS transistor, so the sixth transistor N3 is turned off. In summary, the second signal transmission node Y is coupled to the second terminals of the fifth transistor P3 and the sixth transistor N3, and is directly connected to the first signal transmission node X through the turned-on fifth transistor P3. That is, the output of the second inverter 05 is strongly pulled up to the high level corresponding to logic 1.

[0099] 2. The potential of the first output signal provided by the first signal input line IN1 is the first potential, that is, the first output signal is logic 1. The potential of the first signal transmission node X is the second potential. The first terminal of the fifth transistor P3 is coupled to the first signal transmission node X. The first terminal of the sixth transistor N3 is coupled to the first signal input line IN1. The voltage of the first terminal of the fifth transistor P3 is approximately VSS. The voltage of the first terminal of the sixth transistor N3 is approximately VDD. Therefore, there is never a conducting transistor between the fifth transistor P3 and the sixth transistor N3. That is, the second inverter 05 is in the off state.

[0100] Schematic, when the second output signal provided by the second signal input line IN2 is low, the gate voltage of the fifth transistor P3 is approximately VSS, and the gate-source voltage of the fifth transistor P3 VGS=VSS-VSS=0V, which does not meet the conduction condition of the PMOS transistor, so the fifth transistor P3 is turned off at this time; the gate voltage of the sixth transistor M3 is approximately VSS, and the gate-source voltage of the sixth transistor N3 VGS=VSS-VDD=-VDD<0V, which does not meet the conduction condition of the NMOS transistor, so the sixth transistor N3 is turned off at this time; that is, the second inverter 05 is in the off state. When the second output signal provided by the second signal input line IN2 is high, the gate voltage of the fifth transistor P3 is approximately VDD, and the gate-source voltage of the fifth transistor P3, VGS = VDD - VSS = VDD > 0V, does not meet the conduction condition of the PMOS transistor, so the fifth transistor P3 is turned off at this time; the gate voltage of the sixth transistor M3 is approximately VDD, and the gate-source voltage of the sixth transistor N3, VGS = VDD - VDD = 0V, does not meet the conduction condition of the NMOS transistor, so the sixth transistor N3 is turned off at this time; that is, the second inverter 05 is in the off state.

[0101] The second inverter 05 ensures a signal path for the second input signal by connecting the fifth transistor P3 and the sixth transistor N3, reducing the number of transistors in the logic gate circuit, shortening the interconnect length, optimizing the wiring layout of the logic gate circuit, and reducing parasitic capacitance in the logic gate circuit. This reduces signal propagation delay and improves the overall reliability and yield of the logic gate circuit. When designing chips based on logic gate circuits, this increases chip integration density and reduces chip area and manufacturing cost. Furthermore, the second inverter 05 shapes and amplifies the output signal in the on state, ensuring that the logic gate circuit has stable driving capability.

[0102] In some embodiments, the first inverter 01 and the logic selection circuit 02 are implemented as the core logic module for implementing the XOR operation logic of the logic gate circuit, and the buffer circuit 03 is implemented as a complementary output buffer stage to standardize the output signal of the core logic module and increase the drive current. By directly coupling the core logic module with the buffer circuit 03, the delay loss of the logic gate circuit in the XOR logic operation process is reduced.

[0103] In this circuit, buffer circuit 03 serves as the final output unit in the logic gate circuit, enhancing the drive current through a push-pull output structure. The complementary transistors, consisting of the seventh transistor P4 and the eighth transistor N4 in buffer circuit 03, form a low-impedance direct path to the positive power supply VDD and the negative power supply VSS, ensuring that one of the seventh transistor P4 and the eighth transistor N4 is conducting, thus improving the driving capability of the logic signal corresponding to the second signal transmission node Y. Furthermore, based on the output of logic selection circuit 02, the seventh transistor P4 and the eighth transistor N4 in buffer circuit 03 perform an inversion operation on the logic signal corresponding to the second signal transmission node Y, outputting the result of the XOR logic operation to the output node OUT.

[0104] Schematic, buffer circuit 03 is implemented as an inverter. Specifically, the inversion of the logic signal corresponding to the second signal transmission node Y by the seventh transistor P4 and the eighth transistor N4 includes at least one of the following steps: 1. When logic selection circuit 02 outputs logic 0, meaning the potential of the second signal transmission node Y is at the second potential, the gate voltage of the seventh transistor P4 is approximately VSS, the first terminal voltage of the seventh transistor P4 is VDD, and the gate-source voltage of the seventh transistor P4 is VGS = VSS - VDD = -VDD. That is, the absolute value of the gate-source voltage of the seventh transistor P4 is much greater than the threshold voltage of the PMOS transistor, so the seventh transistor P4 is turned on. Similarly, the gate voltage of the eighth transistor N4 is approximately VSS, the first terminal voltage of the eighth transistor N4 is VSS, and the gate-source voltage of the eighth transistor N4 is VGS = VSS - VSS = 0V, which is less than the threshold voltage of the NMOS transistor, so the eighth transistor N4 is turned off. In summary, the output node OUT is coupled to the second terminals of the seventh transistor P4 and the eighth transistor N4. The conducting seventh transistor P4 is directly connected to the positive power supply VDD. That is, the output of buffer circuit 03 is strongly pulled up to VDD, corresponding to the standard CMOS level of logic 1.

[0105] 2. When logic selection circuit 02 outputs logic 1, i.e., the potential of the second signal transmission node Y is the first potential, the gate voltage of the seventh transistor P4 is approximately VDD, the first terminal voltage of the seventh transistor P4 is VDD, and the gate-source voltage of the seventh transistor P4 is VGS = VDD - VDD = 0V. That is, the gate-source voltage of the seventh transistor P4 does not meet the conduction condition corresponding to the PMOS transistor, so the seventh transistor P4 is turned off. The gate voltage of the eighth transistor N4 is approximately VDD, the first terminal voltage of the eighth transistor N4 is VSS, and the gate-source voltage of the eighth transistor N4 is VGS = VDD - VSS = VDD, which is much greater than the threshold voltage of the NMOS transistor. Therefore, the eighth transistor N4 is turned on. In summary, the output node OUT is coupled to the second terminals of the seventh transistor P4 and the eighth transistor N4. The turned-on eighth transistor N4 is directly connected to the negative terminal of the power supply VSS, i.e., the ground terminal. That is, the output of buffer circuit 03 is strongly pulled down to VSS, corresponding to the standard CMOS level of logic 0.

[0106] Among them, the buffer circuit 03 is implemented as a push-pull output structure. Based on the seventh transistor P4 and the eighth transistor N4, it ensures that the level of the output to the output node OUT is directly determined by the power supply voltage, thereby restoring the signal amplitude, reducing the influence of noise in the logic gate circuit on the output signal, and improving the driving capability of the logic gate circuit.

[0107] Optionally, the push-pull output structure corresponding to the buffer circuit 03 is used to drive large capacitive loads, such as off-chip pins and long buses. By increasing the width-to-length ratio of the seventh transistor P4 and the eighth transistor N4, the on-resistance is reduced and the driving current is increased. That is, based on the design requirements of the logic gate circuit, in order to improve the driving capability of the logic gate circuit used to implement the XOR logic operation, the width-to-length ratio of the transistors in the buffer circuit 03 is increased proportionally. By improving the driving capability of the logic gate circuit, the integrity of the logic signal corresponding to the output node is ensured, and the accuracy of subsequent circuits in recognizing the logic signal is improved.

[0108] In summary, this application provides a logic gate circuit. This logic gate circuit inverts the first input signal provided by the first signal input line using a first inverter and transmits it to the first signal transmission node. Through a logic selection circuit and a buffer circuit, it performs an XOR logic operation on the first and second input signals provided by the first and second signal input lines respectively, thereby increasing the drive current and reducing the power consumption of the logic gate circuit during the XOR logic operation. Furthermore, by integrating the logic gate circuit onto a chip, it reduces the chip's footprint and lowers chip manufacturing costs.

[0109] This application also provides a method for generating logic signals, which is applied to, for example... Figure 3 and Figure 5 Any of the logic gate circuits shown. For example... Figure 7 As shown, the method includes: Step 710: Generate a first inverted signal using the first inverter based on the first input signal and the power supply signal.

[0110] The first inverter of the logic gate circuit generates a first inverted signal based on the first input signal provided by the first signal input line and the power signal provided by the power supply, and transmits it to the first signal transmission node of the logic gate circuit.

[0111] In some embodiments, the first inverter transmits a first inverted signal to the first signal transmission node in response to a first input signal provided by a first signal input line and a power signal provided by a power supply.

[0112] Schematic, the first inverter controls the potential of the first signal transmission node to a second potential when the potential of the first input signal provided by the first signal input line is a first potential; or, when the potential of the first input signal provided by the first signal input line is a second potential, it controls the potential of the first signal transmission node to a first potential; optionally, the first inverter amplifies the first input signal and outputs a larger current to the logic selection circuit. That is, the first inverter transmits the first inverted signal corresponding to the first input signal to the first signal transmission node.

[0113] Step 720: The logic selection circuit generates a first logic signal based on the first input signal, the second input signal, and the first inverted signal.

[0114] The logic selection circuit of the logic gate circuit generates a first logic signal based on the first input signal provided by the first signal input line, the second input signal provided by the second signal input line, and the first inverted signal provided by the first signal transmission node, and transmits the signal to the second signal transmission node of the logic gate circuit.

[0115] In some embodiments, the logic selection circuit transmits a first logic signal to the second signal transmission node in response to a first input signal provided by a first signal input line, a second input signal provided by a second signal input line, and a first inverted signal provided by a first signal transmission node.

[0116] Schematic illustration: When the potential of the first signal transmission node is the second potential, i.e., the potential of the first input signal provided by the first signal input line is the first potential, the logic selection circuit controls the potential of the second signal transmission node to be consistent with the potential of the second input signal provided by the second signal input line; or, when the potential of the first signal transmission node is the first potential, i.e., the potential of the first input signal provided by the first signal input line is the second potential, the logic selection circuit controls the potential of the second signal transmission node to be opposite to the potential of the second input signal provided by the second signal input line. In other words, based on the potential of the first signal transmission node, the logic selection circuit generates a first logic signal and transmits the first logic signal to the second signal transmission node.

[0117] Step 730: The buffer circuit generates and outputs the second logic signal based on the first logic signal.

[0118] The buffer circuit of the logic gate circuit generates a second logic signal based on the first logic signal provided by the second signal transmission node, and drives the output node of the logic gate circuit to output the second logic signal.

[0119] In some embodiments, the buffer circuit responds to the first logic signal provided by the second signal transmission node and drives the output node to output the second logic signal.

[0120] Schematic, the buffer circuit controls the output node's potential to be the second potential when the potential of the second signal transmission node is the first potential, or controls the output node's potential to be the first potential when the potential of the second signal transmission node is the second potential. Using the buffer circuit as a push-pull structure, the output signal of the logic selection circuit is amplified and output to the output node with a larger current. That is, based on the first logic signal, the second logic signal is transmitted to the output node through the buffer circuit. The potential of the second signal transmission node is used to indicate and input the first logic signal to the buffer circuit. The first logic signal is the output of the logic selection circuit, and the second logic signal is the inverted signal of the first logic signal after shaping and amplification.

[0121] In some embodiments, the method for implementing XOR logic operation using the above-described driving logic gate circuit includes the following steps: 1. Signal control is achieved through a first inverter, and the corresponding signal path is selected by a control logic selection circuit based on the first input signal provided by the first signal input line. Specifically, when the potential of the first input signal is the first potential, the inverted signal path of the second input signal is selected by the output control logic selection circuit of the first inverter; when the potential of the first input signal is the second potential, the signal path of the second input signal is selected by the output control logic selection circuit of the first inverter.

[0122] 2. Path switching is achieved through a logic selection circuit. Based on the output of the first inverter, the corresponding signal path is selected, and the second input signal or its inverted signal is output to the second signal transmission node. Specifically, when the signal path of the second input signal is selected, the inverted signal of the second input signal is output to the second signal transmission node; when the inverted signal path of the second input signal is selected, the second input signal is output to the second signal transmission node.

[0123] 3. Buffered output is achieved through a buffer circuit. Based on the output of the logic selection circuit, the logic signal corresponding to the second signal transmission node is converted to a standard CMOS level and shaped and amplified. The stable XOR logic operation result is then output to the output node. Specifically, when the logic selection circuit outputs the inverted signal of the second input signal (i.e., the potential of the second signal transmission node is opposite to the potential of the second input signal), the second input signal is output to the output node; when the logic selection circuit outputs the second input signal (i.e., the potential of the second signal transmission node is the same as the potential of the second input signal), the inverted signal of the second input signal is output to the output node.

[0124] Please refer to Figure 8 It illustrates a flowchart of another logic signal generation method provided in an embodiment of this application, which can be used to drive, for example... Figure 4 and Figure 6 The logic gate circuit shown is an example. Figure 8 As shown, step 720 above also includes steps 722 and 724.

[0125] Step 722: When the first input signal corresponds to the first potential, a first logic signal is generated through the transmission gate based on the first input signal, the second input signal, and the first inverted signal.

[0126] When the first input signal corresponds to the first potential, the transmission gate of the logic selection circuit controls the conduction of the second signal input line and the second signal transmission node according to the first input signal provided by the first signal input line and the first inverted signal provided by the first signal transmission node. The first logic signal is generated according to the first input signal provided by the first signal input line, the second input signal provided by the second signal input line and the first inverted signal provided by the first signal transmission node, and is transmitted to the second signal transmission node.

[0127] In some embodiments, the transmission gate controls the conduction of the second signal input line and the second signal transmission node in response to the first input signal provided by the first signal input line and the first inverted signal provided by the first signal transmission node, and transmits the first logic signal to the second signal transmission node in response to the first input signal provided by the first signal input line and the first inverted signal provided by the first signal transmission node.

[0128] Schematic, when the potential of the first input signal provided by the first signal input line is the second potential, i.e., when the potential of the first signal transmission node is the first potential, the transmission gate controls the second signal input line to disconnect from the second signal transmission node; wherein, disconnection means that the second signal input line cannot provide the second input signal to the second signal transmission node through the transmission gate. Also, when the potential of the first input signal provided by the first signal input line is the first potential, i.e., when the potential of the first signal transmission node is the second potential, the gate controls the second signal input line to conduct to the second signal transmission node, and controls the potential of the second signal transmission node to be consistent with the potential of the second input signal provided by the second signal input line; optionally, the potential of the second signal transmission node is controlled as follows: the second signal input line provides the second input signal to the second signal transmission node through the transmission gate, at which time the levels of the first logic signal and the second input signal are consistent.

[0129] Step 724: When the first input signal corresponds to the second potential, the second inverter generates the first logic signal based on the first input signal, the second input signal, and the first inverted signal.

[0130] When the first input signal corresponds to the second potential, the second inverter of the logic selection circuit controls the conduction of the second signal input line and the second signal transmission node according to the first input signal provided by the first signal input line and the first inverted signal provided by the first signal transmission node. The first logic signal is generated according to the first input signal provided by the first signal input line, the second input signal provided by the second signal input line and the first inverted signal provided by the first signal transmission node, and is transmitted to the second signal transmission node. The first potential is higher than the second potential.

[0131] In some embodiments, the second inverter controls the conduction of the second signal input line and the second signal transmission node in response to the first input signal provided by the first signal input line and the first inverted signal provided by the first signal transmission node, and transmits a first logic signal to the second signal transmission node in response to the first input signal provided by the first signal input line, the second input signal provided by the second signal input line and the first inverted signal provided by the first signal transmission node.

[0132] Schematic, when the potential of the first input signal provided by the first signal input line is the second potential, that is, when the potential of the first signal transmission node is the first potential, the second signal input line is controlled to be connected to the second signal transmission node, and the potential of the second signal transmission node is controlled to be opposite to the potential of the second input signal provided by the second signal input line; optionally, the potential of the second signal transmission node is controlled as follows: the second signal input line provides the inverted signal of the second input signal to the second signal transmission node through the second inverter, at which time the level of the first logic signal is opposite to that of the second input signal.

[0133] And, when the potential of the first input signal provided by the first signal input line is the first potential, that is, when the potential of the first signal transmission node is the second potential, the second signal input line is disconnected from the second signal transmission node; wherein, disconnection means that the second signal input line cannot provide a signal to the second signal transmission node through the second inverter.

[0134] In summary, the embodiments of this application provide a method for generating logic signals. This method is based on a logic gate circuit that inverts a first input signal provided by a first signal input line using a first inverter and transmits it to a first signal transmission node. Through a logic selection circuit and a buffer circuit, an XOR logic operation is performed on the first and second input signals provided by the first and second signal input lines, respectively, increasing the drive current and thus reducing the power consumption of the logic gate circuit during the XOR logic operation. Furthermore, by integrating the logic gate circuit onto a chip, the chip area is reduced, lowering chip manufacturing costs.

[0135] This application also provides a chip. For example... Figure 9As shown, the chip includes: a substrate 10, and logic gate circuits 920 and power rails 930 located on the substrate 910. Combined with... Figures 3 to 6 It can be seen that logic gate circuits include, for example: Figures 3 to 6 Any of the logic gates shown, Figure 9 No longer shown.

[0136] In the logic gate circuit 920, multiple signal lines are coupled to power rails 930. Power rails 930 are metal connections inside the chip used to distribute power, used to couple with the power supply, and to provide the power signals required for transmitting logic signals to the logic gate circuit 920.

[0137] It is understood that since the chip can have essentially the same technical effect as the logic gate circuits described in the above embodiments, the technical effect of the chip will not be repeated here for the sake of brevity.

[0138] Please refer to Figure 10 This diagram illustrates a structural block diagram of a computer device 1000 according to an embodiment of this application. The computer device 1000 includes the logic gate circuits provided in the above-described embodiments. Specifically: The computer device 1000 can be a portable mobile terminal, also referred to as a mobile terminal in this embodiment. Examples include smartphones, tablets, Moving Picture Experts Group Audio Layer III (MP3) players, and Moving Picture Experts Group Audio Layer IV (MP4) players. The computer device 1000 may also be referred to as a user device, portable terminal, or other names.

[0139] Typically, computer device 1000 includes a processor 1001 and a memory 1002.

[0140] Processor 1001 may include one or more processing cores, such as a 4-core processor, a 10-core processor, etc. Processor 1001 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). Processor 1001 may include the logic gate circuits provided in the above-described embodiments.

[0141] The memory 1002 may include one or more computer-readable storage media, which may be tangible and non-transitory. The memory 1002 may also include high-speed random access memory devices and non-volatile storage devices, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1002 are used to store at least one instruction, which is executed by the processor 1002 to implement the logic signal generation method provided in the various method embodiments of this application.

[0142] In some embodiments, the computer device 1000 may also optionally include: a peripheral device interface 1003 and at least one peripheral device.

[0143] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0144] Those skilled in the art will understand that Figure 10 The structure shown does not constitute a limitation on the computer device 1000, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0145] On the other hand, embodiments of this application provide a computer device, which includes a processor, and the processor includes logic gate circuits as provided in the embodiments of this application above.

[0146] On the other hand, embodiments of this application provide a computer-readable storage medium storing at least one instruction, which is loaded and executed by a processor to implement the logic signal generation method provided in the embodiments of this application above.

[0147] On the other hand, embodiments of this application provide a computer program product, including a computer program or instructions, which, when executed by a processor, implement the logic signal generation method provided in the embodiments of this application as described above.

[0148] On the other hand, embodiments of this application provide a computer device, which includes a processor as described above, the processor including the logic gate circuits provided in the embodiments of this application above. Optionally, the processor may be a graphics processing unit (GPU). The computer device may be at least one of a portable computer, a desktop computer, a server, a server cluster, an artificial intelligence (AI) computing cluster, and a cloud computing cluster. The AI ​​computing cluster may also be simply referred to as an intelligent computing cluster or a smart computing cluster.

[0149] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0150] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0151] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0152] It should be noted that the terminology used in the embodiments of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the implementation of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0153] For example, the terms "first," "second," or "third," and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an" or "a," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" covers the element or object listed following "comprising" or "including," and does not exclude other elements or objects. Terms such as "upper," "lower," "left," or "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Coupled" or "connected" refers to an electrical connection.

[0154] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A logic gate circuit, characterized in that, The logic gate circuit includes: The first inverter includes K1 transistors, which are coupled to a first signal input line, a power supply, and a first signal transmission node. In response to receiving a first input signal provided by the first signal input line and a power supply signal provided by the power supply, the first signal transmission node is controlled to invert the first input signal. A logic selection circuit includes K2 transistors, which are coupled to a first signal input line, a second signal input line, a first signal transmission node, and a second signal transmission node. The K2 transistors are used to control the potential of the second signal transmission node in response to receiving a first input signal from the first signal input line, a second input signal from the second signal input line, and the potential of the first signal transmission node. Specifically, when the first input signal corresponds to a first potential, the second input signal is selected to be transmitted to the second signal transmission node; when the first input signal corresponds to a second potential, the inverted signal of the second input signal is selected to be transmitted to the second signal transmission node. The first potential is higher than the second potential. A buffer circuit includes K3 transistors, which are coupled to the power supply, the second signal transmission node, and the output node. The K3 transistors are used to control the potential of the output node in response to the potential change of the second signal transmission node and the power signal received from the power supply, so that the potential of the second signal transmission node is reversed. K1, K2, and K3 are all positive integers, and the sum of K1, K2, and K3 is less than 10.

2. The logic gate circuit according to claim 1, characterized in that, The K1 transistors include: The first transistor has its gate coupled to the first signal input line, its first terminal coupled to the power supply, and its second terminal coupled to the first signal transmission node. The second transistor has its gate coupled to the first signal input line, its first terminal grounded, and its second terminal coupled to the first signal transmission node.

3. The logic gate circuit according to claim 1, characterized in that, The logic selection circuit includes: A transmission gate is used to connect the second signal input line and the second signal transmission node when the first input signal corresponds to the first potential, and to transmit the second input signal to the second signal transmission node; and to disconnect the second signal input line and the second signal transmission node when the first input signal corresponds to the second potential. The second inverter is configured to, when the first input signal corresponds to the second potential, turn on the second signal input line and the second signal transmission node to transmit the inverted signal of the second input signal to the second signal transmission node, and, when the first input signal corresponds to the first potential, turn off the second signal input line and the second signal transmission node.

4. The logic gate circuit according to claim 3, characterized in that, The logic selection circuit includes: The transmission gate is coupled to the first signal input line, the second signal input line, the first signal transmission node, and the second signal transmission node, and is used to control the on / off state of the second signal input line and the second signal transmission node in response to the first input signal provided by the first signal input line and the potential of the first signal transmission node, and to control the potential of the second signal transmission node in response to the first input signal provided by the first signal input line and the potential of the first signal transmission node.

5. The logic gate circuit according to claim 4, characterized in that, The transmission gate includes K4 transistors, and the K2 transistors include the K4 transistors; the K4 transistors include: The third transistor has its gate coupled to the first signal transmission node, its first electrode coupled to the second signal input line, and its second electrode coupled to the second signal transmission node. A fourth transistor, wherein the gate of the fourth transistor is coupled to the first signal input line, the first electrode of the fourth transistor is coupled to the second signal input line, and the second electrode of the fourth transistor is coupled to the second signal transmission node.

6. The logic gate circuit according to claim 3, characterized in that, The logic selection circuit includes: The second inverter is coupled to the first signal input line, the second signal input line, the first signal transmission node, and the second signal transmission node, and is used to control the on / off state of the second signal input line and the second signal transmission node in response to the first input signal provided by the first signal input line and the potential of the first signal transmission node, and to control the potential of the second signal transmission node in response to the first input signal provided by the first signal input line, the second input signal provided by the second signal input line, and the potential of the first signal transmission node.

7. The logic gate circuit according to claim 6, characterized in that, The second inverter includes K5 transistors, and the K2 transistors include the K5 transistors; the K5 transistors include: The fifth transistor has its gate coupled to the second signal input line, its first terminal coupled to the first signal transmission node, and its second terminal coupled to the second signal transmission node. A sixth transistor, wherein the gate of the sixth transistor is coupled to the second signal input line, the first terminal of the sixth transistor is coupled to the first signal input line, and the second terminal of the sixth transistor is coupled to the second signal transmission node.

8. The logic gate circuit according to any one of claims 1 to 7, characterized in that, The K3 transistors include: A seventh transistor, wherein the gate of the seventh transistor is coupled to the second signal transmission node, the first terminal of the seventh transistor is coupled to the power supply, and the second terminal of the seventh transistor is coupled to the output node; The eighth transistor has its gate coupled to the second signal transmission node, its first terminal grounded, and its second terminal coupled to the output node.

9. A method for generating a logic signal, characterized in that, The method is applied to logic gate circuits as described in any one of claims 1 to 8; the method includes: The first inverter of the logic gate circuit generates a first inverted signal based on the first input signal provided by the first signal input line and the power signal provided by the power supply, and transmits it to the first signal transmission node of the logic gate circuit. The logic selection circuit of the logic gate circuit generates a first logic signal based on the first input signal provided by the first signal input line, the second input signal provided by the second signal input line, and the first inverted signal provided by the first signal transmission node, and transmits it to the second signal transmission node of the logic gate circuit. The buffer circuit of the logic gate circuit generates a second logic signal based on the first logic signal provided by the second signal transmission node, and drives the output node of the logic gate circuit to output the second logic signal.

10. The method according to claim 9, characterized in that, The logic selection circuit through the logic gate circuit generates a first logic signal based on the first input signal provided by the first signal input line, the second input signal provided by the second signal input line, and the first inverted signal provided by the first signal transmission node, and transmits the signal to the second signal transmission node of the logic gate circuit, including: When the first input signal corresponds to the first potential, the transmission gate of the logic selection circuit controls the conduction of the second signal input line and the second signal transmission node according to the first input signal provided by the first signal input line and the first inverted signal provided by the first signal transmission node, and generates the first logic signal according to the first input signal provided by the first signal input line, the second input signal provided by the second signal input line and the first inverted signal provided by the first signal transmission node, and transmits it to the second signal transmission node; When the first input signal corresponds to the second potential, the second inverter of the logic selection circuit controls the conduction of the second signal input line and the second signal transmission node according to the first input signal provided by the first signal input line and the first inverted signal provided by the first signal transmission node. The first logic signal is generated according to the first input signal provided by the first signal input line, the second input signal provided by the second signal input line and the first inverted signal provided by the first signal transmission node, and is transmitted to the second signal transmission node. The first potential is higher than the second potential.

11. A processor, characterized in that, The processor includes logic gates as described in any one of claims 1 to 8.

12. A chip, characterized in that, The chip includes a processor, which includes logic gates as described in any one of claims 1 to 8.

13. A computer device, characterized in that, The computer device includes a processor, the processor including logic gates as described in any one of claims 1 to 8.

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