A lockout detection circuit and memory

Abstract

The application discloses a lock loss detection circuit and a memory, wherein the lock loss detection circuit is applied to a delay phase-locked loop configured to output a first phase comparison result based on an input clock and a feedback clock, and comprises: a delay module configured to perform delay processing on the input clock and the feedback clock respectively, so as to obtain a delayed input clock and a delayed feedback clock; a phase detection module configured to perform phase comparison on the delayed input clock and the delayed feedback clock, so as to obtain a second phase comparison result; perform phase comparison on the delayed input clock and the delayed feedback clock, so as to obtain a third phase comparison result; and a lock loss detection module configured to determine that the delay phase-locked loop is in a lock loss state when the first phase comparison result of a plurality of continuous clock cycles is consistent, and the second phase comparison result and the third phase comparison result are consistent. The application can accurately identify the lock loss state of the delay phase-locked loop.

Description

Technical Field

[0001] This application relates to the field of phase-locked loops, specifically to a loss-of-lock detection circuit and a memory. Background Technology

[0002] A delay-locked loop (DLL) is used for delay adjustment and phase calibration of clock signals. During high-speed data transfer in memory, clock signals are easily affected by factors such as temperature changes and voltage fluctuations in the operating environment, resulting in delay deviations. Therefore, the DLL can dynamically adjust the phase of the clock signal inside the memory chip to compensate for timing offsets caused by external environmental changes, thereby improving the synchronization accuracy between the clock signal and the data signal and ensuring the stability and reliability of high-speed data transfer.

[0003] However, when the DLL is affected by factors such as changes in the external environment, noise interference, abnormal delay chain adjustment, or loop operating state drift, the following problem may occur: it cannot continuously and stably lock the output clock within the predetermined phase range, causing the output clock to have a phase deviation from the reference clock that exceeds the allowable range. This state is also known as DLL lockout. Once DLL lockout occurs, the timing correspondence between the clock signal and the data signal will be disrupted, making it difficult to guarantee the correctness of data transmission and causing a large number of data errors. Therefore, it is necessary to accurately identify DLL lockout. Summary of the Invention

[0004] This application provides a loss-of-lock detection circuit and memory to accurately identify DLL loss of lock.

[0005] In a first aspect, this application provides a loss-of-lock detection circuit applied to a delay phase-locked loop (PLL), wherein the PLL is configured to output a first phase comparison result based on an input clock and a feedback clock, including: The delay module is configured to delay the input clock and the feedback clock respectively, thereby obtaining the delayed input clock and the delayed feedback clock. The phase detection module is configured as follows: The phases of the delayed input clock and the feedback clock are compared to obtain a second phase comparison result. A phase comparison is performed between the delayed input clock and the delayed feedback clock to obtain a third phase comparison result; The lockout detection module is configured to determine that the delay phase-locked loop is locked if the first phase comparison results are consistent for multiple consecutive clock cycles, and the second and third phase comparison results are consistent.

[0006] In some embodiments of this application, the unlock detection module is further configured to: The inconsistency in the first phase comparison results across multiple consecutive clock cycles confirms that the delay phase-locked loop has not lost lock. If the first phase comparison results are consistent across multiple consecutive clock cycles, and the second and third phase comparison results are inconsistent, it is determined that the delay phase-locked loop has not lost lock.

[0007] In some embodiments of this application, the unlock detection module includes: The logic unit is configured to compare the second phase comparison result and the third phase comparison result to obtain a comparison result; The counting unit is configured to count the comparison results that represent the same second phase comparison result and the third phase comparison result, and output a lockout flag if the count result exceeds the number threshold within multiple consecutive clock cycles. Delayed phase-locked loops include: The control unit, one end of which is connected to the counting unit, is configured to determine that the delay phase-locked loop is out of lock when a lockout flag is received and the first phase comparison results for multiple consecutive clock cycles are consistent.

[0008] In some embodiments of this application, the delay module includes: The first delay unit is configured to delay the input clock according to the first delay time to obtain the delayed input clock. The second delay unit is configured to delay the feedback clock according to the second delay time to obtain the delayed feedback clock. The second delay time is twice the first delay time.

[0009] In some embodiments of this application, the second phase detection module includes: The second phase detection unit is configured to perform a phase comparison between the delayed input clock and the feedback clock to obtain a second phase comparison result. The third phase detection unit is configured to perform a phase comparison between the delayed input clock and the delayed feedback clock to obtain a third phase comparison result; The second phase detection unit and the third phase detection unit are phase detectors or D flip-flops (DFFs).

[0010] In some embodiments of this application, the first delay time is determined based on the maximum timing deviation in the memory protocol.

[0011] In some embodiments of this application, the number of times threshold is determined based on the maximum timing deviation, the first delay time, and the single-cycle phase adjustment amount of the delay phase-locked loop.

[0012] Secondly, this application also provides a memory, comprising: Delayed phase-locked loop; and The loss-of-lock detection circuit provided in the first aspect is configured to perform loss-of-lock detection on the delayed phase-locked loop.

[0013] In some embodiments of this application, the delay phase-locked loop includes a transmission unit, a delay line, a first phase detection unit, and a control unit; One end of the transmission unit is connected to one end of the delay line, and the other end is connected to one end of the loss-of-lock detection circuit and one end of the first phase detection unit, respectively. The other end of the delay line is connected to one end of the first phase detection unit and one end of the unlock detection circuit, respectively. One end of the control unit is connected to the other end of the first phase detection unit and the other end of the unlock detection circuit, and the other end of the control unit is connected to one end of the delay line.

[0014] In some embodiments of this application, the first phase detection unit is configured to align the rising edges of the feedback clock and the input clock.

[0015] Through one or more embodiments of the above embodiments in this application, at least the following technical effects can be achieved: In the unlock detection circuit provided in this application, the input clock and feedback clock are delayed by a delay module to obtain a delayed input clock and a delayed feedback clock. A phase detection module compares the phases of the delayed input clock and feedback clock, and the delayed input clock and delayed feedback clock, to obtain a second phase comparison result and a third phase comparison result. Based on the consistency between the second and third phase comparison results, it can be determined whether the phase difference between the input clock and feedback clock exceeds a preset phase difference threshold. Furthermore, the unlock detection module determines that the delay phase-locked loop has lost lock when the first phase comparison results for multiple consecutive clock cycles are consistent, and the corresponding second and third phase comparison results are also consistent. Therefore, by utilizing a delay comparison mechanism, the relationship between the phase difference and the phase difference threshold between the DLL input clock and the feedback clock is realized. This eliminates the need for high-precision analog comparators, low-pass filters, and other analog detection circuits, enabling the determination of whether the phase difference exceeds the limit. By introducing consistency judgment across multiple consecutive clock cycles, the possibility of misjudgment caused by factors such as instantaneous jitter and noise interference is effectively reduced, thus balancing the response speed and judgment accuracy of lock-out detection. The lock-out detection circuit provided in this application embodiment can accurately identify the DLL lock-out state. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a phase difference-based unlock detection circuit; Figure 2 This is a schematic diagram of a lock-out detection circuit based on sampling counting; Figure 3 This is a schematic diagram of the unlock detection circuit provided in the embodiment of this application; Figure 4 This is a timing diagram of the delayed phase-locked loop in the unlocked state provided in the embodiments of this application; Figure 5 This is one of the timing diagrams of the delayed phase-locked loop in the unlocked state provided in the embodiments of this application; Figure 6 This is the second timing diagram of the delayed phase-locked loop in the unlocked state provided in the embodiments of this application.

[0018] Explanation of reference numerals in the attached figures: 10. Delayed phase-locked loop; 101. Transmission unit; 102. Delay line; 103. First phase detection unit; 104. Control unit; 20. Unlock detection circuit; 21. Delay module; 211. First delay unit; 212. Second delay unit; 22. Phase detection module; 221. Second phase detection unit; 222. Third phase detection unit; 23. Unlock detection module; 231. Logic unit; 232. Counting unit. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0021] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0022] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not preclude applicability to or configuration to devices performing additional tasks or steps. Furthermore, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more conditions or values ​​may in practice be based on additional conditions or values ​​beyond those conditions.

[0023] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0024] In memory, to ensure correct data transmission, a lock-out detection circuit is typically installed to monitor the DLL (Memory Module) for lock-out in real time. If a DLL lock-out is detected, an interrupt signal is sent to the memory controller to inform it of the risk of lock-out. The controller then resets and recalibrates the DLL based on this interrupt signal to ensure data transmission validity. If the DLL fails to report the lock-out status in a timely manner, it may lead to data sampling errors or even system timing failures. Conversely, if the DLL misjudges a lock-out state while it is actually still locked, it may perform unnecessary reset operations, resulting in decreased memory module performance. Therefore, accurate detection of the DLL lock-out status is crucial for preventing data errors and improving the stability of the storage system.

[0025] Currently, lock loss detection includes lock loss detection based on phase difference and lock loss detection based on sample count.

[0026] Among them, the phase difference-based unlock detection circuit is as follows: Figure 1As shown, it includes a phase-frequency detector (PFD), two low-pass filters (LPF), and two comparators (COMP). The two low-pass filters are LPF-1 and LPF-2, and the two comparators are COMP-1 and COMP-2.

[0027] The phase and frequency detector (PFD) compares the phase of the input clock CK_IN and the feedback clock CK_FB. When the input clock CK_IN leads the feedback clock CK_FB, the PFD outputs PD_OUT_P; when the feedback clock CK_FB leads the input clock CK_IN, the PFD outputs PD_OUT_N.

[0028] By performing a low-pass filter on PD_OUT_P using LPF-1, a voltage signal V_PD_P representing the positive phase deviation is obtained; by performing a low-pass filter on PD_OUT_N using LPF-2, a voltage signal V_PD_N representing the reverse phase deviation is obtained. V_PD_P and V_PD_N respectively reflect the degree of phase deviation in two opposite directions.

[0029] COMP-1 compares V_PD_P with the threshold V_ref. When V_PD_P exceeds the threshold V_ref, it outputs the unlock indication signal LOSE_LOCK_P. COMP-2 compares V_PD_N with the threshold V_ref. When V_PD_N exceeds the threshold V_ref, it outputs the unlock indication signal LOSE_LOCK_N.

[0030] A loss of lock in the DLL is determined when either LOSE_LOCK_P or LOSE_LOCK_N is set to an active level. Specifically, an active LOSE_LOCK_P indicates that the phase difference in one direction exceeds the threshold V_ref, while an active LOSE_LOCK_N indicates that the phase difference in the opposite direction exceeds the threshold V_ref. While phase difference-based lock-out detection can intuitively reflect the phase alignment between clocks, it requires high-precision analog circuits such as low-pass filters and analog voltage comparators. This results in complex circuit implementation, large area and power consumption, and is highly sensitive to process variations, power supply disturbances, and noise interference, affecting the stability and reliability of the lock-out detection results.

[0031] Loss detection circuit based on sampling counting, such as Figure 2 As shown, it includes a phase detector (PD) and two counters, namely counter-1 and counter-2.

[0032] The phase detector (PD) compares the phase of the input clock CK_IN and the feedback clock CK_FB. When the input clock CK_IN leads the feedback clock CK_FB, the phase detector (PD) outputs the signal PD_OUT_P; when the feedback clock CK_FB leads the input clock CK_IN, the phase detector (PD) outputs the signal PD_OUT_N. PD_OUT_P and PD_OUT_N are used to characterize the direction of the current phase deviation.

[0033] Counter-1 periodically samples and counts PD_OUT_P. As long as PD_OUT_P remains valid for multiple consecutive clock cycles, the count value of counter-1 continuously increases. When the count value reaches a preset counting threshold N_ref, counter-1 outputs a lock-out indication signal LOSE_LOCK_P. Similarly, counter-2 periodically samples and counts PD_OUT_N. When PD_OUT_N remains valid for multiple consecutive clock cycles, and the count value of counter-2 reaches a preset counting threshold N_ref, counter-2 outputs a lock-out indication signal LOSE_LOCK_N.

[0034] When either LOSE_LOCK_P or LOSE_LOCK_N exceeds a preset counting threshold, the DLL is considered to have lost lock. Loss detection based on sample counting uses a digital counting circuit, which has advantages such as relatively simple structure, low power consumption, and strong noise immunity. However, this method indirectly determines loss of lock by statistically analyzing the duration or number of cycles of phase deviation, and cannot directly obtain the accurate phase difference between the input clock and the feedback clock. Therefore, in some cases, even if the phase deviation has not actually exceeded the allowable range, as long as the offset in the same direction continues for a set number of times, it may be judged as a loss of lock, thus easily leading to false positives.

[0035] To address the aforementioned problems, this application provides a loss-of-lock detection circuit that simplifies the circuit while enabling fast and accurate loss-of-lock detection. The loss-of-lock detection circuit provided in this application will be described below with reference to the accompanying drawings.

[0036] like Figure 3 As shown, this application embodiment provides a loss-of-lock detection circuit 20, which is used to detect loss of lock in a delayed phase-locked loop 10. The loss-of-lock detection circuit 20 includes a delay module 21, a phase detection module 22, and a loss-of-lock detection module 23.

[0037] Among them, one end of the delay module 21 is connected to one end of the delay phase-locked loop 10, the other end of the delay module 21 is connected to one end of the phase detection module 22, one end of the phase detection module 22 is also connected to one end of the delay phase-locked loop 10, the other end of the phase detection module 22 is connected to one end of the lockout detection module 23, and the other end of the lockout detection module 23 is connected to the other end of the delay phase-locked loop 10.

[0038] The delay-locked loop 10 is configured to output a first phase comparison result PD_OUT based on the input clock CK_IN and the feedback clock CK_FB. It can be understood that the first phase comparison result PD_OUT is used to characterize the phase relationship between the input clock CK_IN and the feedback clock CK_FB. When the input clock CK_IN leads the feedback clock CK_FB, the first phase comparison result PD_OUT is a first logic value; when the input clock CK_IN lags the feedback clock CK_FB, the first phase comparison result PD_OUT is a second logic value. The first and second logic values ​​can be 1 and 0, respectively.

[0039] The delay module 21 is configured to delay the input clock CK_IN and the feedback clock CK_FB respectively, and obtain the delayed input clock CK_IN_DLY and the delayed feedback clock CK_FB_DLY accordingly.

[0040] The phase detection module 22 is configured to perform a phase comparison between the delayed input clock CK_IN_DLY and the feedback clock CK_FB to obtain a second phase comparison result; and to perform a phase comparison between the delayed input clock CK_IN_DLY and the delayed feedback clock CK_FB_DLY to obtain a third phase comparison result.

[0041] Understandably, the second phase comparison result is used to characterize the phase relationship between the delayed input clock CK_IN_DLY and the feedback clock CK_FB. When the delayed input clock CK_IN_DLY leads the feedback clock CK_FB, the second phase comparison result is the first logic value; when the delayed input clock CK_IN_DLY lags the feedback clock CK_FB, the second phase comparison result is the second logic value. Similarly, the third phase comparison result is used to characterize the phase relationship between the delayed input clock CK_IN_DLY and the delayed feedback clock CK_FB_DLY. When the delayed input clock CK_IN_DLY leads the delayed feedback clock CK_FB_DLY, the third phase comparison result is the first logic value; when the delayed input clock CK_IN_DLY lags the delayed feedback clock CK_FB_DLY, the third phase comparison result is the second logic value.

[0042] Since the delayed input clock CK_IN_DLY relative to the input clock CK_IN and the delayed feedback clock CK_FB_DLY relative to the feedback clock CK_FB respectively introduce preset delays, the third phase comparison result essentially characterizes the phase offset direction between the input clock CK_IN and the feedback clock CK_FB. The second phase comparison result, on the other hand, reflects whether the phase order between the input clock and the feedback clock remains unchanged after only changing the input clock CK_IN. Therefore, if the second and third phase comparison results are consistent, it indicates that even with the introduction of a delay offset corresponding to the phase difference threshold, the phase order between the input clock CK_IN and the feedback clock CK_FB has not changed, suggesting that the absolute value of the phase difference between the input clock CK_IN and the feedback clock CK_FB is greater than the phase difference threshold corresponding to the preset delay. Conversely, if the second and third phase comparison results are inconsistent, it indicates that the phase order between the two clocks has been reversed after introducing the preset delay, suggesting that the phase difference between the input clock CK_IN and the feedback clock CK_FB has not yet exceeded the phase difference threshold.

[0043] The phase difference threshold refers to the maximum allowed phase error between the input clock CK_IN and the feedback clock CK_FB when the delay phase-locked loop 10 is in a locked state. Within this maximum phase error range, even if there is a small phase deviation between the input clock CK_IN and the feedback clock CK_FB, the DLL can still maintain normal locking and ensure the correctness of data sampling.

[0044] The lockout detection module 23 is configured to determine that the delay phase-locked loop 10 is locked if the first phase comparison results of multiple consecutive clock cycles are consistent, and the second phase comparison results and the third phase comparison results are consistent.

[0045] It is understandable that the consistent first phase comparison result across multiple consecutive clock cycles indicates that the first phase comparison result PD_OUT maintains the same logical state within a preset number of consecutive clock cycles. That is, within these consecutive clock cycles, the input clock CK_IN consistently leads or lags the feedback clock CK_FB in the same direction, and the phase offset direction does not reverse, thus determining that the delay phase-locked loop 10 is in an unlocked state. Conversely, when the delay phase-locked loop 10 is in a normally locked state, the phase difference between the input clock CK_IN and the feedback clock CK_FB should be controlled within a phase difference threshold range and fluctuate slightly around the threshold. Therefore, the first phase comparison result typically does not maintain the same logical state across multiple consecutive clock cycles.

[0046] Meanwhile, the fact that both the second phase comparison result and the third phase comparison result are consistent means that within the corresponding clock cycle, the second phase comparison result and the third phase comparison result are the same.

[0047] It should be noted that within a single clock cycle, the consistency between the second and third phase comparison results may only reflect a large instantaneous phase deviation, or it may be affected by transient factors such as jitter and noise. To suppress false judgments caused by instantaneous jitter or noise and improve the accuracy and reliability of lockout detection, it is necessary to comprehensively consider the first phase comparison results, the corresponding second phase comparison results, and the third phase comparison results over multiple consecutive clock cycles for lockout judgment. When the first phase comparison results over multiple consecutive clock cycles are consistent, and the corresponding second and third phase comparison results over these clock cycles are also consistent, it indicates that there is a continuous phase offset in the same direction between the input clock CK_IN and the feedback clock CK_FB. This indicates that the delay phase-locked loop 10 can no longer maintain the phase difference between the two within the normal locking range, thus determining that the delay phase-locked loop 10 has lost lock.

[0048] Indicatively, such as Figure 5 As shown, the delayed input clock CK_IN_DLY is located on the same side as the feedback clock CK_FB and the delayed feedback clock CK_FB_DLY, and is ahead of both the feedback clock CK_FB and the delayed feedback clock CK_FB_DLY. Correspondingly, the second phase comparison result between the delayed input clock CK_IN_DLY and the feedback clock CK_FB is always 1. Simultaneously, since the delayed input clock CK_IN_DLY is also ahead of the delayed feedback clock CK_FB_DLY, the third phase comparison result between the delayed input clock CK_IN_DLY and the delayed feedback clock CK_FB_DLY is always 1. Because the second and third phase comparison results are always consistent, it indicates that the phase difference between the input clock CK_IN and the feedback clock CK_FB has exceeded the preset phase difference threshold. Therefore, it is determined that the current delay phase-locked loop (DLL) is in an unlocked state.

[0049] For example, such as Figure 6As shown, the delayed input clock CK_IN_DLY is located on the same side as the feedback clock CK_FB and the delayed feedback clock CK_FB_DLY, and the delayed input clock CK_IN_DLY lags behind the feedback clock CK_FB. Therefore, the second phase comparison result between the delayed input clock CK_IN_DLY and the feedback clock CK_FB is always 0. Simultaneously, since the delayed input clock CK_IN_DLY also lags behind the delayed feedback clock CK_FB_DLY, the third phase comparison result between the delayed input clock CK_IN_DLY and the delayed feedback clock CK_FB_DLY is always 0. Because the second and third phase comparison results are always consistent, it indicates that the phase difference between the input clock CK_IN and the feedback clock CK_FB has exceeded the preset phase difference threshold. Therefore, it can be determined that the current delay phase-locked loop (DLL) is in an unlocked state.

[0050] The unlock detection circuit 20 provided in this embodiment delays the input clock and feedback clock using a delay module 21 to obtain a delayed input clock and a delayed feedback clock. A phase detection module 22 compares the phases of the delayed input clock and feedback clock, and the delayed input clock and delayed feedback clock, to obtain a second phase comparison result and a third phase comparison result. Based on the consistency between the second and third phase comparison results, it can determine whether the phase difference between the input clock and feedback clock exceeds a preset phase difference threshold. Furthermore, the unlock detection module 23 determines that the delay phase-locked loop 10 is unlocked if the first phase comparison results for multiple consecutive clock cycles are consistent, and the corresponding second and third phase comparison results are also consistent. Therefore, by utilizing a delay comparison mechanism, the relationship between the phase difference and the phase difference threshold between the DLL input clock and the feedback clock is realized. This eliminates the need for high-precision analog comparators, low-pass filters, and other analog detection circuits, enabling the determination of whether the phase difference exceeds the limit. By introducing consistency judgment across multiple consecutive clock cycles, the possibility of misjudgment caused by factors such as instantaneous jitter and noise interference is effectively reduced, thus balancing the response speed and judgment accuracy of lock-out detection. The lock-out detection circuit 20 provided in this embodiment can accurately identify the DLL lock-out state.

[0051] In some embodiments of this application, the lock-out detection module 23 is further configured to determine that the delay phase-locked loop 10 has not lost lock if the first phase comparison result is inconsistent in multiple consecutive clock cycles.

[0052] Understandably, the first phase comparison result shows changes between different logic states over multiple consecutive clock cycles. This indicates that the phase offset direction between the input clock CK_IN and the feedback clock CK_FB changes over these multiple clock cycles and does not continuously shift in the same direction. In other words, the delay-locked loop 10 can still dynamically adjust the phase relationship around the lock point, keeping the phase error within the normal fluctuation range, without a continuously accumulating and expanding same-direction phase deviation. Therefore, it can be considered that the delay-locked loop 10 is still in a locked state and has not lost lock.

[0053] The lockout detection module 23 is also configured to determine that the delay phase-locked loop 10 has not lost lock if the first phase comparison results for multiple consecutive clock cycles are consistent and the second and third phase comparison results are inconsistent.

[0054] Understandably, although the first phase comparison result consistently indicates a phase shift in the same direction between the input clock CK_IN and the feedback clock CK_FB over multiple consecutive clock cycles, the inconsistency between the second and third phase comparison results suggests that the phase difference between the input clock CK_IN and the feedback clock CK_FB has not yet exceeded the preset phase difference threshold. In other words, although the DLL exhibits a phase error in the same direction for multiple consecutive cycles, this phase error remains within the normal locking adjustment range of the DLL, possibly indicating that the DLL is performing normal phase tracking or minor correction, and has not reached the level of unlocking. Therefore, it can be determined that the delay phase-locked loop 10 has not lost lock.

[0055] Indicatively, such as Figure 4 As shown, the delayed input clock CK_IN_DLY is located between the feedback clock CK_FB and the delayed feedback clock CK_FB_DLY. The second phase comparison result between the delayed input clock CK_IN_DLY and the feedback clock CK_FB is always 0. The delayed input clock CK_IN_DLY is also located between the feedback clock CK_FB and the delayed feedback clock CK_FB_DLY, and is ahead of the delayed feedback clock CK_FB_DLY. The corresponding third phase comparison result is always 1. Since the second and third phase comparison results are inconsistent, it indicates that the phase difference between the input clock CK_IN and the feedback clock CK_FB does not exceed the preset phase difference threshold. Therefore, it is determined that the current delay phase-locked loop (DLL) is in a normal locked state and no lockout has occurred.

[0056] In some examples, when the power supply voltage VDD changes from 1.2V to 1.14V and then back to 1.2V, the DLL will continuously adjust in the same direction for multiple steps to compensate for the delay caused by the voltage change. If the lockout judgment is based solely on the number of consecutive adjustments in the same direction, then during the voltage disturbance described above, although the DLL will quickly output lockout feedback, the maximum deviation of the parameter tDQSCK during the entire process is only -143ps, which does not exceed the allowable range specified by the protocol. In other words, although the DLL makes multiple consecutive adjustments in the same direction, its phase deviation is actually still within the allowable range of the protocol. However, because the number of consecutive adjustments in the same direction has exceeded the threshold, it will determine that the DLL has lost lock, resulting in a false judgment.

[0057] However, in this embodiment, when the power supply voltage VDD also changes from 1.2V to 1.14V to 1.2V, the DLL will also adjust in the same direction for multiple steps to compensate for the delay caused by the voltage change. However, this application does not rely solely on continuous adjustment in the same direction for judgment, but further combines this with whether the phase difference between the input clock and the feedback clock continuously exceeds a set phase difference threshold for comprehensive judgment. Therefore, although there are multiple consecutive adjustments in this process, the number of times the phase difference threshold is exceeded consecutively determines that the DLL has not lost lock. Experiments show that during the entire voltage disturbance process, the maximum deviation of tDQSCK is -119ps, which is also within the range specified in the protocol, and effectively avoids the problem of misjudging normal adjustment processes as DLL lockout in the prior art. Therefore, this embodiment can more accurately distinguish between normal dynamic compensation processes and actual lockout states in voltage fluctuation scenarios, thereby improving the accuracy and reliability of DLL lockout detection.

[0058] In some embodiments of this application, such as Figure 3 As shown, the unlock detection module 23 includes a logic unit 231 and a counting unit 232. One end of the logic unit 231 is connected to the other end of the phase detection module 22, the other end of the logic unit 231 is connected to one end of the counting unit 232, and the other end of the counting unit 232 is connected to the other end of the phase-locked loop.

[0059] The logic unit 231 is configured to compare the second phase comparison result and the third phase comparison result to obtain a comparison result.

[0060] It is understandable that when the second phase comparison result and the third phase comparison result are the same, the comparison result is characterized as the first comparison state; when the second phase comparison result and the third phase comparison result are different, the comparison result is characterized as the second comparison state. The first comparison state is used to indicate that the phase difference between the input clock and the feedback clock exceeds a preset phase difference threshold, and the second comparison state is used to indicate that the phase difference between the input clock and the feedback clock does not exceed the phase difference threshold. In some examples, logic unit 231 is an XOR gate; in other examples, logic unit 231 can be a combinational logic circuit built using basic logic gates such as AND gates, OR gates, and NOT gates to achieve the equivalent comparison function of the second phase comparison result and the third phase comparison result.

[0061] The counting unit 232 is configured to count the comparison results that represent the same second phase comparison result and the third phase comparison result, and output a lockout flag if the count result exceeds the number threshold within multiple consecutive clock cycles.

[0062] In other words, the counting unit 232 counts when the comparison result is characterized as the first comparison state, and the count result is the number of times the second phase comparison result and the third phase comparison result are the same. When the comparison result is characterized as the second comparison state, it means that the second phase comparison result and the third phase comparison result are different in the current clock cycle. At this time, the counting unit 232 does not accumulate the count result, but performs a clearing, resetting, or recounting process on the current count value to ensure that the count result can reflect the continuous situation that the second phase comparison result and the third phase comparison result remain the same for multiple consecutive clock cycles. Furthermore, when the count result in multiple consecutive clock cycles exceeds a preset number of times, the counting unit 232 outputs an unlock flag, indicating that the state in which the phase difference between the input clock and the feedback clock exceeds the preset phase difference threshold has continued for more than a preset number of times, thereby avoiding misjudgment caused by instantaneous jitter or short-term noise.

[0063] Accordingly, the delay phase-locked loop 10 includes a control unit 104, one end of which is connected to the other end of the counting unit 232.

[0064] The control unit 104 is configured to determine that the delay phase-locked loop 10 is out of lock when a lockout flag is received and the first phase comparison results for multiple consecutive clock cycles are consistent.

[0065] In some embodiments of this application, the delay module 21 includes a first delay unit 211 and a second delay unit 212. One end of the first delay unit 211 and the second delay unit 212 are both connected to one end of the delay phase-locked loop 10, and the other end of the first delay unit 211 and the second delay unit 212 are both connected to one end of the phase detection module 22.

[0066] The first delay unit 211 is configured to delay the input clock according to the first delay time to obtain the delayed input clock.

[0067] The second delay unit 212 is configured to delay the feedback clock according to the second delay time to obtain the delayed feedback clock.

[0068] The second delay time is twice the first delay time.

[0069] In some examples, the first delay time is set to T, and the second delay time is set to 2T. When the input clock CK_IN and the feedback clock CK_FB are locked and their phase difference is small, after the first delay time T, the input clock CK_IN_DLY is located between the feedback clock CK_FB and the feedback clock CK_FB_DLY after the second delay time 2T. That is, after the delay, the input clock CK_IN_DLY is delayed by T relative to the feedback clock CK_FB and advanced by T relative to the feedback clock CK_FB_DLY, thus occupying a symmetrical position between them. Based on this symmetrical positional relationship, when the phase difference between the input clock CK_IN and the feedback clock CK_FB does not exceed a preset threshold, the second phase comparison result and the third phase comparison result are inconsistent. However, when the phase difference between the input clock CK_IN and the feedback clock CK_FB exceeds the preset threshold, CK_IN_DLY will deviate from the symmetrical interval and be located on the same side of CK_FB and CK_FB_DLY, at which point the second phase comparison result and the third phase comparison result are consistent. Therefore, setting the second delay time to twice the first delay time can ensure that the consistency between the second phase comparison result and the third phase comparison result accurately reflects whether the phase difference between the input clock and the feedback clock exceeds the preset threshold.

[0070] If the second delay time is not twice the first delay time, the input clock CK_IN_DLY after the delay will no longer be located at the symmetrical position between the feedback clock CK_FB and the delayed feedback clock CK_FB_DLY in the locked state. This will cause the second phase comparison result to be inconsistent with the third phase comparison result, and will not accurately correspond to whether the phase difference between the input clock and the feedback clock exceeds the preset threshold. This may easily cause the judgment threshold to shift or the detection to be asymmetrical in the two directions.

[0071] In some embodiments of this application, the second phase detection module 22 includes a second phase detection unit 221 and a third phase detection unit 222. One end of the second phase detection unit 221 is connected to the other end of the first delay unit 211, and one end of the third phase detection unit 222 is connected to the other end of the second delay unit 212.

[0072] The second phase detection unit 221 is configured to perform a phase comparison between the delayed input clock and the feedback clock to obtain a second phase comparison result.

[0073] The third phase detection unit 222 is configured to perform a phase comparison between the delayed input clock and the delayed feedback clock to obtain a third phase comparison result.

[0074] It is understandable that the phase order of the input clock after the delay relative to the feedback clock can be obtained through the first delay unit 211 and the second phase detection unit 221; and the phase order of the input clock after the delay relative to the feedback clock after the delay can be obtained through the second delay unit 212 and the third phase detection unit 222.

[0075] Furthermore, since the phase relationship between the input clock and the feedback clock includes both cases where the input clock leads the feedback clock and cases where the input clock lags the feedback clock, the lockout detection of the delay phase-locked loop 10 requires determining whether the phase deviation in one direction exceeds a preset threshold, and also whether the phase deviation in the opposite direction exceeds a preset threshold. That is, detection in only one direction cannot cover all lockout scenarios. Based on this, in this embodiment, two sets of delay units and phase detection units are set, corresponding to the detection branches in the phase-leading and phase-lag directions respectively, to determine whether the phase deviation of the input clock relative to the feedback clock in the two opposite directions exceeds the set phase difference threshold. In this case, as long as the phase deviation in either direction exceeds the set threshold and the first phase comparison results of the corresponding consecutive periods are all consistent, a lockout signal can be fed back. Thus, it can simultaneously cover both phase anomalies of input clock leading and input clock lagging, thereby improving the completeness and reliability of lockout detection and avoiding the omission of lockout states due to detection in only one direction.

[0076] In some examples, the second phase detection unit 221 and the third phase detection unit 222 are phase detectors or D flip-flops (DFFs).

[0077] In some embodiments of this application, the first delay time is determined based on the maximum timing deviation in the memory protocol. It is understood that the first delay time is the aforementioned phase difference threshold, which characterizes the boundary by which the unlock detection circuit 20 determines the phase difference between the input clock and the feedback clock.

[0078] To illustrate, taking the device parameters corresponding to the DDR (Double Data Rate) 4 specification as an example, at a rate of 3.2Gbps, the tDQSCK boundary of DLL enabled mode can reach ±160ps (i.e., the maximum timing deviation). Based on this, the first delay time can be set to 80ps or 100ps, for example, so that the first delay time is less than the maximum timing deviation allowed by the protocol.

[0079] In some embodiments of this application, the number threshold is determined based on the maximum timing deviation, the first delay time, and the single-cycle phase adjustment amount of the delay phase-locked loop 10.

[0080] Schematic, let the maximum timing deviation be Δmax, the first delay time be T, and the single-cycle phase adjustment of the delay phase-locked loop 10 be Δstep. Then, the number of iterations threshold N_ct can be determined based on the relationship between the remaining phase margin and the single-cycle phase adjustment, for example, it can be expressed as: N_ct≈(Δmax) T) / Δstep. The number of times threshold can be set by rounding according to design requirements, such as rounding down, rounding up, or further modified in combination with protection margin.

[0081] Taking the parameter boundaries of a DDR4-3200 device in DLL enabled mode as an example, the relevant device datasheet gives a tDQSCK range of -160ps to +160ps. Assuming that each phase adjustment of the delay-locked loop 10 can adjust the phase by 10ps, then when the maximum timing deviation is 160ps and T (the first delay time) is set to 80ps, the remaining timing margin is 80ps. At this point, approximately 8 consecutive adjustments in the same direction are needed, i.e., (160... 80) / 10=8, so it can be determined that delay-locked loop 10 is out of lock; when delay is set to 100ps, the remaining timing margin is 60ps. At this time, it is necessary to adjust in the same direction for about 6 steps, that is, (160) / 10=8. 100) / 10=6, so it can be determined that the delayed phase-locked loop 10 is out of lock.

[0082] Therefore, the larger the first delay time is set, the closer the warning threshold is to the protocol upper limit, and the fewer consecutive unidirectional adjustments are required to reach the maximum timing deviation; conversely, the smaller the first delay time is set, the larger the corresponding number of adjustments can be.

[0083] This application embodiment also provides a memory including a delay phase-locked loop 10 and a loss-of-lock detection circuit 20. The loss-of-lock detection circuit 20 is configured to detect loss of lock on the delay phase-locked loop 10.

[0084] In some embodiments of this application, such as Figure 3As shown, the delay phase-locked loop 10 includes a transmission unit 101, a delay line 102, a first phase detection unit 103, and a control unit 104.

[0085] One end of the transmission unit 101 is connected to one end of the delay line 102, and the other end is connected to one end of the unlock detection circuit 20 and one end of the first phase detection unit 103, respectively; the other end of the delay line 102 is connected to one end of the first phase detection unit 103 and one end of the unlock detection circuit 20, respectively; one end of the control unit 104 is connected to the other end of the first phase detection unit 103 and the other end of the unlock detection circuit 20, respectively, and the other end of the control unit 104 is connected to one end of the delay line 102.

[0086] Schematic, the transmission unit 101 is located between the input clock and the delay line 102, and is used to receive the input clock and transmit the input clock to the delay line 102. The input terminal of the delay line 102 is connected to the transmission unit 101, and the output terminal of the delay line 102 outputs a feedback clock. The output terminal of the delay line 102 is also connected to the first phase detection unit 103, and is used to provide a feedback clock to the first phase detection unit 103. The first phase detection unit 103 is connected to the control unit 104, and is used to output the first phase comparison result to the control unit 104. The control unit 104 is connected to the delay line 102, and is used to adjust the delay amount of the delay line 102 according to the first phase comparison result output by the first phase detection unit 103 and the unlocking flag output by the unlocking detection circuit 20.

[0087] The transmission unit 101 is used to receive the input clock and perform transmission, distribution and other processing on the input clock, and transmit the input clock to the delay line 102, the first phase detection unit 103 and the unlock detection circuit 20 respectively.

[0088] The delay line 102 is used to adjust the delay of the input clock to output a feedback clock. Specifically, under the control of the control unit 104, the delay amount of the delay line 102 to the input clock can be changed, thereby adjusting the phase relationship between the feedback clock and the input clock so that the feedback clock gradually approaches and aligns with the input clock. At the same time, the feedback clock output by the delay line 102 can also be provided to the first phase detection unit 103 and the unlock detection circuit 20 for subsequent phase comparison and unlock detection.

[0089] The first phase detection unit 103 is used to compare the phase of the input clock output by the transmission unit 101 and the feedback clock output by the delay line 102 to determine the phase order between the input clock and the feedback clock, and output the first phase comparison result. It can be understood that the first phase detection unit 103 determines whether the feedback clock leads, lags, or is aligned with the input clock by detecting the edge relationship between the input clock and the feedback clock, thereby providing a basis for the control unit 104 to adjust the delay line 102.

[0090] The control unit 104 controls the delay amount of the delay line 102 according to the first phase comparison result output by the first phase detection unit 103, so that the feedback clock and the input clock gradually reach a locked state. Furthermore, the control unit 104 can also perform operations such as resetting and recalibrating the delay line 102 according to the first phase comparison result and the unlocking flag output by the unlocking detection circuit 20, so that the delay phase-locked loop 10 returns to the normal locked state.

[0091] In some embodiments of this application, the first phase detection unit 103 is configured to align the rising edges of the feedback clock and the input clock.

[0092] Understandably, the rising edges of the feedback clock and the input clock are aligned by the first phase detection unit 103, thus serving as a reference before the delay phase-locked loop 10 enters normal operation. During subsequent operation, if the phase difference between the feedback clock and the input clock continues to increase, and the DLL cannot promptly pull them back to the normal locking range through closed-loop adjustment, it indicates that the DLL's adjustment capability is insufficient to compensate for the phase shift caused by changes in the external environment. In this case, the unlock detection process provided in this embodiment can quickly and accurately output an unlock signal based on the phase comparison results over multiple consecutive clock cycles, helping the controller to promptly anticipate the DLL's unlock risk and ensuring the effectiveness and reliability of subsequent data transmission.

[0093] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0094] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of various embodiments or some parts of embodiments.

[0095] The above provides a detailed description of a lock-out detection circuit and memory provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A loss-of-lock detection circuit, characterized in that, Applied to a delay-locked loop, the delay-locked loop is configured to output a first phase comparison result based on an input clock and a feedback clock, including: The delay module is configured to delay the input clock and the feedback clock respectively, thereby obtaining the delayed input clock and the delayed feedback clock. The phase detection module is configured as follows: A phase comparison is performed between the delayed input clock and the feedback clock to obtain a second phase comparison result; A phase comparison is performed on the delayed input clock and the delayed feedback clock to obtain a third phase comparison result; The lockout detection module is configured to determine that the delay phase-locked loop is locked if the first phase comparison results are consistent for multiple consecutive clock cycles, and the second phase comparison results and the third phase comparison results are consistent.

2. The unlock detection circuit according to claim 1, characterized in that, The unlock detection module is also configured to: If the first phase comparison result is inconsistent over multiple consecutive clock cycles, it is determined that the delay phase-locked loop has not lost lock. If the first phase comparison results are consistent for multiple consecutive clock cycles, and the second phase comparison results and the third phase comparison results are inconsistent, it is determined that the delay phase-locked loop has not lost lock.

3. The unlock detection circuit according to claim 1, characterized in that, The unlock detection module includes: A logic unit is configured to compare the second phase comparison result and the third phase comparison result to obtain a comparison result; The counting unit is configured to count the comparison results that represent the same second phase comparison result and the third phase comparison result, and to output a lockout flag if the count result exceeds a threshold number of times within multiple consecutive clock cycles. The delay phase-locked loop includes: A control unit, one end of which is connected to the counting unit, is configured to determine that the delay phase-locked loop is out of lock when the unlock flag is received and the first phase comparison results for multiple consecutive clock cycles are consistent.

4. The unlock detection circuit according to claim 3, characterized in that, The delay module includes: The first delay unit is configured to delay the input clock according to a first delay time to obtain the delayed input clock. The second delay unit is configured to delay the feedback clock according to the second delay time to obtain the delayed feedback clock. The second delay time is twice the first delay time.

5. The unlock detection circuit according to any one of claims 1 to 4, characterized in that, The second phase detection module includes: The second phase detection unit is configured to perform a phase comparison between the delayed input clock and the feedback clock to obtain the second phase comparison result. The third phase detection unit is configured to perform a phase comparison between the delayed input clock and the delayed feedback clock to obtain the third phase comparison result; The second phase detection unit and the third phase detection unit are phase detectors or D flip-flops (DFFs).

6. The unlock detection circuit according to claim 4, characterized in that, The first delay time is determined based on the maximum timing deviation in the memory protocol.

7. The unlock detection circuit according to claim 6, characterized in that, The number threshold is determined based on the maximum timing deviation, the first delay time, and the single-cycle phase adjustment amount of the delay phase-locked loop.

8. A memory, characterized in that, include: Delayed phase-locked loop; as well as The loss-of-lock detection circuit as described in any one of claims 1 to 7 is configured to perform loss-of-lock detection on the delayed phase-locked loop.

9. The memory according to claim 8, characterized in that, The delay phase-locked loop includes a transmission unit, a delay line, a first phase detection unit, and a control unit; One end of the transmission unit is connected to one end of the delay line, and the other end is connected to one end of the unlock detection circuit and one end of the first phase detection unit, respectively. The other end of the delay line is connected to one end of the first phase detection unit and one end of the unlock detection circuit, respectively. One end of the control unit is connected to the other end of the first phase detection unit and the other end of the unlock detection circuit, and the other end of the control unit is connected to one end of the delay line.

10. The memory according to claim 9, characterized in that, The first phase detection unit is configured to align the rising edges of the feedback clock and the input clock.

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