A fast background gain calibration method based on bayesian estimation
By combining a hybrid approach of SAR decision logic and Bayesian estimation, and using comparator noise as prior information, a rapid calibration of inter-stage gain error in pipelined SAR ADCs is achieved. This solves the problems of slow convergence speed and high hardware overhead of traditional algorithms, and improves the system's performance and robustness in complex environments.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2026-04-15
- Publication Date
- 2026-07-14
Smart Images
Figure CN122394556A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit design technology, and relates to data converter design technology, specifically to a fast background gain calibration method based on Bayesian estimation applied to data converters. Background Technology
[0002] In a pipelined successive approximation register analog-to-digital converter (SAR ADC) architecture, the accuracy of interstage gain is crucial for ensuring overall performance. Because many designs use open-loop amplifiers between stages to amplify the residual voltage, the actual circuit gain often deviates from the initial design value and is highly susceptible to factors such as process, voltage, and temperature (PVT). Interstage gain errors can cause significant deviations in the ADC transfer curve compared to the ideal transfer curve, ultimately severely impacting performance.
[0003] To address this issue, digital background calibration techniques are widely used. Currently, most mainstream solutions are based on the Least Mean Square (LMS) algorithm, which injects pseudo-random (PN) noise at the input to establish a feedback loop for gain error in the digital domain, thereby achieving real-time gain tracking. However, traditional LMS calibration schemes face the following technical bottlenecks in practical applications: 1) Since the algorithm is essentially based on statistically averaged stochastic gradient descent, millions of sampling points are typically required to achieve convergence in order to offset interference from the input signal. In complex application environments, the slow convergence process makes it difficult for the system to respond quickly to instantaneous gain fluctuations; 2) Increasing hardware resources (such as introducing a reference ADC or a split ADC) can accelerate convergence, but this leads to additional area overhead and introduces problems such as channel mismatch, which in turn introduces additional calibration.
[0004] It is worth noting that traditional methods often overlook the information value inherent in the noise characteristics of the circuit (such as comparators). Therefore, how to utilize the information within the circuit and achieve faster and more accurate gain calibration convergence with fewer samples without significantly increasing hardware complexity has become a key competitive advantage for high-performance ADCs in real-time acquisition scenarios such as the Industrial Internet of Things and smart sensors. Summary of the Invention
[0005] To address the issues of slow convergence speed and difficulty in balancing hardware overhead and convergence accuracy in existing data converter design technologies, this invention provides a fast background gain calibration method based on Bayesian estimation.
[0006] Specifically, this invention designs a hybrid residual estimation method architecture that combines SAR (Successive Approximation Register) decision logic with Bayesian statistical estimation. The residual estimates are directly used for LMS (Least Mean Square) calibration, facilitating rapid convergence of the gain calibration loop. This invention significantly improves the environmental adaptability of pipelined-SAR ADCs and greatly enhances calibration convergence speed. While maintaining low hardware overhead, this method effectively solves the core bottleneck of unstable gain in interstage open-loop amplifiers, providing crucial technical support for high-performance signal acquisition systems in industrial IoT, smart sensors, and energy-efficient edge computing chips.
[0007] The technical solution of this invention is:
[0008] This invention provides a fast background gain calibration method based on Bayesian estimation, applied to the inter-stage gain error background calibration of pipelined successive approximation register analog-to-digital converters. The method includes:
[0009] S1: Perform SAR-assisted comparison on the inter-level residual signal to generate a small SAR ADC output codeword;
[0010] S2: Perform multiple repeated comparisons on the remaining residual signal after the SAR-assisted comparison to obtain the comparison results;
[0011] S3: Based on the results of repeated comparisons and combined with the preset prior distribution, Bayesian estimation is performed on the remaining residual signal to obtain the estimated value of the remaining residual;
[0012] S4: Combine the information obtained from the two stages of the SAR-assisted Bayesian estimator to estimate the residual signal;
[0013] S5: Extract the interstage gain error based on the pipelined SAR ADC output codeword, the remaining residual estimate, and the pseudo-random perturbation signal PN; and update the interstage gain estimate based on the interstage gain error.
[0014] S6: Repeat steps S1 to S5 until the interstage gain error is less than a preset threshold. Determine that the interstage gain estimate has converged to the true gain and complete the background calibration.
[0015] The calibration algorithm designed in this invention achieves a convergence speed 30 times faster than the traditional LMS algorithm while maintaining extremely low hardware and power consumption, and can track the gain fluctuation of interstage amplifiers under different environmental conditions in real time.
[0016] The fast background gain calibration system based on Bayesian estimation of this invention includes: a SAR-assisted Bayesian estimator and an on-chip LMS calibration engine. The core of this invention lies in the SAR-assisted Bayesian estimator, whose main function is to accurately estimate the inter-stage residual signal of a pipelined successive approximation register-type analog-to-digital converter and convert it into binary codewords. The on-chip LMS calibration engine includes PN sequence injection logic and decorrelation logic, a digital calibration operator (including multipliers and shifters), and a gain tracking accumulator. The PN sequence injection logic injects pseudo-random perturbation signals into the calibration loop, the decorrelation logic extracts error information related to the inter-stage gain error, the digital calibration operator performs parameter update operations based on the error information, and the gain tracking accumulator outputs the updated inter-stage gain calibration value. The on-chip LMS calibration engine utilizes the residual and other information estimated by the Bayesian estimator to track and update the inter-stage gain estimate in real time using the LMS algorithm. The SAR-assisted Bayesian estimator works in conjunction with the LMS calibration engine to reduce interference from irrelevant terms in the calibration loop and improve the convergence speed and stability of background gain calibration.
[0017] The specific components of the fast background gain calibration system based on Bayesian estimation proposed in this invention will be described in detail below.
[0018] A. Design a SAR-assisted Bayesian estimator for efficient estimation of residual signals.
[0019] In its specific implementation, this invention employs a hybrid architecture SAR-assisted Bayesian estimator. This estimator includes a small successive approximation register-type analog-to-digital converter (SAR ADC) (the SAR ADC includes a dedicated capacitive digital-to-analog converter (CDAC) for calibration; other components such as comparators and logic circuits can reuse relevant components from the first-stage sub-ADC of a two-stage pipelined SAR ADC), a comparator for Bayesian estimation, and a look-up table (LUT). Its core mechanism is to reuse the hardware resources of the first-stage ADC and utilize the noise statistics of the comparator to extract accurate estimates of the inter-stage residuals in a very short time. Specific details are as follows:
[0020] A1. Design hybrid quantization hardware, including deterministic SAR quantization and probabilistic Bayesian estimation.
[0021] This invention achieves a balance between computational overhead and convergence speed by combining deterministic SAR decision-making with probabilistic Bayesian estimation.
[0022] The SAR-assisted Bayesian estimator comprises a small SAR ADC and a comparator for the Bayesian estimator. The small SAR ADC includes a dedicated capacitor-to-analog converter (CDAC) for calibration; the calibration CDAC is bridged with the main CDAC of the pipelined SAR ADC, with the high-order segment serving as the main CDAC and the low-order segment as the calibration CDAC. This structure significantly reduces the hardware area by segmenting the capacitors while meeting the high-resolution estimation requirements.
[0023] After the first-stage sub-ADC of the pipelined SAR ADC completes quantization and generates the inter-stage residual signal, the SAR-assisted Bayesian estimator uses a small SAR ADC to perform deterministic quantization on the inter-stage residual signal. The resulting codeword is fed back to the calibration CDAC. This deterministic quantization extracts the high-order deterministic information of the residual signal and limits the remaining residual voltage within the sensitive range of the comparator thermal noise.
[0024] The SAR-assisted Bayesian estimator innovatively introduces noise-assisted probabilistic estimation in the second stage. Specifically, after the N2-bit (e.g., 3-bit) small-calibrated SAR ADC completes its decision, its reference level is kept constant, and the comparator is driven to perform M (e.g., 7) repeated comparisons. Then, using the comparator's inherent thermal noise as prior information, the remaining information of the residual signal can be obtained from the output of the multiple comparisons. The specific principle will be explained in A2. By combining the information obtained from the two stages of the SAR-assisted Bayesian estimator, the residual signal can be effectively estimated.
[0025] It is worth noting that this estimator does not use a dedicated high-performance comparator, but instead directly reuses the key comparator in the first stage of the pipeline. This reuse not only saves area and power consumption, but more importantly, it ensures that the noise characteristics on which the calibration is based are completely consistent with the noise in the actual quantization process, thereby eliminating mismatch errors between different comparators.
[0026] In terms of timing control, the quantization process of the Bayesian estimator operates in parallel with the residual amplification phase of the inter-stage open-loop amplifier. This means that while the main signal link completes amplification and transmission, the calibration engine has already completed the prediction of the residual voltage, thus achieving zero-wait-cycle background calibration at the system level.
[0027] A2. Design a Bayesian inference mechanism to extract signal information.
[0028] The core of this invention lies in utilizing Bayes' theorem to extract signal information using the Gaussian distribution characteristics of comparator noise. The operating mechanism is as follows:
[0029] During the conversion process, the estimator repeatedly probes the residual voltage after the first-stage quantization using a comparator with known noise levels. Because the comparator contains Gaussian-distributed thermal noise, when the residual voltage is extremely close to the root mean square value of the comparator's thermal noise, the output of a single comparison will randomly jump due to noise fluctuations. This invention does not treat this noise as interference, but rather as statistical information. By observing the frequency of logic "1" occurrences in the outputs of multiple comparisons, the precise magnitude of the residual voltage is inferred in reverse.
[0030] Building upon this foundation, the system incorporates Bayesian estimation to effectively utilize information. Since the residual signals input to the comparator statistically conform to a specific prior distribution, combined with current observation samples, the system can construct a posterior probability distribution with higher confidence. Specifically, this mechanism uses a pre-calibrated comparator noise variance as a benchmark and, through maximum likelihood mapping, transforms seemingly random discrete decision frequencies into optimal estimates of continuous residual voltages.
[0031] The core value of this reasoning approach lies in its substitution of "hard decision" for "soft decision." Traditional quantization methods can only provide deterministic interval information, while the Bayesian inference mechanism of this invention utilizes the statistical properties of noise to achieve super-resolution sensing of sub-LSB level minute signals. Ultimately, this high-precision residual estimation information is mapped into digital codes and provided to the calibration engine, enabling the system to quickly and accurately extract inter-stage gain errors and significantly shortening the convergence period of the calibration loop.
[0032] A3. Hardware-friendly Mapped Lookup Table (LUT) implementation
[0033] To reduce the complexity of on-chip digital implementation, this invention avoids complex nonlinear mathematical operations by using lookup table technology.
[0034] The comparator's decision needs to be mapped to the final output codeword associated with the Bayesian estimation. Since the comparator output distribution follows a fixed statistical law, the types of output codewords associated with the Bayesian estimation are limited. This invention uses a miniature LUT to replace the complex on-chip function solver. This LUT directly stores the mapping relationship between the decision count value and the corresponding Bayesian estimation code.
[0035] This statistical estimation method enables the calibration loop to more effectively filter out noise interference unrelated to gain. Experimental data shows that this component improves the convergence speed of background calibration by approximately 30 times (reducing it from 600,000 samples to less than 20,000). Furthermore, when power supply voltage variations cause interstage gain changes (approximately 3%), the system only requires about 7,000 samples to reconverge, demonstrating extremely strong environmental robustness.
[0036] B. On-chip LMS calibration engine
[0037] The on-chip LMS calibration engine provided by this invention aims to track inter-stage gain error in real time through closed-loop iteration based on the super-resolution residual information provided by a Bayesian estimator. This engine includes PN sequence injection and decorrelation logic, a digital calibration operator (containing multipliers and shifters), and a gain tracking accumulator. Specific details are as follows:
[0038] B1. PN Sequence Injection and Decorrelation Logic
[0039] This invention utilizes perturbation injection technology to extract background gain errors. The specific implementation details are as follows: The system generates a PN sequence through a Linear Feedback Shift Register (LFSR) and injects it into the main CDAC array as an analog voltage after the first-stage quantization. This sequence is statistically independent of the signal to be converted and serves as a characteristic perturbation label for gain calibration. Subsequently, the calibration engine performs cross-correlation calculations in the digital domain between the injected PN sequence and the digital residual containing the gain error. Since the mean of the PN sequence is zero and independent of quantization noise, through long-term statistical accumulation, the calibration loop can decouple the true inter-stage gain error signal from complex background noise.
[0040] B2. Digital calibration operator based on Bayesian feedback
[0041] Unlike traditional LMS algorithms that directly use quantization results, the core of this invention lies in introducing Bayesian estimates to guide loop updates, thereby optimizing the efficiency of multiply-accumulate operations.
[0042] First, the digital calibration logic receives the injected PN code, the predicted code from the Bayesian estimator, and the output code from the second-stage ADC (sub-ADC) of the two-stage pipelined SAR ADC. Based on the codeword information, the on-chip LMS calibration engine calculates the current inter-stage gain error. When the inter-stage gain error is close to zero, it means that the estimated gain is close to the true gain. The Bayesian estimate is then used to calculate the inter-stage gain error to reduce calibration-irrelevant terms in the inter-stage gain error, thereby improving the calibration convergence speed. To balance convergence speed and hardware overhead, the on-chip LMS calibration engine uses an adjustable-step digital shifter to replace the complex floating-point multiplier to implement learning rate weighting. By controlling the magnitude of gain updates through simple shift operations, the circuit can track instantaneous gain jumps caused by power supply voltage fluctuations (such as switching from 0.65V to 0.7V) while minimizing the area occupied by logic gate circuits.
[0043] B3. Gain Tracking Accumulator
[0044] The gain tracking accumulator is the core component for achieving closed-loop stability of the calibration loop, and is responsible for generating and maintaining the final correction coefficients.
[0045] The accumulator sums the gain increment calculated in each cycle with the estimated gain from the previous time step, using a negative feedback mechanism to force the estimated gain to approximate the physical amplification factor. Thanks to the residual estimation information provided by the Bayesian estimator, which effectively filters out irrelevant interference terms, the gain estimate within the accumulator converges with extremely high efficiency. Compared to traditional schemes, this accumulator only requires approximately 20k sampling points to reach a stable state, improving the convergence speed by 30 times. The final stable gain estimate is output to the post-processing module for real-time compensation of the second-stage quantization results, thereby eliminating DNL / INL degradation caused by inaccurate open-loop amplifier gain between low-voltage stages and ensuring that the system achieves 13-bit linearity in the ADC using 28nm CMOS technology.
[0046] The above-mentioned fast background gain calibration system based on Bayesian estimation proposed in this invention includes the following steps:
[0047] 1) Fabricate hybrid quantization hardware, comprising a small SAR ADC and a comparator for Bayesian estimation. Specifically, fabricate a segmented CDAC structure, comprising an N1-bit (e.g., 6-bit) small CDAC and an N2-bit (e.g., 3-bit) calibration CDAC, integrated in a bridged manner into the front-end of the pipelined SAR ADC. In the first-stage conversion process, the N1-bit miniature CDAC performs conventional SAR logic to determine the main signal range. Subsequently, the newly introduced N2-bit calibration CDAC uses specially designed SAR logic to fine-quantize the generated residual signal, locking the residual voltage within the sensitive range where the comparator's thermal noise is perceptible. Finally, this invention uses the comparator to perform M (e.g., 7) repeated comparisons, innovatively utilizing the comparator's inherent Gaussian thermal noise as prior information, and using the logic "1" frequencies output by these M comparisons as the original observation values. The purpose of this step is to complete the deterministic SAR decision and probabilistic Bayesian estimation, preparing for the next step of mapping lookup table (LUT) to convert the Bayesian estimate into binary codewords, so as to extract sub-LSB level signal features that cannot be obtained by conventional hard decision quantization.
[0048] 2) Preparation of the Mapping Lookup Table (LUT). This invention, for the first time, utilizes pre-calibrated comparator noise variance and Bayesian posterior probability distribution to pre-calculate the mapping relationship between decision frequencies and residual estimates, and embeds it as an on-chip LUT. In real-time operation, the mapping engine directly retrieves the corresponding Bayesian prediction code from the lookup table based on the count of repeated comparisons, generates inter-level remainder estimates with super-resolution characteristics, and transmits them to the on-chip calibration engine in the form of digital codewords. The purpose of this step is to convert the results of multiple comparisons into inter-level residual estimates that can be directly used for digital calibration.
[0049] 3) Construction of the PN perturbation injection and decorrelation module. An LFSR is configured to generate a PN sequence, and at the end of each cycle, an analog perturbation is injected into the signal link through the main CDAC array. At the digital calibration end, decorrelation logic is designed to perform a cross-correlation operation between this PN sequence and the Bayesian prediction value, thereby decoupling the inter-stage gain error information independent of the main signal in the background environment. The purpose of this step is to provide an error signal related to the inter-stage gain error for subsequent gain parameter updates.
[0050] 4) Constructing an LMS-based closed-loop gain calibration loop. Based on the interstage gain error information extracted in step 3), an LMS-based closed-loop gain calibration loop is constructed. Unlike existing technologies, this step utilizes the interstage residual estimate output in step 2) to assist in determining the direction of gain parameter updates. Simultaneously, step-size weighting is performed using a digital shifter with an adjustable learning rate, and the interstage gain estimate is updated in real time using a gain tracking accumulator. After these updates, the system can quickly reconverge to the target calibration value under power supply voltage fluctuations or environmental temperature drift, thereby achieving real-time dynamic background calibration of interstage gain errors.
[0051] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0052] This invention provides a hybrid quantization hardware architecture with deep hardware multiplexing. This architecture achieves accurate residual estimation without adding a high-performance dedicated comparator by multiplexing the existing comparators of the first-stage sub-ADC of the pipelined SARADC for statistical decision-making and combining it with a segmented bridged CDAC design. In terms of circuit implementation, this invention uses a miniature LUT to replace the complex nonlinear mathematical function solver, transforming probabilistic inference logic into extremely simple digital addressing operations, greatly reducing the number of logic gates and area footprint of the on-chip calibration engine. Experimental data shows that, including all calibration overhead, the system still maintains extremely high energy efficiency, demonstrating that this calibration technology maintains high-performance output while exhibiting excellent power efficiency.
[0053] This invention provides a fast background gain calibration scheme based on Bayesian estimation. This scheme introduces a SAR-assisted Bayesian estimator into the traditional LMS algorithm, utilizing comparator thermal noise as prior information to achieve super-resolution sensing of inter-stage residual signals. Compared to the traditional LMS algorithm, which relies on millions of samples, this invention improves the calibration convergence speed by approximately 30 times, requiring only about 20,000 sampling points to reach a stable state. This characteristic enables the ADC to not only significantly shorten power-on initialization time but also to possess the ability to track transient gain jumps caused by power supply voltage fluctuations or ambient temperature drift in real time, significantly enhancing the system's robustness in dynamic environments.
[0054] This invention provides a time-parallel background calibration implementation method. Through ingenious timing arrangement, the quantization process of the Bayesian estimator is fully embedded within the residual amplification phase of the inter-stage open-loop amplifier. This means that the prediction of calibration information and the amplification processing of the main signal link are completed synchronously, and the operation of the calibration engine does not occupy additional analog-to-digital conversion cycles. This zero-time-overhead collaborative working mode ensures that high-precision background calibration can be continuously performed without sacrificing the ADC sampling rate, providing core technical support for the deployment of low-voltage, high-resolution data converters in high-throughput application scenarios such as IoT edge devices. Attached Figure Description
[0055] Figure 1 (a) is a schematic diagram of the fast background gain calibration ADC system based on Bayesian estimation proposed in this invention. Figure 1 (b) is the timing diagram of the ADC.
[0056] The system consists of a pre-stage SAR ADC, an inter-stage open-loop amplifier (Gm-C), a 9-bit post-stage SAR ADC, and a digital calibration engine integrating LFSR and a Bayesian estimator. The first stage contains a 2-bit coarse SAR ADC per cycle, which, through the first-stage conversion phase (Φ... CONV1 By injecting PN codes and using Bayesian algorithms to quickly estimate the background error of the interstage open-loop amplifier gain, the system can output the digitally compensated codeword D in real time. OUT .
[0057] Its timing sequence demonstrates the system's high degree of parallelism: during the sampling phase (Φ S / Φ SC After that, the first stage performs coarse quantization and simultaneously completes the establishment of the main DAC and PN injection; subsequently, the open-loop amplifier between the Gm-C stages... A During this period, the margin signal is amplified, while the Bayesian estimator performs additional comparisons and estimations; finally, the second stage at Φ CONV2 The phased fine quantization ensures gain error correction under high throughput.
[0058] Figure 2 This is a block diagram of the fast background gain calibration logic based on Bayesian estimation proposed in this invention.
[0059] This calibration architecture uses the residual signal V RES1 A pseudo-random noise signal PN is injected into the signal, and the actual gain G is obtained by quantization using a sub-ADC (i.e., the second-stage ADC). A Digital margin V DAC2 Simultaneously, the Bayesian estimator calculates the residual estimate V in real time. res,est1 The calibration engine will V DAC2 Subtract the estimated gain G e Compensated PN signal and V res,est1 The residual signal is obtained, and G is updated by combining the step size factor μ to drive the gain tracking accumulator. e This logic significantly reduces signal interference during correlation operations by introducing Bayesian prior estimation, thereby enabling rapid background calibration and digital compensation for inter-stage open-loop amplifier gain errors.
[0060] Figure 3 The figure shows the performance simulation curves of the calibration method proposed in this invention.
[0061] Among them, (a) shows the relationship between the number of sample points required for convergence and the accuracy of the Bayesian estimator, and compares the convergence speed advantage of the traditional LMS algorithm and the present invention under different comparison numbers; (b) shows the distribution of system power efficiency (FoM) with estimator accuracy under different configurations, proving that the present invention achieves fast convergence while taking into account low power consumption characteristics.
[0062] Figure 4 This is a diagram illustrating the implementation of the fast background gain calibration circuit based on Bayesian estimation according to the present invention.
[0063] This circuit is implemented using bridging capacitors, specifically including a 6-bit miniature CDAC, a 3-bit calibration CDAC, and a coupling capacitor C. B The comparator is used to perform SAR conversion and Bayesian comparison. During calibration, the SAR logic first controls the circuit to perform a 3-bit SAR search to determine the high-order bit value of the residual voltage, and then performs multiple Bayesian comparisons under the control of the enable signal EN. The Bayesian estimator integrates a counter and accumulator to count the frequency of the comparator output being "1", and maps this count value to a binary estimation code D through a LUT. BAYES Finally, the LMS calibration engine combines the pseudo-random code PN and the second-level output D. OUT2 First-level quantization result D OUT_CAL and D BAYES Perform iterative calculations and output the gain estimate. .
[0064] Figure 5 This is a convergence curve diagram of the calibration method of the present invention and the conventional method.
[0065] The vertical axis in the figure represents SNDR, and the horizontal axis represents the number of sampling points N. sample The Bayesian-based LMS algorithm (circles) converges with only about 20k sampling points in the initial stage, while the traditional LMS calibration curve (squares) requires about 600k sampling points. Furthermore, after switching the power supply voltage (from 0.65V to 0.7V) at approximately 70k sampling points, the Bayesian algorithm reconverges with only about 7k sampling points, while the traditional algorithm requires about 200k sampling points. This figure visually demonstrates the significant improvement in convergence speed and dynamic environment tracking capability achieved by this invention. Detailed Implementation
[0066] The present invention will be further illustrated below with reference to the accompanying drawings and embodiments, but the scope of the invention is not limited in any way.
[0067] This invention provides a fast background gain calibration scheme based on Bayesian estimation, which accelerates the convergence of the LMS gain calibration loop through Bayesian statistical methods.
[0068] The fast background gain calibration system based on Bayesian estimation of this invention includes: a SAR-assisted Bayesian estimator and an on-chip LMS calibration engine. The SAR-assisted Bayesian estimator accurately estimates the inter-stage residual signal and converts it into binary codewords. The on-chip LMS calibration engine includes PN sequence injection logic and decorrelation logic, digital calibration operators (including multipliers and shifters), and a gain tracking accumulator, among other digital logic. This engine utilizes the residual information estimated by the Bayesian estimator to track and update the inter-stage gain estimate in real time using the LMS algorithm, greatly reducing interference from uncorrelated signals in the calibration loop and thus accelerating convergence. Together, these two components enable the prediction of inter-stage gain.
[0069] The calibration method provided by this invention is applied to a pipelined SAR ADC architecture, such as... Figure 1 As shown. Its core logic is to track and compensate for the gain error of the inter-stage open-loop amplifier in real time through a digital engine without interrupting the normal conversion of the ADC.
[0070] The workflow of this ADC consists of: sampling, first-stage coarse quantization, residual voltage amplification, and second-stage fine quantization. During the amplification stage, the system transmits the residual voltage V... RES1 A known pseudo-random code PN is injected into it. Finally, the digital code D output by the second stage... OUT2 It includes the amplified residual signal, PN code, and gain error caused by the non-ideal nature of the interstage open-loop amplifier.
[0071] This ADC achieves accurate extraction of gain error through the following three steps:
[0072] 1) First-level coarse quantization and SAR conversion
[0073] In each conversion cycle, the first-stage coarse quantization ADC first performs SAR conversion on the input signal. The first-stage ADC determines the high-order digital code D of the signal through multi-bit SAR decision. OUT1 The main capacitor array (CDAC) is controlled to perform charge switching based on the SAR conversion results, leaving a residual voltage V on the top plate. RES1 After the SAR conversion is completed, a known pseudo-random code PN is injected into the remaining voltage as effective information for extracting subsequent interstage gains.
[0074] 2) Bayesian estimation and LUT mapping
[0075] Before entering the amplification stage, the system reuses the first-stage ADC hardware to perform a fine-grained estimate of the residual voltage to improve the calibration convergence speed: after performing 3-bit SAR conversion, the thermal noise characteristics of the comparator are used to repeatedly compare the current residual voltage, and the number of comparison results of "1" is counted by an on-chip counter; then, a built-in small lookup table is used to replace complex function calculations, directly mapping the statistical frequency to the maximum likelihood estimation code, to obtain the Bayesian estimate V of the residual voltage. res,est1 .
[0076] 3) On-chip engine calculates digital closed-loop gain
[0077] The calibration engine combines the Bayesian estimation results with the output of the second-stage ADC to achieve closed-loop tracking of the gain error. This is achieved by calculating the back-end output D. OUT2 The correlation between the predicted values and the Bayesian estimation is used to eliminate signal interference from the calibration loop. The on-chip LMS calibration engine uses the calculated correlation results to iteratively update the closed-loop gain estimate in the digital domain in real time. .
[0078] Figure 2 The digital logic closed-loop diagram of the on-chip Bayesian background gain calibration engine is shown. Its key feature is that, through the coupling of the forward signal path, the Bayesian estimation path, and the digital correlation accumulation loop, it achieves real-time extraction and compensation of analog gain error: 1) In the forward path, the first-stage residual voltage signal V... RES1 After being superimposed with the pseudo-random sequence PN, and then through the analog gain G A Amplified and quantized by a sub-analog-to-digital converter, the output digital code V is obtained. DAC2 ;2) In the Bayesian estimation path, the Bayesian estimator receives V RES1 Based on relevant information, the first-order estimate V of the remaining voltage is calculated and output using the prior probability distribution. res,est13) In the error extraction logic, the system will use V to assist in subsequent error stripping; DAC2 Subtract the current gain calibration factor G respectively e Modulated PN sequence and V res,est1 This allows the residual error signal to be extracted in the digital domain; 4) In the closed-loop feedback loop, the residual error signal is correlated with the step size factor μ·PN, and its output is processed by the accumulator (z -1 Perform integration updates to generate real-time corrected gain calibration coefficients G. e This information is then fed back to the error extraction logic until the loop converges, thus achieving accurate compensation for the analog gain error.
[0079] Figure 3 (a) shows the curve of the number of sample points required for calibration convergence as a function of the accuracy of the Bayesian estimator, used to characterize the convergence efficiency of the present invention: the convergence speed of the traditional LMS algorithm is limited by statistical properties, and the number of samples required for convergence is close to 10. 6 The proposed SAR-assisted Bayesian estimator significantly reduces the estimation variance by introducing a prior probability distribution, resulting in an exponential decrease in the number of sample points required for convergence as the number of bits in the estimator increases. This achieves an order-of-magnitude improvement in convergence speed while maintaining low hardware overhead.
[0080] Figure 3 Figure (b) illustrates the relationship between normalized power consumption and estimator accuracy under different architectural configurations, characterizing the hardware energy efficiency of this invention. The figure compares the performance of the pure SAR architecture and the hybrid architecture at different accuracies. Considering both convergence speed and energy efficiency, this embodiment selects an architecture scheme with 3-bit SAR logic and 7 Bayesian comparisons. It should be noted that the above selection is not unique, and designers can adjust it according to the specific requirements of the circuit.
[0081] This application provides a Bayesian estimation circuit based on SAR logic assistance (such as...). Figure 4 As shown, the gain error is rapidly estimated by coupling an analog comparison network with digital processing logic. The main circuit includes a charge redistribution network consisting of a 6-bit CDAC and a 3-bit calibration CDAC. SAR logic is used to perform preliminary successive approximation quantization of the residual voltage. Then, Bayesian estimation is performed. When the enable condition is met, the Bayesian estimator receives the comparator output signal, performs statistical analysis using an internal counter and mean calculation unit, and combines this with the prior noise intensity. The mapping function module outputs a high-precision estimate D. BAYES This estimate is used as prior information input to the LMS calibration engine, integrating the reference sequence PN and the sub-quantization output D. OUT2 and calibration code D OUT_CALPerform relevant calculations to extract and output accurate gain estimates in real time. This significantly reduces the convergence cycle of the background calibration.
[0082] like Figure 5 As shown, the robustness and dynamic tracking capability of the proposed algorithm under 28nm CMOS technology were verified through tape-out testing: In the initial calibration stage, the Bayesian-based LMS algorithm only requires about 20,000 sample points to achieve a steady-state SNDR of over 73dB, which is about 30 times faster than the traditional LMS algorithm. Furthermore, when the power supply voltage abruptly changes from 0.65V to 0.7V at approximately 70k sample points, the drastic fluctuation in analog gain necessitates re-convergence of the digital gain estimation. However, this invention, with its rapid extraction of signal features by the Bayesian estimator, achieves near real-time tracking of the gain error, allowing the SNDR to quickly recover to a steady-state level. This result fully demonstrates that the invention maintains extremely high calibration efficiency and conversion accuracy even under dynamic environmental interference.
[0083] This invention provides a fast background gain calibration method based on Bayesian estimation. By embedding a SAR-assisted Bayesian estimator into the traditional LMS calibration loop, the residual features of the sub-LSB level are extracted using comparator thermal noise as prior information. This significantly reduces the interference of uncorrelated terms in the calibration loop and achieves ultra-fast convergence and real-time dynamic compensation of inter-stage gain errors with low hardware overhead.
[0084] The SAR-assisted Bayesian estimator in this invention is specifically implemented as a hybrid quantization architecture, combining deterministic SAR decision-making with probabilistic Bayesian statistical estimation. This estimator reuses the hardware resources of the first-stage ADC and employs a segmented bridged CDAC structure (including a 6-bit main CDAC and a 3-bit calibration CDAC) to initially lock the residual voltage within the comparator's thermal noise sensitivity range. During the estimation process, a comparator with known noise variance is used to repeatedly probe the residual voltage, and the frequency of logic "1" occurrences is used as the observation value. This is then mapped to a high-precision Bayesian estimation code through a built-in miniature LUT. This estimation code serves as prior information input to the on-chip LMS calibration engine, which updates the gain calibration coefficients in real time through digital correlation operations. Because the Bayesian estimator effectively filters out irrelevant interference, the system achieves a convergence speed approximately 30 times faster than the traditional LMS algorithm using a 28nm CMOS process (requiring only about 20,000 sampling points to converge). It can also achieve near real-time re-locking and tracking when the power supply voltage changes abruptly (such as from 0.65V to 0.7V), ensuring the high linearity performance of the ADC in dynamic scenarios such as high-energy-efficiency edge computing.
[0085] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.
Claims
1. A fast background gain calibration method based on Bayesian estimation, characterized in that, Design a successive approximation register SAR-assisted Bayesian estimator for pipelined successive approximation register analog-to-digital converters (SAR ADCs). This estimator enables rapid calibration of the inter-stage gain of the ADC by accurately estimating the inter-stage residual signal. The SAR-assisted Bayesian estimator comprises a small successive approximation register SAR ADC and a comparator for Bayesian estimation. The small SAR ADC includes a dedicated capacitor-to-analog converter (CDAC) for calibration. The comparator used for Bayesian estimation is a comparator from the first-stage sub-ADC of the pipelined SAR ADC. The process of accurately estimating the inter-level residual signal includes: 1) Perform SAR-assisted comparison on the inter-level residual signals to obtain the output codeword of the small SAR ADC; The SAR-assisted Bayesian estimator uses a small SAR ADC for deterministic quantization in the first stage; the quantized codeword is fed back to the calibration CDAC to extract the high-order deterministic information of the residual signal and limit the remaining residual voltage within the sensitive range of the comparator thermal noise. 2) The SAR-assisted Bayesian estimator introduces noise-assisted probabilistic estimation in the second stage. After the small SAR ADC completes the decision, the reference level is kept unchanged, and the comparator is driven to perform multiple repeated comparisons. 3) Using the inherent thermal noise of the comparator as prior distribution information, and combining the results of multiple comparisons, Bayesian estimation is performed on the remaining residual voltage signal to obtain the estimated value of the remaining residual. 4) Combine the information obtained from the two stages of the SAR-assisted Bayesian estimator to estimate the residual signal; 5) Extract interstage gain error information from the output codeword, residual estimate, and pseudo-random disturbance signal of the pipeline SAR ADC; and update the interstage gain estimate based on the interstage gain error information; 6) Repeat steps 1) to 5) until the interstage gain error is less than the preset threshold. That is, the estimated interstage gain value is determined to converge to the true gain, thereby realizing the rapid background calibration of the interstage gain error.
2. The fast background gain calibration method based on Bayesian estimation as described in claim 1, characterized in that, Specifically, the LMS (Least Mean Square) algorithm is used to track and update the interstage gain estimates in real time.
3. A fast background gain calibration system based on Bayesian estimation, characterized in that, include: SAR-assisted Bayesian estimator and on-chip LMS calibration engine; wherein: The SAR-assisted Bayesian estimator is used for accurate estimation of inter-stage residual signals and includes a small successive approximation register-type analog-to-digital converter (SAR ADC), a comparator for Bayesian estimation, and a mapping lookup table. The calibration CDAC of the small successive approximation register-type analog-to-digital converter (SAR ADC) and the main CDAC of the pipeline SAR ADC are combined using a bridging structure. The high-order segment is the main CDAC and the low-order segment is the calibration CDAC. After the first-stage sub-ADC of the pipeline SAR ADC completes quantization and generates the inter-stage residual signal, the SAR-assisted Bayesian estimator uses the small SAR ADC to perform deterministic quantization on the inter-stage residual signal in the first stage. In the second stage, noise-assisted probabilistic estimation is introduced. After the small SAR ADC completes the decision in the first stage, it maintains the reference level and drives the comparator to perform multiple repeated comparisons. The on-chip LMS calibration engine uses the residual information estimated by the Bayesian estimator to track and update the interstage gain estimate in real time through the LMS algorithm.
4. The fast background gain calibration system based on Bayesian estimation as described in claim 3, characterized in that, The mapping lookup table specifically uses a miniature LUT to directly store the mapping relationship between decision counts and corresponding Bayesian estimation codes.
5. The fast background gain calibration system based on Bayesian estimation as described in claim 3, characterized in that, The on-chip LMS calibration engine includes PN sequence injection logic and decorrelation logic, digital calibration operators, and a gain tracking accumulator; among which, The PN sequence injection logic is used to inject pseudo-random perturbation signals into the calibration loop; The decorrelation logic is used to extract error information related to interstage gain error; The digital calibration operator is used to perform parameter update operations based on the error information; The gain tracking accumulator is used to output the updated interstage gain calibration value.
6. The fast background gain calibration system based on Bayesian estimation as described in claim 5, characterized in that, The PN sequence injection logic and decorrelation logic utilize perturbation injection technology to achieve background-based gain error extraction. The specific process includes: A PN sequence is generated by a linear feedback shift register (LFSR) and injected into the main CDAC array as an analog voltage after the first stage of quantization. This PN sequence is statistically independent of the signal to be converted and serves as a characteristic perturbation label for gain calibration. Subsequently, the on-chip LMS calibration engine performs cross-correlation calculations in the digital domain between the injected PN sequence and the digital residual containing gain error.
7. The fast background gain calibration system based on Bayesian estimation as described in claim 5, characterized in that, Digital calibration operators include multipliers and shifters.
8. The fast background gain calibration system based on Bayesian estimation as described in claim 7, characterized in that, The digital calibration operator is a Bayesian feedback-based digital calibration operator that guides loop updates by introducing Bayesian estimates.
9. The fast background gain calibration system based on Bayesian estimation as described in claim 8, characterized in that, The loop update process includes: The digital calibration logic receives the injected PN code, the predicted code from the Bayesian estimator, and the output code of the second-stage ADC. The on-chip LMS calibration engine uses Bayesian estimates to calculate the current prediction error term; when the prediction error term is close to zero, it means that the estimated gain is close to the true gain. This reduces calibration-irrelevant terms in the prediction error term, thereby improving the calibration convergence speed.
10. The fast background gain calibration system based on Bayesian estimation as described in claim 9, characterized in that, The on-chip LMS calibration engine uses a digital shifter with adjustable step size to achieve learning rate weighting.