Delta-sigma modulator based on unipolar thin film transistors

Abstract

The application discloses a single-polarity thin film transistor-based Delta-Sigma modulator, comprising an integrator module, a quantizer module and a digital-to-analog converter feedback module; an analog input signal is integrated through the integrator module first, then is quantized through the quantizer module, and the quantization result is fed back to the input end through the digital-to-analog converter feedback module; the output of each quantization is summed with the input signal through feedback, and the summed signal is input to the integrator module again. The continuous-time Delta-Sigma modulator of the application adopts a system structure of a second-order integrator cascade feedback, expands the single-polarity thin film transistor-based Delta-Sigma modulator system structure to a second-order noise shaping level, reduces the use of capacitors, adopts the advantages of large amplifier voltage gain and the like, successfully realizes a higher signal-to-noise distortion ratio in a larger bandwidth range, simultaneously has a higher working speed, and realizes more excellent performance.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to a Delta-Sigma modulator based on a unipolar thin-film transistor. Technical Background In integrated circuit systems, analog-to-digital converters (ADCs) are crucial modules responsible for converting analog signals into digital signals, playing an indispensable role, especially in integrated sensing systems. Common ADCs include pipeline, successive approximation (SAR), flash, and Delta-Sigma types. Delta-Sigma ADCs can be further divided into discrete-time (DT) and continuous-time (CT) types. A Delta-Sigma ADC consists of a modulator and a digital filter. The modulator mainly comprises integrators, quantizers, and digital-to-analog converters. Through oversampling, noise shaping, and digital filtering, Delta-Sigma ADCs can achieve a higher signal-to-noise ratio within a specific bandwidth.

[0002] Metal-oxide thin-film transistors (MO TFTs) are considered to have broad development prospects in the field of flexible integrated circuits due to their advantages such as high mobility, good uniformity, low cost, and the ability to be fabricated on flexible substrates. In recent years, MO TFTs have been widely used in flexible displays, biosignal monitoring, electronic skin, and other applications.

[0003] However, currently only N-type metal-oxide-slim (MTS) transistors can achieve superior electrical performance and reliable stability, and are therefore the only type used for integration. Consequently, popular CMOS circuit structures cannot be used in circuit designs employing MTS. Existing amplifiers based on unipolar MTS suffer from low gain and narrow bandwidth, while Delta-Sigma modulators based on unipolar MTS are mostly discrete-time modulators, employing only first-order modulation structures, resulting in poor performance, low accuracy, and low operating speed.

[0004] An existing first-order discrete-time (DT) Delta-Sigma modulator is fabricated using a unipolar metal-oxide-slim transistor (Deng ZY, Chen RS, Lin DL, et al. A Fully MOTFT-Based Tactile Sensing and Amplifying System[J]. IEEE Sensors Journal, 2025, 25(14):26492-26498.). This modulator uses a switched-capacitor integrator. Because the switched-capacitor integrator charges and discharges multiple capacitors, achieving precise signal changes requires a longer time, making it difficult to simultaneously achieve high precision and high speed. In contrast, the resistive-capacitive integrator used in this invention processes analog signals continuously, eliminating the need for an additional clock signal and reducing the use of capacitors and switches, thus achieving a higher operating speed. An existing first-order continuous-time Delta-Sigma modulator using thin-film transistor technology (Xu WX, Chen JR, Li FF, et al. A 65-dB SNDR Continuous-Time Delta-Sigma ADC Integrated by IZO Thin-Film Transistors[J].2024, 71(4):1804-1808.) employs a first-order modulation structure consisting of a single-stage continuous-time integrator, comparator, register, and digital-to-analog conversion feedback, achieving a faster operating speed than discrete-time modulators. However, since the first-order modulation structure can only achieve first-order noise shaping, the signal-to-noise ratio (SNDR) of this modulator can only reach a maximum of 65 dB in a small bandwidth range of 30 Hz, and only 43 dB in a bandwidth range of 300 Hz. In contrast, this invention extends the continuous-time Delta-Sigma modulator system structure to second-order modulation, enabling second-order noise shaping, and achieving an SNDR of 71 dB in a bandwidth range of 100 Hz, significantly improving performance in terms of bandwidth and accuracy.

[0005] Existing Delta-Sigma modulators based on unipolar metal-oxide-slim transistor (MOS) technology are generally discrete-time and first-order modulation structures. On the one hand, discrete-time Delta-Sigma modulators use switched-capacitor integrators, making it difficult to simultaneously achieve high speed and high precision. On the other hand, first-order modulation structures have weak noise shaping capabilities, making it difficult to achieve higher signal-to-noise ratios and more effective bits. Summary of the Invention

[0006] This invention employs depletion-mode metal-oxide-slim transistor (MTBT) technology to design a second-order modulation continuous-time Delta-Sigma modulator module circuit scheme. On the one hand, it improves the operating speed of the modulator module, and on the other hand, it achieves better noise shaping effect through the second-order modulation structure, thereby improving the signal-to-noise ratio and effective bit number of the Delta-Sigma modulator under the MTBT process.

[0007] The present invention is achieved by at least one of the following technical solutions.

[0008] The Delta-Sigma modulator based on unipolar thin-film transistors includes a first integrator module, a second integrator module, a quantizer module, a digital-to-analog converter feedback module, and an output buffer module. The first integrator module, the second integrator module, and the quantizer module are connected in sequence. The output terminal of the quantizer module is connected to the input terminal of the digital-to-analog converter feedback module and the input terminal of the output buffer module. The analog input signal is first integrated by the integrator module, then quantized by the quantizer module. The quantization result is fed back to the input terminal by the digital-to-analog converter feedback module. Each quantization output is summed with the input signal through the feedback, and the summed signal is then input back to the integrator module.

[0009] Furthermore, the first integrator module and the second integrator module have the same structure, both adopting a resistive-capacitive integrator, and both include a resistor, a capacitor and an amplifier.

[0010] Furthermore, the quantizer module includes an amplifier, a comparator, a voltage matching module, and a D flip-flop, which are connected in sequence.

[0011] Furthermore, the amplifier employs a 0 VGS bias thin-film transistor load amplification structure.

[0012] Furthermore, comparator COMP1 is a continuous comparator, which does not require clock control.

[0013] Furthermore, the voltage matching module includes two series-connected capacitor bootstrap inverters to convert the comparator output voltage to a value that meets the high and low level requirements of the D flip-flop input.

[0014] Furthermore, the D flip-flop employs a Master-Slave structure consisting of multiple inverters and switching transistors, and adds multiple series inverters at the output to optimize the output level.

[0015] Furthermore, the digital-to-analog converter feedback module includes a voltage regulation module and a current rudder. The output signal of the quantizer module first passes through the voltage regulation module to convert the high and low levels, and then is connected to the control gate of the current rudder to adjust the magnitude of the current of the current rudder. The current rudder is connected to the input terminal of the modulator and passes through an integrating resistor. The summation with the input signal is achieved through the voltage drop formed by the current across the resistor.

[0016] Furthermore, the current rudder is connected to the node between the integrating resistor and the amplifier in the first integrator module and the second integrator module, and achieves summation with the input signal through the voltage drop formed by the current across the resistor.

[0017] Furthermore, the output buffer module includes two inverters. The input of one inverter is connected to the non-inverting output of a D flip-flop, and its output serves as the inverting output of a Delta-Sigma modulator. The input of the other inverter is connected to the inverting output of a D flip-flop, and its output serves as the non-inverting output of a Delta-Sigma modulator.

[0018] Compared with existing technologies, the beneficial effects of the present invention are as follows: In this invention, the amplifier employs a circuit structure with a 0VGS biased TFT as the load, effectively increasing the load of the common-source amplifier and achieving a larger voltage gain while maintaining a wider bandwidth. The designed continuous-time Delta-Sigma modulator uses a second-order integrator cascaded feedback system structure, extending the Delta-Sigma modulator system structure based on unipolar thin-film transistor technology to the second-order noise shaping level and reducing the use of capacitors. Combining the advantages of the amplifier with high voltage gain used in this modulator, a higher signal-to-noise ratio is successfully achieved over a wider bandwidth, while also maintaining a higher operating speed, resulting in superior performance. Attached Figure Description

[0019] Figure 1 This is a structural diagram of a Delta-Sigma modulator based on a unipolar thin-film transistor, as shown in the embodiment.

[0020] Figure 2 This is a structural diagram of the integrator module in an embodiment.

[0021] Figure 3 This is a structural diagram of the amplifier circuit for an embodiment.

[0022] Figure 4 This is a structural diagram of the quantizer module in an embodiment.

[0023] Figure 5 The diagram shows the structure of the comparator COMP1 circuit in the embodiment.

[0024] Figure 6The diagram shows the structure of the Master-Slave D flip-flop in this embodiment.

[0025] Figure 7 This is a structural diagram of the DAC feedback circuit in an embodiment.

[0026] Figure 8 The amplifier frequency response characteristics analysis diagram is shown in the example.

[0027] Figure 9 The modulator output signal spectrum is shown in the example. Detailed Implementation

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] The purpose of this invention is to provide a second-order continuous-time Delta-Sigma modulator based on a unipolar thin-film transistor, addressing the common problems of low operating speed and accuracy in existing thin-film transistor Delta-Sigma modulators. Furthermore, it proposes an amplifier circuit structure using a 0 VGS biased thin-film transistor as the load, achieving higher gain and greater bandwidth performance than existing unipolar TFT amplifiers.

[0030] like Figure 1 As shown, the Delta-Sigma modulator in this embodiment includes a first integrator module, a second integrator module, a quantizer module, a digital-to-analog converter (DAC) feedback module, and an output buffer module. The first and second integrator modules and the quantizer module are connected sequentially. The output of the quantizer module is connected to the input of the DAC feedback module and the input of the output buffer module. The feedback loop of the DAC feedback module is connected to the amplifier inputs of the first and second integrator modules. The output of the output buffer module serves as the output of the Delta-Sigma modulator. The overall working principle is as follows: the analog input signal is first integrated by the integrator module, then quantized by the quantizer module. The quantization result is fed back to the amplifier inputs of the first and second integrator modules via the DAC feedback module. Each quantized output is summed with the input signal through feedback, and the summed signal is then input to the integrator module and subsequent stages. The quantizer is followed by the output buffer module, which outputs the final processed signal. Under the loop's action, low-frequency noise is shaped to the high-frequency region, achieving a high signal-to-noise ratio within the low-pass bandwidth.

[0031] In one embodiment, the first integrator module and the second integrator module have the same structure, both employing a resistive-capacitive integrator (RC integrator), and both including resistors, capacitors, and amplifiers. The resistors are implemented by four thin-film transistors (T1~T4) operating in the linear region. The gates of the four thin-film transistors (T1~T4) are all connected to a control signal V. b1 The drains of the first thin-film transistor T1 and the second thin-film transistor T2 are connected to the differential input signal, and their sources are connected to the input terminal of the first amplifier AMP1. One end of the first capacitor C1 is connected to the non-inverting input terminal of the first amplifier AMP1, and the other end is connected to the inverting output terminal of the first amplifier AMP1. One end of the second capacitor C2 is connected to the inverting input terminal of the first amplifier AMP1, and the other end is connected to the non-inverting output terminal of the first amplifier AMP1. The drain of the third thin-film transistor T3 is connected to the inverting output terminal of the first amplifier AMP1, and its source is connected to the inverting input terminal of the second amplifier AMP2. The drain of the fourth thin-film transistor T4 is connected to the non-inverting output terminal of the first amplifier AMP1, and its source is connected to the non-inverting input terminal of the second amplifier AMP2. One end of the third capacitor C3 is connected to the inverting input terminal of the second amplifier AMP2, and the other end is connected to the non-inverting output terminal of the second amplifier AMP2. One end of the fourth capacitor C4 is connected to the non-inverting input terminal of the second amplifier AMP2, and the other end is connected to the inverting output terminal of the second amplifier AMP2. The output terminal of the second amplifier AMP2 outputs the differential output signal of the integrator module. The non-inverting input terminal of the first amplifier is connected to the second feedback loop I. f2 The inverting input terminal is connected to the first feedback loop I. f1 The non-inverting input of the second amplifier is connected to the fourth feedback loop I. f4 The inverting input is connected to the third feedback loop I. f3 .

[0032] Both the first amplifier AMP1 and the second amplifier AMP2 employ a 0 VGS biased thin-film transistor load amplification structure, including a differential input pair, a 0 VGS biased thin-film transistor load, a source follower, and a biased thin-film transistor T. a5 The differential input pair includes a fifth thin-film transistor T. a1 and the sixth thin-film transistor T a3 The 0 VGS biased thin-film transistor load includes the seventh thin-film transistor T. a2 and the eighth thin-film transistor T a4 The source follower includes the ninth thin-film transistor T. a6 10th Thin Film Transistor T a7 Eleventh Thin Film Transistor T a8 and the twelfth thin-film transistor T a9 The fifth thin-film transistor T a1 and the sixth thin-film transistor T a3The gate is connected to the differential input signal, and the source is connected to the bias thin-film transistor T. a5 The drain of the fifth thin-film transistor T. a1 The drain of the seventh thin-film transistor T is connected. a2 The gate and source of the sixth thin-film transistor T a3 The drain of the eighth thin-film transistor T is connected. a4 The gate and source of the transistor. The ninth thin-film transistor T. a6 The gate of the fifth thin-film transistor T is connected. a1 The drain. The eleventh thin-film transistor T a8 The gate connection of the sixth thin-film transistor T a3 The drain of the tenth thin-film transistor T. a7 The drain is connected to the ninth thin-film transistor T. a6 The source. The twelfth thin-film transistor T. a9 The drain is connected to the eleventh thin-film transistor T. a8 The source. The seventh thin-film transistor T. a2 and the eighth thin-film transistor T a4 Ninth Thin Film Transistor T a6 Eleventh Thin Film Transistor T a8 The drains of both transistors are connected to the power supply VDD. The biased thin-film transistor T... a5 10th Thin Film Transistor T a7 The twelfth thin-film transistor T a9 The sources of all transistors are connected to ground. Bias thin-film transistor T a5 Gate connection control signal V b2 The tenth thin-film transistor T a7 The twelfth thin-film transistor T a9 The gates of all are connected to the control signal V. b3 The ninth thin-film transistor T a6 Eleventh Thin Film Transistor T a8 The differential output signal of the source-output amplifier. This structure increases the amplifier load, thereby achieving better voltage gain and bandwidth performance. For example... Figure 2 , Figure 3 As shown, the RC integrator continuously integrates the signal, resulting in a higher operating speed than the switched capacitor integrator.

[0033] The quantizer module includes a third amplifier AMP3, a comparator COMP1, a voltage matching module, and a D flip-flop DFF. These components are connected sequentially, as shown below. Figure 4 As shown. The third amplifier AMP3 employs a 0 VGS bias thin-film transistor load amplification structure, identical to the circuit structures of the first amplifier AMP1 and the second amplifier AMP2. Figure 3As shown. Comparator COMP1 is a continuous comparator, requiring no clock control, as... Figure 5 As shown. Comparator COMP1 consists of the twelfth thin-film transistor T. c1 Thirteenth Thin Film Transistor T c2 The fourteenth thin-film transistor T c3 The fifteenth thin-film transistor T c4 The sixteenth thin-film transistor T c5 Composition. Twelfth Thin Film Transistor T c1 The fourteenth thin-film transistor T c3 The gate is connected to the differential input signal, and the source is connected to the sixteenth thin-film transistor T. c5 The drain. The twelfth thin-film transistor T. c1 The drain connection of the thirteenth thin-film transistor T c2 The source. The fourteenth thin-film transistor T. c3 The drain of the 15th thin-film transistor T is connected. c4 The source and gate. The thirteenth thin-film transistor T. c2 The gate connection of the fifteenth thin-film transistor T c4 The gate. The thirteenth thin-film transistor T. c2 and the fifteenth thin-film transistor T c4 The drains of both transistors are connected to the power supply VDD. (Sixteenth Thin Film Transistor T) c5 Gate connection control signal V b1 The source is connected to the ground.

[0034] The voltage matching module includes two series-connected common capacitor bootstrap inverters (first inverter INV1 and second inverter INV2) to convert the comparator output voltage to a value that meets the high and low level requirements of the D flip-flop input.

[0035] The D flip-flop uses a common master-slave structure, including a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, and a first switching transistor T. D1 Second switching transistor T D2 Third switching transistor T D3 Fourth switching transistor T D4 Furthermore, multiple inverters connected in series—the ninth inverter INV9, the tenth inverter INV10, the eleventh inverter INV11, the twelfth inverter INV12, and the thirteenth inverter INV13—are added to the output terminal to optimize the output level. The first switching transistor T... D1 The drain of the transistor is connected to the input signal, and the source is connected to the input of the fifth inverter INV5 and the second switching transistor T. D2The drain of the fifth inverter, INV5, is connected to the input of the sixth inverter, INV6. The output of the sixth inverter, INV6, is connected to the second switching transistor, T. D2 The source. The third switching transistor T. D3 The drain of the transistor is connected to the output of inverter INV5, and the source is connected to the input of the seventh inverter INV7 and the fourth switching transistor T. D4 The drain of the seventh inverter, INV7, is connected to the input of the eighth inverter, INV8. The output of the eighth inverter, INV8, is connected to the fourth switching transistor, T. D4 The source of the second switching transistor T. D2 Third switching transistor T D3 The gate of the transistor is connected to the in-phase clock control signal. The first switching transistor T... D1 Fourth switching transistor T D4 Connect the inverting clock control signal. The input of the ninth inverter INV9 is connected to the output of the seventh inverter INV7. The ninth inverter INV9, tenth inverter INV10, eleventh inverter INV11, twelfth inverter INV12, and thirteenth inverter INV13 are connected in series. The output of the twelfth inverter INV12 serves as the non-inverting output of the D flip-flop. The output of the thirteenth inverter INV13 serves as the inverting output of the D flip-flop. The output of the D flip-flop is the output of the quantizer module. Figure 6 As shown. The fifth inverter INV5, sixth inverter INV6, seventh inverter INV7, and eighth inverter INV8 are commonly used capacitor bootstrap inverters; the ninth inverter INV9, tenth inverter INV10, eleventh inverter INV11, twelfth inverter INV12, and thirteenth inverter INV13 are commonly used pseudo-CMOS inverters. The D flip-flops are edge-triggered, ensuring that the output is unaffected by changes in the input signal within the same sample-and-hold period under clock control.

[0036] In one embodiment, the digital-to-analog converter feedback module includes a voltage regulation module and a current regulator. The voltage regulation module includes a bias circuit, a first source follower circuit, a common-source amplifier circuit, and a second source follower circuit. The bias circuit includes a seventeenth thin-film transistor T. f1 The eighteenth thin-film transistor T f2 The seventeenth thin-film transistor T f1 The drain and gate are connected to the power supply VDD, and the source is connected to the eighteenth thin-film transistor T. f2 The drain and gate. The eighteenth thin-film transistor T. f2 The source of the twentieth thin-film transistor T is connected to ground, and the gate is connected to the load of the first source follower circuit and the second source follower circuit. f4 22 Thin Film Transistor Tf6 28th Thin Film Transistor T f12 Thirtieth Thin Film Transistor T f14 The gate of the first source follower circuit includes the nineteenth thin-film transistor T. f3 20th Thin Film Transistor T f4 21 Thin Film Transistor T f5 22 Thin Film Transistor T f6 The nineteenth thin-film transistor T f3 21 Thin Film Transistor T f5 The gate of the transistor is connected to the differential input signal, and the drain is connected to the power supply VDD. (Nineteenth Thin Film Transistor T) f3 The source of the twentieth thin-film transistor T is connected. f4 The drain. The 21st thin-film transistor T f5 The source of the 22nd thin-film transistor T is connected. f6 The drain. The twentieth thin-film transistor T. f4 22 Thin Film Transistor T f6 The sources of all transistors are connected to ground. The common-source amplifier circuit includes the twenty-third thin-film transistor T. f7 24th Thin Film Transistor T f8 25th Thin Film Transistor T f9 26th Thin Film Transistor T f10 The 24th Thin Film Transistor T f8 The gate connection of the nineteenth thin-film transistor T f3 The source and drain are connected to the 23rd thin-film transistor T. f7 The source. The twenty-sixth thin-film transistor T. f10 The gate connection of the twenty-first thin-film transistor T f5 The source and drain of the 25th thin-film transistor T are connected. f9 The source. The twenty-fourth thin-film transistor T. f8 26th Thin Film Transistor T f10 The sources of all transistors are connected to ground. The twenty-third thin-film transistor T... f7 25th Thin Film Transistor T f9 Both the gate and drain are connected to the power supply VDD. The second source follower includes the twenty-seventh thin-film transistor T. f11 28th Thin Film Transistor T f12 29th Thin Film Transistor T f13 Thirtieth Thin Film Transistor T f14 The circuit structure is the same as the first source follower. The twenty-seventh thin-film transistor T... f11 The gate is connected to the twenty-third thin-film transistor T. f7 The source. The 29th thin-film transistor T. f13The gate is connected to the 25th thin-film transistor T. f9 The source. The current rudder includes the thirty-first thin-film transistor T. f15 Thirty-second thin-film transistor T f16 Thirty-third Thin Film Transistor T f17 Thirty-fourth Thin Film Transistor T f18 Thirty-fifth Thin Film Transistor T f19 Thirty-sixth Thin Film Transistor T f20 Thirty-first Thin Film Transistor T f15 The drain is connected to the first feedback loop I. f1 The gate is connected to the twenty-seventh thin-film transistor T. f11 The source. Thirty-second thin-film transistor T f16 The drain is connected to the second feedback loop I. f2 The gate is connected to the twenty-ninth thin-film transistor T. f13 The source. Thirty-first thin-film transistor T f15 Thirty-second thin-film transistor T f16 The source of each is connected to the 33rd thin-film transistor T. f17 The drain. Thirty-fourth thin-film transistor T f18 The drain is connected to the third feedback loop I. f3 The gate is connected to the twenty-seventh thin-film transistor T. f11 The source. Thirty-fifth Thin Film Transistor T f19 The drain is connected to the fourth feedback loop I. f4 The gate is connected to the twenty-ninth thin-film transistor T. f13 The source. Thirty-fourth thin-film transistor T f18 Thirty-fifth Thin Film Transistor T f19 The source of each is connected to the 36th thin-film transistor T. f20 The drain. Thirty-third thin-film transistor T f17 Thirty-sixth Thin Film Transistor T f20 The gates of all are connected to the control signal V. b3 The source terminals are all connected to ground. The quantizer output signal first passes through a voltage regulation module to convert the high and low levels to an appropriate magnitude before being connected to the control gate of the current rudder to adjust the current rudder current I. f1 I f2 I f3 I f4 The current rudder is connected at the node between the integrating resistor and the amplifier in the first integrator module and the second integrator module. The summation with the input signal is achieved through the voltage drop across the resistor caused by the current. For example... Figure 7 As shown.

[0037] The output buffer module consists of a third inverter (INV3) and a fourth inverter (INV4) using a common pseudo-CMOS structure. The input of the third inverter (INV3) is connected to the non-inverting output of a D flip-flop, and its output serves as the inverting output of the Delta-Sigma modulator. The input of the fourth inverter (INV4) is connected to the inverting output of a D flip-flop, and its output serves as the non-inverting output of the Delta-Sigma modulator.

[0038] Figure 8 The frequency response characteristics of the 0 VGS biased thin-film transistor (TFT) load amplifier are shown, with a gain of 44 dB, a bandwidth of 23 kHz, and a phase margin of 68°. Table 1 summarizes the performance of this amplifier and compares it with other TFT amplifiers. This approach offers greater gain, wider bandwidth, stable phase margin, and extremely low power consumption.

[0039] Table 1. Performance Comparison of MO TFT Amplifiers

[0040] like Figure 9 As shown, in the Delta-Sigma modulator V in+ and V in- A sinusoidal voltage signal is input to the input terminal, and the output signal of the Delta-Sigma modulator is detected to obtain the output spectrum. The results show that at an operating frequency of 25600 Hz, the Delta-Sigma modulator can achieve a signal-to-noise ratio (SNDR) of 71.6 dB within a 100 Hz bandwidth, corresponding to an effective bit depth of 11.6 bits. Table 2 summarizes the modulator's performance and compares it with other TFT Delta-Sigma modulators. Compared with previous TFT Delta-Sigma modulators, this technology offers higher operating speed, a larger SNDR, a larger bandwidth (BW), and a better factor of quality (FOM).

[0041] Table 2 Performance Comparison of TFT Δ-Σ Modulators

[0042] The references in the table are: [1] Meng FZ, Li Y, Li J, et al. A Performance Optimized OperationalAmplifier Using Transconductance Enhancement Topology Based on a-IGZO TFTs[J]. IEEE Journal of the Electron Devices Society, 2024, 12:159-164. [2] Zhao MJ, Li LQ, Liu R, et al. A 43.5dB Gain Unipolar a-IGZO TFTAmplifier With Parallel Bootstrap Capacitor for Bio-Signals SensingApplications[J]. IEEE Transactions on Biomedical Circuits and Systems, 2024,18(6):1371 – 1381. [3] Deng ZY, Chen RS, Lin DL, et al. A Fully MOTFT-Based TactileSensing and Amplifying System[J]. IEEE Sensors Journal, 2025, 25(14):26492-26498. [4] Garripoli C, van der Steen JLPJ, Smits E, et al. An a-IGZOAsynchronous Delta-Sigma Modulator on Foil Achieving up to 43dB SNR and 40dBSNDR in 300Hz Bandwidth[C]. 2017 IEEE International Solid-State CircuitsConference (ISSCC), 2017. [5] Xu WX, Chen JR, Li FF, et al. A 65-dB SNDR Continuous-Time Delta-Sigma ADC Integrated by IZO Thin-Film Transistors[J]. 2024, 71(4):1804-1808. [6] Deng ZY, Chen RS, Lin DL, et al. A 4.5 mW 58.7 dB SNDR discrete-time delta-sigma modulator based on MOTFTs for ECG signal recording[J]. 2025,166:106877. In summary, this invention realizes a continuous-time cascaded feedback (CIFB) integrator structure MO TFT Delta-Sigma modulator using unipolar metal-oxide-slim transistor (MOSFET) technology, thereby improving the noise shaping capability of TFT Delta-Sigma modulators. The amplifier of this invention employs a 0 VGS bias MOSFET load amplification structure, providing 44 dB gain while maintaining a large bandwidth of 23 kHz, along with a 68° phase margin and extremely low power consumption.

[0043] This invention employs a quantization method using a continuous comparator and a D flip-flop, resulting in a more stable output and enabling a higher operating frequency while reducing kickback noise. This unipolar TFT Delta-Sigma modulator scheme operates at a higher frequency and achieves a higher signal-to-noise ratio (SNR) of 71.6 dB over a wider 100 Hz bandwidth. The modulator also exhibits a better FOM (Forward Object Model) factor of only 0.04 nJ / cs.

[0044] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, enabling those skilled in the art to better understand and utilize the invention.

Claims

1. A Delta-Sigma modulator based on a unipolar thin-film transistor, characterized in that, It includes a first integrator module, a second integrator module, a quantizer module, a digital-to-analog converter feedback module, and an output buffer module. The first integrator module, the second integrator module, and the quantizer module are connected in sequence. The output terminal of the quantizer module is connected to the input terminal of the digital-to-analog converter feedback module and the input terminal of the output buffer module. The analog input signal is first integrated by the integrator module, then quantized by the quantizer module. The quantization result is fed back to the input terminal by the digital-to-analog converter feedback module. Each quantization output is summed with the input signal through the feedback, and the summed signal is then input back to the integrator module.

2. The Delta-Sigma modulator based on a unipolar thin-film transistor according to claim 1, characterized in that, The first integrator module and the second integrator module have the same structure, both using a resistor-capacitor integrator, and both include a resistor, a capacitor and an amplifier.

3. The Delta-Sigma modulator based on a unipolar thin-film transistor according to claim 1, characterized in that, The quantizer module includes an amplifier, a comparator, a voltage matching module, and a D flip-flop, which are connected in sequence.

4. The Delta-Sigma modulator based on a unipolar thin-film transistor according to claims 1-3, characterized in that, The amplifier employs a thin-film transistor load amplification structure with 0 VGS bias.

5. The Delta-Sigma modulator based on a unipolar thin-film transistor according to claim 3, characterized in that, Comparator COMP1 is a continuous comparator and does not require clock control.

6. The Delta-Sigma modulator based on a unipolar thin-film transistor according to claim 3, characterized in that, The voltage matching module includes two series-connected capacitor bootstrap inverters to convert the comparator output voltage to a value that meets the high and low level requirements of the D flip-flop input.

7. The Delta-Sigma modulator based on a unipolar thin-film transistor according to claim 3, characterized in that, The D flip-flop employs a master-slave structure consisting of multiple inverters and switching transistors, and adds multiple series inverters at the output to optimize the output level.

8. The Delta-Sigma modulator based on a unipolar thin-film transistor according to claim 1, characterized in that, The digital-to-analog converter feedback module includes a voltage regulation module and a current rudder. The output signal of the quantizer module first passes through the voltage regulation module to convert the high and low levels, and then is connected to the control gate of the current rudder to adjust the magnitude of the current. The current rudder is connected to the input terminal of the modulator and passes through an integrating resistor. The voltage drop formed by the current across the resistor is used to sum with the input signal.

9. The Delta-Sigma modulator based on a unipolar thin-film transistor according to claim 1, characterized in that, The current rudder is connected to the node between the integrating resistor and the amplifier in the first integrator module and the second integrator module. It achieves summation with the input signal through the voltage drop formed by the current across the resistor.

10. The Delta-Sigma modulator based on a unipolar thin-film transistor according to claim 3, characterized in that, The output buffer module includes two inverters. The input of one inverter is connected to the non-inverting output of a D flip-flop, and its output serves as the inverting output of a Delta-Sigma modulator. The input of the other inverter is connected to the inverting output of a D flip-flop, and its output serves as the non-inverting output of a Delta-Sigma modulator.

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